1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2013 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 /* $FreeBSD$ */ 42 43 #include <sys/param.h> 44 #include <sys/endian.h> 45 #include <sys/epoch.h> 46 #include <sys/eventhandler.h> 47 #include <sys/malloc.h> 48 #include <sys/module.h> 49 #include <sys/kernel.h> 50 #include <sys/bus.h> 51 #include <sys/mbuf.h> 52 #include <sys/priv.h> 53 #include <sys/rman.h> 54 #include <sys/socket.h> 55 #include <sys/sockio.h> 56 #include <sys/sockopt.h> 57 #include <sys/queue.h> 58 #include <sys/taskqueue.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/sysctl.h> 62 #include <sys/random.h> 63 #include <sys/firmware.h> 64 #include <sys/systm.h> 65 #include <sys/proc.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <net/bpf.h> 71 #include <net/ethernet.h> 72 #include <net/if.h> 73 #include <net/if_var.h> 74 #include <net/if_types.h> 75 #include <net/if_media.h> 76 #include <net/if_vlan_var.h> 77 #include <net/if_dl.h> 78 79 #include <netinet/in.h> 80 #include <netinet/in_systm.h> 81 #include <netinet/in_var.h> 82 #include <netinet/if_ether.h> 83 #include <netinet/ip.h> 84 #include <netinet/ip6.h> 85 #include <netinet6/in6_var.h> 86 #include <netinet6/ip6_mroute.h> 87 88 #include <netinet/udp.h> 89 #include <netinet/tcp.h> 90 #include <netinet/sctp.h> 91 #include <netinet/tcp_lro.h> 92 #include <netinet/icmp6.h> 93 94 #include <machine/bus.h> 95 96 #include "oce_hw.h" 97 98 /* OCE device driver module component revision informaiton */ 99 #define COMPONENT_REVISION "11.0.50.0" 100 101 /* OCE devices supported by this driver */ 102 #define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 103 #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 104 #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 105 #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 106 #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 107 #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ 108 #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */ 109 110 #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 111 (sc->flags & OCE_FLAGS_BE2))? 1:0) 112 #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3) 113 #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2) 114 #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 115 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) 116 #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0) 117 118 #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \ 119 (sc->function_mode & FNM_UMC_MODE) || \ 120 (sc->function_mode & FNM_VNIC_MODE)) 121 #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40 122 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC) 123 124 /* proportion Service Level Interface queues */ 125 #define OCE_MAX_UNITS 2 126 #define OCE_MAX_PPORT OCE_MAX_UNITS 127 #define OCE_MAX_VPORT OCE_MAX_UNITS 128 129 extern int mp_ncpus; /* system's total active cpu cores */ 130 #define OCE_NCPUS mp_ncpus 131 132 /* This should be powers of 2. Like 2,4,8 & 16 */ 133 #define OCE_MAX_RSS 8 134 #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ 135 #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc)) 136 137 #define OCE_MIN_RQ 1 138 #define OCE_MIN_WQ 1 139 140 #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 141 #define OCE_MAX_WQ 8 142 143 #define OCE_MAX_EQ 32 144 #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */ 145 #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */ 146 147 #define OCE_DEFAULT_WQ_EQD 16 148 #define OCE_MAX_PACKET_Q 16 149 #define OCE_LSO_MAX_SIZE (64 * 1024) 150 #define LONG_TIMEOUT 30 151 #define OCE_MAX_JUMBO_FRAME_SIZE 9018 152 #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \ 153 ETHER_VLAN_ENCAP_LEN - \ 154 ETHER_HDR_LEN) 155 156 #define OCE_RDMA_VECTORS 2 157 158 #define OCE_MAX_TX_ELEMENTS 29 159 #define OCE_MAX_TX_DESC 1024 160 #define OCE_MAX_TX_SIZE 65535 161 #define OCE_MAX_TSO_SIZE (65535 - ETHER_HDR_LEN) 162 #define OCE_MAX_RX_SIZE 4096 163 #define OCE_MAX_RQ_POSTS 255 164 #define OCE_HWLRO_MAX_RQ_POSTS 64 165 #define OCE_DEFAULT_PROMISCUOUS 0 166 167 #define RSS_ENABLE_IPV4 0x1 168 #define RSS_ENABLE_TCP_IPV4 0x2 169 #define RSS_ENABLE_IPV6 0x4 170 #define RSS_ENABLE_TCP_IPV6 0x8 171 172 #define INDIRECTION_TABLE_ENTRIES 128 173 174 /* flow control definitions */ 175 #define OCE_FC_NONE 0x00000000 176 #define OCE_FC_TX 0x00000001 177 #define OCE_FC_RX 0x00000002 178 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 179 180 /* Interface capabilities to give device when creating interface */ 181 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 182 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 183 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 184 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \ 185 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 186 MBX_RX_IFACE_FLAGS_RSS | \ 187 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 188 189 /* Interface capabilities to enable by default (others set dynamically) */ 190 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 191 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 192 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 193 194 #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 195 #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 196 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \ 197 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU) 198 #define OCE_IF_HWASSIST_NONE 0 199 #define OCE_IF_CAPABILITIES_NONE 0 200 201 #define MAX_VLANFILTER_SIZE 64 202 #define MAX_VLANS 4096 203 204 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 205 #define BSWAP_8(x) ((x) & 0xff) 206 #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8)) 207 #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \ 208 BSWAP_16((x) >> 16)) 209 #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 210 BSWAP_32((x) >> 32)) 211 212 #define for_all_wq_queues(sc, wq, i) \ 213 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 214 #define for_all_rq_queues(sc, rq, i) \ 215 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) 216 #define for_all_rss_queues(sc, rq, i) \ 217 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \ 218 i++, rq = sc->rq[i + 1]) 219 #define for_all_evnt_queues(sc, eq, i) \ 220 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 221 #define for_all_cq_queues(sc, cq, i) \ 222 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 223 224 /* Flash specific */ 225 #define IOCTL_COOKIE "SERVERENGINES CORP" 226 #define MAX_FLASH_COMP 32 227 228 #define IMG_ISCSI 160 229 #define IMG_REDBOOT 224 230 #define IMG_BIOS 34 231 #define IMG_PXEBIOS 32 232 #define IMG_FCOEBIOS 33 233 #define IMG_ISCSI_BAK 176 234 #define IMG_FCOE 162 235 #define IMG_FCOE_BAK 178 236 #define IMG_NCSI 16 237 #define IMG_PHY 192 238 #define FLASHROM_OPER_FLASH 1 239 #define FLASHROM_OPER_SAVE 2 240 #define FLASHROM_OPER_REPORT 4 241 #define FLASHROM_OPER_FLASH_PHY 9 242 #define FLASHROM_OPER_SAVE_PHY 10 243 #define TN_8022 13 244 245 enum { 246 PHY_TYPE_CX4_10GB = 0, 247 PHY_TYPE_XFP_10GB, 248 PHY_TYPE_SFP_1GB, 249 PHY_TYPE_SFP_PLUS_10GB, 250 PHY_TYPE_KR_10GB, 251 PHY_TYPE_KX4_10GB, 252 PHY_TYPE_BASET_10GB, 253 PHY_TYPE_BASET_1GB, 254 PHY_TYPE_BASEX_1GB, 255 PHY_TYPE_SGMII, 256 PHY_TYPE_DISABLED = 255 257 }; 258 259 /** 260 * @brief Define and hold all necessary info for a single interrupt 261 */ 262 #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */ 263 #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */ 264 265 typedef struct oce_intr_info { 266 void *tag; /* cookie returned by bus_setup_intr */ 267 struct resource *intr_res; /* PCI resource container */ 268 int irq_rr; /* resource id for the interrupt */ 269 struct oce_softc *sc; /* pointer to the parent soft c */ 270 struct oce_eq *eq; /* pointer to the connected EQ */ 271 struct taskqueue *tq; /* Associated task queue */ 272 struct task task; /* task queue task */ 273 char task_name[32]; /* task name */ 274 int vector; /* interrupt vector number */ 275 } OCE_INTR_INFO, *POCE_INTR_INFO; 276 277 /* Ring related */ 278 #define GET_Q_NEXT(_START, _STEP, _END) \ 279 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ 280 : (((_START) + (_STEP)) - (_END))) 281 282 #define DBUF_PA(obj) ((obj)->addr) 283 #define DBUF_VA(obj) ((obj)->ptr) 284 #define DBUF_TAG(obj) ((obj)->tag) 285 #define DBUF_MAP(obj) ((obj)->map) 286 #define DBUF_SYNC(obj, flags) \ 287 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags)) 288 289 #define RING_NUM_PENDING(ring) ring->num_used 290 #define RING_FULL(ring) (ring->num_used == ring->num_items) 291 #define RING_EMPTY(ring) (ring->num_used == 0) 292 #define RING_NUM_FREE(ring) \ 293 (uint32_t)(ring->num_items - ring->num_used) 294 #define RING_GET(ring, n) \ 295 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items) 296 #define RING_PUT(ring, n) \ 297 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items) 298 299 #define RING_GET_CONSUMER_ITEM_VA(ring, type) \ 300 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx) 301 #define RING_GET_CONSUMER_ITEM_PA(ring, type) \ 302 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx) 303 #define RING_GET_PRODUCER_ITEM_VA(ring, type) \ 304 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx) 305 #define RING_GET_PRODUCER_ITEM_PA(ring, type) \ 306 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx) 307 308 #define OCE_DMAPTR(o, c) ((c *)(o)->ptr) 309 310 struct oce_packet_desc { 311 struct mbuf *mbuf; 312 bus_dmamap_t map; 313 int nsegs; 314 uint32_t wqe_idx; 315 }; 316 317 typedef struct oce_dma_mem { 318 bus_dma_tag_t tag; 319 bus_dmamap_t map; 320 void *ptr; 321 bus_addr_t paddr; 322 } OCE_DMA_MEM, *POCE_DMA_MEM; 323 324 typedef struct oce_ring_buffer_s { 325 uint16_t cidx; /* Get ptr */ 326 uint16_t pidx; /* Put Ptr */ 327 size_t item_size; 328 size_t num_items; 329 uint32_t num_used; 330 OCE_DMA_MEM dma; 331 } oce_ring_buffer_t; 332 333 /* Stats */ 334 #define OCE_UNICAST_PACKET 0 335 #define OCE_MULTICAST_PACKET 1 336 #define OCE_BROADCAST_PACKET 2 337 #define OCE_RSVD_PACKET 3 338 339 struct oce_rx_stats { 340 /* Total Receive Stats*/ 341 uint64_t t_rx_pkts; 342 uint64_t t_rx_bytes; 343 uint32_t t_rx_frags; 344 uint32_t t_rx_mcast_pkts; 345 uint32_t t_rx_ucast_pkts; 346 uint32_t t_rxcp_errs; 347 }; 348 struct oce_tx_stats { 349 /*Total Transmit Stats */ 350 uint64_t t_tx_pkts; 351 uint64_t t_tx_bytes; 352 uint32_t t_tx_reqs; 353 uint32_t t_tx_stops; 354 uint32_t t_tx_wrbs; 355 uint32_t t_tx_compl; 356 uint32_t t_ipv6_ext_hdr_tx_drop; 357 }; 358 359 struct oce_be_stats { 360 uint8_t be_on_die_temperature; 361 uint32_t be_tx_events; 362 uint32_t eth_red_drops; 363 uint32_t rx_drops_no_pbuf; 364 uint32_t rx_drops_no_txpb; 365 uint32_t rx_drops_no_erx_descr; 366 uint32_t rx_drops_no_tpre_descr; 367 uint32_t rx_drops_too_many_frags; 368 uint32_t rx_drops_invalid_ring; 369 uint32_t forwarded_packets; 370 uint32_t rx_drops_mtu; 371 uint32_t rx_crc_errors; 372 uint32_t rx_alignment_symbol_errors; 373 uint32_t rx_pause_frames; 374 uint32_t rx_priority_pause_frames; 375 uint32_t rx_control_frames; 376 uint32_t rx_in_range_errors; 377 uint32_t rx_out_range_errors; 378 uint32_t rx_frame_too_long; 379 uint32_t rx_address_match_errors; 380 uint32_t rx_dropped_too_small; 381 uint32_t rx_dropped_too_short; 382 uint32_t rx_dropped_header_too_small; 383 uint32_t rx_dropped_tcp_length; 384 uint32_t rx_dropped_runt; 385 uint32_t rx_ip_checksum_errs; 386 uint32_t rx_tcp_checksum_errs; 387 uint32_t rx_udp_checksum_errs; 388 uint32_t rx_switched_unicast_packets; 389 uint32_t rx_switched_multicast_packets; 390 uint32_t rx_switched_broadcast_packets; 391 uint32_t tx_pauseframes; 392 uint32_t tx_priority_pauseframes; 393 uint32_t tx_controlframes; 394 uint32_t rxpp_fifo_overflow_drop; 395 uint32_t rx_input_fifo_overflow_drop; 396 uint32_t pmem_fifo_overflow_drop; 397 uint32_t jabber_events; 398 }; 399 400 struct oce_xe201_stats { 401 uint64_t tx_pkts; 402 uint64_t tx_unicast_pkts; 403 uint64_t tx_multicast_pkts; 404 uint64_t tx_broadcast_pkts; 405 uint64_t tx_bytes; 406 uint64_t tx_unicast_bytes; 407 uint64_t tx_multicast_bytes; 408 uint64_t tx_broadcast_bytes; 409 uint64_t tx_discards; 410 uint64_t tx_errors; 411 uint64_t tx_pause_frames; 412 uint64_t tx_pause_on_frames; 413 uint64_t tx_pause_off_frames; 414 uint64_t tx_internal_mac_errors; 415 uint64_t tx_control_frames; 416 uint64_t tx_pkts_64_bytes; 417 uint64_t tx_pkts_65_to_127_bytes; 418 uint64_t tx_pkts_128_to_255_bytes; 419 uint64_t tx_pkts_256_to_511_bytes; 420 uint64_t tx_pkts_512_to_1023_bytes; 421 uint64_t tx_pkts_1024_to_1518_bytes; 422 uint64_t tx_pkts_1519_to_2047_bytes; 423 uint64_t tx_pkts_2048_to_4095_bytes; 424 uint64_t tx_pkts_4096_to_8191_bytes; 425 uint64_t tx_pkts_8192_to_9216_bytes; 426 uint64_t tx_lso_pkts; 427 uint64_t rx_pkts; 428 uint64_t rx_unicast_pkts; 429 uint64_t rx_multicast_pkts; 430 uint64_t rx_broadcast_pkts; 431 uint64_t rx_bytes; 432 uint64_t rx_unicast_bytes; 433 uint64_t rx_multicast_bytes; 434 uint64_t rx_broadcast_bytes; 435 uint32_t rx_unknown_protos; 436 uint64_t rx_discards; 437 uint64_t rx_errors; 438 uint64_t rx_crc_errors; 439 uint64_t rx_alignment_errors; 440 uint64_t rx_symbol_errors; 441 uint64_t rx_pause_frames; 442 uint64_t rx_pause_on_frames; 443 uint64_t rx_pause_off_frames; 444 uint64_t rx_frames_too_long; 445 uint64_t rx_internal_mac_errors; 446 uint32_t rx_undersize_pkts; 447 uint32_t rx_oversize_pkts; 448 uint32_t rx_fragment_pkts; 449 uint32_t rx_jabbers; 450 uint64_t rx_control_frames; 451 uint64_t rx_control_frames_unknown_opcode; 452 uint32_t rx_in_range_errors; 453 uint32_t rx_out_of_range_errors; 454 uint32_t rx_address_match_errors; 455 uint32_t rx_vlan_mismatch_errors; 456 uint32_t rx_dropped_too_small; 457 uint32_t rx_dropped_too_short; 458 uint32_t rx_dropped_header_too_small; 459 uint32_t rx_dropped_invalid_tcp_length; 460 uint32_t rx_dropped_runt; 461 uint32_t rx_ip_checksum_errors; 462 uint32_t rx_tcp_checksum_errors; 463 uint32_t rx_udp_checksum_errors; 464 uint32_t rx_non_rss_pkts; 465 uint64_t rx_ipv4_pkts; 466 uint64_t rx_ipv6_pkts; 467 uint64_t rx_ipv4_bytes; 468 uint64_t rx_ipv6_bytes; 469 uint64_t rx_nic_pkts; 470 uint64_t rx_tcp_pkts; 471 uint64_t rx_iscsi_pkts; 472 uint64_t rx_management_pkts; 473 uint64_t rx_switched_unicast_pkts; 474 uint64_t rx_switched_multicast_pkts; 475 uint64_t rx_switched_broadcast_pkts; 476 uint64_t num_forwards; 477 uint32_t rx_fifo_overflow; 478 uint32_t rx_input_fifo_overflow; 479 uint64_t rx_drops_too_many_frags; 480 uint32_t rx_drops_invalid_queue; 481 uint64_t rx_drops_mtu; 482 uint64_t rx_pkts_64_bytes; 483 uint64_t rx_pkts_65_to_127_bytes; 484 uint64_t rx_pkts_128_to_255_bytes; 485 uint64_t rx_pkts_256_to_511_bytes; 486 uint64_t rx_pkts_512_to_1023_bytes; 487 uint64_t rx_pkts_1024_to_1518_bytes; 488 uint64_t rx_pkts_1519_to_2047_bytes; 489 uint64_t rx_pkts_2048_to_4095_bytes; 490 uint64_t rx_pkts_4096_to_8191_bytes; 491 uint64_t rx_pkts_8192_to_9216_bytes; 492 }; 493 494 struct oce_drv_stats { 495 struct oce_rx_stats rx; 496 struct oce_tx_stats tx; 497 union { 498 struct oce_be_stats be; 499 struct oce_xe201_stats xe201; 500 } u0; 501 }; 502 503 #define INTR_RATE_HWM 15000 504 #define INTR_RATE_LWM 10000 505 506 #define OCE_MAX_EQD 128u 507 #define OCE_MIN_EQD 0u 508 509 struct oce_set_eqd { 510 uint32_t eq_id; 511 uint32_t phase; 512 uint32_t delay_multiplier; 513 }; 514 515 struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 516 boolean_t enable; 517 uint32_t min_eqd; /* in usecs */ 518 uint32_t max_eqd; /* in usecs */ 519 uint32_t cur_eqd; /* in usecs */ 520 uint32_t et_eqd; /* configured value when aic is off */ 521 uint64_t ticks; 522 uint64_t prev_rxpkts; 523 uint64_t prev_txreqs; 524 }; 525 526 #define MAX_LOCK_DESC_LEN 32 527 struct oce_lock { 528 struct mtx mutex; 529 char name[MAX_LOCK_DESC_LEN+1]; 530 }; 531 #define OCE_LOCK struct oce_lock 532 533 #define LOCK_CREATE(lock, desc) { \ 534 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \ 535 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \ 536 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \ 537 } 538 #define LOCK_DESTROY(lock) \ 539 if (mtx_initialized(&(lock)->mutex))\ 540 mtx_destroy(&(lock)->mutex) 541 #define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex) 542 #define LOCK(lock) mtx_lock(&(lock)->mutex) 543 #define LOCKED(lock) mtx_owned(&(lock)->mutex) 544 #define UNLOCK(lock) mtx_unlock(&(lock)->mutex) 545 546 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) 547 #define MBX_READY_TIMEOUT (1 * 1000 * 1000) 548 #define DEFAULT_DRAIN_TIME 200 549 #define MBX_TIMEOUT_SEC 5 550 #define STAT_TIMEOUT 2000000 551 552 /* size of the packet descriptor array in a transmit queue */ 553 #define OCE_TX_RING_SIZE 2048 554 #define OCE_RX_RING_SIZE 1024 555 #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2) 556 #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE) 557 558 struct oce_dev; 559 560 enum eq_len { 561 EQ_LEN_256 = 256, 562 EQ_LEN_512 = 512, 563 EQ_LEN_1024 = 1024, 564 EQ_LEN_2048 = 2048, 565 EQ_LEN_4096 = 4096 566 }; 567 568 enum eqe_size { 569 EQE_SIZE_4 = 4, 570 EQE_SIZE_16 = 16 571 }; 572 573 enum qtype { 574 QTYPE_EQ, 575 QTYPE_MQ, 576 QTYPE_WQ, 577 QTYPE_RQ, 578 QTYPE_CQ, 579 QTYPE_RSS 580 }; 581 582 typedef enum qstate_e { 583 QDELETED = 0x0, 584 QCREATED = 0x1 585 } qstate_t; 586 587 struct eq_config { 588 enum eq_len q_len; 589 enum eqe_size item_size; 590 uint32_t q_vector_num; 591 uint8_t min_eqd; 592 uint8_t max_eqd; 593 uint8_t cur_eqd; 594 uint8_t pad; 595 }; 596 597 struct oce_eq { 598 uint32_t eq_id; 599 void *parent; 600 void *cb_context; 601 oce_ring_buffer_t *ring; 602 uint32_t ref_count; 603 qstate_t qstate; 604 struct oce_cq *cq[OCE_MAX_CQ_EQ]; 605 int cq_valid; 606 struct eq_config eq_cfg; 607 int vector; 608 uint64_t intr; 609 }; 610 611 enum cq_len { 612 CQ_LEN_256 = 256, 613 CQ_LEN_512 = 512, 614 CQ_LEN_1024 = 1024, 615 CQ_LEN_2048 = 2048 616 }; 617 618 struct cq_config { 619 enum cq_len q_len; 620 uint32_t item_size; 621 boolean_t is_eventable; 622 boolean_t sol_eventable; 623 boolean_t nodelay; 624 uint16_t dma_coalescing; 625 }; 626 627 typedef uint16_t(*cq_handler_t) (void *arg1); 628 629 struct oce_cq { 630 uint32_t cq_id; 631 void *parent; 632 struct oce_eq *eq; 633 cq_handler_t cq_handler; 634 void *cb_arg; 635 oce_ring_buffer_t *ring; 636 qstate_t qstate; 637 struct cq_config cq_cfg; 638 uint32_t ref_count; 639 }; 640 641 struct mq_config { 642 uint32_t eqd; 643 uint8_t q_len; 644 uint8_t pad[3]; 645 }; 646 647 struct oce_mq { 648 void *parent; 649 oce_ring_buffer_t *ring; 650 uint32_t mq_id; 651 struct oce_cq *cq; 652 struct oce_cq *async_cq; 653 uint32_t mq_free; 654 qstate_t qstate; 655 struct mq_config cfg; 656 }; 657 658 struct oce_mbx_ctx { 659 struct oce_mbx *mbx; 660 void (*cb) (void *ctx); 661 void *cb_ctx; 662 }; 663 664 struct wq_config { 665 uint8_t wq_type; 666 uint16_t buf_size; 667 uint8_t pad[1]; 668 uint32_t q_len; 669 uint16_t pd_id; 670 uint16_t pci_fn_num; 671 uint32_t eqd; /* interrupt delay */ 672 uint32_t nbufs; 673 uint32_t nhdl; 674 }; 675 676 struct oce_tx_queue_stats { 677 uint64_t tx_pkts; 678 uint64_t tx_bytes; 679 uint32_t tx_reqs; 680 uint32_t tx_stops; /* number of times TX Q was stopped */ 681 uint32_t tx_wrbs; 682 uint32_t tx_compl; 683 uint32_t tx_rate; 684 uint32_t ipv6_ext_hdr_tx_drop; 685 }; 686 687 struct oce_wq { 688 OCE_LOCK tx_lock; 689 OCE_LOCK tx_compl_lock; 690 void *parent; 691 oce_ring_buffer_t *ring; 692 struct oce_cq *cq; 693 bus_dma_tag_t tag; 694 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; 695 uint32_t pkt_desc_tail; 696 uint32_t pkt_desc_head; 697 uint32_t wqm_used; 698 boolean_t resched; 699 uint32_t wq_free; 700 uint32_t tx_deferd; 701 uint32_t pkt_drops; 702 qstate_t qstate; 703 uint16_t wq_id; 704 struct wq_config cfg; 705 int queue_index; 706 struct oce_tx_queue_stats tx_stats; 707 struct buf_ring *br; 708 struct task txtask; 709 uint32_t db_offset; 710 }; 711 712 struct rq_config { 713 uint32_t q_len; 714 uint32_t frag_size; 715 uint32_t mtu; 716 uint32_t if_id; 717 uint32_t is_rss_queue; 718 uint32_t eqd; 719 uint32_t nbufs; 720 }; 721 722 struct oce_rx_queue_stats { 723 uint32_t rx_post_fail; 724 uint32_t rx_ucast_pkts; 725 uint32_t rx_compl; 726 uint64_t rx_bytes; 727 uint64_t rx_bytes_prev; 728 uint64_t rx_pkts; 729 uint32_t rx_rate; 730 uint32_t rx_mcast_pkts; 731 uint32_t rxcp_err; 732 uint32_t rx_frags; 733 uint32_t prev_rx_frags; 734 uint32_t rx_fps; 735 uint32_t rx_drops_no_frags; /* HW has no fetched frags */ 736 }; 737 738 struct oce_rq { 739 struct rq_config cfg; 740 uint32_t rq_id; 741 int queue_index; 742 uint32_t rss_cpuid; 743 void *parent; 744 oce_ring_buffer_t *ring; 745 struct oce_cq *cq; 746 void *pad1; 747 bus_dma_tag_t tag; 748 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE]; 749 uint32_t pending; 750 #ifdef notdef 751 struct mbuf *head; 752 struct mbuf *tail; 753 int fragsleft; 754 #endif 755 qstate_t qstate; 756 OCE_LOCK rx_lock; 757 struct oce_rx_queue_stats rx_stats; 758 struct lro_ctrl lro; 759 int lro_pkts_queued; 760 int islro; 761 struct nic_hwlro_cqe_part1 *cqe_firstpart; 762 763 }; 764 765 struct link_status { 766 uint8_t phys_port_speed; 767 uint8_t logical_link_status; 768 uint16_t qos_link_speed; 769 }; 770 771 #define OCE_FLAGS_PCIX 0x00000001 772 #define OCE_FLAGS_PCIE 0x00000002 773 #define OCE_FLAGS_MSI_CAPABLE 0x00000004 774 #define OCE_FLAGS_MSIX_CAPABLE 0x00000008 775 #define OCE_FLAGS_USING_MSI 0x00000010 776 #define OCE_FLAGS_USING_MSIX 0x00000020 777 #define OCE_FLAGS_FUNCRESET_RQD 0x00000040 778 #define OCE_FLAGS_VIRTUAL_PORT 0x00000080 779 #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 780 #define OCE_FLAGS_BE3 0x00000200 781 #define OCE_FLAGS_XE201 0x00000400 782 #define OCE_FLAGS_BE2 0x00000800 783 #define OCE_FLAGS_SH 0x00001000 784 #define OCE_FLAGS_OS2BMC 0x00002000 785 786 #define OCE_DEV_BE2_CFG_BAR 1 787 #define OCE_DEV_CFG_BAR 0 788 #define OCE_PCI_CSR_BAR 2 789 #define OCE_PCI_DB_BAR 4 790 791 typedef struct oce_softc { 792 device_t dev; 793 OCE_LOCK dev_lock; 794 795 uint32_t flags; 796 797 uint32_t pcie_link_speed; 798 uint32_t pcie_link_width; 799 800 uint8_t fn; /* PCI function number */ 801 802 struct resource *devcfg_res; 803 bus_space_tag_t devcfg_btag; 804 bus_space_handle_t devcfg_bhandle; 805 void *devcfg_vhandle; 806 807 struct resource *csr_res; 808 bus_space_tag_t csr_btag; 809 bus_space_handle_t csr_bhandle; 810 void *csr_vhandle; 811 812 struct resource *db_res; 813 bus_space_tag_t db_btag; 814 bus_space_handle_t db_bhandle; 815 void *db_vhandle; 816 817 OCE_INTR_INFO intrs[OCE_MAX_EQ]; 818 int intr_count; 819 int roce_intr_count; 820 821 struct ifnet *ifp; 822 823 struct ifmedia media; 824 uint8_t link_status; 825 uint8_t link_speed; 826 uint8_t duplex; 827 uint32_t qos_link_speed; 828 uint32_t speed; 829 uint32_t enable_hwlro; 830 831 char fw_version[32]; 832 struct mac_address_format macaddr; 833 834 OCE_DMA_MEM bsmbx; 835 OCE_LOCK bmbx_lock; 836 837 uint32_t config_number; 838 uint32_t asic_revision; 839 uint32_t port_id; 840 uint32_t function_mode; 841 uint32_t function_caps; 842 uint32_t max_tx_rings; 843 uint32_t max_rx_rings; 844 845 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */ 846 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */ 847 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 848 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 849 struct oce_mq *mq; /* Mailbox queue */ 850 851 uint32_t neqs; 852 uint32_t ncqs; 853 uint32_t nrqs; 854 uint32_t nwqs; 855 uint32_t nrssqs; 856 857 uint32_t tx_ring_size; 858 uint32_t rx_ring_size; 859 uint32_t rq_frag_size; 860 861 uint32_t if_id; /* interface ID */ 862 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 863 uint32_t pmac_id; /* PMAC id */ 864 865 uint32_t if_cap_flags; 866 867 uint32_t flow_control; 868 uint8_t promisc; 869 870 struct oce_aic_obj aic_obj[OCE_MAX_EQ]; 871 872 /*Vlan Filtering related */ 873 eventhandler_tag vlan_attach; 874 eventhandler_tag vlan_detach; 875 uint16_t vlans_added; 876 uint8_t vlan_tag[MAX_VLANS]; 877 /*stats */ 878 OCE_DMA_MEM stats_mem; 879 struct oce_drv_stats oce_stats_info; 880 struct callout timer; 881 int8_t be3_native; 882 uint8_t hw_error; 883 uint16_t qnq_debug_event; 884 uint16_t qnqid; 885 uint32_t pvid; 886 uint32_t max_vlans; 887 uint32_t bmc_filt_mask; 888 889 void *rdma_context; 890 uint32_t rdma_flags; 891 struct oce_softc *next; 892 893 } OCE_SOFTC, *POCE_SOFTC; 894 895 #define OCE_RDMA_FLAG_SUPPORTED 0x00000001 896 897 /************************************************** 898 * BUS memory read/write macros 899 * BE3: accesses three BAR spaces (CFG, CSR, DB) 900 * Lancer: accesses one BAR space (CFG) 901 **************************************************/ 902 #define OCE_READ_CSR_MPU(sc, space, o) \ 903 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 904 (sc)->space##_bhandle,o)) \ 905 : (bus_space_read_4((sc)->devcfg_btag, \ 906 (sc)->devcfg_bhandle,o))) 907 #define OCE_READ_REG32(sc, space, o) \ 908 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 909 (sc)->space##_bhandle,o)) \ 910 : (bus_space_read_4((sc)->devcfg_btag, \ 911 (sc)->devcfg_bhandle,o))) 912 #define OCE_READ_REG16(sc, space, o) \ 913 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 914 (sc)->space##_bhandle,o)) \ 915 : (bus_space_read_2((sc)->devcfg_btag, \ 916 (sc)->devcfg_bhandle,o))) 917 #define OCE_READ_REG8(sc, space, o) \ 918 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 919 (sc)->space##_bhandle,o)) \ 920 : (bus_space_read_1((sc)->devcfg_btag, \ 921 (sc)->devcfg_bhandle,o))) 922 923 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \ 924 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 925 (sc)->space##_bhandle,o,v)) \ 926 : (bus_space_write_4((sc)->devcfg_btag, \ 927 (sc)->devcfg_bhandle,o,v))) 928 #define OCE_WRITE_REG32(sc, space, o, v) \ 929 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 930 (sc)->space##_bhandle,o,v)) \ 931 : (bus_space_write_4((sc)->devcfg_btag, \ 932 (sc)->devcfg_bhandle,o,v))) 933 #define OCE_WRITE_REG16(sc, space, o, v) \ 934 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \ 935 (sc)->space##_bhandle,o,v)) \ 936 : (bus_space_write_2((sc)->devcfg_btag, \ 937 (sc)->devcfg_bhandle,o,v))) 938 #define OCE_WRITE_REG8(sc, space, o, v) \ 939 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \ 940 (sc)->space##_bhandle,o,v)) \ 941 : (bus_space_write_1((sc)->devcfg_btag, \ 942 (sc)->devcfg_bhandle,o,v))) 943 944 void oce_rx_flush_lro(struct oce_rq *rq); 945 /*********************************************************** 946 * DMA memory functions 947 ***********************************************************/ 948 #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 949 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 950 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); 951 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error); 952 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring); 953 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc, 954 uint32_t q_len, uint32_t num_entries); 955 /************************************************************ 956 * oce_hw_xxx functions 957 ************************************************************/ 958 int oce_clear_rx_buf(struct oce_rq *rq); 959 int oce_hw_pci_alloc(POCE_SOFTC sc); 960 int oce_hw_init(POCE_SOFTC sc); 961 int oce_hw_start(POCE_SOFTC sc); 962 int oce_create_nw_interface(POCE_SOFTC sc); 963 int oce_pci_soft_reset(POCE_SOFTC sc); 964 int oce_hw_update_multicast(POCE_SOFTC sc); 965 void oce_delete_nw_interface(POCE_SOFTC sc); 966 void oce_hw_shutdown(POCE_SOFTC sc); 967 void oce_hw_intr_enable(POCE_SOFTC sc); 968 void oce_hw_intr_disable(POCE_SOFTC sc); 969 void oce_hw_pci_free(POCE_SOFTC sc); 970 971 /*********************************************************** 972 * oce_queue_xxx functions 973 ***********************************************************/ 974 int oce_queue_init_all(POCE_SOFTC sc); 975 int oce_start_rq(struct oce_rq *rq); 976 int oce_start_wq(struct oce_wq *wq); 977 int oce_start_mq(struct oce_mq *mq); 978 int oce_start_rx(POCE_SOFTC sc); 979 void oce_arm_eq(POCE_SOFTC sc, 980 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint); 981 void oce_queue_release_all(POCE_SOFTC sc); 982 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm); 983 void oce_drain_eq(struct oce_eq *eq); 984 void oce_drain_mq_cq(void *arg); 985 void oce_drain_rq_cq(struct oce_rq *rq); 986 void oce_drain_wq_cq(struct oce_wq *wq); 987 988 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list); 989 990 /*********************************************************** 991 * cleanup functions 992 ***********************************************************/ 993 void oce_stop_rx(POCE_SOFTC sc); 994 void oce_discard_rx_comp(struct oce_rq *rq, int num_frags); 995 void oce_rx_cq_clean(struct oce_rq *rq); 996 void oce_rx_cq_clean_hwlro(struct oce_rq *rq); 997 void oce_intr_free(POCE_SOFTC sc); 998 void oce_free_posted_rxbuf(struct oce_rq *rq); 999 #if defined(INET6) || defined(INET) 1000 void oce_free_lro(POCE_SOFTC sc); 1001 #endif 1002 1003 /************************************************************ 1004 * Mailbox functions 1005 ************************************************************/ 1006 int oce_fw_clean(POCE_SOFTC sc); 1007 int oce_wait_ready(POCE_SOFTC sc); 1008 int oce_reset_fun(POCE_SOFTC sc); 1009 int oce_mbox_init(POCE_SOFTC sc); 1010 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec); 1011 int oce_get_fw_version(POCE_SOFTC sc); 1012 int oce_first_mcc_cmd(POCE_SOFTC sc); 1013 1014 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm, 1015 uint8_t type, struct mac_address_format *mac); 1016 int oce_get_fw_config(POCE_SOFTC sc); 1017 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags, 1018 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 1019 int oce_if_del(POCE_SOFTC sc, uint32_t if_id); 1020 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id, 1021 struct normal_vlan *vtag_arr, uint8_t vtag_cnt, 1022 uint32_t untagged, uint32_t enable_promisc); 1023 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control); 1024 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss); 1025 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable); 1026 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl); 1027 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link); 1028 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1029 int oce_mbox_get_nic_stats_v1(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1030 int oce_mbox_get_nic_stats_v2(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1031 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1032 uint32_t reset_stats); 1033 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1034 uint32_t req_size, uint32_t reset_stats); 1035 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem); 1036 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size); 1037 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id); 1038 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1039 uint32_t if_id, uint32_t *pmac_id); 1040 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1041 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1042 uint64_t pattern); 1043 1044 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1045 uint8_t loopback_type, uint8_t enable); 1046 1047 int oce_mbox_check_native_mode(POCE_SOFTC sc); 1048 int oce_mbox_post(POCE_SOFTC sc, 1049 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx); 1050 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1051 POCE_DMA_MEM pdma_mem, uint32_t num_bytes); 1052 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1053 uint32_t data_offset,POCE_DMA_MEM pdma_mem, 1054 uint32_t *written_data, uint32_t *additional_status); 1055 1056 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1057 uint32_t offset, uint32_t optype); 1058 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info); 1059 int oce_mbox_create_rq(struct oce_rq *rq); 1060 int oce_mbox_create_wq(struct oce_wq *wq); 1061 int oce_mbox_create_eq(struct oce_eq *eq); 1062 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 1063 uint32_t is_eventable); 1064 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num); 1065 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1066 int num); 1067 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss); 1068 int oce_get_func_config(POCE_SOFTC sc); 1069 void mbx_common_req_hdr_init(struct mbx_hdr *hdr, 1070 uint8_t dom, 1071 uint8_t port, 1072 uint8_t subsys, 1073 uint8_t opcode, 1074 uint32_t timeout, uint32_t pyld_len, 1075 uint8_t version); 1076 1077 uint16_t oce_mq_handler(void *arg); 1078 1079 /************************************************************ 1080 * Transmit functions 1081 ************************************************************/ 1082 uint16_t oce_wq_handler(void *arg); 1083 void oce_start(struct ifnet *ifp); 1084 void oce_tx_task(void *arg, int npending); 1085 1086 /************************************************************ 1087 * Receive functions 1088 ************************************************************/ 1089 int oce_alloc_rx_bufs(struct oce_rq *rq, int count); 1090 uint16_t oce_rq_handler(void *arg); 1091 1092 /* Sysctl functions */ 1093 void oce_add_sysctls(POCE_SOFTC sc); 1094 void oce_refresh_queue_stats(POCE_SOFTC sc); 1095 int oce_refresh_nic_stats(POCE_SOFTC sc); 1096 int oce_stats_init(POCE_SOFTC sc); 1097 void oce_stats_free(POCE_SOFTC sc); 1098 1099 /* hw lro functions */ 1100 int oce_mbox_nic_query_lro_capabilities(POCE_SOFTC sc, uint32_t *lro_rq_cnt, uint32_t *lro_flags); 1101 int oce_mbox_nic_set_iface_lro_config(POCE_SOFTC sc, int enable); 1102 int oce_mbox_create_rq_v2(struct oce_rq *rq); 1103 1104 /* Capabilities */ 1105 #define OCE_MODCAP_RSS 1 1106 #define OCE_MAX_RSP_HANDLED 64 1107 extern uint32_t oce_max_rsp_handled; /* max responses */ 1108 extern uint32_t oce_rq_buf_size; 1109 1110 #define OCE_MAC_LOOPBACK 0x0 1111 #define OCE_PHY_LOOPBACK 0x1 1112 #define OCE_ONE_PORT_EXT_LOOPBACK 0x2 1113 #define OCE_NO_LOOPBACK 0xff 1114 1115 #undef IFM_40G_SR4 1116 #define IFM_40G_SR4 28 1117 1118 #define atomic_inc_32(x) atomic_add_32(x, 1) 1119 #define atomic_dec_32(x) atomic_subtract_32(x, 1) 1120 1121 #define LE_64(x) htole64(x) 1122 #define LE_32(x) htole32(x) 1123 #define LE_16(x) htole16(x) 1124 #define HOST_64(x) le64toh(x) 1125 #define HOST_32(x) le32toh(x) 1126 #define HOST_16(x) le16toh(x) 1127 #define DW_SWAP(x, l) 1128 #define IS_ALIGNED(x,a) ((x % a) == 0) 1129 #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 1130 #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 1131 1132 #define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 1133 #define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 1134 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) 1135 1136 #define OCE_LOG2(x) (oce_highbit(x)) 1137 static inline uint32_t oce_highbit(uint32_t x) 1138 { 1139 int i; 1140 int c; 1141 int b; 1142 1143 c = 0; 1144 b = 0; 1145 1146 for (i = 0; i < 32; i++) { 1147 if ((1 << i) & x) { 1148 c++; 1149 b = i; 1150 } 1151 } 1152 1153 if (c == 1) 1154 return b; 1155 1156 return 0; 1157 } 1158 1159 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc) 1160 { 1161 if (IS_BE(sc)) 1162 return MPU_EP_SEMAPHORE_BE3; 1163 else if (IS_SH(sc)) 1164 return MPU_EP_SEMAPHORE_SH; 1165 else 1166 return MPU_EP_SEMAPHORE_XE201; 1167 } 1168 1169 #define TRANSCEIVER_DATA_NUM_ELE 64 1170 #define TRANSCEIVER_DATA_SIZE 256 1171 #define TRANSCEIVER_A0_SIZE 128 1172 #define TRANSCEIVER_A2_SIZE 128 1173 #define PAGE_NUM_A0 0xa0 1174 #define PAGE_NUM_A2 0xa2 1175 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\ 1176 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE))) 1177 extern uint8_t sfp_vpd_dump_buffer[TRANSCEIVER_DATA_SIZE]; 1178 1179 struct oce_rdma_info; 1180 extern struct oce_rdma_if *oce_rdma_if; 1181 1182 /* OS2BMC related */ 1183 1184 #define DHCP_CLIENT_PORT 68 1185 #define DHCP_SERVER_PORT 67 1186 #define NET_BIOS_PORT1 137 1187 #define NET_BIOS_PORT2 138 1188 #define DHCPV6_RAS_PORT 547 1189 1190 #define BMC_FILT_BROADCAST_ARP ((uint32_t)(1)) 1191 #define BMC_FILT_BROADCAST_DHCP_CLIENT ((uint32_t)(1 << 1)) 1192 #define BMC_FILT_BROADCAST_DHCP_SERVER ((uint32_t)(1 << 2)) 1193 #define BMC_FILT_BROADCAST_NET_BIOS ((uint32_t)(1 << 3)) 1194 #define BMC_FILT_BROADCAST ((uint32_t)(1 << 4)) 1195 #define BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER ((uint32_t)(1 << 5)) 1196 #define BMC_FILT_MULTICAST_IPV6_RA ((uint32_t)(1 << 6)) 1197 #define BMC_FILT_MULTICAST_IPV6_RAS ((uint32_t)(1 << 7)) 1198 #define BMC_FILT_MULTICAST ((uint32_t)(1 << 8)) 1199 1200 #define ND_ROUTER_ADVERT 134 1201 #define ND_NEIGHBOR_ADVERT 136 1202 1203 #define is_mc_allowed_on_bmc(sc, eh) \ 1204 (!is_multicast_filt_enabled(sc) && \ 1205 ETHER_IS_MULTICAST(eh->ether_dhost) && \ 1206 !ETHER_IS_BROADCAST(eh->ether_dhost)) 1207 1208 #define is_bc_allowed_on_bmc(sc, eh) \ 1209 (!is_broadcast_filt_enabled(sc) && \ 1210 ETHER_IS_BROADCAST(eh->ether_dhost)) 1211 1212 #define is_arp_allowed_on_bmc(sc, et) \ 1213 (is_arp(et) && is_arp_filt_enabled(sc)) 1214 1215 #define is_arp(et) (et == ETHERTYPE_ARP) 1216 1217 #define is_arp_filt_enabled(sc) \ 1218 (sc->bmc_filt_mask & (BMC_FILT_BROADCAST_ARP)) 1219 1220 #define is_dhcp_client_filt_enabled(sc) \ 1221 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_CLIENT) 1222 1223 #define is_dhcp_srvr_filt_enabled(sc) \ 1224 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_DHCP_SERVER) 1225 1226 #define is_nbios_filt_enabled(sc) \ 1227 (sc->bmc_filt_mask & BMC_FILT_BROADCAST_NET_BIOS) 1228 1229 #define is_ipv6_na_filt_enabled(sc) \ 1230 (sc->bmc_filt_mask & \ 1231 BMC_FILT_MULTICAST_IPV6_NEIGH_ADVER) 1232 1233 #define is_ipv6_ra_filt_enabled(sc) \ 1234 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RA) 1235 1236 #define is_ipv6_ras_filt_enabled(sc) \ 1237 (sc->bmc_filt_mask & BMC_FILT_MULTICAST_IPV6_RAS) 1238 1239 #define is_broadcast_filt_enabled(sc) \ 1240 (sc->bmc_filt_mask & BMC_FILT_BROADCAST) 1241 1242 #define is_multicast_filt_enabled(sc) \ 1243 (sc->bmc_filt_mask & BMC_FILT_MULTICAST) 1244 1245 #define is_os2bmc_enabled(sc) (sc->flags & OCE_FLAGS_OS2BMC) 1246 1247 #define LRO_FLAGS_HASH_MODE 0x00000001 1248 #define LRO_FLAGS_RSS_MODE 0x00000004 1249 #define LRO_FLAGS_CLSC_IPV4 0x00000010 1250 #define LRO_FLAGS_CLSC_IPV6 0x00000020 1251 #define NIC_RQ_FLAGS_RSS 0x0001 1252 #define NIC_RQ_FLAGS_LRO 0x0020 1253