1 /*- 2 * Copyright (C) 2013 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Emulex Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39 /* $FreeBSD$ */ 40 41 #include <sys/param.h> 42 #include <sys/endian.h> 43 #include <sys/eventhandler.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/mbuf.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sockopt.h> 53 #include <sys/queue.h> 54 #include <sys/taskqueue.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/sysctl.h> 58 #include <sys/random.h> 59 #include <sys/firmware.h> 60 #include <sys/systm.h> 61 #include <sys/proc.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 66 #include <net/bpf.h> 67 #include <net/ethernet.h> 68 #include <net/if.h> 69 #include <net/if_var.h> 70 #include <net/if_types.h> 71 #include <net/if_media.h> 72 #include <net/if_vlan_var.h> 73 #include <net/if_dl.h> 74 75 #include <netinet/in.h> 76 #include <netinet/in_systm.h> 77 #include <netinet/in_var.h> 78 #include <netinet/if_ether.h> 79 #include <netinet/ip.h> 80 #include <netinet/ip6.h> 81 #include <netinet6/in6_var.h> 82 #include <netinet6/ip6_mroute.h> 83 84 #include <netinet/udp.h> 85 #include <netinet/tcp.h> 86 #include <netinet/sctp.h> 87 #include <netinet/tcp_lro.h> 88 89 #include <machine/bus.h> 90 91 #include "oce_hw.h" 92 93 /* OCE device driver module component revision informaiton */ 94 #define COMPONENT_REVISION "10.0.664.0" 95 96 /* OCE devices supported by this driver */ 97 #define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 98 #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 99 #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 100 #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 101 #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 102 #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ 103 #define PCI_PRODUCT_SH 0x0720 /* Skyhawk network adapter */ 104 105 #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 106 (sc->flags & OCE_FLAGS_BE2))? 1:0) 107 #define IS_BE3(sc) (sc->flags & OCE_FLAGS_BE3) 108 #define IS_BE2(sc) (sc->flags & OCE_FLAGS_BE2) 109 #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 110 #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) 111 #define IS_SH(sc) ((sc->flags & OCE_FLAGS_SH) ? 1 : 0) 112 113 #define is_be_mode_mc(sc) ((sc->function_mode & FNM_FLEX10_MODE) || \ 114 (sc->function_mode & FNM_UMC_MODE) || \ 115 (sc->function_mode & FNM_VNIC_MODE)) 116 #define OCE_FUNCTION_CAPS_SUPER_NIC 0x40 117 #define IS_PROFILE_SUPER_NIC(sc) (sc->function_caps & OCE_FUNCTION_CAPS_SUPER_NIC) 118 119 120 /* proportion Service Level Interface queues */ 121 #define OCE_MAX_UNITS 2 122 #define OCE_MAX_PPORT OCE_MAX_UNITS 123 #define OCE_MAX_VPORT OCE_MAX_UNITS 124 125 extern int mp_ncpus; /* system's total active cpu cores */ 126 #define OCE_NCPUS mp_ncpus 127 128 /* This should be powers of 2. Like 2,4,8 & 16 */ 129 #define OCE_MAX_RSS 8 130 #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ 131 #define is_rss_enabled(sc) ((sc->function_caps & FNC_RSS) && !is_be_mode_mc(sc)) 132 133 #define OCE_MIN_RQ 1 134 #define OCE_MIN_WQ 1 135 136 #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 137 #define OCE_MAX_WQ 8 138 139 #define OCE_MAX_EQ 32 140 #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */ 141 #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */ 142 143 #define OCE_DEFAULT_WQ_EQD 16 144 #define OCE_MAX_PACKET_Q 16 145 #define OCE_RQ_BUF_SIZE 2048 146 #define OCE_LSO_MAX_SIZE (64 * 1024) 147 #define LONG_TIMEOUT 30 148 #define OCE_MAX_JUMBO_FRAME_SIZE 9018 149 #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \ 150 ETHER_VLAN_ENCAP_LEN - \ 151 ETHER_HDR_LEN) 152 153 #define OCE_MAX_TX_ELEMENTS 29 154 #define OCE_MAX_TX_DESC 1024 155 #define OCE_MAX_TX_SIZE 65535 156 #define OCE_MAX_RX_SIZE 4096 157 #define OCE_MAX_RQ_POSTS 255 158 #define OCE_DEFAULT_PROMISCUOUS 0 159 160 161 #define RSS_ENABLE_IPV4 0x1 162 #define RSS_ENABLE_TCP_IPV4 0x2 163 #define RSS_ENABLE_IPV6 0x4 164 #define RSS_ENABLE_TCP_IPV6 0x8 165 166 #define INDIRECTION_TABLE_ENTRIES 128 167 168 /* flow control definitions */ 169 #define OCE_FC_NONE 0x00000000 170 #define OCE_FC_TX 0x00000001 171 #define OCE_FC_RX 0x00000002 172 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 173 174 175 /* Interface capabilities to give device when creating interface */ 176 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 177 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 178 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 179 MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS | \ 180 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 181 MBX_RX_IFACE_FLAGS_RSS | \ 182 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 183 184 /* Interface capabilities to enable by default (others set dynamically) */ 185 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 186 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 187 MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 188 189 #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 190 #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 191 IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \ 192 IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU) 193 #define OCE_IF_HWASSIST_NONE 0 194 #define OCE_IF_CAPABILITIES_NONE 0 195 196 197 #define ETH_ADDR_LEN 6 198 #define MAX_VLANFILTER_SIZE 64 199 #define MAX_VLANS 4096 200 201 #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 202 #define BSWAP_8(x) ((x) & 0xff) 203 #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8)) 204 #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \ 205 BSWAP_16((x) >> 16)) 206 #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 207 BSWAP_32((x) >> 32)) 208 209 #define for_all_wq_queues(sc, wq, i) \ 210 for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 211 #define for_all_rq_queues(sc, rq, i) \ 212 for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) 213 #define for_all_rss_queues(sc, rq, i) \ 214 for (i = 0, rq = sc->rq[i + 1]; i < (sc->nrqs - 1); \ 215 i++, rq = sc->rq[i + 1]) 216 #define for_all_evnt_queues(sc, eq, i) \ 217 for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 218 #define for_all_cq_queues(sc, cq, i) \ 219 for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 220 221 222 /* Flash specific */ 223 #define IOCTL_COOKIE "SERVERENGINES CORP" 224 #define MAX_FLASH_COMP 32 225 226 #define IMG_ISCSI 160 227 #define IMG_REDBOOT 224 228 #define IMG_BIOS 34 229 #define IMG_PXEBIOS 32 230 #define IMG_FCOEBIOS 33 231 #define IMG_ISCSI_BAK 176 232 #define IMG_FCOE 162 233 #define IMG_FCOE_BAK 178 234 #define IMG_NCSI 16 235 #define IMG_PHY 192 236 #define FLASHROM_OPER_FLASH 1 237 #define FLASHROM_OPER_SAVE 2 238 #define FLASHROM_OPER_REPORT 4 239 #define FLASHROM_OPER_FLASH_PHY 9 240 #define FLASHROM_OPER_SAVE_PHY 10 241 #define TN_8022 13 242 243 enum { 244 PHY_TYPE_CX4_10GB = 0, 245 PHY_TYPE_XFP_10GB, 246 PHY_TYPE_SFP_1GB, 247 PHY_TYPE_SFP_PLUS_10GB, 248 PHY_TYPE_KR_10GB, 249 PHY_TYPE_KX4_10GB, 250 PHY_TYPE_BASET_10GB, 251 PHY_TYPE_BASET_1GB, 252 PHY_TYPE_BASEX_1GB, 253 PHY_TYPE_SGMII, 254 PHY_TYPE_DISABLED = 255 255 }; 256 257 /** 258 * @brief Define and hold all necessary info for a single interrupt 259 */ 260 #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */ 261 #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */ 262 263 typedef struct oce_intr_info { 264 void *tag; /* cookie returned by bus_setup_intr */ 265 struct resource *intr_res; /* PCI resource container */ 266 int irq_rr; /* resource id for the interrupt */ 267 struct oce_softc *sc; /* pointer to the parent soft c */ 268 struct oce_eq *eq; /* pointer to the connected EQ */ 269 struct taskqueue *tq; /* Associated task queue */ 270 struct task task; /* task queue task */ 271 char task_name[32]; /* task name */ 272 int vector; /* interrupt vector number */ 273 } OCE_INTR_INFO, *POCE_INTR_INFO; 274 275 276 /* Ring related */ 277 #define GET_Q_NEXT(_START, _STEP, _END) \ 278 (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ 279 : (((_START) + (_STEP)) - (_END))) 280 281 #define DBUF_PA(obj) ((obj)->addr) 282 #define DBUF_VA(obj) ((obj)->ptr) 283 #define DBUF_TAG(obj) ((obj)->tag) 284 #define DBUF_MAP(obj) ((obj)->map) 285 #define DBUF_SYNC(obj, flags) \ 286 (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags)) 287 288 #define RING_NUM_PENDING(ring) ring->num_used 289 #define RING_FULL(ring) (ring->num_used == ring->num_items) 290 #define RING_EMPTY(ring) (ring->num_used == 0) 291 #define RING_NUM_FREE(ring) \ 292 (uint32_t)(ring->num_items - ring->num_used) 293 #define RING_GET(ring, n) \ 294 ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items) 295 #define RING_PUT(ring, n) \ 296 ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items) 297 298 #define RING_GET_CONSUMER_ITEM_VA(ring, type) \ 299 (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx) 300 #define RING_GET_CONSUMER_ITEM_PA(ring, type) \ 301 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx) 302 #define RING_GET_PRODUCER_ITEM_VA(ring, type) \ 303 (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx) 304 #define RING_GET_PRODUCER_ITEM_PA(ring, type) \ 305 (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx) 306 307 #define OCE_DMAPTR(o, c) ((c *)(o)->ptr) 308 309 struct oce_packet_desc { 310 struct mbuf *mbuf; 311 bus_dmamap_t map; 312 int nsegs; 313 uint32_t wqe_idx; 314 }; 315 316 typedef struct oce_dma_mem { 317 bus_dma_tag_t tag; 318 bus_dmamap_t map; 319 void *ptr; 320 bus_addr_t paddr; 321 } OCE_DMA_MEM, *POCE_DMA_MEM; 322 323 typedef struct oce_ring_buffer_s { 324 uint16_t cidx; /* Get ptr */ 325 uint16_t pidx; /* Put Ptr */ 326 size_t item_size; 327 size_t num_items; 328 uint32_t num_used; 329 OCE_DMA_MEM dma; 330 } oce_ring_buffer_t; 331 332 /* Stats */ 333 #define OCE_UNICAST_PACKET 0 334 #define OCE_MULTICAST_PACKET 1 335 #define OCE_BROADCAST_PACKET 2 336 #define OCE_RSVD_PACKET 3 337 338 struct oce_rx_stats { 339 /* Total Receive Stats*/ 340 uint64_t t_rx_pkts; 341 uint64_t t_rx_bytes; 342 uint32_t t_rx_frags; 343 uint32_t t_rx_mcast_pkts; 344 uint32_t t_rx_ucast_pkts; 345 uint32_t t_rxcp_errs; 346 }; 347 struct oce_tx_stats { 348 /*Total Transmit Stats */ 349 uint64_t t_tx_pkts; 350 uint64_t t_tx_bytes; 351 uint32_t t_tx_reqs; 352 uint32_t t_tx_stops; 353 uint32_t t_tx_wrbs; 354 uint32_t t_tx_compl; 355 uint32_t t_ipv6_ext_hdr_tx_drop; 356 }; 357 358 struct oce_be_stats { 359 uint8_t be_on_die_temperature; 360 uint32_t be_tx_events; 361 uint32_t eth_red_drops; 362 uint32_t rx_drops_no_pbuf; 363 uint32_t rx_drops_no_txpb; 364 uint32_t rx_drops_no_erx_descr; 365 uint32_t rx_drops_no_tpre_descr; 366 uint32_t rx_drops_too_many_frags; 367 uint32_t rx_drops_invalid_ring; 368 uint32_t forwarded_packets; 369 uint32_t rx_drops_mtu; 370 uint32_t rx_crc_errors; 371 uint32_t rx_alignment_symbol_errors; 372 uint32_t rx_pause_frames; 373 uint32_t rx_priority_pause_frames; 374 uint32_t rx_control_frames; 375 uint32_t rx_in_range_errors; 376 uint32_t rx_out_range_errors; 377 uint32_t rx_frame_too_long; 378 uint32_t rx_address_match_errors; 379 uint32_t rx_dropped_too_small; 380 uint32_t rx_dropped_too_short; 381 uint32_t rx_dropped_header_too_small; 382 uint32_t rx_dropped_tcp_length; 383 uint32_t rx_dropped_runt; 384 uint32_t rx_ip_checksum_errs; 385 uint32_t rx_tcp_checksum_errs; 386 uint32_t rx_udp_checksum_errs; 387 uint32_t rx_switched_unicast_packets; 388 uint32_t rx_switched_multicast_packets; 389 uint32_t rx_switched_broadcast_packets; 390 uint32_t tx_pauseframes; 391 uint32_t tx_priority_pauseframes; 392 uint32_t tx_controlframes; 393 uint32_t rxpp_fifo_overflow_drop; 394 uint32_t rx_input_fifo_overflow_drop; 395 uint32_t pmem_fifo_overflow_drop; 396 uint32_t jabber_events; 397 }; 398 399 struct oce_xe201_stats { 400 uint64_t tx_pkts; 401 uint64_t tx_unicast_pkts; 402 uint64_t tx_multicast_pkts; 403 uint64_t tx_broadcast_pkts; 404 uint64_t tx_bytes; 405 uint64_t tx_unicast_bytes; 406 uint64_t tx_multicast_bytes; 407 uint64_t tx_broadcast_bytes; 408 uint64_t tx_discards; 409 uint64_t tx_errors; 410 uint64_t tx_pause_frames; 411 uint64_t tx_pause_on_frames; 412 uint64_t tx_pause_off_frames; 413 uint64_t tx_internal_mac_errors; 414 uint64_t tx_control_frames; 415 uint64_t tx_pkts_64_bytes; 416 uint64_t tx_pkts_65_to_127_bytes; 417 uint64_t tx_pkts_128_to_255_bytes; 418 uint64_t tx_pkts_256_to_511_bytes; 419 uint64_t tx_pkts_512_to_1023_bytes; 420 uint64_t tx_pkts_1024_to_1518_bytes; 421 uint64_t tx_pkts_1519_to_2047_bytes; 422 uint64_t tx_pkts_2048_to_4095_bytes; 423 uint64_t tx_pkts_4096_to_8191_bytes; 424 uint64_t tx_pkts_8192_to_9216_bytes; 425 uint64_t tx_lso_pkts; 426 uint64_t rx_pkts; 427 uint64_t rx_unicast_pkts; 428 uint64_t rx_multicast_pkts; 429 uint64_t rx_broadcast_pkts; 430 uint64_t rx_bytes; 431 uint64_t rx_unicast_bytes; 432 uint64_t rx_multicast_bytes; 433 uint64_t rx_broadcast_bytes; 434 uint32_t rx_unknown_protos; 435 uint64_t rx_discards; 436 uint64_t rx_errors; 437 uint64_t rx_crc_errors; 438 uint64_t rx_alignment_errors; 439 uint64_t rx_symbol_errors; 440 uint64_t rx_pause_frames; 441 uint64_t rx_pause_on_frames; 442 uint64_t rx_pause_off_frames; 443 uint64_t rx_frames_too_long; 444 uint64_t rx_internal_mac_errors; 445 uint32_t rx_undersize_pkts; 446 uint32_t rx_oversize_pkts; 447 uint32_t rx_fragment_pkts; 448 uint32_t rx_jabbers; 449 uint64_t rx_control_frames; 450 uint64_t rx_control_frames_unknown_opcode; 451 uint32_t rx_in_range_errors; 452 uint32_t rx_out_of_range_errors; 453 uint32_t rx_address_match_errors; 454 uint32_t rx_vlan_mismatch_errors; 455 uint32_t rx_dropped_too_small; 456 uint32_t rx_dropped_too_short; 457 uint32_t rx_dropped_header_too_small; 458 uint32_t rx_dropped_invalid_tcp_length; 459 uint32_t rx_dropped_runt; 460 uint32_t rx_ip_checksum_errors; 461 uint32_t rx_tcp_checksum_errors; 462 uint32_t rx_udp_checksum_errors; 463 uint32_t rx_non_rss_pkts; 464 uint64_t rx_ipv4_pkts; 465 uint64_t rx_ipv6_pkts; 466 uint64_t rx_ipv4_bytes; 467 uint64_t rx_ipv6_bytes; 468 uint64_t rx_nic_pkts; 469 uint64_t rx_tcp_pkts; 470 uint64_t rx_iscsi_pkts; 471 uint64_t rx_management_pkts; 472 uint64_t rx_switched_unicast_pkts; 473 uint64_t rx_switched_multicast_pkts; 474 uint64_t rx_switched_broadcast_pkts; 475 uint64_t num_forwards; 476 uint32_t rx_fifo_overflow; 477 uint32_t rx_input_fifo_overflow; 478 uint64_t rx_drops_too_many_frags; 479 uint32_t rx_drops_invalid_queue; 480 uint64_t rx_drops_mtu; 481 uint64_t rx_pkts_64_bytes; 482 uint64_t rx_pkts_65_to_127_bytes; 483 uint64_t rx_pkts_128_to_255_bytes; 484 uint64_t rx_pkts_256_to_511_bytes; 485 uint64_t rx_pkts_512_to_1023_bytes; 486 uint64_t rx_pkts_1024_to_1518_bytes; 487 uint64_t rx_pkts_1519_to_2047_bytes; 488 uint64_t rx_pkts_2048_to_4095_bytes; 489 uint64_t rx_pkts_4096_to_8191_bytes; 490 uint64_t rx_pkts_8192_to_9216_bytes; 491 }; 492 493 struct oce_drv_stats { 494 struct oce_rx_stats rx; 495 struct oce_tx_stats tx; 496 union { 497 struct oce_be_stats be; 498 struct oce_xe201_stats xe201; 499 } u0; 500 }; 501 502 #define INTR_RATE_HWM 15000 503 #define INTR_RATE_LWM 10000 504 505 #define OCE_MAX_EQD 128u 506 #define OCE_MIN_EQD 50u 507 508 struct oce_set_eqd { 509 uint32_t eq_id; 510 uint32_t phase; 511 uint32_t delay_multiplier; 512 }; 513 514 struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 515 boolean_t enable; 516 uint32_t min_eqd; /* in usecs */ 517 uint32_t max_eqd; /* in usecs */ 518 uint32_t cur_eqd; /* in usecs */ 519 uint32_t et_eqd; /* configured value when aic is off */ 520 uint64_t ticks; 521 uint64_t intr_prev; 522 }; 523 524 #define MAX_LOCK_DESC_LEN 32 525 struct oce_lock { 526 struct mtx mutex; 527 char name[MAX_LOCK_DESC_LEN+1]; 528 }; 529 #define OCE_LOCK struct oce_lock 530 531 #define LOCK_CREATE(lock, desc) { \ 532 strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \ 533 (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \ 534 mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \ 535 } 536 #define LOCK_DESTROY(lock) \ 537 if (mtx_initialized(&(lock)->mutex))\ 538 mtx_destroy(&(lock)->mutex) 539 #define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex) 540 #define LOCK(lock) mtx_lock(&(lock)->mutex) 541 #define LOCKED(lock) mtx_owned(&(lock)->mutex) 542 #define UNLOCK(lock) mtx_unlock(&(lock)->mutex) 543 544 #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) 545 #define MBX_READY_TIMEOUT (1 * 1000 * 1000) 546 #define DEFAULT_DRAIN_TIME 200 547 #define MBX_TIMEOUT_SEC 5 548 #define STAT_TIMEOUT 2000000 549 550 /* size of the packet descriptor array in a transmit queue */ 551 #define OCE_TX_RING_SIZE 2048 552 #define OCE_RX_RING_SIZE 1024 553 #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2) 554 #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE) 555 556 struct oce_dev; 557 558 enum eq_len { 559 EQ_LEN_256 = 256, 560 EQ_LEN_512 = 512, 561 EQ_LEN_1024 = 1024, 562 EQ_LEN_2048 = 2048, 563 EQ_LEN_4096 = 4096 564 }; 565 566 enum eqe_size { 567 EQE_SIZE_4 = 4, 568 EQE_SIZE_16 = 16 569 }; 570 571 enum qtype { 572 QTYPE_EQ, 573 QTYPE_MQ, 574 QTYPE_WQ, 575 QTYPE_RQ, 576 QTYPE_CQ, 577 QTYPE_RSS 578 }; 579 580 typedef enum qstate_e { 581 QDELETED = 0x0, 582 QCREATED = 0x1 583 } qstate_t; 584 585 struct eq_config { 586 enum eq_len q_len; 587 enum eqe_size item_size; 588 uint32_t q_vector_num; 589 uint8_t min_eqd; 590 uint8_t max_eqd; 591 uint8_t cur_eqd; 592 uint8_t pad; 593 }; 594 595 struct oce_eq { 596 uint32_t eq_id; 597 void *parent; 598 void *cb_context; 599 oce_ring_buffer_t *ring; 600 uint32_t ref_count; 601 qstate_t qstate; 602 struct oce_cq *cq[OCE_MAX_CQ_EQ]; 603 int cq_valid; 604 struct eq_config eq_cfg; 605 int vector; 606 uint64_t intr; 607 }; 608 609 enum cq_len { 610 CQ_LEN_256 = 256, 611 CQ_LEN_512 = 512, 612 CQ_LEN_1024 = 1024 613 }; 614 615 struct cq_config { 616 enum cq_len q_len; 617 uint32_t item_size; 618 boolean_t is_eventable; 619 boolean_t sol_eventable; 620 boolean_t nodelay; 621 uint16_t dma_coalescing; 622 }; 623 624 typedef uint16_t(*cq_handler_t) (void *arg1); 625 626 struct oce_cq { 627 uint32_t cq_id; 628 void *parent; 629 struct oce_eq *eq; 630 cq_handler_t cq_handler; 631 void *cb_arg; 632 oce_ring_buffer_t *ring; 633 qstate_t qstate; 634 struct cq_config cq_cfg; 635 uint32_t ref_count; 636 }; 637 638 639 struct mq_config { 640 uint32_t eqd; 641 uint8_t q_len; 642 uint8_t pad[3]; 643 }; 644 645 646 struct oce_mq { 647 void *parent; 648 oce_ring_buffer_t *ring; 649 uint32_t mq_id; 650 struct oce_cq *cq; 651 struct oce_cq *async_cq; 652 uint32_t mq_free; 653 qstate_t qstate; 654 struct mq_config cfg; 655 }; 656 657 struct oce_mbx_ctx { 658 struct oce_mbx *mbx; 659 void (*cb) (void *ctx); 660 void *cb_ctx; 661 }; 662 663 struct wq_config { 664 uint8_t wq_type; 665 uint16_t buf_size; 666 uint8_t pad[1]; 667 uint32_t q_len; 668 uint16_t pd_id; 669 uint16_t pci_fn_num; 670 uint32_t eqd; /* interrupt delay */ 671 uint32_t nbufs; 672 uint32_t nhdl; 673 }; 674 675 struct oce_tx_queue_stats { 676 uint64_t tx_pkts; 677 uint64_t tx_bytes; 678 uint32_t tx_reqs; 679 uint32_t tx_stops; /* number of times TX Q was stopped */ 680 uint32_t tx_wrbs; 681 uint32_t tx_compl; 682 uint32_t tx_rate; 683 uint32_t ipv6_ext_hdr_tx_drop; 684 }; 685 686 struct oce_wq { 687 OCE_LOCK tx_lock; 688 void *parent; 689 oce_ring_buffer_t *ring; 690 struct oce_cq *cq; 691 bus_dma_tag_t tag; 692 struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; 693 uint32_t pkt_desc_tail; 694 uint32_t pkt_desc_head; 695 uint32_t wqm_used; 696 boolean_t resched; 697 uint32_t wq_free; 698 uint32_t tx_deferd; 699 uint32_t pkt_drops; 700 qstate_t qstate; 701 uint16_t wq_id; 702 struct wq_config cfg; 703 int queue_index; 704 struct oce_tx_queue_stats tx_stats; 705 struct buf_ring *br; 706 struct task txtask; 707 uint32_t db_offset; 708 }; 709 710 struct rq_config { 711 uint32_t q_len; 712 uint32_t frag_size; 713 uint32_t mtu; 714 uint32_t if_id; 715 uint32_t is_rss_queue; 716 uint32_t eqd; 717 uint32_t nbufs; 718 }; 719 720 struct oce_rx_queue_stats { 721 uint32_t rx_post_fail; 722 uint32_t rx_ucast_pkts; 723 uint32_t rx_compl; 724 uint64_t rx_bytes; 725 uint64_t rx_bytes_prev; 726 uint64_t rx_pkts; 727 uint32_t rx_rate; 728 uint32_t rx_mcast_pkts; 729 uint32_t rxcp_err; 730 uint32_t rx_frags; 731 uint32_t prev_rx_frags; 732 uint32_t rx_fps; 733 }; 734 735 736 struct oce_rq { 737 struct rq_config cfg; 738 uint32_t rq_id; 739 int queue_index; 740 uint32_t rss_cpuid; 741 void *parent; 742 oce_ring_buffer_t *ring; 743 struct oce_cq *cq; 744 void *pad1; 745 bus_dma_tag_t tag; 746 struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE]; 747 uint32_t packets_in; 748 uint32_t packets_out; 749 uint32_t pending; 750 #ifdef notdef 751 struct mbuf *head; 752 struct mbuf *tail; 753 int fragsleft; 754 #endif 755 qstate_t qstate; 756 OCE_LOCK rx_lock; 757 struct oce_rx_queue_stats rx_stats; 758 struct lro_ctrl lro; 759 int lro_pkts_queued; 760 761 }; 762 763 struct link_status { 764 uint8_t phys_port_speed; 765 uint8_t logical_link_status; 766 uint16_t qos_link_speed; 767 }; 768 769 770 771 #define OCE_FLAGS_PCIX 0x00000001 772 #define OCE_FLAGS_PCIE 0x00000002 773 #define OCE_FLAGS_MSI_CAPABLE 0x00000004 774 #define OCE_FLAGS_MSIX_CAPABLE 0x00000008 775 #define OCE_FLAGS_USING_MSI 0x00000010 776 #define OCE_FLAGS_USING_MSIX 0x00000020 777 #define OCE_FLAGS_FUNCRESET_RQD 0x00000040 778 #define OCE_FLAGS_VIRTUAL_PORT 0x00000080 779 #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 780 #define OCE_FLAGS_BE3 0x00000200 781 #define OCE_FLAGS_XE201 0x00000400 782 #define OCE_FLAGS_BE2 0x00000800 783 #define OCE_FLAGS_SH 0x00001000 784 785 #define OCE_DEV_BE2_CFG_BAR 1 786 #define OCE_DEV_CFG_BAR 0 787 #define OCE_PCI_CSR_BAR 2 788 #define OCE_PCI_DB_BAR 4 789 790 typedef struct oce_softc { 791 device_t dev; 792 OCE_LOCK dev_lock; 793 794 uint32_t flags; 795 796 uint32_t pcie_link_speed; 797 uint32_t pcie_link_width; 798 799 uint8_t fn; /* PCI function number */ 800 801 struct resource *devcfg_res; 802 bus_space_tag_t devcfg_btag; 803 bus_space_handle_t devcfg_bhandle; 804 void *devcfg_vhandle; 805 806 struct resource *csr_res; 807 bus_space_tag_t csr_btag; 808 bus_space_handle_t csr_bhandle; 809 void *csr_vhandle; 810 811 struct resource *db_res; 812 bus_space_tag_t db_btag; 813 bus_space_handle_t db_bhandle; 814 void *db_vhandle; 815 816 OCE_INTR_INFO intrs[OCE_MAX_EQ]; 817 int intr_count; 818 819 struct ifnet *ifp; 820 821 struct ifmedia media; 822 uint8_t link_status; 823 uint8_t link_speed; 824 uint8_t duplex; 825 uint32_t qos_link_speed; 826 uint32_t speed; 827 828 char fw_version[32]; 829 struct mac_address_format macaddr; 830 831 OCE_DMA_MEM bsmbx; 832 OCE_LOCK bmbx_lock; 833 834 uint32_t config_number; 835 uint32_t asic_revision; 836 uint32_t port_id; 837 uint32_t function_mode; 838 uint32_t function_caps; 839 uint32_t max_tx_rings; 840 uint32_t max_rx_rings; 841 842 struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */ 843 struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */ 844 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 845 struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 846 struct oce_mq *mq; /* Mailbox queue */ 847 848 uint32_t neqs; 849 uint32_t ncqs; 850 uint32_t nrqs; 851 uint32_t nwqs; 852 uint32_t nrssqs; 853 854 uint32_t tx_ring_size; 855 uint32_t rx_ring_size; 856 uint32_t rq_frag_size; 857 858 uint32_t if_id; /* interface ID */ 859 uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 860 uint32_t pmac_id; /* PMAC id */ 861 862 uint32_t if_cap_flags; 863 864 uint32_t flow_control; 865 uint8_t promisc; 866 867 struct oce_aic_obj aic_obj[OCE_MAX_EQ]; 868 869 /*Vlan Filtering related */ 870 eventhandler_tag vlan_attach; 871 eventhandler_tag vlan_detach; 872 uint16_t vlans_added; 873 uint8_t vlan_tag[MAX_VLANS]; 874 /*stats */ 875 OCE_DMA_MEM stats_mem; 876 struct oce_drv_stats oce_stats_info; 877 struct callout timer; 878 int8_t be3_native; 879 uint8_t hw_error; 880 uint16_t qnq_debug_event; 881 uint16_t qnqid; 882 uint32_t pvid; 883 uint32_t max_vlans; 884 885 } OCE_SOFTC, *POCE_SOFTC; 886 887 888 889 /************************************************** 890 * BUS memory read/write macros 891 * BE3: accesses three BAR spaces (CFG, CSR, DB) 892 * Lancer: accesses one BAR space (CFG) 893 **************************************************/ 894 #define OCE_READ_CSR_MPU(sc, space, o) \ 895 ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 896 (sc)->space##_bhandle,o)) \ 897 : (bus_space_read_4((sc)->devcfg_btag, \ 898 (sc)->devcfg_bhandle,o))) 899 #define OCE_READ_REG32(sc, space, o) \ 900 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 901 (sc)->space##_bhandle,o)) \ 902 : (bus_space_read_4((sc)->devcfg_btag, \ 903 (sc)->devcfg_bhandle,o))) 904 #define OCE_READ_REG16(sc, space, o) \ 905 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 906 (sc)->space##_bhandle,o)) \ 907 : (bus_space_read_2((sc)->devcfg_btag, \ 908 (sc)->devcfg_bhandle,o))) 909 #define OCE_READ_REG8(sc, space, o) \ 910 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 911 (sc)->space##_bhandle,o)) \ 912 : (bus_space_read_1((sc)->devcfg_btag, \ 913 (sc)->devcfg_bhandle,o))) 914 915 #define OCE_WRITE_CSR_MPU(sc, space, o, v) \ 916 ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 917 (sc)->space##_bhandle,o,v)) \ 918 : (bus_space_write_4((sc)->devcfg_btag, \ 919 (sc)->devcfg_bhandle,o,v))) 920 #define OCE_WRITE_REG32(sc, space, o, v) \ 921 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 922 (sc)->space##_bhandle,o,v)) \ 923 : (bus_space_write_4((sc)->devcfg_btag, \ 924 (sc)->devcfg_bhandle,o,v))) 925 #define OCE_WRITE_REG16(sc, space, o, v) \ 926 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_2((sc)->space##_btag, \ 927 (sc)->space##_bhandle,o,v)) \ 928 : (bus_space_write_2((sc)->devcfg_btag, \ 929 (sc)->devcfg_bhandle,o,v))) 930 #define OCE_WRITE_REG8(sc, space, o, v) \ 931 ((IS_BE(sc) || IS_SH(sc)) ? (bus_space_write_1((sc)->space##_btag, \ 932 (sc)->space##_bhandle,o,v)) \ 933 : (bus_space_write_1((sc)->devcfg_btag, \ 934 (sc)->devcfg_bhandle,o,v))) 935 936 937 /*********************************************************** 938 * DMA memory functions 939 ***********************************************************/ 940 #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 941 int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 942 void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); 943 void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error); 944 void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring); 945 oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc, 946 uint32_t q_len, uint32_t num_entries); 947 /************************************************************ 948 * oce_hw_xxx functions 949 ************************************************************/ 950 int oce_clear_rx_buf(struct oce_rq *rq); 951 int oce_hw_pci_alloc(POCE_SOFTC sc); 952 int oce_hw_init(POCE_SOFTC sc); 953 int oce_hw_start(POCE_SOFTC sc); 954 int oce_create_nw_interface(POCE_SOFTC sc); 955 int oce_pci_soft_reset(POCE_SOFTC sc); 956 int oce_hw_update_multicast(POCE_SOFTC sc); 957 void oce_delete_nw_interface(POCE_SOFTC sc); 958 void oce_hw_shutdown(POCE_SOFTC sc); 959 void oce_hw_intr_enable(POCE_SOFTC sc); 960 void oce_hw_intr_disable(POCE_SOFTC sc); 961 void oce_hw_pci_free(POCE_SOFTC sc); 962 963 /*********************************************************** 964 * oce_queue_xxx functions 965 ***********************************************************/ 966 int oce_queue_init_all(POCE_SOFTC sc); 967 int oce_start_rq(struct oce_rq *rq); 968 int oce_start_wq(struct oce_wq *wq); 969 int oce_start_mq(struct oce_mq *mq); 970 int oce_start_rx(POCE_SOFTC sc); 971 void oce_arm_eq(POCE_SOFTC sc, 972 int16_t qid, int npopped, uint32_t rearm, uint32_t clearint); 973 void oce_queue_release_all(POCE_SOFTC sc); 974 void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm); 975 void oce_drain_eq(struct oce_eq *eq); 976 void oce_drain_mq_cq(void *arg); 977 void oce_drain_rq_cq(struct oce_rq *rq); 978 void oce_drain_wq_cq(struct oce_wq *wq); 979 980 uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list); 981 982 /*********************************************************** 983 * cleanup functions 984 ***********************************************************/ 985 void oce_stop_rx(POCE_SOFTC sc); 986 void oce_intr_free(POCE_SOFTC sc); 987 void oce_free_posted_rxbuf(struct oce_rq *rq); 988 #if defined(INET6) || defined(INET) 989 void oce_free_lro(POCE_SOFTC sc); 990 #endif 991 992 993 /************************************************************ 994 * Mailbox functions 995 ************************************************************/ 996 int oce_fw_clean(POCE_SOFTC sc); 997 int oce_reset_fun(POCE_SOFTC sc); 998 int oce_mbox_init(POCE_SOFTC sc); 999 int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec); 1000 int oce_get_fw_version(POCE_SOFTC sc); 1001 int oce_first_mcc_cmd(POCE_SOFTC sc); 1002 1003 int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm, 1004 uint8_t type, struct mac_address_format *mac); 1005 int oce_get_fw_config(POCE_SOFTC sc); 1006 int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags, 1007 uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 1008 int oce_if_del(POCE_SOFTC sc, uint32_t if_id); 1009 int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id, 1010 struct normal_vlan *vtag_arr, uint8_t vtag_cnt, 1011 uint32_t untagged, uint32_t enable_promisc); 1012 int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control); 1013 int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss); 1014 int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint8_t enable); 1015 int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl); 1016 int oce_get_link_status(POCE_SOFTC sc, struct link_status *link); 1017 int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1018 int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 1019 int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1020 uint32_t reset_stats); 1021 int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 1022 uint32_t req_size, uint32_t reset_stats); 1023 int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem); 1024 int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size); 1025 int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id); 1026 int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 1027 uint32_t if_id, uint32_t *pmac_id); 1028 int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 1029 uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 1030 uint64_t pattern); 1031 1032 int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 1033 uint8_t loopback_type, uint8_t enable); 1034 1035 int oce_mbox_check_native_mode(POCE_SOFTC sc); 1036 int oce_mbox_post(POCE_SOFTC sc, 1037 struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx); 1038 int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 1039 POCE_DMA_MEM pdma_mem, uint32_t num_bytes); 1040 int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 1041 uint32_t data_offset,POCE_DMA_MEM pdma_mem, 1042 uint32_t *written_data, uint32_t *additional_status); 1043 1044 int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 1045 uint32_t offset, uint32_t optype); 1046 int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info); 1047 int oce_mbox_create_rq(struct oce_rq *rq); 1048 int oce_mbox_create_wq(struct oce_wq *wq); 1049 int oce_mbox_create_eq(struct oce_eq *eq); 1050 int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 1051 uint32_t is_eventable); 1052 int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num); 1053 void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1054 int num); 1055 int oce_get_profile_config(POCE_SOFTC sc, uint32_t max_rss); 1056 int oce_get_func_config(POCE_SOFTC sc); 1057 void mbx_common_req_hdr_init(struct mbx_hdr *hdr, 1058 uint8_t dom, 1059 uint8_t port, 1060 uint8_t subsys, 1061 uint8_t opcode, 1062 uint32_t timeout, uint32_t pyld_len, 1063 uint8_t version); 1064 1065 1066 uint16_t oce_mq_handler(void *arg); 1067 1068 /************************************************************ 1069 * Transmit functions 1070 ************************************************************/ 1071 uint16_t oce_wq_handler(void *arg); 1072 void oce_start(struct ifnet *ifp); 1073 void oce_tx_task(void *arg, int npending); 1074 1075 /************************************************************ 1076 * Receive functions 1077 ************************************************************/ 1078 int oce_alloc_rx_bufs(struct oce_rq *rq, int count); 1079 uint16_t oce_rq_handler(void *arg); 1080 1081 1082 /* Sysctl functions */ 1083 void oce_add_sysctls(POCE_SOFTC sc); 1084 void oce_refresh_queue_stats(POCE_SOFTC sc); 1085 int oce_refresh_nic_stats(POCE_SOFTC sc); 1086 int oce_stats_init(POCE_SOFTC sc); 1087 void oce_stats_free(POCE_SOFTC sc); 1088 1089 /* Capabilities */ 1090 #define OCE_MODCAP_RSS 1 1091 #define OCE_MAX_RSP_HANDLED 64 1092 extern uint32_t oce_max_rsp_handled; /* max responses */ 1093 1094 #define OCE_MAC_LOOPBACK 0x0 1095 #define OCE_PHY_LOOPBACK 0x1 1096 #define OCE_ONE_PORT_EXT_LOOPBACK 0x2 1097 #define OCE_NO_LOOPBACK 0xff 1098 1099 #undef IFM_40G_SR4 1100 #define IFM_40G_SR4 28 1101 1102 #define atomic_inc_32(x) atomic_add_32(x, 1) 1103 #define atomic_dec_32(x) atomic_subtract_32(x, 1) 1104 1105 #define LE_64(x) htole64(x) 1106 #define LE_32(x) htole32(x) 1107 #define LE_16(x) htole16(x) 1108 #define HOST_64(x) le64toh(x) 1109 #define HOST_32(x) le32toh(x) 1110 #define HOST_16(x) le16toh(x) 1111 #define DW_SWAP(x, l) 1112 #define IS_ALIGNED(x,a) ((x % a) == 0) 1113 #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 1114 #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 1115 1116 #define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 1117 #define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 1118 #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) 1119 1120 #define OCE_LOG2(x) (oce_highbit(x)) 1121 static inline uint32_t oce_highbit(uint32_t x) 1122 { 1123 int i; 1124 int c; 1125 int b; 1126 1127 c = 0; 1128 b = 0; 1129 1130 for (i = 0; i < 32; i++) { 1131 if ((1 << i) & x) { 1132 c++; 1133 b = i; 1134 } 1135 } 1136 1137 if (c == 1) 1138 return b; 1139 1140 return 0; 1141 } 1142 1143 static inline int MPU_EP_SEMAPHORE(POCE_SOFTC sc) 1144 { 1145 if (IS_BE(sc)) 1146 return MPU_EP_SEMAPHORE_BE3; 1147 else if (IS_SH(sc)) 1148 return MPU_EP_SEMAPHORE_SH; 1149 else 1150 return MPU_EP_SEMAPHORE_XE201; 1151 } 1152 1153 #define TRANSCEIVER_DATA_NUM_ELE 64 1154 #define TRANSCEIVER_DATA_SIZE 256 1155 #define TRANSCEIVER_A0_SIZE 128 1156 #define TRANSCEIVER_A2_SIZE 128 1157 #define PAGE_NUM_A0 0xa0 1158 #define PAGE_NUM_A2 0xa2 1159 #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\ 1160 || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE))) 1161 1162