12f345d8eSLuigi Rizzo /*- 22f345d8eSLuigi Rizzo * Copyright (C) 2012 Emulex 32f345d8eSLuigi Rizzo * All rights reserved. 42f345d8eSLuigi Rizzo * 52f345d8eSLuigi Rizzo * Redistribution and use in source and binary forms, with or without 62f345d8eSLuigi Rizzo * modification, are permitted provided that the following conditions are met: 72f345d8eSLuigi Rizzo * 82f345d8eSLuigi Rizzo * 1. Redistributions of source code must retain the above copyright notice, 92f345d8eSLuigi Rizzo * this list of conditions and the following disclaimer. 102f345d8eSLuigi Rizzo * 112f345d8eSLuigi Rizzo * 2. Redistributions in binary form must reproduce the above copyright 122f345d8eSLuigi Rizzo * notice, this list of conditions and the following disclaimer in the 132f345d8eSLuigi Rizzo * documentation and/or other materials provided with the distribution. 142f345d8eSLuigi Rizzo * 152f345d8eSLuigi Rizzo * 3. Neither the name of the Emulex Corporation nor the names of its 162f345d8eSLuigi Rizzo * contributors may be used to endorse or promote products derived from 172f345d8eSLuigi Rizzo * this software without specific prior written permission. 182f345d8eSLuigi Rizzo * 192f345d8eSLuigi Rizzo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 202f345d8eSLuigi Rizzo * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 212f345d8eSLuigi Rizzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 222f345d8eSLuigi Rizzo * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 232f345d8eSLuigi Rizzo * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 242f345d8eSLuigi Rizzo * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 252f345d8eSLuigi Rizzo * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 262f345d8eSLuigi Rizzo * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 272f345d8eSLuigi Rizzo * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 282f345d8eSLuigi Rizzo * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 292f345d8eSLuigi Rizzo * POSSIBILITY OF SUCH DAMAGE. 302f345d8eSLuigi Rizzo * 312f345d8eSLuigi Rizzo * Contact Information: 322f345d8eSLuigi Rizzo * freebsd-drivers@emulex.com 332f345d8eSLuigi Rizzo * 342f345d8eSLuigi Rizzo * Emulex 352f345d8eSLuigi Rizzo * 3333 Susan Street 362f345d8eSLuigi Rizzo * Costa Mesa, CA 92626 372f345d8eSLuigi Rizzo */ 382f345d8eSLuigi Rizzo 39*cdaba892SXin LI 402f345d8eSLuigi Rizzo /* $FreeBSD$ */ 412f345d8eSLuigi Rizzo 422f345d8eSLuigi Rizzo #include <sys/param.h> 432f345d8eSLuigi Rizzo #include <sys/endian.h> 442f345d8eSLuigi Rizzo #include <sys/module.h> 452f345d8eSLuigi Rizzo #include <sys/kernel.h> 462f345d8eSLuigi Rizzo #include <sys/bus.h> 472f345d8eSLuigi Rizzo #include <sys/mbuf.h> 482f345d8eSLuigi Rizzo #include <sys/rman.h> 492f345d8eSLuigi Rizzo #include <sys/socket.h> 502f345d8eSLuigi Rizzo #include <sys/sockio.h> 512f345d8eSLuigi Rizzo #include <sys/sockopt.h> 522f345d8eSLuigi Rizzo #include <sys/queue.h> 532f345d8eSLuigi Rizzo #include <sys/taskqueue.h> 542f345d8eSLuigi Rizzo #include <sys/lock.h> 552f345d8eSLuigi Rizzo #include <sys/mutex.h> 562f345d8eSLuigi Rizzo #include <sys/sysctl.h> 572f345d8eSLuigi Rizzo #include <sys/random.h> 582f345d8eSLuigi Rizzo #include <sys/firmware.h> 592f345d8eSLuigi Rizzo #include <sys/systm.h> 602f345d8eSLuigi Rizzo #include <sys/proc.h> 612f345d8eSLuigi Rizzo 622f345d8eSLuigi Rizzo #include <dev/pci/pcireg.h> 632f345d8eSLuigi Rizzo #include <dev/pci/pcivar.h> 642f345d8eSLuigi Rizzo 652f345d8eSLuigi Rizzo #include <net/bpf.h> 662f345d8eSLuigi Rizzo #include <net/ethernet.h> 672f345d8eSLuigi Rizzo #include <net/if.h> 682f345d8eSLuigi Rizzo #include <net/if_types.h> 692f345d8eSLuigi Rizzo #include <net/if_media.h> 702f345d8eSLuigi Rizzo #include <net/if_vlan_var.h> 712f345d8eSLuigi Rizzo #include <net/if_dl.h> 722f345d8eSLuigi Rizzo 732f345d8eSLuigi Rizzo #include <netinet/in.h> 742f345d8eSLuigi Rizzo #include <netinet/in_systm.h> 752f345d8eSLuigi Rizzo #include <netinet/in_var.h> 762f345d8eSLuigi Rizzo #include <netinet/if_ether.h> 772f345d8eSLuigi Rizzo #include <netinet/ip.h> 782f345d8eSLuigi Rizzo #include <netinet/ip6.h> 792f345d8eSLuigi Rizzo #include <netinet6/in6_var.h> 802f345d8eSLuigi Rizzo #include <netinet6/ip6_mroute.h> 812f345d8eSLuigi Rizzo 822f345d8eSLuigi Rizzo #include <netinet/udp.h> 832f345d8eSLuigi Rizzo #include <netinet/tcp.h> 842f345d8eSLuigi Rizzo #include <netinet/sctp.h> 852f345d8eSLuigi Rizzo #include <netinet/tcp_lro.h> 862f345d8eSLuigi Rizzo 872f345d8eSLuigi Rizzo #include <machine/bus.h> 882f345d8eSLuigi Rizzo 892f345d8eSLuigi Rizzo #include "oce_hw.h" 902f345d8eSLuigi Rizzo 91*cdaba892SXin LI #define COMPONENT_REVISION "4.6.95.0" 922f345d8eSLuigi Rizzo 932f345d8eSLuigi Rizzo /* OCE devices supported by this driver */ 942f345d8eSLuigi Rizzo #define PCI_VENDOR_EMULEX 0x10df /* Emulex */ 952f345d8eSLuigi Rizzo #define PCI_VENDOR_SERVERENGINES 0x19a2 /* ServerEngines (BE) */ 962f345d8eSLuigi Rizzo #define PCI_PRODUCT_BE2 0x0700 /* BE2 network adapter */ 972f345d8eSLuigi Rizzo #define PCI_PRODUCT_BE3 0x0710 /* BE3 network adapter */ 982f345d8eSLuigi Rizzo #define PCI_PRODUCT_XE201 0xe220 /* XE201 network adapter */ 992f345d8eSLuigi Rizzo #define PCI_PRODUCT_XE201_VF 0xe228 /* XE201 with VF in Lancer */ 1002f345d8eSLuigi Rizzo 1012f345d8eSLuigi Rizzo #define IS_BE(sc) (((sc->flags & OCE_FLAGS_BE3) | \ 1022f345d8eSLuigi Rizzo (sc->flags & OCE_FLAGS_BE2))? 1:0) 1032f345d8eSLuigi Rizzo #define IS_XE201(sc) ((sc->flags & OCE_FLAGS_XE201) ? 1:0) 1042f345d8eSLuigi Rizzo #define HAS_A0_CHIP(sc) ((sc->flags & OCE_FLAGS_HAS_A0_CHIP) ? 1:0) 1052f345d8eSLuigi Rizzo 1062f345d8eSLuigi Rizzo 1072f345d8eSLuigi Rizzo /* proportion Service Level Interface queues */ 1082f345d8eSLuigi Rizzo #define OCE_MAX_UNITS 2 1092f345d8eSLuigi Rizzo #define OCE_MAX_PPORT OCE_MAX_UNITS 1102f345d8eSLuigi Rizzo #define OCE_MAX_VPORT OCE_MAX_UNITS 1112f345d8eSLuigi Rizzo 1122f345d8eSLuigi Rizzo extern int mp_ncpus; /* system's total active cpu cores */ 1132f345d8eSLuigi Rizzo #define OCE_NCPUS mp_ncpus 1149bd3250aSLuigi Rizzo 1159bd3250aSLuigi Rizzo /* This should be powers of 2. Like 2,4,8 & 16 */ 1169bd3250aSLuigi Rizzo #define OCE_MAX_RSS 4 /* TODO: 8*/ 1172f345d8eSLuigi Rizzo #define OCE_LEGACY_MODE_RSS 4 /* For BE3 Legacy mode*/ 1182f345d8eSLuigi Rizzo 1192f345d8eSLuigi Rizzo #define OCE_MIN_RQ 1 1202f345d8eSLuigi Rizzo #define OCE_MIN_WQ 1 1212f345d8eSLuigi Rizzo 1222f345d8eSLuigi Rizzo #define OCE_MAX_RQ OCE_MAX_RSS + 1 /* one default queue */ 1232f345d8eSLuigi Rizzo #define OCE_MAX_WQ 8 1242f345d8eSLuigi Rizzo 1252f345d8eSLuigi Rizzo #define OCE_MAX_EQ 32 1262f345d8eSLuigi Rizzo #define OCE_MAX_CQ OCE_MAX_RQ + OCE_MAX_WQ + 1 /* one MCC queue */ 1272f345d8eSLuigi Rizzo #define OCE_MAX_CQ_EQ 8 /* Max CQ that can attached to an EQ */ 1282f345d8eSLuigi Rizzo 1292f345d8eSLuigi Rizzo #define OCE_DEFAULT_WQ_EQD 16 1302f345d8eSLuigi Rizzo #define OCE_MAX_PACKET_Q 16 1312f345d8eSLuigi Rizzo #define OCE_RQ_BUF_SIZE 2048 1322f345d8eSLuigi Rizzo #define OCE_LSO_MAX_SIZE (64 * 1024) 1332f345d8eSLuigi Rizzo #define LONG_TIMEOUT 30 134*cdaba892SXin LI #define OCE_MAX_JUMBO_FRAME_SIZE 9018 1352f345d8eSLuigi Rizzo #define OCE_MAX_MTU (OCE_MAX_JUMBO_FRAME_SIZE - \ 1362f345d8eSLuigi Rizzo ETHER_VLAN_ENCAP_LEN - \ 1372f345d8eSLuigi Rizzo ETHER_HDR_LEN) 1382f345d8eSLuigi Rizzo 1392f345d8eSLuigi Rizzo #define OCE_MAX_TX_ELEMENTS 29 1402f345d8eSLuigi Rizzo #define OCE_MAX_TX_DESC 1024 1412f345d8eSLuigi Rizzo #define OCE_MAX_TX_SIZE 65535 1422f345d8eSLuigi Rizzo #define OCE_MAX_RX_SIZE 4096 1432f345d8eSLuigi Rizzo #define OCE_MAX_RQ_POSTS 255 1442f345d8eSLuigi Rizzo #define OCE_DEFAULT_PROMISCUOUS 0 1452f345d8eSLuigi Rizzo 1462f345d8eSLuigi Rizzo 1472f345d8eSLuigi Rizzo #define RSS_ENABLE_IPV4 0x1 1482f345d8eSLuigi Rizzo #define RSS_ENABLE_TCP_IPV4 0x2 1492f345d8eSLuigi Rizzo #define RSS_ENABLE_IPV6 0x4 1502f345d8eSLuigi Rizzo #define RSS_ENABLE_TCP_IPV6 0x8 1512f345d8eSLuigi Rizzo 1522f345d8eSLuigi Rizzo 1532f345d8eSLuigi Rizzo /* flow control definitions */ 1542f345d8eSLuigi Rizzo #define OCE_FC_NONE 0x00000000 1552f345d8eSLuigi Rizzo #define OCE_FC_TX 0x00000001 1562f345d8eSLuigi Rizzo #define OCE_FC_RX 0x00000002 1572f345d8eSLuigi Rizzo #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 1582f345d8eSLuigi Rizzo 1592f345d8eSLuigi Rizzo 1602f345d8eSLuigi Rizzo /* Interface capabilities to give device when creating interface */ 1612f345d8eSLuigi Rizzo #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 1622f345d8eSLuigi Rizzo MBX_RX_IFACE_FLAGS_UNTAGGED | \ 1632f345d8eSLuigi Rizzo MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 1642f345d8eSLuigi Rizzo MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 1652f345d8eSLuigi Rizzo MBX_RX_IFACE_FLAGS_RSS | \ 1662f345d8eSLuigi Rizzo MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 1672f345d8eSLuigi Rizzo 1682f345d8eSLuigi Rizzo /* Interface capabilities to enable by default (others set dynamically) */ 1692f345d8eSLuigi Rizzo #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 1702f345d8eSLuigi Rizzo MBX_RX_IFACE_FLAGS_UNTAGGED | \ 1712f345d8eSLuigi Rizzo MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR) 1722f345d8eSLuigi Rizzo 1732f345d8eSLuigi Rizzo #define OCE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP) 1742f345d8eSLuigi Rizzo #define OCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \ 1752f345d8eSLuigi Rizzo IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | \ 1769bd3250aSLuigi Rizzo IFCAP_JUMBO_MTU | IFCAP_VLAN_MTU) 1772f345d8eSLuigi Rizzo #define OCE_IF_HWASSIST_NONE 0 1782f345d8eSLuigi Rizzo #define OCE_IF_CAPABILITIES_NONE 0 1792f345d8eSLuigi Rizzo 1802f345d8eSLuigi Rizzo 1812f345d8eSLuigi Rizzo #define ETH_ADDR_LEN 6 1822f345d8eSLuigi Rizzo #define MAX_VLANFILTER_SIZE 64 1832f345d8eSLuigi Rizzo #define MAX_VLANS 4096 1842f345d8eSLuigi Rizzo 1852f345d8eSLuigi Rizzo #define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) 1862f345d8eSLuigi Rizzo #define BSWAP_8(x) ((x) & 0xff) 1872f345d8eSLuigi Rizzo #define BSWAP_16(x) ((BSWAP_8(x) << 8) | BSWAP_8((x) >> 8)) 1882f345d8eSLuigi Rizzo #define BSWAP_32(x) ((BSWAP_16(x) << 16) | \ 1892f345d8eSLuigi Rizzo BSWAP_16((x) >> 16)) 1902f345d8eSLuigi Rizzo #define BSWAP_64(x) ((BSWAP_32(x) << 32) | \ 1912f345d8eSLuigi Rizzo BSWAP_32((x) >> 32)) 1922f345d8eSLuigi Rizzo 1932f345d8eSLuigi Rizzo #define for_all_wq_queues(sc, wq, i) \ 1942f345d8eSLuigi Rizzo for (i = 0, wq = sc->wq[0]; i < sc->nwqs; i++, wq = sc->wq[i]) 1952f345d8eSLuigi Rizzo #define for_all_rq_queues(sc, rq, i) \ 1962f345d8eSLuigi Rizzo for (i = 0, rq = sc->rq[0]; i < sc->nrqs; i++, rq = sc->rq[i]) 1972f345d8eSLuigi Rizzo #define for_all_evnt_queues(sc, eq, i) \ 1982f345d8eSLuigi Rizzo for (i = 0, eq = sc->eq[0]; i < sc->neqs; i++, eq = sc->eq[i]) 1992f345d8eSLuigi Rizzo #define for_all_cq_queues(sc, cq, i) \ 2002f345d8eSLuigi Rizzo for (i = 0, cq = sc->cq[0]; i < sc->ncqs; i++, cq = sc->cq[i]) 2012f345d8eSLuigi Rizzo 2022f345d8eSLuigi Rizzo 2032f345d8eSLuigi Rizzo /* Flash specific */ 2042f345d8eSLuigi Rizzo #define IOCTL_COOKIE "SERVERENGINES CORP" 2052f345d8eSLuigi Rizzo #define MAX_FLASH_COMP 32 2062f345d8eSLuigi Rizzo 2072f345d8eSLuigi Rizzo #define IMG_ISCSI 160 2082f345d8eSLuigi Rizzo #define IMG_REDBOOT 224 2092f345d8eSLuigi Rizzo #define IMG_BIOS 34 2102f345d8eSLuigi Rizzo #define IMG_PXEBIOS 32 2112f345d8eSLuigi Rizzo #define IMG_FCOEBIOS 33 2122f345d8eSLuigi Rizzo #define IMG_ISCSI_BAK 176 2132f345d8eSLuigi Rizzo #define IMG_FCOE 162 2142f345d8eSLuigi Rizzo #define IMG_FCOE_BAK 178 2152f345d8eSLuigi Rizzo #define IMG_NCSI 16 2162f345d8eSLuigi Rizzo #define IMG_PHY 192 2172f345d8eSLuigi Rizzo #define FLASHROM_OPER_FLASH 1 2182f345d8eSLuigi Rizzo #define FLASHROM_OPER_SAVE 2 2192f345d8eSLuigi Rizzo #define FLASHROM_OPER_REPORT 4 2202f345d8eSLuigi Rizzo #define FLASHROM_OPER_FLASH_PHY 9 2212f345d8eSLuigi Rizzo #define FLASHROM_OPER_SAVE_PHY 10 2222f345d8eSLuigi Rizzo #define TN_8022 13 2232f345d8eSLuigi Rizzo 2242f345d8eSLuigi Rizzo enum { 2252f345d8eSLuigi Rizzo PHY_TYPE_CX4_10GB = 0, 2262f345d8eSLuigi Rizzo PHY_TYPE_XFP_10GB, 2272f345d8eSLuigi Rizzo PHY_TYPE_SFP_1GB, 2282f345d8eSLuigi Rizzo PHY_TYPE_SFP_PLUS_10GB, 2292f345d8eSLuigi Rizzo PHY_TYPE_KR_10GB, 2302f345d8eSLuigi Rizzo PHY_TYPE_KX4_10GB, 2312f345d8eSLuigi Rizzo PHY_TYPE_BASET_10GB, 2322f345d8eSLuigi Rizzo PHY_TYPE_BASET_1GB, 2332f345d8eSLuigi Rizzo PHY_TYPE_BASEX_1GB, 2342f345d8eSLuigi Rizzo PHY_TYPE_SGMII, 2352f345d8eSLuigi Rizzo PHY_TYPE_DISABLED = 255 2362f345d8eSLuigi Rizzo }; 2372f345d8eSLuigi Rizzo 2382f345d8eSLuigi Rizzo /** 2392f345d8eSLuigi Rizzo * @brief Define and hold all necessary info for a single interrupt 2402f345d8eSLuigi Rizzo */ 2412f345d8eSLuigi Rizzo #define OCE_MAX_MSI 32 /* Message Signaled Interrupts */ 2422f345d8eSLuigi Rizzo #define OCE_MAX_MSIX 2048 /* PCI Express MSI Interrrupts */ 2432f345d8eSLuigi Rizzo 2442f345d8eSLuigi Rizzo typedef struct oce_intr_info { 2452f345d8eSLuigi Rizzo void *tag; /* cookie returned by bus_setup_intr */ 2462f345d8eSLuigi Rizzo struct resource *intr_res; /* PCI resource container */ 2472f345d8eSLuigi Rizzo int irq_rr; /* resource id for the interrupt */ 2482f345d8eSLuigi Rizzo struct oce_softc *sc; /* pointer to the parent soft c */ 2492f345d8eSLuigi Rizzo struct oce_eq *eq; /* pointer to the connected EQ */ 2502f345d8eSLuigi Rizzo struct taskqueue *tq; /* Associated task queue */ 2512f345d8eSLuigi Rizzo struct task task; /* task queue task */ 2522f345d8eSLuigi Rizzo char task_name[32]; /* task name */ 2532f345d8eSLuigi Rizzo int vector; /* interrupt vector number */ 2542f345d8eSLuigi Rizzo } OCE_INTR_INFO, *POCE_INTR_INFO; 2552f345d8eSLuigi Rizzo 2562f345d8eSLuigi Rizzo 2572f345d8eSLuigi Rizzo /* Ring related */ 2582f345d8eSLuigi Rizzo #define GET_Q_NEXT(_START, _STEP, _END) \ 2592f345d8eSLuigi Rizzo (((_START) + (_STEP)) < (_END) ? ((_START) + (_STEP)) \ 2602f345d8eSLuigi Rizzo : (((_START) + (_STEP)) - (_END))) 2612f345d8eSLuigi Rizzo 2622f345d8eSLuigi Rizzo #define DBUF_PA(obj) ((obj)->addr) 2632f345d8eSLuigi Rizzo #define DBUF_VA(obj) ((obj)->ptr) 2642f345d8eSLuigi Rizzo #define DBUF_TAG(obj) ((obj)->tag) 2652f345d8eSLuigi Rizzo #define DBUF_MAP(obj) ((obj)->map) 2662f345d8eSLuigi Rizzo #define DBUF_SYNC(obj, flags) \ 2672f345d8eSLuigi Rizzo (void) bus_dmamap_sync(DBUF_TAG(obj), DBUF_MAP(obj), (flags)) 2682f345d8eSLuigi Rizzo 2692f345d8eSLuigi Rizzo #define RING_NUM_PENDING(ring) ring->num_used 2702f345d8eSLuigi Rizzo #define RING_FULL(ring) (ring->num_used == ring->num_items) 2712f345d8eSLuigi Rizzo #define RING_EMPTY(ring) (ring->num_used == 0) 2722f345d8eSLuigi Rizzo #define RING_NUM_FREE(ring) \ 2732f345d8eSLuigi Rizzo (uint32_t)(ring->num_items - ring->num_used) 2742f345d8eSLuigi Rizzo #define RING_GET(ring, n) \ 2752f345d8eSLuigi Rizzo ring->cidx = GET_Q_NEXT(ring->cidx, n, ring->num_items) 2762f345d8eSLuigi Rizzo #define RING_PUT(ring, n) \ 2772f345d8eSLuigi Rizzo ring->pidx = GET_Q_NEXT(ring->pidx, n, ring->num_items) 2782f345d8eSLuigi Rizzo 2792f345d8eSLuigi Rizzo #define RING_GET_CONSUMER_ITEM_VA(ring, type) \ 2802f345d8eSLuigi Rizzo (void*)((type *)DBUF_VA(&ring->dma) + ring->cidx) 2812f345d8eSLuigi Rizzo #define RING_GET_CONSUMER_ITEM_PA(ring, type) \ 2822f345d8eSLuigi Rizzo (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->cidx) 2832f345d8eSLuigi Rizzo #define RING_GET_PRODUCER_ITEM_VA(ring, type) \ 2842f345d8eSLuigi Rizzo (void *)(((type *)DBUF_VA(&ring->dma)) + ring->pidx) 2852f345d8eSLuigi Rizzo #define RING_GET_PRODUCER_ITEM_PA(ring, type) \ 2862f345d8eSLuigi Rizzo (uint64_t)(((type *)DBUF_PA(ring->dbuf)) + ring->pidx) 2872f345d8eSLuigi Rizzo 2882f345d8eSLuigi Rizzo #define OCE_DMAPTR(o, c) ((c *)(o)->ptr) 2892f345d8eSLuigi Rizzo 2902f345d8eSLuigi Rizzo struct oce_packet_desc { 2912f345d8eSLuigi Rizzo struct mbuf *mbuf; 2922f345d8eSLuigi Rizzo bus_dmamap_t map; 2932f345d8eSLuigi Rizzo int nsegs; 2942f345d8eSLuigi Rizzo uint32_t wqe_idx; 2952f345d8eSLuigi Rizzo }; 2962f345d8eSLuigi Rizzo 2972f345d8eSLuigi Rizzo typedef struct oce_dma_mem { 2982f345d8eSLuigi Rizzo bus_dma_tag_t tag; 2992f345d8eSLuigi Rizzo bus_dmamap_t map; 3002f345d8eSLuigi Rizzo void *ptr; 3012f345d8eSLuigi Rizzo bus_addr_t paddr; 3022f345d8eSLuigi Rizzo } OCE_DMA_MEM, *POCE_DMA_MEM; 3032f345d8eSLuigi Rizzo 3042f345d8eSLuigi Rizzo typedef struct oce_ring_buffer_s { 3052f345d8eSLuigi Rizzo uint16_t cidx; /* Get ptr */ 3062f345d8eSLuigi Rizzo uint16_t pidx; /* Put Ptr */ 3072f345d8eSLuigi Rizzo size_t item_size; 3082f345d8eSLuigi Rizzo size_t num_items; 3092f345d8eSLuigi Rizzo uint32_t num_used; 3102f345d8eSLuigi Rizzo OCE_DMA_MEM dma; 3112f345d8eSLuigi Rizzo } oce_ring_buffer_t; 3122f345d8eSLuigi Rizzo 3132f345d8eSLuigi Rizzo /* Stats */ 3142f345d8eSLuigi Rizzo #define OCE_UNICAST_PACKET 0 3152f345d8eSLuigi Rizzo #define OCE_MULTICAST_PACKET 1 3162f345d8eSLuigi Rizzo #define OCE_BROADCAST_PACKET 2 3172f345d8eSLuigi Rizzo #define OCE_RSVD_PACKET 3 3182f345d8eSLuigi Rizzo 3192f345d8eSLuigi Rizzo struct oce_rx_stats { 3202f345d8eSLuigi Rizzo /* Total Receive Stats*/ 3212f345d8eSLuigi Rizzo uint64_t t_rx_pkts; 3222f345d8eSLuigi Rizzo uint64_t t_rx_bytes; 3232f345d8eSLuigi Rizzo uint32_t t_rx_frags; 3242f345d8eSLuigi Rizzo uint32_t t_rx_mcast_pkts; 3252f345d8eSLuigi Rizzo uint32_t t_rx_ucast_pkts; 3262f345d8eSLuigi Rizzo uint32_t t_rxcp_errs; 3272f345d8eSLuigi Rizzo }; 3282f345d8eSLuigi Rizzo struct oce_tx_stats { 3292f345d8eSLuigi Rizzo /*Total Transmit Stats */ 3302f345d8eSLuigi Rizzo uint64_t t_tx_pkts; 3312f345d8eSLuigi Rizzo uint64_t t_tx_bytes; 3322f345d8eSLuigi Rizzo uint32_t t_tx_reqs; 3332f345d8eSLuigi Rizzo uint32_t t_tx_stops; 3342f345d8eSLuigi Rizzo uint32_t t_tx_wrbs; 3352f345d8eSLuigi Rizzo uint32_t t_tx_compl; 3362f345d8eSLuigi Rizzo uint32_t t_ipv6_ext_hdr_tx_drop; 3372f345d8eSLuigi Rizzo }; 3382f345d8eSLuigi Rizzo 3392f345d8eSLuigi Rizzo struct oce_be_stats { 3402f345d8eSLuigi Rizzo uint8_t be_on_die_temperature; 3412f345d8eSLuigi Rizzo uint32_t be_tx_events; 3422f345d8eSLuigi Rizzo uint32_t eth_red_drops; 3432f345d8eSLuigi Rizzo uint32_t rx_drops_no_pbuf; 3442f345d8eSLuigi Rizzo uint32_t rx_drops_no_txpb; 3452f345d8eSLuigi Rizzo uint32_t rx_drops_no_erx_descr; 3462f345d8eSLuigi Rizzo uint32_t rx_drops_no_tpre_descr; 3472f345d8eSLuigi Rizzo uint32_t rx_drops_too_many_frags; 3482f345d8eSLuigi Rizzo uint32_t rx_drops_invalid_ring; 3492f345d8eSLuigi Rizzo uint32_t forwarded_packets; 3502f345d8eSLuigi Rizzo uint32_t rx_drops_mtu; 3512f345d8eSLuigi Rizzo uint32_t rx_crc_errors; 3522f345d8eSLuigi Rizzo uint32_t rx_alignment_symbol_errors; 3532f345d8eSLuigi Rizzo uint32_t rx_pause_frames; 3542f345d8eSLuigi Rizzo uint32_t rx_priority_pause_frames; 3552f345d8eSLuigi Rizzo uint32_t rx_control_frames; 3562f345d8eSLuigi Rizzo uint32_t rx_in_range_errors; 3572f345d8eSLuigi Rizzo uint32_t rx_out_range_errors; 3582f345d8eSLuigi Rizzo uint32_t rx_frame_too_long; 3592f345d8eSLuigi Rizzo uint32_t rx_address_match_errors; 3602f345d8eSLuigi Rizzo uint32_t rx_dropped_too_small; 3612f345d8eSLuigi Rizzo uint32_t rx_dropped_too_short; 3622f345d8eSLuigi Rizzo uint32_t rx_dropped_header_too_small; 3632f345d8eSLuigi Rizzo uint32_t rx_dropped_tcp_length; 3642f345d8eSLuigi Rizzo uint32_t rx_dropped_runt; 3652f345d8eSLuigi Rizzo uint32_t rx_ip_checksum_errs; 3662f345d8eSLuigi Rizzo uint32_t rx_tcp_checksum_errs; 3672f345d8eSLuigi Rizzo uint32_t rx_udp_checksum_errs; 3682f345d8eSLuigi Rizzo uint32_t rx_switched_unicast_packets; 3692f345d8eSLuigi Rizzo uint32_t rx_switched_multicast_packets; 3702f345d8eSLuigi Rizzo uint32_t rx_switched_broadcast_packets; 3712f345d8eSLuigi Rizzo uint32_t tx_pauseframes; 3722f345d8eSLuigi Rizzo uint32_t tx_priority_pauseframes; 3732f345d8eSLuigi Rizzo uint32_t tx_controlframes; 3742f345d8eSLuigi Rizzo uint32_t rxpp_fifo_overflow_drop; 3752f345d8eSLuigi Rizzo uint32_t rx_input_fifo_overflow_drop; 3762f345d8eSLuigi Rizzo uint32_t pmem_fifo_overflow_drop; 3772f345d8eSLuigi Rizzo uint32_t jabber_events; 3782f345d8eSLuigi Rizzo }; 3792f345d8eSLuigi Rizzo 3802f345d8eSLuigi Rizzo struct oce_xe201_stats { 3812f345d8eSLuigi Rizzo uint64_t tx_pkts; 3822f345d8eSLuigi Rizzo uint64_t tx_unicast_pkts; 3832f345d8eSLuigi Rizzo uint64_t tx_multicast_pkts; 3842f345d8eSLuigi Rizzo uint64_t tx_broadcast_pkts; 3852f345d8eSLuigi Rizzo uint64_t tx_bytes; 3862f345d8eSLuigi Rizzo uint64_t tx_unicast_bytes; 3872f345d8eSLuigi Rizzo uint64_t tx_multicast_bytes; 3882f345d8eSLuigi Rizzo uint64_t tx_broadcast_bytes; 3892f345d8eSLuigi Rizzo uint64_t tx_discards; 3902f345d8eSLuigi Rizzo uint64_t tx_errors; 3912f345d8eSLuigi Rizzo uint64_t tx_pause_frames; 3922f345d8eSLuigi Rizzo uint64_t tx_pause_on_frames; 3932f345d8eSLuigi Rizzo uint64_t tx_pause_off_frames; 3942f345d8eSLuigi Rizzo uint64_t tx_internal_mac_errors; 3952f345d8eSLuigi Rizzo uint64_t tx_control_frames; 3962f345d8eSLuigi Rizzo uint64_t tx_pkts_64_bytes; 3972f345d8eSLuigi Rizzo uint64_t tx_pkts_65_to_127_bytes; 3982f345d8eSLuigi Rizzo uint64_t tx_pkts_128_to_255_bytes; 3992f345d8eSLuigi Rizzo uint64_t tx_pkts_256_to_511_bytes; 4002f345d8eSLuigi Rizzo uint64_t tx_pkts_512_to_1023_bytes; 4012f345d8eSLuigi Rizzo uint64_t tx_pkts_1024_to_1518_bytes; 4022f345d8eSLuigi Rizzo uint64_t tx_pkts_1519_to_2047_bytes; 4032f345d8eSLuigi Rizzo uint64_t tx_pkts_2048_to_4095_bytes; 4042f345d8eSLuigi Rizzo uint64_t tx_pkts_4096_to_8191_bytes; 4052f345d8eSLuigi Rizzo uint64_t tx_pkts_8192_to_9216_bytes; 4062f345d8eSLuigi Rizzo uint64_t tx_lso_pkts; 4072f345d8eSLuigi Rizzo uint64_t rx_pkts; 4082f345d8eSLuigi Rizzo uint64_t rx_unicast_pkts; 4092f345d8eSLuigi Rizzo uint64_t rx_multicast_pkts; 4102f345d8eSLuigi Rizzo uint64_t rx_broadcast_pkts; 4112f345d8eSLuigi Rizzo uint64_t rx_bytes; 4122f345d8eSLuigi Rizzo uint64_t rx_unicast_bytes; 4132f345d8eSLuigi Rizzo uint64_t rx_multicast_bytes; 4142f345d8eSLuigi Rizzo uint64_t rx_broadcast_bytes; 4152f345d8eSLuigi Rizzo uint32_t rx_unknown_protos; 4162f345d8eSLuigi Rizzo uint64_t rx_discards; 4172f345d8eSLuigi Rizzo uint64_t rx_errors; 4182f345d8eSLuigi Rizzo uint64_t rx_crc_errors; 4192f345d8eSLuigi Rizzo uint64_t rx_alignment_errors; 4202f345d8eSLuigi Rizzo uint64_t rx_symbol_errors; 4212f345d8eSLuigi Rizzo uint64_t rx_pause_frames; 4222f345d8eSLuigi Rizzo uint64_t rx_pause_on_frames; 4232f345d8eSLuigi Rizzo uint64_t rx_pause_off_frames; 4242f345d8eSLuigi Rizzo uint64_t rx_frames_too_long; 4252f345d8eSLuigi Rizzo uint64_t rx_internal_mac_errors; 4262f345d8eSLuigi Rizzo uint32_t rx_undersize_pkts; 4272f345d8eSLuigi Rizzo uint32_t rx_oversize_pkts; 4282f345d8eSLuigi Rizzo uint32_t rx_fragment_pkts; 4292f345d8eSLuigi Rizzo uint32_t rx_jabbers; 4302f345d8eSLuigi Rizzo uint64_t rx_control_frames; 4312f345d8eSLuigi Rizzo uint64_t rx_control_frames_unknown_opcode; 4322f345d8eSLuigi Rizzo uint32_t rx_in_range_errors; 4332f345d8eSLuigi Rizzo uint32_t rx_out_of_range_errors; 4342f345d8eSLuigi Rizzo uint32_t rx_address_match_errors; 4352f345d8eSLuigi Rizzo uint32_t rx_vlan_mismatch_errors; 4362f345d8eSLuigi Rizzo uint32_t rx_dropped_too_small; 4372f345d8eSLuigi Rizzo uint32_t rx_dropped_too_short; 4382f345d8eSLuigi Rizzo uint32_t rx_dropped_header_too_small; 4392f345d8eSLuigi Rizzo uint32_t rx_dropped_invalid_tcp_length; 4402f345d8eSLuigi Rizzo uint32_t rx_dropped_runt; 4412f345d8eSLuigi Rizzo uint32_t rx_ip_checksum_errors; 4422f345d8eSLuigi Rizzo uint32_t rx_tcp_checksum_errors; 4432f345d8eSLuigi Rizzo uint32_t rx_udp_checksum_errors; 4442f345d8eSLuigi Rizzo uint32_t rx_non_rss_pkts; 4452f345d8eSLuigi Rizzo uint64_t rx_ipv4_pkts; 4462f345d8eSLuigi Rizzo uint64_t rx_ipv6_pkts; 4472f345d8eSLuigi Rizzo uint64_t rx_ipv4_bytes; 4482f345d8eSLuigi Rizzo uint64_t rx_ipv6_bytes; 4492f345d8eSLuigi Rizzo uint64_t rx_nic_pkts; 4502f345d8eSLuigi Rizzo uint64_t rx_tcp_pkts; 4512f345d8eSLuigi Rizzo uint64_t rx_iscsi_pkts; 4522f345d8eSLuigi Rizzo uint64_t rx_management_pkts; 4532f345d8eSLuigi Rizzo uint64_t rx_switched_unicast_pkts; 4542f345d8eSLuigi Rizzo uint64_t rx_switched_multicast_pkts; 4552f345d8eSLuigi Rizzo uint64_t rx_switched_broadcast_pkts; 4562f345d8eSLuigi Rizzo uint64_t num_forwards; 4572f345d8eSLuigi Rizzo uint32_t rx_fifo_overflow; 4582f345d8eSLuigi Rizzo uint32_t rx_input_fifo_overflow; 4592f345d8eSLuigi Rizzo uint64_t rx_drops_too_many_frags; 4602f345d8eSLuigi Rizzo uint32_t rx_drops_invalid_queue; 4612f345d8eSLuigi Rizzo uint64_t rx_drops_mtu; 4622f345d8eSLuigi Rizzo uint64_t rx_pkts_64_bytes; 4632f345d8eSLuigi Rizzo uint64_t rx_pkts_65_to_127_bytes; 4642f345d8eSLuigi Rizzo uint64_t rx_pkts_128_to_255_bytes; 4652f345d8eSLuigi Rizzo uint64_t rx_pkts_256_to_511_bytes; 4662f345d8eSLuigi Rizzo uint64_t rx_pkts_512_to_1023_bytes; 4672f345d8eSLuigi Rizzo uint64_t rx_pkts_1024_to_1518_bytes; 4682f345d8eSLuigi Rizzo uint64_t rx_pkts_1519_to_2047_bytes; 4692f345d8eSLuigi Rizzo uint64_t rx_pkts_2048_to_4095_bytes; 4702f345d8eSLuigi Rizzo uint64_t rx_pkts_4096_to_8191_bytes; 4712f345d8eSLuigi Rizzo uint64_t rx_pkts_8192_to_9216_bytes; 4722f345d8eSLuigi Rizzo }; 4732f345d8eSLuigi Rizzo 4742f345d8eSLuigi Rizzo struct oce_drv_stats { 4752f345d8eSLuigi Rizzo struct oce_rx_stats rx; 4762f345d8eSLuigi Rizzo struct oce_tx_stats tx; 4772f345d8eSLuigi Rizzo union { 4782f345d8eSLuigi Rizzo struct oce_be_stats be; 4792f345d8eSLuigi Rizzo struct oce_xe201_stats xe201; 4802f345d8eSLuigi Rizzo } u0; 4812f345d8eSLuigi Rizzo }; 4822f345d8eSLuigi Rizzo 483*cdaba892SXin LI #define INTR_RATE_HWM 15000 484*cdaba892SXin LI #define INTR_RATE_LWM 10000 4852f345d8eSLuigi Rizzo 486*cdaba892SXin LI #define OCE_MAX_EQD 128u 487*cdaba892SXin LI #define OCE_MIN_EQD 50u 488*cdaba892SXin LI 489*cdaba892SXin LI struct oce_set_eqd { 490*cdaba892SXin LI uint32_t eq_id; 491*cdaba892SXin LI uint32_t phase; 492*cdaba892SXin LI uint32_t delay_multiplier; 493*cdaba892SXin LI }; 494*cdaba892SXin LI 495*cdaba892SXin LI struct oce_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 496*cdaba892SXin LI boolean_t enable; 497*cdaba892SXin LI uint32_t min_eqd; /* in usecs */ 498*cdaba892SXin LI uint32_t max_eqd; /* in usecs */ 499*cdaba892SXin LI uint32_t cur_eqd; /* in usecs */ 500*cdaba892SXin LI uint32_t et_eqd; /* configured value when aic is off */ 501*cdaba892SXin LI uint64_t ticks; 502*cdaba892SXin LI uint64_t intr_prev; 503*cdaba892SXin LI }; 5042f345d8eSLuigi Rizzo 5052f345d8eSLuigi Rizzo #define MAX_LOCK_DESC_LEN 32 5062f345d8eSLuigi Rizzo struct oce_lock { 5072f345d8eSLuigi Rizzo struct mtx mutex; 5082f345d8eSLuigi Rizzo char name[MAX_LOCK_DESC_LEN+1]; 5092f345d8eSLuigi Rizzo }; 5102f345d8eSLuigi Rizzo #define OCE_LOCK struct oce_lock 5112f345d8eSLuigi Rizzo 5122f345d8eSLuigi Rizzo #define LOCK_CREATE(lock, desc) { \ 5132f345d8eSLuigi Rizzo strncpy((lock)->name, (desc), MAX_LOCK_DESC_LEN); \ 5142f345d8eSLuigi Rizzo (lock)->name[MAX_LOCK_DESC_LEN] = '\0'; \ 515beb0f7e7SJosh Paetzel mtx_init(&(lock)->mutex, (lock)->name, NULL, MTX_DEF); \ 5162f345d8eSLuigi Rizzo } 5172f345d8eSLuigi Rizzo #define LOCK_DESTROY(lock) \ 5182f345d8eSLuigi Rizzo if (mtx_initialized(&(lock)->mutex))\ 5192f345d8eSLuigi Rizzo mtx_destroy(&(lock)->mutex) 5202f345d8eSLuigi Rizzo #define TRY_LOCK(lock) mtx_trylock(&(lock)->mutex) 5212f345d8eSLuigi Rizzo #define LOCK(lock) mtx_lock(&(lock)->mutex) 5222f345d8eSLuigi Rizzo #define LOCKED(lock) mtx_owned(&(lock)->mutex) 5232f345d8eSLuigi Rizzo #define UNLOCK(lock) mtx_unlock(&(lock)->mutex) 5242f345d8eSLuigi Rizzo 5252f345d8eSLuigi Rizzo #define DEFAULT_MQ_MBOX_TIMEOUT (5 * 1000 * 1000) 5262f345d8eSLuigi Rizzo #define MBX_READY_TIMEOUT (1 * 1000 * 1000) 5272f345d8eSLuigi Rizzo #define DEFAULT_DRAIN_TIME 200 5282f345d8eSLuigi Rizzo #define MBX_TIMEOUT_SEC 5 5292f345d8eSLuigi Rizzo #define STAT_TIMEOUT 2000000 5302f345d8eSLuigi Rizzo 5312f345d8eSLuigi Rizzo /* size of the packet descriptor array in a transmit queue */ 5322f345d8eSLuigi Rizzo #define OCE_TX_RING_SIZE 2048 5332f345d8eSLuigi Rizzo #define OCE_RX_RING_SIZE 1024 5342f345d8eSLuigi Rizzo #define OCE_WQ_PACKET_ARRAY_SIZE (OCE_TX_RING_SIZE/2) 5352f345d8eSLuigi Rizzo #define OCE_RQ_PACKET_ARRAY_SIZE (OCE_RX_RING_SIZE) 5362f345d8eSLuigi Rizzo 5372f345d8eSLuigi Rizzo struct oce_dev; 5382f345d8eSLuigi Rizzo 5392f345d8eSLuigi Rizzo enum eq_len { 5402f345d8eSLuigi Rizzo EQ_LEN_256 = 256, 5412f345d8eSLuigi Rizzo EQ_LEN_512 = 512, 5422f345d8eSLuigi Rizzo EQ_LEN_1024 = 1024, 5432f345d8eSLuigi Rizzo EQ_LEN_2048 = 2048, 5442f345d8eSLuigi Rizzo EQ_LEN_4096 = 4096 5452f345d8eSLuigi Rizzo }; 5462f345d8eSLuigi Rizzo 5472f345d8eSLuigi Rizzo enum eqe_size { 5482f345d8eSLuigi Rizzo EQE_SIZE_4 = 4, 5492f345d8eSLuigi Rizzo EQE_SIZE_16 = 16 5502f345d8eSLuigi Rizzo }; 5512f345d8eSLuigi Rizzo 5522f345d8eSLuigi Rizzo enum qtype { 5532f345d8eSLuigi Rizzo QTYPE_EQ, 5542f345d8eSLuigi Rizzo QTYPE_MQ, 5552f345d8eSLuigi Rizzo QTYPE_WQ, 5562f345d8eSLuigi Rizzo QTYPE_RQ, 5572f345d8eSLuigi Rizzo QTYPE_CQ, 5582f345d8eSLuigi Rizzo QTYPE_RSS 5592f345d8eSLuigi Rizzo }; 5602f345d8eSLuigi Rizzo 5612f345d8eSLuigi Rizzo typedef enum qstate_e { 5622f345d8eSLuigi Rizzo QDELETED = 0x0, 5632f345d8eSLuigi Rizzo QCREATED = 0x1 5642f345d8eSLuigi Rizzo } qstate_t; 5652f345d8eSLuigi Rizzo 5662f345d8eSLuigi Rizzo struct eq_config { 5672f345d8eSLuigi Rizzo enum eq_len q_len; 5682f345d8eSLuigi Rizzo enum eqe_size item_size; 5692f345d8eSLuigi Rizzo uint32_t q_vector_num; 5702f345d8eSLuigi Rizzo uint8_t min_eqd; 5712f345d8eSLuigi Rizzo uint8_t max_eqd; 5722f345d8eSLuigi Rizzo uint8_t cur_eqd; 5732f345d8eSLuigi Rizzo uint8_t pad; 5742f345d8eSLuigi Rizzo }; 5752f345d8eSLuigi Rizzo 5762f345d8eSLuigi Rizzo struct oce_eq { 5772f345d8eSLuigi Rizzo uint32_t eq_id; 5782f345d8eSLuigi Rizzo void *parent; 5792f345d8eSLuigi Rizzo void *cb_context; 5802f345d8eSLuigi Rizzo oce_ring_buffer_t *ring; 5812f345d8eSLuigi Rizzo uint32_t ref_count; 5822f345d8eSLuigi Rizzo qstate_t qstate; 5832f345d8eSLuigi Rizzo struct oce_cq *cq[OCE_MAX_CQ_EQ]; 5842f345d8eSLuigi Rizzo int cq_valid; 5852f345d8eSLuigi Rizzo struct eq_config eq_cfg; 5862f345d8eSLuigi Rizzo int vector; 587*cdaba892SXin LI uint64_t intr; 5882f345d8eSLuigi Rizzo }; 5892f345d8eSLuigi Rizzo 5902f345d8eSLuigi Rizzo enum cq_len { 5912f345d8eSLuigi Rizzo CQ_LEN_256 = 256, 5922f345d8eSLuigi Rizzo CQ_LEN_512 = 512, 5932f345d8eSLuigi Rizzo CQ_LEN_1024 = 1024 5942f345d8eSLuigi Rizzo }; 5952f345d8eSLuigi Rizzo 5962f345d8eSLuigi Rizzo struct cq_config { 5972f345d8eSLuigi Rizzo enum cq_len q_len; 5982f345d8eSLuigi Rizzo uint32_t item_size; 5992f345d8eSLuigi Rizzo boolean_t is_eventable; 6002f345d8eSLuigi Rizzo boolean_t sol_eventable; 6012f345d8eSLuigi Rizzo boolean_t nodelay; 6022f345d8eSLuigi Rizzo uint16_t dma_coalescing; 6032f345d8eSLuigi Rizzo }; 6042f345d8eSLuigi Rizzo 6052f345d8eSLuigi Rizzo typedef uint16_t(*cq_handler_t) (void *arg1); 6062f345d8eSLuigi Rizzo 6072f345d8eSLuigi Rizzo struct oce_cq { 6082f345d8eSLuigi Rizzo uint32_t cq_id; 6092f345d8eSLuigi Rizzo void *parent; 6102f345d8eSLuigi Rizzo struct oce_eq *eq; 6112f345d8eSLuigi Rizzo cq_handler_t cq_handler; 6122f345d8eSLuigi Rizzo void *cb_arg; 6132f345d8eSLuigi Rizzo oce_ring_buffer_t *ring; 6142f345d8eSLuigi Rizzo qstate_t qstate; 6152f345d8eSLuigi Rizzo struct cq_config cq_cfg; 6162f345d8eSLuigi Rizzo uint32_t ref_count; 6172f345d8eSLuigi Rizzo }; 6182f345d8eSLuigi Rizzo 6192f345d8eSLuigi Rizzo 6202f345d8eSLuigi Rizzo struct mq_config { 6212f345d8eSLuigi Rizzo uint32_t eqd; 6222f345d8eSLuigi Rizzo uint8_t q_len; 6232f345d8eSLuigi Rizzo uint8_t pad[3]; 6242f345d8eSLuigi Rizzo }; 6252f345d8eSLuigi Rizzo 6262f345d8eSLuigi Rizzo 6272f345d8eSLuigi Rizzo struct oce_mq { 6282f345d8eSLuigi Rizzo void *parent; 6292f345d8eSLuigi Rizzo oce_ring_buffer_t *ring; 6302f345d8eSLuigi Rizzo uint32_t mq_id; 6312f345d8eSLuigi Rizzo struct oce_cq *cq; 6322f345d8eSLuigi Rizzo struct oce_cq *async_cq; 6332f345d8eSLuigi Rizzo uint32_t mq_free; 6342f345d8eSLuigi Rizzo qstate_t qstate; 6352f345d8eSLuigi Rizzo struct mq_config cfg; 6362f345d8eSLuigi Rizzo }; 6372f345d8eSLuigi Rizzo 6382f345d8eSLuigi Rizzo struct oce_mbx_ctx { 6392f345d8eSLuigi Rizzo struct oce_mbx *mbx; 6402f345d8eSLuigi Rizzo void (*cb) (void *ctx); 6412f345d8eSLuigi Rizzo void *cb_ctx; 6422f345d8eSLuigi Rizzo }; 6432f345d8eSLuigi Rizzo 6442f345d8eSLuigi Rizzo struct wq_config { 6452f345d8eSLuigi Rizzo uint8_t wq_type; 6462f345d8eSLuigi Rizzo uint16_t buf_size; 6472f345d8eSLuigi Rizzo uint8_t pad[1]; 6482f345d8eSLuigi Rizzo uint32_t q_len; 6492f345d8eSLuigi Rizzo uint16_t pd_id; 6502f345d8eSLuigi Rizzo uint16_t pci_fn_num; 6512f345d8eSLuigi Rizzo uint32_t eqd; /* interrupt delay */ 6522f345d8eSLuigi Rizzo uint32_t nbufs; 6532f345d8eSLuigi Rizzo uint32_t nhdl; 6542f345d8eSLuigi Rizzo }; 6552f345d8eSLuigi Rizzo 6562f345d8eSLuigi Rizzo struct oce_tx_queue_stats { 6572f345d8eSLuigi Rizzo uint64_t tx_pkts; 6582f345d8eSLuigi Rizzo uint64_t tx_bytes; 6592f345d8eSLuigi Rizzo uint32_t tx_reqs; 6602f345d8eSLuigi Rizzo uint32_t tx_stops; /* number of times TX Q was stopped */ 6612f345d8eSLuigi Rizzo uint32_t tx_wrbs; 6622f345d8eSLuigi Rizzo uint32_t tx_compl; 6632f345d8eSLuigi Rizzo uint32_t tx_rate; 6642f345d8eSLuigi Rizzo uint32_t ipv6_ext_hdr_tx_drop; 6652f345d8eSLuigi Rizzo }; 6662f345d8eSLuigi Rizzo 6672f345d8eSLuigi Rizzo struct oce_wq { 6682f345d8eSLuigi Rizzo OCE_LOCK tx_lock; 6692f345d8eSLuigi Rizzo void *parent; 6702f345d8eSLuigi Rizzo oce_ring_buffer_t *ring; 6712f345d8eSLuigi Rizzo struct oce_cq *cq; 6722f345d8eSLuigi Rizzo bus_dma_tag_t tag; 6732f345d8eSLuigi Rizzo struct oce_packet_desc pckts[OCE_WQ_PACKET_ARRAY_SIZE]; 6742f345d8eSLuigi Rizzo uint32_t packets_in; 6752f345d8eSLuigi Rizzo uint32_t packets_out; 6762f345d8eSLuigi Rizzo uint32_t wqm_used; 6772f345d8eSLuigi Rizzo boolean_t resched; 6782f345d8eSLuigi Rizzo uint32_t wq_free; 6792f345d8eSLuigi Rizzo uint32_t tx_deferd; 6802f345d8eSLuigi Rizzo uint32_t pkt_drops; 6812f345d8eSLuigi Rizzo qstate_t qstate; 6822f345d8eSLuigi Rizzo uint16_t wq_id; 6832f345d8eSLuigi Rizzo struct wq_config cfg; 6842f345d8eSLuigi Rizzo int queue_index; 6852f345d8eSLuigi Rizzo struct oce_tx_queue_stats tx_stats; 6862f345d8eSLuigi Rizzo struct buf_ring *br; 6872f345d8eSLuigi Rizzo struct task txtask; 6882f345d8eSLuigi Rizzo }; 6892f345d8eSLuigi Rizzo 6902f345d8eSLuigi Rizzo struct rq_config { 6912f345d8eSLuigi Rizzo uint32_t q_len; 6922f345d8eSLuigi Rizzo uint32_t frag_size; 6932f345d8eSLuigi Rizzo uint32_t mtu; 6942f345d8eSLuigi Rizzo uint32_t if_id; 6952f345d8eSLuigi Rizzo uint32_t is_rss_queue; 6962f345d8eSLuigi Rizzo uint32_t eqd; 6972f345d8eSLuigi Rizzo uint32_t nbufs; 6982f345d8eSLuigi Rizzo }; 6992f345d8eSLuigi Rizzo 7002f345d8eSLuigi Rizzo struct oce_rx_queue_stats { 7012f345d8eSLuigi Rizzo uint32_t rx_post_fail; 7022f345d8eSLuigi Rizzo uint32_t rx_ucast_pkts; 7032f345d8eSLuigi Rizzo uint32_t rx_compl; 7042f345d8eSLuigi Rizzo uint64_t rx_bytes; 7052f345d8eSLuigi Rizzo uint64_t rx_bytes_prev; 7062f345d8eSLuigi Rizzo uint64_t rx_pkts; 7072f345d8eSLuigi Rizzo uint32_t rx_rate; 7082f345d8eSLuigi Rizzo uint32_t rx_mcast_pkts; 7092f345d8eSLuigi Rizzo uint32_t rxcp_err; 7102f345d8eSLuigi Rizzo uint32_t rx_frags; 7112f345d8eSLuigi Rizzo uint32_t prev_rx_frags; 7122f345d8eSLuigi Rizzo uint32_t rx_fps; 7132f345d8eSLuigi Rizzo }; 7142f345d8eSLuigi Rizzo 7152f345d8eSLuigi Rizzo 7162f345d8eSLuigi Rizzo struct oce_rq { 7172f345d8eSLuigi Rizzo struct rq_config cfg; 7182f345d8eSLuigi Rizzo uint32_t rq_id; 7192f345d8eSLuigi Rizzo int queue_index; 7202f345d8eSLuigi Rizzo uint32_t rss_cpuid; 7212f345d8eSLuigi Rizzo void *parent; 7222f345d8eSLuigi Rizzo oce_ring_buffer_t *ring; 7232f345d8eSLuigi Rizzo struct oce_cq *cq; 7242f345d8eSLuigi Rizzo void *pad1; 7252f345d8eSLuigi Rizzo bus_dma_tag_t tag; 7262f345d8eSLuigi Rizzo struct oce_packet_desc pckts[OCE_RQ_PACKET_ARRAY_SIZE]; 7272f345d8eSLuigi Rizzo uint32_t packets_in; 7282f345d8eSLuigi Rizzo uint32_t packets_out; 7292f345d8eSLuigi Rizzo uint32_t pending; 7302f345d8eSLuigi Rizzo #ifdef notdef 7312f345d8eSLuigi Rizzo struct mbuf *head; 7322f345d8eSLuigi Rizzo struct mbuf *tail; 7332f345d8eSLuigi Rizzo int fragsleft; 7342f345d8eSLuigi Rizzo #endif 7352f345d8eSLuigi Rizzo qstate_t qstate; 7362f345d8eSLuigi Rizzo OCE_LOCK rx_lock; 7372f345d8eSLuigi Rizzo struct oce_rx_queue_stats rx_stats; 7382f345d8eSLuigi Rizzo struct lro_ctrl lro; 7392f345d8eSLuigi Rizzo int lro_pkts_queued; 7402f345d8eSLuigi Rizzo 7412f345d8eSLuigi Rizzo }; 7422f345d8eSLuigi Rizzo 7432f345d8eSLuigi Rizzo struct link_status { 7442f345d8eSLuigi Rizzo uint8_t physical_port; 7452f345d8eSLuigi Rizzo uint8_t mac_duplex; 7462f345d8eSLuigi Rizzo uint8_t mac_speed; 7472f345d8eSLuigi Rizzo uint8_t mac_fault; 7482f345d8eSLuigi Rizzo uint8_t mgmt_mac_duplex; 7492f345d8eSLuigi Rizzo uint8_t mgmt_mac_speed; 7502f345d8eSLuigi Rizzo uint16_t qos_link_speed; 7512f345d8eSLuigi Rizzo uint32_t logical_link_status; 7522f345d8eSLuigi Rizzo }; 7532f345d8eSLuigi Rizzo 7542f345d8eSLuigi Rizzo 7552f345d8eSLuigi Rizzo 7562f345d8eSLuigi Rizzo #define OCE_FLAGS_PCIX 0x00000001 7572f345d8eSLuigi Rizzo #define OCE_FLAGS_PCIE 0x00000002 7582f345d8eSLuigi Rizzo #define OCE_FLAGS_MSI_CAPABLE 0x00000004 7592f345d8eSLuigi Rizzo #define OCE_FLAGS_MSIX_CAPABLE 0x00000008 7602f345d8eSLuigi Rizzo #define OCE_FLAGS_USING_MSI 0x00000010 7612f345d8eSLuigi Rizzo #define OCE_FLAGS_USING_MSIX 0x00000020 7622f345d8eSLuigi Rizzo #define OCE_FLAGS_FUNCRESET_RQD 0x00000040 7632f345d8eSLuigi Rizzo #define OCE_FLAGS_VIRTUAL_PORT 0x00000080 7642f345d8eSLuigi Rizzo #define OCE_FLAGS_MBOX_ENDIAN_RQD 0x00000100 7652f345d8eSLuigi Rizzo #define OCE_FLAGS_BE3 0x00000200 7662f345d8eSLuigi Rizzo #define OCE_FLAGS_XE201 0x00000400 7672f345d8eSLuigi Rizzo #define OCE_FLAGS_BE2 0x00000800 7682f345d8eSLuigi Rizzo 7692f345d8eSLuigi Rizzo #define OCE_DEV_BE2_CFG_BAR 1 7702f345d8eSLuigi Rizzo #define OCE_DEV_CFG_BAR 0 7712f345d8eSLuigi Rizzo #define OCE_PCI_CSR_BAR 2 7722f345d8eSLuigi Rizzo #define OCE_PCI_DB_BAR 4 7732f345d8eSLuigi Rizzo 7742f345d8eSLuigi Rizzo typedef struct oce_softc { 7752f345d8eSLuigi Rizzo device_t dev; 7762f345d8eSLuigi Rizzo OCE_LOCK dev_lock; 7772f345d8eSLuigi Rizzo 7782f345d8eSLuigi Rizzo uint32_t flags; 7792f345d8eSLuigi Rizzo 7802f345d8eSLuigi Rizzo uint32_t pcie_link_speed; 7812f345d8eSLuigi Rizzo uint32_t pcie_link_width; 7822f345d8eSLuigi Rizzo 7832f345d8eSLuigi Rizzo uint8_t fn; /* PCI function number */ 7842f345d8eSLuigi Rizzo 7852f345d8eSLuigi Rizzo struct resource *devcfg_res; 7862f345d8eSLuigi Rizzo bus_space_tag_t devcfg_btag; 7872f345d8eSLuigi Rizzo bus_space_handle_t devcfg_bhandle; 7882f345d8eSLuigi Rizzo void *devcfg_vhandle; 7892f345d8eSLuigi Rizzo 7902f345d8eSLuigi Rizzo struct resource *csr_res; 7912f345d8eSLuigi Rizzo bus_space_tag_t csr_btag; 7922f345d8eSLuigi Rizzo bus_space_handle_t csr_bhandle; 7932f345d8eSLuigi Rizzo void *csr_vhandle; 7942f345d8eSLuigi Rizzo 7952f345d8eSLuigi Rizzo struct resource *db_res; 7962f345d8eSLuigi Rizzo bus_space_tag_t db_btag; 7972f345d8eSLuigi Rizzo bus_space_handle_t db_bhandle; 7982f345d8eSLuigi Rizzo void *db_vhandle; 7992f345d8eSLuigi Rizzo 8002f345d8eSLuigi Rizzo OCE_INTR_INFO intrs[OCE_MAX_EQ]; 8012f345d8eSLuigi Rizzo int intr_count; 8022f345d8eSLuigi Rizzo 8032f345d8eSLuigi Rizzo struct ifnet *ifp; 8042f345d8eSLuigi Rizzo 8052f345d8eSLuigi Rizzo struct ifmedia media; 8062f345d8eSLuigi Rizzo uint8_t link_status; 8072f345d8eSLuigi Rizzo uint8_t link_speed; 8082f345d8eSLuigi Rizzo uint8_t duplex; 8092f345d8eSLuigi Rizzo uint32_t qos_link_speed; 8102f345d8eSLuigi Rizzo uint32_t speed; 8112f345d8eSLuigi Rizzo 8122f345d8eSLuigi Rizzo char fw_version[32]; 8132f345d8eSLuigi Rizzo struct mac_address_format macaddr; 8142f345d8eSLuigi Rizzo 8152f345d8eSLuigi Rizzo OCE_DMA_MEM bsmbx; 8162f345d8eSLuigi Rizzo OCE_LOCK bmbx_lock; 8172f345d8eSLuigi Rizzo 8182f345d8eSLuigi Rizzo uint32_t config_number; 8192f345d8eSLuigi Rizzo uint32_t asic_revision; 8202f345d8eSLuigi Rizzo uint32_t port_id; 8212f345d8eSLuigi Rizzo uint32_t function_mode; 8222f345d8eSLuigi Rizzo uint32_t function_caps; 8232f345d8eSLuigi Rizzo uint32_t max_tx_rings; 8242f345d8eSLuigi Rizzo uint32_t max_rx_rings; 8252f345d8eSLuigi Rizzo 8262f345d8eSLuigi Rizzo struct oce_wq *wq[OCE_MAX_WQ]; /* TX work queues */ 8272f345d8eSLuigi Rizzo struct oce_rq *rq[OCE_MAX_RQ]; /* RX work queues */ 8282f345d8eSLuigi Rizzo struct oce_cq *cq[OCE_MAX_CQ]; /* Completion queues */ 8292f345d8eSLuigi Rizzo struct oce_eq *eq[OCE_MAX_EQ]; /* Event queues */ 8302f345d8eSLuigi Rizzo struct oce_mq *mq; /* Mailbox queue */ 8312f345d8eSLuigi Rizzo 8322f345d8eSLuigi Rizzo uint32_t neqs; 8332f345d8eSLuigi Rizzo uint32_t ncqs; 8342f345d8eSLuigi Rizzo uint32_t nrqs; 8352f345d8eSLuigi Rizzo uint32_t nwqs; 8362f345d8eSLuigi Rizzo 8372f345d8eSLuigi Rizzo uint32_t tx_ring_size; 8382f345d8eSLuigi Rizzo uint32_t rx_ring_size; 8392f345d8eSLuigi Rizzo uint32_t rq_frag_size; 8402f345d8eSLuigi Rizzo uint32_t rss_enable; 8412f345d8eSLuigi Rizzo 8422f345d8eSLuigi Rizzo uint32_t if_id; /* interface ID */ 8432f345d8eSLuigi Rizzo uint32_t nifs; /* number of adapter interfaces, 0 or 1 */ 8442f345d8eSLuigi Rizzo uint32_t pmac_id; /* PMAC id */ 8452f345d8eSLuigi Rizzo 8462f345d8eSLuigi Rizzo uint32_t if_cap_flags; 8472f345d8eSLuigi Rizzo 8482f345d8eSLuigi Rizzo uint32_t flow_control; 8492f345d8eSLuigi Rizzo uint32_t promisc; 850*cdaba892SXin LI 851*cdaba892SXin LI struct oce_aic_obj aic_obj[OCE_MAX_EQ]; 852*cdaba892SXin LI 8532f345d8eSLuigi Rizzo /*Vlan Filtering related */ 8542f345d8eSLuigi Rizzo eventhandler_tag vlan_attach; 8552f345d8eSLuigi Rizzo eventhandler_tag vlan_detach; 8562f345d8eSLuigi Rizzo uint16_t vlans_added; 8572f345d8eSLuigi Rizzo uint8_t vlan_tag[MAX_VLANS]; 8582f345d8eSLuigi Rizzo /*stats */ 8592f345d8eSLuigi Rizzo OCE_DMA_MEM stats_mem; 8602f345d8eSLuigi Rizzo struct oce_drv_stats oce_stats_info; 8612f345d8eSLuigi Rizzo struct callout timer; 8622f345d8eSLuigi Rizzo int8_t be3_native; 863*cdaba892SXin LI uint16_t qnq_debug_event; 864*cdaba892SXin LI uint16_t qnqid; 865*cdaba892SXin LI uint16_t pvid; 8662f345d8eSLuigi Rizzo 8672f345d8eSLuigi Rizzo } OCE_SOFTC, *POCE_SOFTC; 8682f345d8eSLuigi Rizzo 8692f345d8eSLuigi Rizzo 8702f345d8eSLuigi Rizzo 8712f345d8eSLuigi Rizzo /************************************************** 8722f345d8eSLuigi Rizzo * BUS memory read/write macros 8732f345d8eSLuigi Rizzo * BE3: accesses three BAR spaces (CFG, CSR, DB) 8742f345d8eSLuigi Rizzo * Lancer: accesses one BAR space (CFG) 8752f345d8eSLuigi Rizzo **************************************************/ 8762f345d8eSLuigi Rizzo #define OCE_READ_REG32(sc, space, o) \ 8772f345d8eSLuigi Rizzo ((IS_BE(sc)) ? (bus_space_read_4((sc)->space##_btag, \ 8782f345d8eSLuigi Rizzo (sc)->space##_bhandle,o)) \ 8792f345d8eSLuigi Rizzo : (bus_space_read_4((sc)->devcfg_btag, \ 8802f345d8eSLuigi Rizzo (sc)->devcfg_bhandle,o))) 8812f345d8eSLuigi Rizzo #define OCE_READ_REG16(sc, space, o) \ 8822f345d8eSLuigi Rizzo ((IS_BE(sc)) ? (bus_space_read_2((sc)->space##_btag, \ 8832f345d8eSLuigi Rizzo (sc)->space##_bhandle,o)) \ 8842f345d8eSLuigi Rizzo : (bus_space_read_2((sc)->devcfg_btag, \ 8852f345d8eSLuigi Rizzo (sc)->devcfg_bhandle,o))) 8862f345d8eSLuigi Rizzo #define OCE_READ_REG8(sc, space, o) \ 8872f345d8eSLuigi Rizzo ((IS_BE(sc)) ? (bus_space_read_1((sc)->space##_btag, \ 8882f345d8eSLuigi Rizzo (sc)->space##_bhandle,o)) \ 8892f345d8eSLuigi Rizzo : (bus_space_read_1((sc)->devcfg_btag, \ 8902f345d8eSLuigi Rizzo (sc)->devcfg_bhandle,o))) 8912f345d8eSLuigi Rizzo 8922f345d8eSLuigi Rizzo #define OCE_WRITE_REG32(sc, space, o, v) \ 8932f345d8eSLuigi Rizzo ((IS_BE(sc)) ? (bus_space_write_4((sc)->space##_btag, \ 8942f345d8eSLuigi Rizzo (sc)->space##_bhandle,o,v)) \ 8952f345d8eSLuigi Rizzo : (bus_space_write_4((sc)->devcfg_btag, \ 8962f345d8eSLuigi Rizzo (sc)->devcfg_bhandle,o,v))) 8972f345d8eSLuigi Rizzo #define OCE_WRITE_REG16(sc, space, o, v) \ 8982f345d8eSLuigi Rizzo ((IS_BE(sc)) ? (bus_space_write_2((sc)->space##_btag, \ 8992f345d8eSLuigi Rizzo (sc)->space##_bhandle,o,v)) \ 9002f345d8eSLuigi Rizzo : (bus_space_write_2((sc)->devcfg_btag, \ 9012f345d8eSLuigi Rizzo (sc)->devcfg_bhandle,o,v))) 9022f345d8eSLuigi Rizzo #define OCE_WRITE_REG8(sc, space, o, v) \ 9032f345d8eSLuigi Rizzo ((IS_BE(sc)) ? (bus_space_write_1((sc)->space##_btag, \ 9042f345d8eSLuigi Rizzo (sc)->space##_bhandle,o,v)) \ 9052f345d8eSLuigi Rizzo : (bus_space_write_1((sc)->devcfg_btag, \ 9062f345d8eSLuigi Rizzo (sc)->devcfg_bhandle,o,v))) 9072f345d8eSLuigi Rizzo 9082f345d8eSLuigi Rizzo 9092f345d8eSLuigi Rizzo /*********************************************************** 9102f345d8eSLuigi Rizzo * DMA memory functions 9112f345d8eSLuigi Rizzo ***********************************************************/ 9122f345d8eSLuigi Rizzo #define oce_dma_sync(d, f) bus_dmamap_sync((d)->tag, (d)->map, f) 9132f345d8eSLuigi Rizzo int oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags); 9142f345d8eSLuigi Rizzo void oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma); 9152f345d8eSLuigi Rizzo void oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error); 9162f345d8eSLuigi Rizzo void oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring); 9172f345d8eSLuigi Rizzo oce_ring_buffer_t *oce_create_ring_buffer(POCE_SOFTC sc, 9182f345d8eSLuigi Rizzo uint32_t q_len, uint32_t num_entries); 9192f345d8eSLuigi Rizzo /************************************************************ 9202f345d8eSLuigi Rizzo * oce_hw_xxx functions 9212f345d8eSLuigi Rizzo ************************************************************/ 9222f345d8eSLuigi Rizzo int oce_clear_rx_buf(struct oce_rq *rq); 9232f345d8eSLuigi Rizzo int oce_hw_pci_alloc(POCE_SOFTC sc); 9242f345d8eSLuigi Rizzo int oce_hw_init(POCE_SOFTC sc); 9252f345d8eSLuigi Rizzo int oce_hw_start(POCE_SOFTC sc); 9262f345d8eSLuigi Rizzo int oce_create_nw_interface(POCE_SOFTC sc); 9272f345d8eSLuigi Rizzo int oce_pci_soft_reset(POCE_SOFTC sc); 9282f345d8eSLuigi Rizzo int oce_hw_update_multicast(POCE_SOFTC sc); 9292f345d8eSLuigi Rizzo void oce_delete_nw_interface(POCE_SOFTC sc); 9302f345d8eSLuigi Rizzo void oce_hw_shutdown(POCE_SOFTC sc); 9312f345d8eSLuigi Rizzo void oce_hw_intr_enable(POCE_SOFTC sc); 9322f345d8eSLuigi Rizzo void oce_hw_intr_disable(POCE_SOFTC sc); 9332f345d8eSLuigi Rizzo void oce_hw_pci_free(POCE_SOFTC sc); 9342f345d8eSLuigi Rizzo 9352f345d8eSLuigi Rizzo /*********************************************************** 9362f345d8eSLuigi Rizzo * oce_queue_xxx functions 9372f345d8eSLuigi Rizzo ***********************************************************/ 9382f345d8eSLuigi Rizzo int oce_queue_init_all(POCE_SOFTC sc); 9392f345d8eSLuigi Rizzo int oce_start_rq(struct oce_rq *rq); 9402f345d8eSLuigi Rizzo int oce_start_wq(struct oce_wq *wq); 9412f345d8eSLuigi Rizzo int oce_start_mq(struct oce_mq *mq); 9422f345d8eSLuigi Rizzo int oce_start_rx(POCE_SOFTC sc); 9432f345d8eSLuigi Rizzo void oce_arm_eq(POCE_SOFTC sc, 9442f345d8eSLuigi Rizzo int16_t qid, int npopped, uint32_t rearm, uint32_t clearint); 9452f345d8eSLuigi Rizzo void oce_queue_release_all(POCE_SOFTC sc); 9462f345d8eSLuigi Rizzo void oce_arm_cq(POCE_SOFTC sc, int16_t qid, int npopped, uint32_t rearm); 9472f345d8eSLuigi Rizzo void oce_drain_eq(struct oce_eq *eq); 9482f345d8eSLuigi Rizzo void oce_drain_mq_cq(void *arg); 9492f345d8eSLuigi Rizzo void oce_drain_rq_cq(struct oce_rq *rq); 9502f345d8eSLuigi Rizzo void oce_drain_wq_cq(struct oce_wq *wq); 9512f345d8eSLuigi Rizzo 9522f345d8eSLuigi Rizzo uint32_t oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list); 9532f345d8eSLuigi Rizzo 9542f345d8eSLuigi Rizzo /*********************************************************** 9552f345d8eSLuigi Rizzo * cleanup functions 9562f345d8eSLuigi Rizzo ***********************************************************/ 9572f345d8eSLuigi Rizzo void oce_stop_rx(POCE_SOFTC sc); 9582f345d8eSLuigi Rizzo void oce_intr_free(POCE_SOFTC sc); 9592f345d8eSLuigi Rizzo void oce_free_posted_rxbuf(struct oce_rq *rq); 9609bd3250aSLuigi Rizzo #if defined(INET6) || defined(INET) 9619bd3250aSLuigi Rizzo void oce_free_lro(POCE_SOFTC sc); 9629bd3250aSLuigi Rizzo #endif 9632f345d8eSLuigi Rizzo 9642f345d8eSLuigi Rizzo 9652f345d8eSLuigi Rizzo /************************************************************ 9662f345d8eSLuigi Rizzo * Mailbox functions 9672f345d8eSLuigi Rizzo ************************************************************/ 9682f345d8eSLuigi Rizzo int oce_fw_clean(POCE_SOFTC sc); 9692f345d8eSLuigi Rizzo int oce_reset_fun(POCE_SOFTC sc); 9702f345d8eSLuigi Rizzo int oce_mbox_init(POCE_SOFTC sc); 9712f345d8eSLuigi Rizzo int oce_mbox_dispatch(POCE_SOFTC sc, uint32_t tmo_sec); 9722f345d8eSLuigi Rizzo int oce_get_fw_version(POCE_SOFTC sc); 9739bd3250aSLuigi Rizzo int oce_first_mcc_cmd(POCE_SOFTC sc); 9749bd3250aSLuigi Rizzo 9752f345d8eSLuigi Rizzo int oce_read_mac_addr(POCE_SOFTC sc, uint32_t if_id, uint8_t perm, 9762f345d8eSLuigi Rizzo uint8_t type, struct mac_address_format *mac); 9772f345d8eSLuigi Rizzo int oce_get_fw_config(POCE_SOFTC sc); 9782f345d8eSLuigi Rizzo int oce_if_create(POCE_SOFTC sc, uint32_t cap_flags, uint32_t en_flags, 9792f345d8eSLuigi Rizzo uint16_t vlan_tag, uint8_t *mac_addr, uint32_t *if_id); 9802f345d8eSLuigi Rizzo int oce_if_del(POCE_SOFTC sc, uint32_t if_id); 9812f345d8eSLuigi Rizzo int oce_config_vlan(POCE_SOFTC sc, uint32_t if_id, 9822f345d8eSLuigi Rizzo struct normal_vlan *vtag_arr, uint8_t vtag_cnt, 9832f345d8eSLuigi Rizzo uint32_t untagged, uint32_t enable_promisc); 9842f345d8eSLuigi Rizzo int oce_set_flow_control(POCE_SOFTC sc, uint32_t flow_control); 9852f345d8eSLuigi Rizzo int oce_config_nic_rss(POCE_SOFTC sc, uint32_t if_id, uint16_t enable_rss); 9862f345d8eSLuigi Rizzo int oce_rxf_set_promiscuous(POCE_SOFTC sc, uint32_t enable); 9872f345d8eSLuigi Rizzo int oce_set_common_iface_rx_filter(POCE_SOFTC sc, POCE_DMA_MEM sgl); 9882f345d8eSLuigi Rizzo int oce_get_link_status(POCE_SOFTC sc, struct link_status *link); 9892f345d8eSLuigi Rizzo int oce_mbox_get_nic_stats_v0(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 9902f345d8eSLuigi Rizzo int oce_mbox_get_nic_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem); 9912f345d8eSLuigi Rizzo int oce_mbox_get_pport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 9922f345d8eSLuigi Rizzo uint32_t reset_stats); 9932f345d8eSLuigi Rizzo int oce_mbox_get_vport_stats(POCE_SOFTC sc, POCE_DMA_MEM pstats_dma_mem, 9942f345d8eSLuigi Rizzo uint32_t req_size, uint32_t reset_stats); 9952f345d8eSLuigi Rizzo int oce_update_multicast(POCE_SOFTC sc, POCE_DMA_MEM pdma_mem); 9962f345d8eSLuigi Rizzo int oce_pass_through_mbox(POCE_SOFTC sc, POCE_DMA_MEM dma_mem, uint32_t req_size); 9972f345d8eSLuigi Rizzo int oce_mbox_macaddr_del(POCE_SOFTC sc, uint32_t if_id, uint32_t pmac_id); 9982f345d8eSLuigi Rizzo int oce_mbox_macaddr_add(POCE_SOFTC sc, uint8_t *mac_addr, 9992f345d8eSLuigi Rizzo uint32_t if_id, uint32_t *pmac_id); 10002f345d8eSLuigi Rizzo int oce_mbox_cmd_test_loopback(POCE_SOFTC sc, uint32_t port_num, 10012f345d8eSLuigi Rizzo uint32_t loopback_type, uint32_t pkt_size, uint32_t num_pkts, 10022f345d8eSLuigi Rizzo uint64_t pattern); 10032f345d8eSLuigi Rizzo 10042f345d8eSLuigi Rizzo int oce_mbox_cmd_set_loopback(POCE_SOFTC sc, uint8_t port_num, 10052f345d8eSLuigi Rizzo uint8_t loopback_type, uint8_t enable); 10062f345d8eSLuigi Rizzo 10072f345d8eSLuigi Rizzo int oce_mbox_check_native_mode(POCE_SOFTC sc); 10082f345d8eSLuigi Rizzo int oce_mbox_post(POCE_SOFTC sc, 10092f345d8eSLuigi Rizzo struct oce_mbx *mbx, struct oce_mbx_ctx *mbxctx); 10102f345d8eSLuigi Rizzo int oce_mbox_write_flashrom(POCE_SOFTC sc, uint32_t optype,uint32_t opcode, 10112f345d8eSLuigi Rizzo POCE_DMA_MEM pdma_mem, uint32_t num_bytes); 10122f345d8eSLuigi Rizzo int oce_mbox_lancer_write_flashrom(POCE_SOFTC sc, uint32_t data_size, 10132f345d8eSLuigi Rizzo uint32_t data_offset,POCE_DMA_MEM pdma_mem, 10142f345d8eSLuigi Rizzo uint32_t *written_data, uint32_t *additional_status); 10152f345d8eSLuigi Rizzo 10162f345d8eSLuigi Rizzo int oce_mbox_get_flashrom_crc(POCE_SOFTC sc, uint8_t *flash_crc, 10172f345d8eSLuigi Rizzo uint32_t offset, uint32_t optype); 10182f345d8eSLuigi Rizzo int oce_mbox_get_phy_info(POCE_SOFTC sc, struct oce_phy_info *phy_info); 10192f345d8eSLuigi Rizzo int oce_mbox_create_rq(struct oce_rq *rq); 10202f345d8eSLuigi Rizzo int oce_mbox_create_wq(struct oce_wq *wq); 10212f345d8eSLuigi Rizzo int oce_mbox_create_eq(struct oce_eq *eq); 10222f345d8eSLuigi Rizzo int oce_mbox_cq_create(struct oce_cq *cq, uint32_t ncoalesce, 10232f345d8eSLuigi Rizzo uint32_t is_eventable); 1024*cdaba892SXin LI int oce_mbox_read_transrecv_data(POCE_SOFTC sc, uint32_t page_num); 1025*cdaba892SXin LI void oce_mbox_eqd_modify_periodic(POCE_SOFTC sc, struct oce_set_eqd *set_eqd, 1026*cdaba892SXin LI int num); 10272f345d8eSLuigi Rizzo void mbx_common_req_hdr_init(struct mbx_hdr *hdr, 10282f345d8eSLuigi Rizzo uint8_t dom, 10292f345d8eSLuigi Rizzo uint8_t port, 10302f345d8eSLuigi Rizzo uint8_t subsys, 10312f345d8eSLuigi Rizzo uint8_t opcode, 10322f345d8eSLuigi Rizzo uint32_t timeout, uint32_t pyld_len, 10332f345d8eSLuigi Rizzo uint8_t version); 10342f345d8eSLuigi Rizzo 10352f345d8eSLuigi Rizzo 10362f345d8eSLuigi Rizzo uint16_t oce_mq_handler(void *arg); 10372f345d8eSLuigi Rizzo 10382f345d8eSLuigi Rizzo /************************************************************ 10392f345d8eSLuigi Rizzo * Transmit functions 10402f345d8eSLuigi Rizzo ************************************************************/ 10412f345d8eSLuigi Rizzo uint16_t oce_wq_handler(void *arg); 10422f345d8eSLuigi Rizzo void oce_start(struct ifnet *ifp); 10432f345d8eSLuigi Rizzo void oce_tx_task(void *arg, int npending); 10442f345d8eSLuigi Rizzo 10452f345d8eSLuigi Rizzo /************************************************************ 10462f345d8eSLuigi Rizzo * Receive functions 10472f345d8eSLuigi Rizzo ************************************************************/ 10482f345d8eSLuigi Rizzo int oce_alloc_rx_bufs(struct oce_rq *rq, int count); 10492f345d8eSLuigi Rizzo uint16_t oce_rq_handler(void *arg); 10502f345d8eSLuigi Rizzo 10512f345d8eSLuigi Rizzo 10522f345d8eSLuigi Rizzo /* Sysctl functions */ 10532f345d8eSLuigi Rizzo void oce_add_sysctls(POCE_SOFTC sc); 10542f345d8eSLuigi Rizzo void oce_refresh_queue_stats(POCE_SOFTC sc); 10552f345d8eSLuigi Rizzo int oce_refresh_nic_stats(POCE_SOFTC sc); 10562f345d8eSLuigi Rizzo int oce_stats_init(POCE_SOFTC sc); 10572f345d8eSLuigi Rizzo void oce_stats_free(POCE_SOFTC sc); 10582f345d8eSLuigi Rizzo 10592f345d8eSLuigi Rizzo /* Capabilities */ 10602f345d8eSLuigi Rizzo #define OCE_MODCAP_RSS 1 10612f345d8eSLuigi Rizzo #define OCE_MAX_RSP_HANDLED 64 10622f345d8eSLuigi Rizzo extern uint32_t oce_max_rsp_handled; /* max responses */ 10632f345d8eSLuigi Rizzo 10642f345d8eSLuigi Rizzo #define OCE_MAC_LOOPBACK 0x0 10652f345d8eSLuigi Rizzo #define OCE_PHY_LOOPBACK 0x1 10662f345d8eSLuigi Rizzo #define OCE_ONE_PORT_EXT_LOOPBACK 0x2 10672f345d8eSLuigi Rizzo #define OCE_NO_LOOPBACK 0xff 10682f345d8eSLuigi Rizzo 10692f345d8eSLuigi Rizzo #define atomic_inc_32(x) atomic_add_32(x, 1) 10702f345d8eSLuigi Rizzo #define atomic_dec_32(x) atomic_subtract_32(x, 1) 10712f345d8eSLuigi Rizzo 10722f345d8eSLuigi Rizzo #define LE_64(x) htole64(x) 10732f345d8eSLuigi Rizzo #define LE_32(x) htole32(x) 10742f345d8eSLuigi Rizzo #define LE_16(x) htole16(x) 10752f345d8eSLuigi Rizzo #define DW_SWAP(x, l) 10762f345d8eSLuigi Rizzo #define IS_ALIGNED(x,a) ((x % a) == 0) 10772f345d8eSLuigi Rizzo #define ADDR_HI(x) ((uint32_t)((uint64_t)(x) >> 32)) 10782f345d8eSLuigi Rizzo #define ADDR_LO(x) ((uint32_t)((uint64_t)(x) & 0xffffffff)); 10792f345d8eSLuigi Rizzo 10802f345d8eSLuigi Rizzo #define IF_LRO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_LRO) ? 1:0) 10812f345d8eSLuigi Rizzo #define IF_LSO_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_TSO4) ? 1:0) 10822f345d8eSLuigi Rizzo #define IF_CSUM_ENABLED(sc) (((sc)->ifp->if_capenable & IFCAP_HWCSUM) ? 1:0) 10832f345d8eSLuigi Rizzo 10842f345d8eSLuigi Rizzo #define OCE_LOG2(x) (oce_highbit(x)) 10852f345d8eSLuigi Rizzo static inline uint32_t oce_highbit(uint32_t x) 10862f345d8eSLuigi Rizzo { 10872f345d8eSLuigi Rizzo int i; 10882f345d8eSLuigi Rizzo int c; 10892f345d8eSLuigi Rizzo int b; 10902f345d8eSLuigi Rizzo 10912f345d8eSLuigi Rizzo c = 0; 10922f345d8eSLuigi Rizzo b = 0; 10932f345d8eSLuigi Rizzo 10942f345d8eSLuigi Rizzo for (i = 0; i < 32; i++) { 10952f345d8eSLuigi Rizzo if ((1 << i) & x) { 10962f345d8eSLuigi Rizzo c++; 10972f345d8eSLuigi Rizzo b = i; 10982f345d8eSLuigi Rizzo } 10992f345d8eSLuigi Rizzo } 11002f345d8eSLuigi Rizzo 11012f345d8eSLuigi Rizzo if (c == 1) 11022f345d8eSLuigi Rizzo return b; 11032f345d8eSLuigi Rizzo 11042f345d8eSLuigi Rizzo return 0; 11052f345d8eSLuigi Rizzo } 11062f345d8eSLuigi Rizzo 1107*cdaba892SXin LI #define TRANSCEIVER_DATA_NUM_ELE 64 1108*cdaba892SXin LI #define TRANSCEIVER_DATA_SIZE 256 1109*cdaba892SXin LI #define TRANSCEIVER_A0_SIZE 128 1110*cdaba892SXin LI #define TRANSCEIVER_A2_SIZE 128 1111*cdaba892SXin LI #define PAGE_NUM_A0 0xa0 1112*cdaba892SXin LI #define PAGE_NUM_A2 0xa2 1113*cdaba892SXin LI #define IS_QNQ_OR_UMC(sc) ((sc->pvid && (sc->function_mode & FNM_UMC_MODE ))\ 1114*cdaba892SXin LI || (sc->qnqid && (sc->function_mode & FNM_FLEX10_MODE))) 1115*cdaba892SXin LI 1116