1 /*- 2 * Copyright (C) 2013 Emulex 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Emulex Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * Contact Information: 32 * freebsd-drivers@emulex.com 33 * 34 * Emulex 35 * 3333 Susan Street 36 * Costa Mesa, CA 92626 37 */ 38 39 /* $FreeBSD$ */ 40 41 #include <sys/types.h> 42 43 #undef _BIG_ENDIAN /* TODO */ 44 #pragma pack(1) 45 46 #define OC_CNA_GEN2 0x2 47 #define OC_CNA_GEN3 0x3 48 #define DEVID_TIGERSHARK 0x700 49 #define DEVID_TOMCAT 0x710 50 51 /* PCI CSR offsets */ 52 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 53 #define PCICFG_SEMAPHORE 0xbc 54 #define PCICFG_SOFT_RESET 0x5c 55 #define PCICFG_UE_STATUS_HI_MASK 0xac 56 #define PCICFG_UE_STATUS_LO_MASK 0xa8 57 #define PCICFG_ONLINE0 0xb0 58 #define PCICFG_ONLINE1 0xb4 59 #define INTR_EN 0x20000000 60 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 61 62 63 /********* UE Status and Mask Registers ***/ 64 #define PCICFG_UE_STATUS_LOW 0xA0 65 #define PCICFG_UE_STATUS_HIGH 0xA4 66 #define PCICFG_UE_STATUS_LOW_MASK 0xA8 67 68 /* Lancer SLIPORT registers */ 69 #define SLIPORT_STATUS_OFFSET 0x404 70 #define SLIPORT_CONTROL_OFFSET 0x408 71 #define SLIPORT_ERROR1_OFFSET 0x40C 72 #define SLIPORT_ERROR2_OFFSET 0x410 73 #define PHYSDEV_CONTROL_OFFSET 0x414 74 75 #define SLIPORT_STATUS_ERR_MASK 0x80000000 76 #define SLIPORT_STATUS_DIP_MASK 0x02000000 77 #define SLIPORT_STATUS_RN_MASK 0x01000000 78 #define SLIPORT_STATUS_RDY_MASK 0x00800000 79 #define SLI_PORT_CONTROL_IP_MASK 0x08000000 80 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 81 #define PHYSDEV_CONTROL_DD_MASK 0x00000004 82 #define PHYSDEV_CONTROL_INP_MASK 0x40000000 83 84 #define SLIPORT_ERROR_NO_RESOURCE1 0x2 85 #define SLIPORT_ERROR_NO_RESOURCE2 0x9 86 /* CSR register offsets */ 87 #define MPU_EP_CONTROL 0 88 #define MPU_EP_SEMAPHORE_BE3 0xac 89 #define MPU_EP_SEMAPHORE_XE201 0x400 90 #define MPU_EP_SEMAPHORE_SH 0x94 91 #define PCICFG_INTR_CTRL 0xfc 92 #define HOSTINTR_MASK (1 << 29) 93 #define HOSTINTR_PFUNC_SHIFT 26 94 #define HOSTINTR_PFUNC_MASK 7 95 96 /* POST status reg struct */ 97 #define POST_STAGE_POWER_ON_RESET 0x00 98 #define POST_STAGE_AWAITING_HOST_RDY 0x01 99 #define POST_STAGE_HOST_RDY 0x02 100 #define POST_STAGE_CHIP_RESET 0x03 101 #define POST_STAGE_ARMFW_READY 0xc000 102 #define POST_STAGE_ARMFW_UE 0xf000 103 104 /* DOORBELL registers */ 105 #define PD_RXULP_DB 0x0100 106 #define PD_TXULP_DB 0x0060 107 #define DB_RQ_ID_MASK 0x3FF 108 109 #define PD_CQ_DB 0x0120 110 #define PD_EQ_DB PD_CQ_DB 111 #define PD_MPU_MBOX_DB 0x0160 112 #define PD_MQ_DB 0x0140 113 114 /* EQE completion types */ 115 #define EQ_MINOR_CODE_COMPLETION 0x00 116 #define EQ_MINOR_CODE_OTHER 0x01 117 #define EQ_MAJOR_CODE_COMPLETION 0x00 118 119 /* Link Status field values */ 120 #define PHY_LINK_FAULT_NONE 0x0 121 #define PHY_LINK_FAULT_LOCAL 0x01 122 #define PHY_LINK_FAULT_REMOTE 0x02 123 124 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 125 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 126 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 127 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 128 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 129 130 #define PHY_LINK_DUPLEX_NONE 0x0 131 #define PHY_LINK_DUPLEX_HALF 0x1 132 #define PHY_LINK_DUPLEX_FULL 0x2 133 134 #define NTWK_PORT_A 0x0 /* (Port A) */ 135 #define NTWK_PORT_B 0x1 /* (Port B) */ 136 137 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 138 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 139 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 140 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 141 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 142 143 /* Hardware Address types */ 144 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 145 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 146 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 147 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 148 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 149 150 /* CREATE_IFACE capability and cap_en flags */ 151 #define MBX_RX_IFACE_FLAGS_RSS 0x4 152 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 153 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 154 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 155 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 156 #define MBX_RX_IFACE_FLAGS_VLAN 0x100 157 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 158 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400 159 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800 160 #define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000 161 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000 162 #define MBX_RX_IFACE_FLAGS_HDS 0x4000 163 #define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000 164 #define MBX_RX_IFACE_FLAGS_VMQ 0x10000 165 #define MBX_RX_IFACE_FLAGS_NETQ 0x20000 166 #define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000 167 #define MBX_RX_IFACE_FLAGS_LSO 0x80000 168 #define MBX_RX_IFACE_FLAGS_LRO 0x100000 169 170 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 171 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 172 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 173 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 174 175 #define MBX_DB_READY_BIT 0x1 176 #define MBX_DB_HI_BIT 0x2 177 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 178 #define ASYNC_EVENT_LINK_UP 0x1 179 #define ASYNC_EVENT_LINK_DOWN 0x0 180 #define ASYNC_EVENT_GRP5 0x5 181 #define ASYNC_EVENT_CODE_DEBUG 0x6 182 #define ASYNC_EVENT_PVID_STATE 0x3 183 #define ASYNC_EVENT_DEBUG_QNQ 0x1 184 #define ASYNC_EVENT_CODE_SLIPORT 0x11 185 #define VLAN_VID_MASK 0x0FFF 186 187 /* port link_status */ 188 #define ASYNC_EVENT_LOGICAL 0x02 189 190 /* Logical Link Status */ 191 #define NTWK_LOGICAL_LINK_DOWN 0 192 #define NTWK_LOGICAL_LINK_UP 1 193 194 /* Rx filter bits */ 195 #define NTWK_RX_FILTER_IP_CKSUM 0x1 196 #define NTWK_RX_FILTER_TCP_CKSUM 0x2 197 #define NTWK_RX_FILTER_UDP_CKSUM 0x4 198 #define NTWK_RX_FILTER_STRIP_CRC 0x8 199 200 /* max SGE per mbx */ 201 #define MAX_MBX_SGE 19 202 203 /* Max multicast filter size*/ 204 #define OCE_MAX_MC_FILTER_SIZE 64 205 206 /* PCI SLI (Service Level Interface) capabilities register */ 207 #define OCE_INTF_REG_OFFSET 0x58 208 #define OCE_INTF_VALID_SIG 6 /* register's signature */ 209 #define OCE_INTF_FUNC_RESET_REQD 1 210 #define OCE_INTF_HINT1_NOHINT 0 211 #define OCE_INTF_HINT1_SEMAINIT 1 212 #define OCE_INTF_HINT1_STATCTRL 2 213 #define OCE_INTF_IF_TYPE_0 0 214 #define OCE_INTF_IF_TYPE_1 1 215 #define OCE_INTF_IF_TYPE_2 2 216 #define OCE_INTF_IF_TYPE_3 3 217 #define OCE_INTF_SLI_REV3 3 /* not supported by driver */ 218 #define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */ 219 #define OCE_INTF_PHYS_FUNC 0 220 #define OCE_INTF_VIRT_FUNC 1 221 #define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */ 222 #define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */ 223 #define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */ 224 #define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */ 225 226 #define NIC_WQE_SIZE 16 227 #define NIC_UNICAST 0x00 228 #define NIC_MULTICAST 0x01 229 #define NIC_BROADCAST 0x02 230 231 #define NIC_HDS_NO_SPLIT 0x00 232 #define NIC_HDS_SPLIT_L3PL 0x01 233 #define NIC_HDS_SPLIT_L4PL 0x02 234 235 #define NIC_WQ_TYPE_FORWARDING 0x01 236 #define NIC_WQ_TYPE_STANDARD 0x02 237 #define NIC_WQ_TYPE_LOW_LATENCY 0x04 238 239 #define OCE_RESET_STATS 1 240 #define OCE_RETAIN_STATS 0 241 #define OCE_TXP_SW_SZ 48 242 243 typedef union pci_sli_intf_u { 244 uint32_t dw0; 245 struct { 246 #ifdef _BIG_ENDIAN 247 uint32_t sli_valid:3; 248 uint32_t sli_hint2:5; 249 uint32_t sli_hint1:8; 250 uint32_t sli_if_type:4; 251 uint32_t sli_family:4; 252 uint32_t sli_rev:4; 253 uint32_t rsv0:3; 254 uint32_t sli_func_type:1; 255 #else 256 uint32_t sli_func_type:1; 257 uint32_t rsv0:3; 258 uint32_t sli_rev:4; 259 uint32_t sli_family:4; 260 uint32_t sli_if_type:4; 261 uint32_t sli_hint1:8; 262 uint32_t sli_hint2:5; 263 uint32_t sli_valid:3; 264 #endif 265 } bits; 266 } pci_sli_intf_t; 267 268 269 270 /* physical address structure to be used in MBX */ 271 struct phys_addr { 272 /* dw0 */ 273 uint32_t lo; 274 /* dw1 */ 275 uint32_t hi; 276 }; 277 278 279 280 typedef union pcicfg_intr_ctl_u { 281 uint32_t dw0; 282 struct { 283 #ifdef _BIG_ENDIAN 284 uint32_t winselect:2; 285 uint32_t hostintr:1; 286 uint32_t pfnum:3; 287 uint32_t vf_cev_int_line_en:1; 288 uint32_t winaddr:23; 289 uint32_t membarwinen:1; 290 #else 291 uint32_t membarwinen:1; 292 uint32_t winaddr:23; 293 uint32_t vf_cev_int_line_en:1; 294 uint32_t pfnum:3; 295 uint32_t hostintr:1; 296 uint32_t winselect:2; 297 #endif 298 } bits; 299 } pcicfg_intr_ctl_t; 300 301 302 303 304 typedef union pcicfg_semaphore_u { 305 uint32_t dw0; 306 struct { 307 #ifdef _BIG_ENDIAN 308 uint32_t rsvd:31; 309 uint32_t lock:1; 310 #else 311 uint32_t lock:1; 312 uint32_t rsvd:31; 313 #endif 314 } bits; 315 } pcicfg_semaphore_t; 316 317 318 319 320 typedef union pcicfg_soft_reset_u { 321 uint32_t dw0; 322 struct { 323 #ifdef _BIG_ENDIAN 324 uint32_t nec_ll_rcvdetect:8; 325 uint32_t dbg_all_reqs_62_49:14; 326 uint32_t scratchpad0:1; 327 uint32_t exception_oe:1; 328 uint32_t soft_reset:1; 329 uint32_t rsvd0:7; 330 #else 331 uint32_t rsvd0:7; 332 uint32_t soft_reset:1; 333 uint32_t exception_oe:1; 334 uint32_t scratchpad0:1; 335 uint32_t dbg_all_reqs_62_49:14; 336 uint32_t nec_ll_rcvdetect:8; 337 #endif 338 } bits; 339 } pcicfg_soft_reset_t; 340 341 342 343 344 typedef union pcicfg_online1_u { 345 uint32_t dw0; 346 struct { 347 #ifdef _BIG_ENDIAN 348 uint32_t host8_online:1; 349 uint32_t host7_online:1; 350 uint32_t host6_online:1; 351 uint32_t host5_online:1; 352 uint32_t host4_online:1; 353 uint32_t host3_online:1; 354 uint32_t host2_online:1; 355 uint32_t ipc_online:1; 356 uint32_t arm_online:1; 357 uint32_t txp_online:1; 358 uint32_t xaui_online:1; 359 uint32_t rxpp_online:1; 360 uint32_t txpb_online:1; 361 uint32_t rr_online:1; 362 uint32_t pmem_online:1; 363 uint32_t pctl1_online:1; 364 uint32_t pctl0_online:1; 365 uint32_t pcs1online_online:1; 366 uint32_t mpu_iram_online:1; 367 uint32_t pcs0online_online:1; 368 uint32_t mgmt_mac_online:1; 369 uint32_t lpcmemhost_online:1; 370 #else 371 uint32_t lpcmemhost_online:1; 372 uint32_t mgmt_mac_online:1; 373 uint32_t pcs0online_online:1; 374 uint32_t mpu_iram_online:1; 375 uint32_t pcs1online_online:1; 376 uint32_t pctl0_online:1; 377 uint32_t pctl1_online:1; 378 uint32_t pmem_online:1; 379 uint32_t rr_online:1; 380 uint32_t txpb_online:1; 381 uint32_t rxpp_online:1; 382 uint32_t xaui_online:1; 383 uint32_t txp_online:1; 384 uint32_t arm_online:1; 385 uint32_t ipc_online:1; 386 uint32_t host2_online:1; 387 uint32_t host3_online:1; 388 uint32_t host4_online:1; 389 uint32_t host5_online:1; 390 uint32_t host6_online:1; 391 uint32_t host7_online:1; 392 uint32_t host8_online:1; 393 #endif 394 } bits; 395 } pcicfg_online1_t; 396 397 398 399 typedef union mpu_ep_semaphore_u { 400 uint32_t dw0; 401 struct { 402 #ifdef _BIG_ENDIAN 403 uint32_t error:1; 404 uint32_t backup_fw:1; 405 uint32_t iscsi_no_ip:1; 406 uint32_t iscsi_ip_conflict:1; 407 uint32_t option_rom_installed:1; 408 uint32_t iscsi_drv_loaded:1; 409 uint32_t rsvd0:10; 410 uint32_t stage:16; 411 #else 412 uint32_t stage:16; 413 uint32_t rsvd0:10; 414 uint32_t iscsi_drv_loaded:1; 415 uint32_t option_rom_installed:1; 416 uint32_t iscsi_ip_conflict:1; 417 uint32_t iscsi_no_ip:1; 418 uint32_t backup_fw:1; 419 uint32_t error:1; 420 #endif 421 } bits; 422 } mpu_ep_semaphore_t; 423 424 425 426 427 typedef union mpu_ep_control_u { 428 uint32_t dw0; 429 struct { 430 #ifdef _BIG_ENDIAN 431 uint32_t cpu_reset:1; 432 uint32_t rsvd1:15; 433 uint32_t ep_ram_init_status:1; 434 uint32_t rsvd0:12; 435 uint32_t m2_rxpbuf:1; 436 uint32_t m1_rxpbuf:1; 437 uint32_t m0_rxpbuf:1; 438 #else 439 uint32_t m0_rxpbuf:1; 440 uint32_t m1_rxpbuf:1; 441 uint32_t m2_rxpbuf:1; 442 uint32_t rsvd0:12; 443 uint32_t ep_ram_init_status:1; 444 uint32_t rsvd1:15; 445 uint32_t cpu_reset:1; 446 #endif 447 } bits; 448 } mpu_ep_control_t; 449 450 451 452 453 /* RX doorbell */ 454 typedef union pd_rxulp_db_u { 455 uint32_t dw0; 456 struct { 457 #ifdef _BIG_ENDIAN 458 uint32_t num_posted:8; 459 uint32_t invalidate:1; 460 uint32_t rsvd1:13; 461 uint32_t qid:10; 462 #else 463 uint32_t qid:10; 464 uint32_t rsvd1:13; 465 uint32_t invalidate:1; 466 uint32_t num_posted:8; 467 #endif 468 } bits; 469 } pd_rxulp_db_t; 470 471 472 /* TX doorbell */ 473 typedef union pd_txulp_db_u { 474 uint32_t dw0; 475 struct { 476 #ifdef _BIG_ENDIAN 477 uint32_t rsvd1:2; 478 uint32_t num_posted:14; 479 uint32_t rsvd0:6; 480 uint32_t qid:10; 481 #else 482 uint32_t qid:10; 483 uint32_t rsvd0:6; 484 uint32_t num_posted:14; 485 uint32_t rsvd1:2; 486 #endif 487 } bits; 488 } pd_txulp_db_t; 489 490 /* CQ doorbell */ 491 typedef union cq_db_u { 492 uint32_t dw0; 493 struct { 494 #ifdef _BIG_ENDIAN 495 uint32_t rsvd1:2; 496 uint32_t rearm:1; 497 uint32_t num_popped:13; 498 uint32_t rsvd0:5; 499 uint32_t event:1; 500 uint32_t qid:10; 501 #else 502 uint32_t qid:10; 503 uint32_t event:1; 504 uint32_t rsvd0:5; 505 uint32_t num_popped:13; 506 uint32_t rearm:1; 507 uint32_t rsvd1:2; 508 #endif 509 } bits; 510 } cq_db_t; 511 512 /* EQ doorbell */ 513 typedef union eq_db_u { 514 uint32_t dw0; 515 struct { 516 #ifdef _BIG_ENDIAN 517 uint32_t rsvd1:2; 518 uint32_t rearm:1; 519 uint32_t num_popped:13; 520 uint32_t rsvd0:5; 521 uint32_t event:1; 522 uint32_t clrint:1; 523 uint32_t qid:9; 524 #else 525 uint32_t qid:9; 526 uint32_t clrint:1; 527 uint32_t event:1; 528 uint32_t rsvd0:5; 529 uint32_t num_popped:13; 530 uint32_t rearm:1; 531 uint32_t rsvd1:2; 532 #endif 533 } bits; 534 } eq_db_t; 535 536 /* bootstrap mbox doorbell */ 537 typedef union pd_mpu_mbox_db_u { 538 uint32_t dw0; 539 struct { 540 #ifdef _BIG_ENDIAN 541 uint32_t address:30; 542 uint32_t hi:1; 543 uint32_t ready:1; 544 #else 545 uint32_t ready:1; 546 uint32_t hi:1; 547 uint32_t address:30; 548 #endif 549 } bits; 550 } pd_mpu_mbox_db_t; 551 552 /* MQ ring doorbell */ 553 typedef union pd_mq_db_u { 554 uint32_t dw0; 555 struct { 556 #ifdef _BIG_ENDIAN 557 uint32_t rsvd1:2; 558 uint32_t num_posted:14; 559 uint32_t rsvd0:5; 560 uint32_t mq_id:11; 561 #else 562 uint32_t mq_id:11; 563 uint32_t rsvd0:5; 564 uint32_t num_posted:14; 565 uint32_t rsvd1:2; 566 #endif 567 } bits; 568 } pd_mq_db_t; 569 570 /* 571 * Event Queue Entry 572 */ 573 struct oce_eqe { 574 uint32_t evnt; 575 }; 576 577 /* MQ scatter gather entry. Array of these make an SGL */ 578 struct oce_mq_sge { 579 uint32_t pa_lo; 580 uint32_t pa_hi; 581 uint32_t length; 582 }; 583 584 /* 585 * payload can contain an SGL or an embedded array of upto 59 dwords 586 */ 587 struct oce_mbx_payload { 588 union { 589 union { 590 struct oce_mq_sge sgl[MAX_MBX_SGE]; 591 uint32_t embedded[59]; 592 } u1; 593 uint32_t dw[59]; 594 } u0; 595 }; 596 597 /* 598 * MQ MBX structure 599 */ 600 struct oce_mbx { 601 union { 602 struct { 603 #ifdef _BIG_ENDIAN 604 uint32_t special:8; 605 uint32_t rsvd1:16; 606 uint32_t sge_count:5; 607 uint32_t rsvd0:2; 608 uint32_t embedded:1; 609 #else 610 uint32_t embedded:1; 611 uint32_t rsvd0:2; 612 uint32_t sge_count:5; 613 uint32_t rsvd1:16; 614 uint32_t special:8; 615 #endif 616 } s; 617 uint32_t dw0; 618 } u0; 619 620 uint32_t payload_length; 621 uint32_t tag[2]; 622 uint32_t rsvd2[1]; 623 struct oce_mbx_payload payload; 624 }; 625 626 /* completion queue entry for MQ */ 627 struct oce_mq_cqe { 628 union { 629 struct { 630 #ifdef _BIG_ENDIAN 631 /* dw0 */ 632 uint32_t extended_status:16; 633 uint32_t completion_status:16; 634 /* dw1 dw2 */ 635 uint32_t mq_tag[2]; 636 /* dw3 */ 637 uint32_t valid:1; 638 uint32_t async_event:1; 639 uint32_t hpi_buffer_cmpl:1; 640 uint32_t completed:1; 641 uint32_t consumed:1; 642 uint32_t rsvd0:3; 643 uint32_t async_type:8; 644 uint32_t event_type:8; 645 uint32_t rsvd1:8; 646 #else 647 /* dw0 */ 648 uint32_t completion_status:16; 649 uint32_t extended_status:16; 650 /* dw1 dw2 */ 651 uint32_t mq_tag[2]; 652 /* dw3 */ 653 uint32_t rsvd1:8; 654 uint32_t event_type:8; 655 uint32_t async_type:8; 656 uint32_t rsvd0:3; 657 uint32_t consumed:1; 658 uint32_t completed:1; 659 uint32_t hpi_buffer_cmpl:1; 660 uint32_t async_event:1; 661 uint32_t valid:1; 662 #endif 663 } s; 664 uint32_t dw[4]; 665 } u0; 666 }; 667 668 /* Mailbox Completion Status Codes */ 669 enum MBX_COMPLETION_STATUS { 670 MBX_CQE_STATUS_SUCCESS = 0x00, 671 MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01, 672 MBX_CQE_STATUS_INVALID_PARAMETER = 0x02, 673 MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03, 674 MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04, 675 MBX_CQE_STATUS_DMA_FAILED = 0x05 676 }; 677 678 struct oce_async_cqe_link_state { 679 union { 680 struct { 681 #ifdef _BIG_ENDIAN 682 /* dw0 */ 683 uint8_t speed; 684 uint8_t duplex; 685 uint8_t link_status; 686 uint8_t phy_port; 687 /* dw1 */ 688 uint16_t qos_link_speed; 689 uint8_t rsvd0; 690 uint8_t fault; 691 /* dw2 */ 692 uint32_t event_tag; 693 /* dw3 */ 694 uint32_t valid:1; 695 uint32_t async_event:1; 696 uint32_t rsvd2:6; 697 uint32_t event_type:8; 698 uint32_t event_code:8; 699 uint32_t rsvd1:8; 700 #else 701 /* dw0 */ 702 uint8_t phy_port; 703 uint8_t link_status; 704 uint8_t duplex; 705 uint8_t speed; 706 /* dw1 */ 707 uint8_t fault; 708 uint8_t rsvd0; 709 uint16_t qos_link_speed; 710 /* dw2 */ 711 uint32_t event_tag; 712 /* dw3 */ 713 uint32_t rsvd1:8; 714 uint32_t event_code:8; 715 uint32_t event_type:8; 716 uint32_t rsvd2:6; 717 uint32_t async_event:1; 718 uint32_t valid:1; 719 #endif 720 } s; 721 uint32_t dw[4]; 722 } u0; 723 }; 724 725 726 /* PVID aync event */ 727 struct oce_async_event_grp5_pvid_state { 728 uint8_t enabled; 729 uint8_t rsvd0; 730 uint16_t tag; 731 uint32_t event_tag; 732 uint32_t rsvd1; 733 uint32_t code; 734 }; 735 736 /* async event indicating outer VLAN tag in QnQ */ 737 struct oce_async_event_qnq { 738 uint8_t valid; /* Indicates if outer VLAN is valid */ 739 uint8_t rsvd0; 740 uint16_t vlan_tag; 741 uint32_t event_tag; 742 uint8_t rsvd1[4]; 743 uint32_t code; 744 } ; 745 746 747 typedef union oce_mq_ext_ctx_u { 748 uint32_t dw[6]; 749 struct { 750 #ifdef _BIG_ENDIAN 751 /* dw0 */ 752 uint32_t dw4rsvd1:16; 753 uint32_t num_pages:16; 754 /* dw1 */ 755 uint32_t async_evt_bitmap; 756 /* dw2 */ 757 uint32_t cq_id:10; 758 uint32_t dw5rsvd2:2; 759 uint32_t ring_size:4; 760 uint32_t dw5rsvd1:16; 761 /* dw3 */ 762 uint32_t valid:1; 763 uint32_t dw6rsvd1:31; 764 /* dw4 */ 765 uint32_t dw7rsvd1:21; 766 uint32_t async_cq_id:10; 767 uint32_t async_cq_valid:1; 768 #else 769 /* dw0 */ 770 uint32_t num_pages:16; 771 uint32_t dw4rsvd1:16; 772 /* dw1 */ 773 uint32_t async_evt_bitmap; 774 /* dw2 */ 775 uint32_t dw5rsvd1:16; 776 uint32_t ring_size:4; 777 uint32_t dw5rsvd2:2; 778 uint32_t cq_id:10; 779 /* dw3 */ 780 uint32_t dw6rsvd1:31; 781 uint32_t valid:1; 782 /* dw4 */ 783 uint32_t async_cq_valid:1; 784 uint32_t async_cq_id:10; 785 uint32_t dw7rsvd1:21; 786 #endif 787 /* dw5 */ 788 uint32_t dw8rsvd1; 789 } v0; 790 struct { 791 #ifdef _BIG_ENDIAN 792 /* dw0 */ 793 uint32_t cq_id:16; 794 uint32_t num_pages:16; 795 /* dw1 */ 796 uint32_t async_evt_bitmap; 797 /* dw2 */ 798 uint32_t dw5rsvd2:12; 799 uint32_t ring_size:4; 800 uint32_t async_cq_id:16; 801 /* dw3 */ 802 uint32_t valid:1; 803 uint32_t dw6rsvd1:31; 804 /* dw4 */ 805 uint32_t dw7rsvd1:31; 806 uint32_t async_cq_valid:1; 807 #else 808 /* dw0 */ 809 uint32_t num_pages:16; 810 uint32_t cq_id:16; 811 /* dw1 */ 812 uint32_t async_evt_bitmap; 813 /* dw2 */ 814 uint32_t async_cq_id:16; 815 uint32_t ring_size:4; 816 uint32_t dw5rsvd2:12; 817 /* dw3 */ 818 uint32_t dw6rsvd1:31; 819 uint32_t valid:1; 820 /* dw4 */ 821 uint32_t async_cq_valid:1; 822 uint32_t dw7rsvd1:31; 823 #endif 824 /* dw5 */ 825 uint32_t dw8rsvd1; 826 } v1; 827 828 } oce_mq_ext_ctx_t; 829 830 831 /* MQ mailbox structure */ 832 struct oce_bmbx { 833 struct oce_mbx mbx; 834 struct oce_mq_cqe cqe; 835 }; 836 837 /* ---[ MBXs start here ]---------------------------------------------- */ 838 /* MBXs sub system codes */ 839 enum MBX_SUBSYSTEM_CODES { 840 MBX_SUBSYSTEM_RSVD = 0, 841 MBX_SUBSYSTEM_COMMON = 1, 842 MBX_SUBSYSTEM_COMMON_ISCSI = 2, 843 MBX_SUBSYSTEM_NIC = 3, 844 MBX_SUBSYSTEM_TOE = 4, 845 MBX_SUBSYSTEM_PXE_UNDI = 5, 846 MBX_SUBSYSTEM_ISCSI_INI = 6, 847 MBX_SUBSYSTEM_ISCSI_TGT = 7, 848 MBX_SUBSYSTEM_MILI_PTL = 8, 849 MBX_SUBSYSTEM_MILI_TMD = 9, 850 MBX_SUBSYSTEM_RDMA = 10, 851 MBX_SUBSYSTEM_LOWLEVEL = 11, 852 MBX_SUBSYSTEM_LRO = 13, 853 IOCBMBX_SUBSYSTEM_DCBX = 15, 854 IOCBMBX_SUBSYSTEM_DIAG = 16, 855 IOCBMBX_SUBSYSTEM_VENDOR = 17 856 }; 857 858 /* common ioctl opcodes */ 859 enum COMMON_SUBSYSTEM_OPCODES { 860 /* These opcodes are common to both networking and storage PCI functions 861 * They are used to reserve resources and configure CNA. These opcodes 862 * all use the MBX_SUBSYSTEM_COMMON subsystem code. 863 */ 864 OPCODE_COMMON_QUERY_IFACE_MAC = 1, 865 OPCODE_COMMON_SET_IFACE_MAC = 2, 866 OPCODE_COMMON_SET_IFACE_MULTICAST = 3, 867 OPCODE_COMMON_CONFIG_IFACE_VLAN = 4, 868 OPCODE_COMMON_QUERY_LINK_CONFIG = 5, 869 OPCODE_COMMON_READ_FLASHROM = 6, 870 OPCODE_COMMON_WRITE_FLASHROM = 7, 871 OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8, 872 OPCODE_COMMON_CREATE_CQ = 12, 873 OPCODE_COMMON_CREATE_EQ = 13, 874 OPCODE_COMMON_CREATE_MQ = 21, 875 OPCODE_COMMON_GET_QOS = 27, 876 OPCODE_COMMON_SET_QOS = 28, 877 OPCODE_COMMON_READ_EPROM = 30, 878 OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32, 879 OPCODE_COMMON_NOP = 33, 880 OPCODE_COMMON_SET_IFACE_RX_FILTER = 34, 881 OPCODE_COMMON_GET_FW_VERSION = 35, 882 OPCODE_COMMON_SET_FLOW_CONTROL = 36, 883 OPCODE_COMMON_GET_FLOW_CONTROL = 37, 884 OPCODE_COMMON_SET_FRAME_SIZE = 39, 885 OPCODE_COMMON_MODIFY_EQ_DELAY = 41, 886 OPCODE_COMMON_CREATE_IFACE = 50, 887 OPCODE_COMMON_DESTROY_IFACE = 51, 888 OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52, 889 OPCODE_COMMON_DESTROY_MQ = 53, 890 OPCODE_COMMON_DESTROY_CQ = 54, 891 OPCODE_COMMON_DESTROY_EQ = 55, 892 OPCODE_COMMON_UPLOAD_TCP = 56, 893 OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57, 894 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58, 895 OPCODE_COMMON_ADD_IFACE_MAC = 59, 896 OPCODE_COMMON_DEL_IFACE_MAC = 60, 897 OPCODE_COMMON_FUNCTION_RESET = 61, 898 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62, 899 OPCODE_COMMON_GET_BOOT_CONFIG = 66, 900 OPCPDE_COMMON_SET_BOOT_CONFIG = 67, 901 OPCODE_COMMON_SET_BEACON_CONFIG = 69, 902 OPCODE_COMMON_GET_BEACON_CONFIG = 70, 903 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71, 904 OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73, 905 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76, 906 OPCODE_COMMON_GET_PORT_NAME = 77, 907 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78, 908 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79, 909 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80, 910 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81, 911 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82, 912 OPCODE_COMMON_GET_RESET_NEEDED = 84, 913 OPCODE_COMMON_GET_SERIAL_NUMBER = 85, 914 OPCODE_COMMON_GET_NCSI_CONFIG = 86, 915 OPCODE_COMMON_SET_NCSI_CONFIG = 87, 916 OPCODE_COMMON_CREATE_MQ_EXT = 90, 917 OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100, 918 OPCODE_COMMON_SET_VF_PORT_TYPE = 101, 919 OPCODE_COMMON_GET_PHY_CONFIG = 102, 920 OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103, 921 OPCODE_COMMON_GET_ADAPTER_ID = 110, 922 OPCODE_COMMON_GET_UPGRADE_FEATURES = 111, 923 OPCODE_COMMON_GET_INSTALLED_FEATURES = 112, 924 OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113, 925 OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114, 926 OPCODE_COMMON_SEND_ACTIVATION = 115, 927 OPCODE_COMMON_RESET_LICENSES = 116, 928 OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121, 929 OPCODE_COMMON_QUERY_TCB = 144, 930 OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145, 931 OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146, 932 OPCODE_COMMON_GET_IFACE_MAC_LIST = 147, 933 OPCODE_COMMON_SET_IFACE_MAC_LIST = 148, 934 OPCODE_COMMON_MODIFY_CQ = 149, 935 OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150, 936 OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151, 937 OPCODE_COMMON_GET_HSW_CONFIG = 152, 938 OPCODE_COMMON_SET_HSW_CONFIG = 153, 939 OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154, 940 OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155, 941 OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156, 942 OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157, 943 OPCODE_COMMON_SET_DIAG_REGISTERS = 158, 944 OPCODE_COMMON_GET_FUNCTION_CONFIG = 160, 945 OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161, 946 OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162, 947 OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163, 948 OPCODE_COMMON_GET_PROFILE_CONFIG = 164, 949 OPCODE_COMMON_SET_PROFILE_CONFIG = 165, 950 OPCODE_COMMON_GET_PROFILE_LIST = 166, 951 OPCODE_COMMON_GET_ACTIVE_PROFILE = 167, 952 OPCODE_COMMON_SET_ACTIVE_PROFILE = 168, 953 OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170, 954 OPCODE_COMMON_READ_OBJECT = 171, 955 OPCODE_COMMON_WRITE_OBJECT = 172 956 }; 957 958 /* common ioctl header */ 959 #define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */ 960 #define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */ 961 #define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */ 962 struct mbx_hdr { 963 union { 964 uint32_t dw[4]; 965 struct { 966 #ifdef _BIG_ENDIAN 967 /* dw 0 */ 968 uint32_t domain:8; 969 uint32_t port_number:8; 970 uint32_t subsystem:8; 971 uint32_t opcode:8; 972 /* dw 1 */ 973 uint32_t timeout; 974 /* dw 2 */ 975 uint32_t request_length; 976 /* dw 3 */ 977 uint32_t rsvd0:24; 978 uint32_t version:8; 979 #else 980 /* dw 0 */ 981 uint32_t opcode:8; 982 uint32_t subsystem:8; 983 uint32_t port_number:8; 984 uint32_t domain:8; 985 /* dw 1 */ 986 uint32_t timeout; 987 /* dw 2 */ 988 uint32_t request_length; 989 /* dw 3 */ 990 uint32_t version:8; 991 uint32_t rsvd0:24; 992 #endif 993 } req; 994 struct { 995 #ifdef _BIG_ENDIAN 996 /* dw 0 */ 997 uint32_t domain:8; 998 uint32_t rsvd0:8; 999 uint32_t subsystem:8; 1000 uint32_t opcode:8; 1001 /* dw 1 */ 1002 uint32_t rsvd1:16; 1003 uint32_t additional_status:8; 1004 uint32_t status:8; 1005 #else 1006 /* dw 0 */ 1007 uint32_t opcode:8; 1008 uint32_t subsystem:8; 1009 uint32_t rsvd0:8; 1010 uint32_t domain:8; 1011 /* dw 1 */ 1012 uint32_t status:8; 1013 uint32_t additional_status:8; 1014 uint32_t rsvd1:16; 1015 #endif 1016 uint32_t rsp_length; 1017 uint32_t actual_rsp_length; 1018 } rsp; 1019 } u0; 1020 }; 1021 #define OCE_BMBX_RHDR_SZ 20 1022 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 1023 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 1024 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 1025 1026 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG_V1 */ 1027 struct mbx_query_common_link_config { 1028 struct mbx_hdr hdr; 1029 union { 1030 struct { 1031 uint32_t rsvd0; 1032 } req; 1033 1034 struct { 1035 #ifdef _BIG_ENDIAN 1036 uint32_t physical_port_fault:8; 1037 uint32_t physical_port_speed:8; 1038 uint32_t link_duplex:8; 1039 uint32_t pt:2; 1040 uint32_t port_number:6; 1041 1042 uint16_t qos_link_speed; 1043 uint16_t rsvd0; 1044 1045 uint32_t rsvd1:21; 1046 uint32_t phys_fcv:1; 1047 uint32_t phys_rxf:1; 1048 uint32_t phys_txf:1; 1049 uint32_t logical_link_status:8; 1050 #else 1051 uint32_t port_number:6; 1052 uint32_t pt:2; 1053 uint32_t link_duplex:8; 1054 uint32_t physical_port_speed:8; 1055 uint32_t physical_port_fault:8; 1056 1057 uint16_t rsvd0; 1058 uint16_t qos_link_speed; 1059 1060 uint32_t logical_link_status:8; 1061 uint32_t phys_txf:1; 1062 uint32_t phys_rxf:1; 1063 uint32_t phys_fcv:1; 1064 uint32_t rsvd1:21; 1065 #endif 1066 } rsp; 1067 } params; 1068 }; 1069 1070 /* [57] OPCODE_COMMON_SET_LINK_SPEED */ 1071 struct mbx_set_common_link_speed { 1072 struct mbx_hdr hdr; 1073 union { 1074 struct { 1075 #ifdef _BIG_ENDIAN 1076 uint8_t rsvd0; 1077 uint8_t mac_speed; 1078 uint8_t virtual_port; 1079 uint8_t physical_port; 1080 #else 1081 uint8_t physical_port; 1082 uint8_t virtual_port; 1083 uint8_t mac_speed; 1084 uint8_t rsvd0; 1085 #endif 1086 } req; 1087 1088 struct { 1089 uint32_t rsvd0; 1090 } rsp; 1091 1092 uint32_t dw; 1093 } params; 1094 }; 1095 1096 struct mac_address_format { 1097 uint16_t size_of_struct; 1098 uint8_t mac_addr[6]; 1099 }; 1100 1101 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */ 1102 struct mbx_query_common_iface_mac { 1103 struct mbx_hdr hdr; 1104 union { 1105 struct { 1106 #ifdef _BIG_ENDIAN 1107 uint16_t if_id; 1108 uint8_t permanent; 1109 uint8_t type; 1110 #else 1111 uint8_t type; 1112 uint8_t permanent; 1113 uint16_t if_id; 1114 #endif 1115 1116 } req; 1117 1118 struct { 1119 struct mac_address_format mac; 1120 } rsp; 1121 } params; 1122 }; 1123 1124 /* [02] OPCODE_COMMON_SET_IFACE_MAC */ 1125 struct mbx_set_common_iface_mac { 1126 struct mbx_hdr hdr; 1127 union { 1128 struct { 1129 #ifdef _BIG_ENDIAN 1130 /* dw 0 */ 1131 uint16_t if_id; 1132 uint8_t invalidate; 1133 uint8_t type; 1134 #else 1135 /* dw 0 */ 1136 uint8_t type; 1137 uint8_t invalidate; 1138 uint16_t if_id; 1139 #endif 1140 /* dw 1 */ 1141 struct mac_address_format mac; 1142 } req; 1143 1144 struct { 1145 uint32_t rsvd0; 1146 } rsp; 1147 1148 uint32_t dw[2]; 1149 } params; 1150 }; 1151 1152 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */ 1153 struct mbx_set_common_iface_multicast { 1154 struct mbx_hdr hdr; 1155 union { 1156 struct { 1157 /* dw 0 */ 1158 uint16_t num_mac; 1159 uint8_t promiscuous; 1160 uint8_t if_id; 1161 /* dw 1-48 */ 1162 struct { 1163 uint8_t byte[6]; 1164 } mac[32]; 1165 1166 } req; 1167 1168 struct { 1169 uint32_t rsvd0; 1170 } rsp; 1171 1172 uint32_t dw[49]; 1173 } params; 1174 }; 1175 1176 struct qinq_vlan { 1177 #ifdef _BIG_ENDIAN 1178 uint16_t inner; 1179 uint16_t outer; 1180 #else 1181 uint16_t outer; 1182 uint16_t inner; 1183 #endif 1184 }; 1185 1186 struct normal_vlan { 1187 uint16_t vtag; 1188 }; 1189 1190 struct ntwk_if_vlan_tag { 1191 union { 1192 struct normal_vlan normal; 1193 struct qinq_vlan qinq; 1194 } u0; 1195 }; 1196 1197 /* [50] OPCODE_COMMON_CREATE_IFACE */ 1198 struct mbx_create_common_iface { 1199 struct mbx_hdr hdr; 1200 union { 1201 struct { 1202 uint32_t version; 1203 uint32_t cap_flags; 1204 uint32_t enable_flags; 1205 uint8_t mac_addr[6]; 1206 uint8_t rsvd0; 1207 uint8_t mac_invalid; 1208 struct ntwk_if_vlan_tag vlan_tag; 1209 } req; 1210 1211 struct { 1212 uint32_t if_id; 1213 uint32_t pmac_id; 1214 } rsp; 1215 uint32_t dw[4]; 1216 } params; 1217 }; 1218 1219 /* [51] OPCODE_COMMON_DESTROY_IFACE */ 1220 struct mbx_destroy_common_iface { 1221 struct mbx_hdr hdr; 1222 union { 1223 struct { 1224 uint32_t if_id; 1225 } req; 1226 1227 struct { 1228 uint32_t rsvd0; 1229 } rsp; 1230 1231 uint32_t dw; 1232 } params; 1233 }; 1234 1235 /* event queue context structure */ 1236 struct oce_eq_ctx { 1237 #ifdef _BIG_ENDIAN 1238 uint32_t dw4rsvd1:16; 1239 uint32_t num_pages:16; 1240 1241 uint32_t size:1; 1242 uint32_t dw5rsvd2:1; 1243 uint32_t valid:1; 1244 uint32_t dw5rsvd1:29; 1245 1246 uint32_t armed:1; 1247 uint32_t dw6rsvd2:2; 1248 uint32_t count:3; 1249 uint32_t dw6rsvd1:26; 1250 1251 uint32_t dw7rsvd2:9; 1252 uint32_t delay_mult:10; 1253 uint32_t dw7rsvd1:13; 1254 1255 uint32_t dw8rsvd1; 1256 #else 1257 uint32_t num_pages:16; 1258 uint32_t dw4rsvd1:16; 1259 1260 uint32_t dw5rsvd1:29; 1261 uint32_t valid:1; 1262 uint32_t dw5rsvd2:1; 1263 uint32_t size:1; 1264 1265 uint32_t dw6rsvd1:26; 1266 uint32_t count:3; 1267 uint32_t dw6rsvd2:2; 1268 uint32_t armed:1; 1269 1270 uint32_t dw7rsvd1:13; 1271 uint32_t delay_mult:10; 1272 uint32_t dw7rsvd2:9; 1273 1274 uint32_t dw8rsvd1; 1275 #endif 1276 }; 1277 1278 /* [13] OPCODE_COMMON_CREATE_EQ */ 1279 struct mbx_create_common_eq { 1280 struct mbx_hdr hdr; 1281 union { 1282 struct { 1283 struct oce_eq_ctx ctx; 1284 struct phys_addr pages[8]; 1285 } req; 1286 1287 struct { 1288 uint16_t eq_id; 1289 uint16_t rsvd0; 1290 } rsp; 1291 } params; 1292 }; 1293 1294 /* [55] OPCODE_COMMON_DESTROY_EQ */ 1295 struct mbx_destroy_common_eq { 1296 struct mbx_hdr hdr; 1297 union { 1298 struct { 1299 #ifdef _BIG_ENDIAN 1300 uint16_t rsvd0; 1301 uint16_t id; 1302 #else 1303 uint16_t id; 1304 uint16_t rsvd0; 1305 #endif 1306 } req; 1307 1308 struct { 1309 uint32_t rsvd0; 1310 } rsp; 1311 } params; 1312 }; 1313 1314 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */ 1315 typedef union oce_cq_ctx_u { 1316 uint32_t dw[5]; 1317 struct { 1318 #ifdef _BIG_ENDIAN 1319 /* dw4 */ 1320 uint32_t dw4rsvd1:16; 1321 uint32_t num_pages:16; 1322 /* dw5 */ 1323 uint32_t eventable:1; 1324 uint32_t dw5rsvd3:1; 1325 uint32_t valid:1; 1326 uint32_t count:2; 1327 uint32_t dw5rsvd2:12; 1328 uint32_t nodelay:1; 1329 uint32_t coalesce_wm:2; 1330 uint32_t dw5rsvd1:12; 1331 /* dw6 */ 1332 uint32_t armed:1; 1333 uint32_t dw6rsvd2:1; 1334 uint32_t eq_id:8; 1335 uint32_t dw6rsvd1:22; 1336 #else 1337 /* dw4 */ 1338 uint32_t num_pages:16; 1339 uint32_t dw4rsvd1:16; 1340 /* dw5 */ 1341 uint32_t dw5rsvd1:12; 1342 uint32_t coalesce_wm:2; 1343 uint32_t nodelay:1; 1344 uint32_t dw5rsvd2:12; 1345 uint32_t count:2; 1346 uint32_t valid:1; 1347 uint32_t dw5rsvd3:1; 1348 uint32_t eventable:1; 1349 /* dw6 */ 1350 uint32_t dw6rsvd1:22; 1351 uint32_t eq_id:8; 1352 uint32_t dw6rsvd2:1; 1353 uint32_t armed:1; 1354 #endif 1355 /* dw7 */ 1356 uint32_t dw7rsvd1; 1357 /* dw8 */ 1358 uint32_t dw8rsvd1; 1359 } v0; 1360 struct { 1361 #ifdef _BIG_ENDIAN 1362 /* dw4 */ 1363 uint32_t dw4rsvd1:8; 1364 uint32_t page_size:8; 1365 uint32_t num_pages:16; 1366 /* dw5 */ 1367 uint32_t eventable:1; 1368 uint32_t dw5rsvd3:1; 1369 uint32_t valid:1; 1370 uint32_t count:2; 1371 uint32_t dw5rsvd2:11; 1372 uint32_t autovalid:1; 1373 uint32_t nodelay:1; 1374 uint32_t coalesce_wm:2; 1375 uint32_t dw5rsvd1:12; 1376 /* dw6 */ 1377 uint32_t armed:1; 1378 uint32_t dw6rsvd1:15; 1379 uint32_t eq_id:16; 1380 /* dw7 */ 1381 uint32_t dw7rsvd1:16; 1382 uint32_t cqe_count:16; 1383 #else 1384 /* dw4 */ 1385 uint32_t num_pages:16; 1386 uint32_t page_size:8; 1387 uint32_t dw4rsvd1:8; 1388 /* dw5 */ 1389 uint32_t dw5rsvd1:12; 1390 uint32_t coalesce_wm:2; 1391 uint32_t nodelay:1; 1392 uint32_t autovalid:1; 1393 uint32_t dw5rsvd2:11; 1394 uint32_t count:2; 1395 uint32_t valid:1; 1396 uint32_t dw5rsvd3:1; 1397 uint32_t eventable:1; 1398 /* dw6 */ 1399 uint32_t eq_id:8; 1400 uint32_t dw6rsvd1:15; 1401 uint32_t armed:1; 1402 /* dw7 */ 1403 uint32_t cqe_count:16; 1404 uint32_t dw7rsvd1:16; 1405 #endif 1406 /* dw8 */ 1407 uint32_t dw8rsvd1; 1408 } v2; 1409 } oce_cq_ctx_t; 1410 1411 /* [12] OPCODE_COMMON_CREATE_CQ */ 1412 struct mbx_create_common_cq { 1413 struct mbx_hdr hdr; 1414 union { 1415 struct { 1416 oce_cq_ctx_t cq_ctx; 1417 struct phys_addr pages[4]; 1418 } req; 1419 1420 struct { 1421 uint16_t cq_id; 1422 uint16_t rsvd0; 1423 } rsp; 1424 } params; 1425 }; 1426 1427 /* [54] OPCODE_COMMON_DESTROY_CQ */ 1428 struct mbx_destroy_common_cq { 1429 struct mbx_hdr hdr; 1430 union { 1431 struct { 1432 #ifdef _BIG_ENDIAN 1433 uint16_t rsvd0; 1434 uint16_t id; 1435 #else 1436 uint16_t id; 1437 uint16_t rsvd0; 1438 #endif 1439 } req; 1440 1441 struct { 1442 uint32_t rsvd0; 1443 } rsp; 1444 } params; 1445 }; 1446 1447 typedef union oce_mq_ctx_u { 1448 uint32_t dw[5]; 1449 struct { 1450 #ifdef _BIG_ENDIAN 1451 /* dw4 */ 1452 uint32_t dw4rsvd1:16; 1453 uint32_t num_pages:16; 1454 /* dw5 */ 1455 uint32_t cq_id:10; 1456 uint32_t dw5rsvd2:2; 1457 uint32_t ring_size:4; 1458 uint32_t dw5rsvd1:16; 1459 /* dw6 */ 1460 uint32_t valid:1; 1461 uint32_t dw6rsvd1:31; 1462 /* dw7 */ 1463 uint32_t dw7rsvd1:21; 1464 uint32_t async_cq_id:10; 1465 uint32_t async_cq_valid:1; 1466 #else 1467 /* dw4 */ 1468 uint32_t num_pages:16; 1469 uint32_t dw4rsvd1:16; 1470 /* dw5 */ 1471 uint32_t dw5rsvd1:16; 1472 uint32_t ring_size:4; 1473 uint32_t dw5rsvd2:2; 1474 uint32_t cq_id:10; 1475 /* dw6 */ 1476 uint32_t dw6rsvd1:31; 1477 uint32_t valid:1; 1478 /* dw7 */ 1479 uint32_t async_cq_valid:1; 1480 uint32_t async_cq_id:10; 1481 uint32_t dw7rsvd1:21; 1482 #endif 1483 /* dw8 */ 1484 uint32_t dw8rsvd1; 1485 } v0; 1486 } oce_mq_ctx_t; 1487 1488 /** 1489 * @brief [21] OPCODE_COMMON_CREATE_MQ 1490 * A MQ must be at least 16 entries deep (corresponding to 1 page) and 1491 * at most 128 entries deep (corresponding to 8 pages). 1492 */ 1493 struct mbx_create_common_mq { 1494 struct mbx_hdr hdr; 1495 union { 1496 struct { 1497 oce_mq_ctx_t context; 1498 struct phys_addr pages[8]; 1499 } req; 1500 1501 struct { 1502 uint32_t mq_id:16; 1503 uint32_t rsvd0:16; 1504 } rsp; 1505 } params; 1506 }; 1507 1508 struct mbx_create_common_mq_ex { 1509 struct mbx_hdr hdr; 1510 union { 1511 struct { 1512 oce_mq_ext_ctx_t context; 1513 struct phys_addr pages[8]; 1514 } req; 1515 1516 struct { 1517 uint32_t mq_id:16; 1518 uint32_t rsvd0:16; 1519 } rsp; 1520 } params; 1521 }; 1522 1523 1524 1525 /* [53] OPCODE_COMMON_DESTROY_MQ */ 1526 struct mbx_destroy_common_mq { 1527 struct mbx_hdr hdr; 1528 union { 1529 struct { 1530 #ifdef _BIG_ENDIAN 1531 uint16_t rsvd0; 1532 uint16_t id; 1533 #else 1534 uint16_t id; 1535 uint16_t rsvd0; 1536 #endif 1537 } req; 1538 1539 struct { 1540 uint32_t rsvd0; 1541 } rsp; 1542 } params; 1543 }; 1544 1545 /* [35] OPCODE_COMMON_GET_ FW_VERSION */ 1546 struct mbx_get_common_fw_version { 1547 struct mbx_hdr hdr; 1548 union { 1549 struct { 1550 uint32_t rsvd0; 1551 } req; 1552 1553 struct { 1554 uint8_t fw_ver_str[32]; 1555 uint8_t fw_on_flash_ver_str[32]; 1556 } rsp; 1557 } params; 1558 }; 1559 1560 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1561 struct mbx_common_cev_modify_msi_messages { 1562 struct mbx_hdr hdr; 1563 union { 1564 struct { 1565 uint32_t num_msi_msgs; 1566 } req; 1567 1568 struct { 1569 uint32_t rsvd0; 1570 } rsp; 1571 } params; 1572 }; 1573 1574 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */ 1575 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */ 1576 struct mbx_common_get_set_flow_control { 1577 struct mbx_hdr hdr; 1578 #ifdef _BIG_ENDIAN 1579 uint16_t tx_flow_control; 1580 uint16_t rx_flow_control; 1581 #else 1582 uint16_t rx_flow_control; 1583 uint16_t tx_flow_control; 1584 #endif 1585 }; 1586 1587 enum e_flash_opcode { 1588 MGMT_FLASHROM_OPCODE_FLASH = 1, 1589 MGMT_FLASHROM_OPCODE_SAVE = 2 1590 }; 1591 1592 /* [06] OPCODE_READ_COMMON_FLASHROM */ 1593 /* [07] OPCODE_WRITE_COMMON_FLASHROM */ 1594 1595 struct mbx_common_read_write_flashrom { 1596 struct mbx_hdr hdr; 1597 uint32_t flash_op_code; 1598 uint32_t flash_op_type; 1599 uint32_t data_buffer_size; 1600 uint32_t data_offset; 1601 uint8_t data_buffer[32768]; /* + IMAGE_TRANSFER_SIZE */ 1602 uint8_t rsvd[4]; 1603 }; 1604 1605 struct oce_phy_info { 1606 uint16_t phy_type; 1607 uint16_t interface_type; 1608 uint32_t misc_params; 1609 uint16_t ext_phy_details; 1610 uint16_t rsvd; 1611 uint16_t auto_speeds_supported; 1612 uint16_t fixed_speeds_supported; 1613 uint32_t future_use[2]; 1614 }; 1615 1616 struct mbx_common_phy_info { 1617 struct mbx_hdr hdr; 1618 union { 1619 struct { 1620 uint32_t rsvd0[4]; 1621 } req; 1622 struct { 1623 struct oce_phy_info phy_info; 1624 } rsp; 1625 } params; 1626 }; 1627 1628 /*Lancer firmware*/ 1629 1630 struct mbx_lancer_common_write_object { 1631 union { 1632 struct { 1633 struct mbx_hdr hdr; 1634 uint32_t write_length: 24; 1635 uint32_t rsvd: 7; 1636 uint32_t eof: 1; 1637 uint32_t write_offset; 1638 uint8_t object_name[104]; 1639 uint32_t descriptor_count; 1640 uint32_t buffer_length; 1641 uint32_t address_lower; 1642 uint32_t address_upper; 1643 } req; 1644 struct { 1645 uint8_t opcode; 1646 uint8_t subsystem; 1647 uint8_t rsvd1[2]; 1648 uint8_t status; 1649 uint8_t additional_status; 1650 uint8_t rsvd2[2]; 1651 uint32_t response_length; 1652 uint32_t actual_response_length; 1653 uint32_t actual_write_length; 1654 } rsp; 1655 } params; 1656 }; 1657 1658 /** 1659 * @brief MBX Common Quiery Firmaware Config 1660 * This command retrieves firmware configuration parameters and adapter 1661 * resources available to the driver originating the request. The firmware 1662 * configuration defines supported protocols by the installed adapter firmware. 1663 * This includes which ULP processors support the specified protocols and 1664 * the number of TCP connections allowed for that protocol. 1665 */ 1666 struct mbx_common_query_fw_config { 1667 struct mbx_hdr hdr; 1668 union { 1669 struct { 1670 uint32_t rsvd0[30]; 1671 } req; 1672 1673 struct { 1674 uint32_t config_number; 1675 uint32_t asic_revision; 1676 uint32_t port_id; /* used for stats retrieval */ 1677 uint32_t function_mode; 1678 struct { 1679 1680 uint32_t ulp_mode; 1681 uint32_t nic_wqid_base; 1682 uint32_t nic_wq_tot; 1683 uint32_t toe_wqid_base; 1684 uint32_t toe_wq_tot; 1685 uint32_t toe_rqid_base; 1686 uint32_t toe_rqid_tot; 1687 uint32_t toe_defrqid_base; 1688 uint32_t toe_defrqid_count; 1689 uint32_t lro_rqid_base; 1690 uint32_t lro_rqid_tot; 1691 uint32_t iscsi_icd_base; 1692 uint32_t iscsi_icd_count; 1693 } ulp[2]; 1694 uint32_t function_caps; 1695 uint32_t cqid_base; 1696 uint32_t cqid_tot; 1697 uint32_t eqid_base; 1698 uint32_t eqid_tot; 1699 } rsp; 1700 } params; 1701 }; 1702 1703 enum CQFW_CONFIG_NUMBER { 1704 FCN_NIC_ISCSI_Initiator = 0x0, 1705 FCN_ISCSI_Target = 0x3, 1706 FCN_FCoE = 0x7, 1707 FCN_ISCSI_Initiator_Target = 0x9, 1708 FCN_NIC_RDMA_TOE = 0xA, 1709 FCN_NIC_RDMA_FCoE = 0xB, 1710 FCN_NIC_RDMA_iSCSI = 0xC, 1711 FCN_NIC_iSCSI_FCoE = 0xD 1712 }; 1713 1714 /** 1715 * @brief Function Capabilites 1716 * This field contains the flags indicating the capabilities of 1717 * the SLI Host’s PCI function. 1718 */ 1719 enum CQFW_FUNCTION_CAPABILITIES { 1720 FNC_UNCLASSIFIED_STATS = 0x1, 1721 FNC_RSS = 0x2, 1722 FNC_PROMISCUOUS = 0x4, 1723 FNC_LEGACY_MODE = 0x8, 1724 FNC_HDS = 0x4000, 1725 FNC_VMQ = 0x10000, 1726 FNC_NETQ = 0x20000, 1727 FNC_QGROUPS = 0x40000, 1728 FNC_LRO = 0x100000, 1729 FNC_VLAN_OFFLOAD = 0x800000 1730 }; 1731 1732 enum CQFW_ULP_MODES_SUPPORTED { 1733 ULP_TOE_MODE = 0x1, 1734 ULP_NIC_MODE = 0x2, 1735 ULP_RDMA_MODE = 0x4, 1736 ULP_ISCSI_INI_MODE = 0x10, 1737 ULP_ISCSI_TGT_MODE = 0x20, 1738 ULP_FCOE_INI_MODE = 0x40, 1739 ULP_FCOE_TGT_MODE = 0x80, 1740 ULP_DAL_MODE = 0x100, 1741 ULP_LRO_MODE = 0x200 1742 }; 1743 1744 /** 1745 * @brief Function Modes Supported 1746 * Valid function modes (or protocol-types) supported on the SLI-Host’s 1747 * PCIe function. This field is a logical OR of the following values: 1748 */ 1749 enum CQFW_FUNCTION_MODES_SUPPORTED { 1750 FNM_TOE_MODE = 0x1, /* TCP offload supported */ 1751 FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */ 1752 FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */ 1753 FNM_VM_MODE = 0x8, /* Virtual Machines supported */ 1754 FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */ 1755 FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 1756 FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */ 1757 FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */ 1758 FNM_DAL_MODE = 0x100, /* DAL supported */ 1759 FNM_LRO_MODE = 0x200, /* LRO supported */ 1760 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */ 1761 FNM_NCSI_MODE = 0x800, /* NCSI supported */ 1762 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */ 1763 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/ 1764 FNM_INVALID_MODE = 0x8000, /* Invalid */ 1765 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */ 1766 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */ 1767 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */ 1768 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */ 1769 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */ 1770 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */ 1771 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */ 1772 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */ 1773 }; 1774 1775 1776 struct mbx_common_config_vlan { 1777 struct mbx_hdr hdr; 1778 union { 1779 struct { 1780 #ifdef _BIG_ENDIAN 1781 uint8_t num_vlans; 1782 uint8_t untagged; 1783 uint8_t promisc; 1784 uint8_t if_id; 1785 #else 1786 uint8_t if_id; 1787 uint8_t promisc; 1788 uint8_t untagged; 1789 uint8_t num_vlans; 1790 #endif 1791 union { 1792 struct normal_vlan normal_vlans[64]; 1793 struct qinq_vlan qinq_vlans[32]; 1794 } tags; 1795 } req; 1796 1797 struct { 1798 uint32_t rsvd; 1799 } rsp; 1800 } params; 1801 }; 1802 1803 typedef struct iface_rx_filter_ctx { 1804 uint32_t global_flags_mask; 1805 uint32_t global_flags; 1806 uint32_t iface_flags_mask; 1807 uint32_t iface_flags; 1808 uint32_t if_id; 1809 #define IFACE_RX_NUM_MCAST_MAX 64 1810 uint32_t num_mcast; 1811 struct mbx_mcast_addr { 1812 uint8_t byte[6]; 1813 } mac[IFACE_RX_NUM_MCAST_MAX]; 1814 } iface_rx_filter_ctx_t; 1815 1816 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */ 1817 struct mbx_set_common_iface_rx_filter { 1818 struct mbx_hdr hdr; 1819 union { 1820 iface_rx_filter_ctx_t req; 1821 iface_rx_filter_ctx_t rsp; 1822 } params; 1823 }; 1824 1825 struct be_set_eqd { 1826 uint32_t eq_id; 1827 uint32_t phase; 1828 uint32_t dm; 1829 }; 1830 1831 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */ 1832 struct mbx_modify_common_eq_delay { 1833 struct mbx_hdr hdr; 1834 union { 1835 struct { 1836 uint32_t num_eq; 1837 struct { 1838 uint32_t eq_id; 1839 uint32_t phase; 1840 uint32_t dm; 1841 } delay[8]; 1842 } req; 1843 1844 struct { 1845 uint32_t rsvd0; 1846 } rsp; 1847 } params; 1848 }; 1849 1850 /* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */ 1851 1852 struct mgmt_hba_attr { 1853 int8_t flashrom_ver_str[32]; 1854 int8_t manufac_name[32]; 1855 uint32_t supp_modes; 1856 int8_t seeprom_ver_lo; 1857 int8_t seeprom_ver_hi; 1858 int8_t rsvd0[2]; 1859 uint32_t ioctl_data_struct_ver; 1860 uint32_t ep_fw_data_struct_ver; 1861 uint8_t ncsi_ver_str[12]; 1862 uint32_t def_ext_to; 1863 int8_t cntl_mod_num[32]; 1864 int8_t cntl_desc[64]; 1865 int8_t cntl_ser_num[32]; 1866 int8_t ip_ver_str[32]; 1867 int8_t fw_ver_str[32]; 1868 int8_t bios_ver_str[32]; 1869 int8_t redboot_ver_str[32]; 1870 int8_t drv_ver_str[32]; 1871 int8_t fw_on_flash_ver_str[32]; 1872 uint32_t funcs_supp; 1873 uint16_t max_cdblen; 1874 uint8_t asic_rev; 1875 uint8_t gen_guid[16]; 1876 uint8_t hba_port_count; 1877 uint16_t default_link_down_timeout; 1878 uint8_t iscsi_ver_min_max; 1879 uint8_t multifunc_dev; 1880 uint8_t cache_valid; 1881 uint8_t hba_status; 1882 uint8_t max_domains_supp; 1883 uint8_t phy_port; 1884 uint32_t fw_post_status; 1885 uint32_t hba_mtu[8]; 1886 uint8_t iSCSI_feat; 1887 uint8_t asic_gen; 1888 uint8_t future_u8[2]; 1889 uint32_t future_u32[3]; 1890 }; 1891 1892 struct mgmt_cntl_attr { 1893 struct mgmt_hba_attr hba_attr; 1894 uint16_t pci_vendor_id; 1895 uint16_t pci_device_id; 1896 uint16_t pci_sub_vendor_id; 1897 uint16_t pci_sub_system_id; 1898 uint8_t pci_bus_num; 1899 uint8_t pci_dev_num; 1900 uint8_t pci_func_num; 1901 uint8_t interface_type; 1902 uint64_t unique_id; 1903 uint8_t netfilters; 1904 uint8_t rsvd0[3]; 1905 uint32_t future_u32[4]; 1906 }; 1907 1908 struct mbx_common_get_cntl_attr { 1909 struct mbx_hdr hdr; 1910 union { 1911 struct { 1912 uint32_t rsvd0; 1913 } req; 1914 struct { 1915 struct mgmt_cntl_attr cntl_attr_info; 1916 } rsp; 1917 } params; 1918 }; 1919 1920 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1921 struct mbx_add_common_iface_mac { 1922 struct mbx_hdr hdr; 1923 union { 1924 struct { 1925 uint32_t if_id; 1926 uint8_t mac_address[6]; 1927 uint8_t rsvd0[2]; 1928 } req; 1929 struct { 1930 uint32_t pmac_id; 1931 } rsp; 1932 } params; 1933 }; 1934 1935 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1936 struct mbx_del_common_iface_mac { 1937 struct mbx_hdr hdr; 1938 union { 1939 struct { 1940 uint32_t if_id; 1941 uint32_t pmac_id; 1942 } req; 1943 struct { 1944 uint32_t rsvd0; 1945 } rsp; 1946 } params; 1947 }; 1948 1949 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1950 struct mbx_query_common_max_mbx_buffer_size { 1951 struct mbx_hdr hdr; 1952 struct { 1953 uint32_t max_ioctl_bufsz; 1954 } rsp; 1955 }; 1956 1957 /* [61] OPCODE_COMMON_FUNCTION_RESET */ 1958 struct ioctl_common_function_reset { 1959 struct mbx_hdr hdr; 1960 }; 1961 1962 /* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */ 1963 struct mbx_read_common_transrecv_data { 1964 struct mbx_hdr hdr; 1965 union { 1966 struct { 1967 uint32_t page_num; 1968 uint32_t port; 1969 } req; 1970 struct { 1971 uint32_t page_num; 1972 uint32_t port; 1973 uint32_t page_data[32]; 1974 } rsp; 1975 } params; 1976 1977 }; 1978 1979 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 1980 struct mbx_common_func_link_cfg { 1981 struct mbx_hdr hdr; 1982 union { 1983 struct { 1984 uint32_t enable; 1985 } req; 1986 struct { 1987 uint32_t rsvd0; 1988 } rsp; 1989 } params; 1990 }; 1991 1992 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */ 1993 #define CAP_SW_TIMESTAMPS 2 1994 #define CAP_BE3_NATIVE_ERX_API 4 1995 1996 struct mbx_common_set_function_cap { 1997 struct mbx_hdr hdr; 1998 union { 1999 struct { 2000 uint32_t valid_capability_flags; 2001 uint32_t capability_flags; 2002 uint8_t sbz[212]; 2003 } req; 2004 struct { 2005 uint32_t valid_capability_flags; 2006 uint32_t capability_flags; 2007 uint8_t sbz[212]; 2008 } rsp; 2009 } params; 2010 }; 2011 struct mbx_lowlevel_test_loopback_mode { 2012 struct mbx_hdr hdr; 2013 union { 2014 struct { 2015 uint32_t loopback_type; 2016 uint32_t num_pkts; 2017 uint64_t pattern; 2018 uint32_t src_port; 2019 uint32_t dest_port; 2020 uint32_t pkt_size; 2021 }req; 2022 struct { 2023 uint32_t status; 2024 uint32_t num_txfer; 2025 uint32_t num_rx; 2026 uint32_t miscomp_off; 2027 uint32_t ticks_compl; 2028 }rsp; 2029 } params; 2030 }; 2031 2032 struct mbx_lowlevel_set_loopback_mode { 2033 struct mbx_hdr hdr; 2034 union { 2035 struct { 2036 uint8_t src_port; 2037 uint8_t dest_port; 2038 uint8_t loopback_type; 2039 uint8_t loopback_state; 2040 } req; 2041 struct { 2042 uint8_t rsvd0[4]; 2043 } rsp; 2044 } params; 2045 }; 2046 #define MAX_RESC_DESC 256 2047 #define RESC_DESC_SIZE 88 2048 #define ACTIVE_PROFILE 2 2049 #define NIC_RESC_DESC_TYPE_V0 0x41 2050 #define NIC_RESC_DESC_TYPE_V1 0x51 2051 /* OPCODE_COMMON_GET_FUNCTION_CONFIG */ 2052 struct mbx_common_get_func_config { 2053 struct mbx_hdr hdr; 2054 union { 2055 struct { 2056 uint8_t rsvd; 2057 uint8_t type; 2058 uint16_t rsvd1; 2059 } req; 2060 struct { 2061 uint32_t desc_count; 2062 uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2063 } rsp; 2064 } params; 2065 }; 2066 2067 2068 /* OPCODE_COMMON_GET_PROFILE_CONFIG */ 2069 2070 struct mbx_common_get_profile_config { 2071 struct mbx_hdr hdr; 2072 union { 2073 struct { 2074 uint8_t rsvd; 2075 uint8_t type; 2076 uint16_t rsvd1; 2077 } req; 2078 struct { 2079 uint32_t desc_count; 2080 uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2081 } rsp; 2082 } params; 2083 }; 2084 2085 struct oce_nic_resc_desc { 2086 uint8_t desc_type; 2087 uint8_t desc_len; 2088 uint8_t rsvd1; 2089 uint8_t flags; 2090 uint8_t vf_num; 2091 uint8_t rsvd2; 2092 uint8_t pf_num; 2093 uint8_t rsvd3; 2094 uint16_t unicast_mac_count; 2095 uint8_t rsvd4[6]; 2096 uint16_t mcc_count; 2097 uint16_t vlan_count; 2098 uint16_t mcast_mac_count; 2099 uint16_t txq_count; 2100 uint16_t rq_count; 2101 uint16_t rssq_count; 2102 uint16_t lro_count; 2103 uint16_t cq_count; 2104 uint16_t toe_conn_count; 2105 uint16_t eq_count; 2106 uint32_t rsvd5; 2107 uint32_t cap_flags; 2108 uint8_t link_param; 2109 uint8_t rsvd6[3]; 2110 uint32_t bw_min; 2111 uint32_t bw_max; 2112 uint8_t acpi_params; 2113 uint8_t wol_param; 2114 uint16_t rsvd7; 2115 uint32_t rsvd8[7]; 2116 2117 }; 2118 2119 2120 struct flash_file_hdr { 2121 uint8_t sign[52]; 2122 uint8_t ufi_version[4]; 2123 uint32_t file_len; 2124 uint32_t cksum; 2125 uint32_t antidote; 2126 uint32_t num_imgs; 2127 uint8_t build[24]; 2128 uint8_t asic_type_rev; 2129 uint8_t rsvd[31]; 2130 }; 2131 2132 struct image_hdr { 2133 uint32_t imageid; 2134 uint32_t imageoffset; 2135 uint32_t imagelength; 2136 uint32_t image_checksum; 2137 uint8_t image_version[32]; 2138 }; 2139 2140 struct flash_section_hdr { 2141 uint32_t format_rev; 2142 uint32_t cksum; 2143 uint32_t antidote; 2144 uint32_t num_images; 2145 uint8_t id_string[128]; 2146 uint32_t rsvd[4]; 2147 }; 2148 2149 struct flash_section_entry { 2150 uint32_t type; 2151 uint32_t offset; 2152 uint32_t pad_size; 2153 uint32_t image_size; 2154 uint32_t cksum; 2155 uint32_t entry_point; 2156 uint32_t rsvd0; 2157 uint32_t rsvd1; 2158 uint8_t ver_data[32]; 2159 }; 2160 2161 struct flash_sec_info { 2162 uint8_t cookie[32]; 2163 struct flash_section_hdr fsec_hdr; 2164 struct flash_section_entry fsec_entry[32]; 2165 }; 2166 2167 2168 enum LOWLEVEL_SUBSYSTEM_OPCODES { 2169 /* Opcodes used for lowlevel functions common to many subystems. 2170 * Some of these opcodes are used for diagnostic functions only. 2171 * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code. 2172 */ 2173 OPCODE_LOWLEVEL_TEST_LOOPBACK = 18, 2174 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19, 2175 OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20 2176 }; 2177 2178 enum LLDP_SUBSYSTEM_OPCODES { 2179 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */ 2180 OPCODE_LLDP_GET_CFG = 1, 2181 OPCODE_LLDP_SET_CFG = 2, 2182 OPCODE_LLDP_GET_STATS = 3 2183 }; 2184 2185 enum DCBX_SUBSYSTEM_OPCODES { 2186 /* Opcodes used for DCBX. */ 2187 OPCODE_DCBX_GET_CFG = 1, 2188 OPCODE_DCBX_SET_CFG = 2, 2189 OPCODE_DCBX_GET_MIB_INFO = 3, 2190 OPCODE_DCBX_GET_DCBX_MODE = 4, 2191 OPCODE_DCBX_SET_MODE = 5 2192 }; 2193 2194 enum DMTF_SUBSYSTEM_OPCODES { 2195 /* Opcodes used for DCBX subsystem. */ 2196 OPCODE_DMTF_EXEC_CLP_CMD = 1 2197 }; 2198 2199 enum DIAG_SUBSYSTEM_OPCODES { 2200 /* Opcodes used for diag functions common to many subsystems. */ 2201 OPCODE_DIAG_RUN_DMA_TEST = 1, 2202 OPCODE_DIAG_RUN_MDIO_TEST = 2, 2203 OPCODE_DIAG_RUN_NLB_TEST = 3, 2204 OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4, 2205 OPCODE_DIAG_GET_MAC = 5 2206 }; 2207 2208 enum VENDOR_SUBSYSTEM_OPCODES { 2209 /* Opcodes used for Vendor subsystem. */ 2210 OPCODE_VENDOR_SLI = 1 2211 }; 2212 2213 /* Management Status Codes */ 2214 enum MGMT_STATUS_SUCCESS { 2215 MGMT_SUCCESS = 0, 2216 MGMT_FAILED = 1, 2217 MGMT_ILLEGAL_REQUEST = 2, 2218 MGMT_ILLEGAL_FIELD = 3, 2219 MGMT_INSUFFICIENT_BUFFER = 4, 2220 MGMT_UNAUTHORIZED_REQUEST = 5, 2221 MGMT_INVALID_ISNS_ADDRESS = 10, 2222 MGMT_INVALID_IPADDR = 11, 2223 MGMT_INVALID_GATEWAY = 12, 2224 MGMT_INVALID_SUBNETMASK = 13, 2225 MGMT_INVALID_TARGET_IPADDR = 16, 2226 MGMT_TGTTBL_FULL = 20, 2227 MGMT_FLASHROM_SAVE_FAILED = 23, 2228 MGMT_IOCTLHANDLE_ALLOC_FAILED = 27, 2229 MGMT_INVALID_SESSION = 31, 2230 MGMT_INVALID_CONNECTION = 32, 2231 MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33, 2232 MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34, 2233 MGMT_BTL_PATH_TGTID_OCCUPIED = 35, 2234 MGMT_BTL_NO_FREE_SLOT_PATH = 36, 2235 MGMT_BTL_NO_FREE_SLOT_TGTID = 37, 2236 MGMT_POLL_IOCTL_TIMEOUT = 40, 2237 MGMT_ERROR_ACITISCSI = 41, 2238 MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43, 2239 MGMT_REBOOT_REQUIRED = 44, 2240 MGMT_INSUFFICIENT_TIMEOUT = 45, 2241 MGMT_IPADDR_NOT_SET = 46, 2242 MGMT_IPADDR_DUP_DETECTED = 47, 2243 MGMT_CANT_REMOVE_LAST_CONNECTION = 48, 2244 MGMT_TARGET_BUSY = 49, 2245 MGMT_TGT_ERR_LISTEN_SOCKET = 50, 2246 MGMT_TGT_ERR_BIND_SOCKET = 51, 2247 MGMT_TGT_ERR_NO_SOCKET = 52, 2248 MGMT_TGT_ERR_ISNS_COMM_FAILED = 55, 2249 MGMT_CANNOT_DELETE_BOOT_TARGET = 56, 2250 MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57, 2251 MGMT_FCF_IN_USE = 58 , 2252 MGMT_NO_CQE = 59, 2253 MGMT_TARGET_NOT_FOUND = 65, 2254 MGMT_NOT_SUPPORTED = 66, 2255 MGMT_NO_FCF_RECORDS = 67, 2256 MGMT_FEATURE_NOT_SUPPORTED = 68, 2257 MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69, 2258 MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70, 2259 MGMT_INVALID_NON_EMBEDDED_WRB = 71, 2260 MGMT_OOR = 100, 2261 MGMT_INVALID_PD = 101, 2262 MGMT_STATUS_PD_INUSE = 102, 2263 MGMT_INVALID_CQ = 103, 2264 MGMT_INVALID_QP = 104, 2265 MGMT_INVALID_STAG = 105, 2266 MGMT_ORD_EXCEEDS = 106, 2267 MGMT_IRD_EXCEEDS = 107, 2268 MGMT_SENDQ_WQE_EXCEEDS = 108, 2269 MGMT_RECVQ_RQE_EXCEEDS = 109, 2270 MGMT_SGE_SEND_EXCEEDS = 110, 2271 MGMT_SGE_WRITE_EXCEEDS = 111, 2272 MGMT_SGE_RECV_EXCEEDS = 112, 2273 MGMT_INVALID_STATE_CHANGE = 113, 2274 MGMT_MW_BOUND = 114, 2275 MGMT_INVALID_VA = 115, 2276 MGMT_INVALID_LENGTH = 116, 2277 MGMT_INVALID_FBO = 117, 2278 MGMT_INVALID_ACC_RIGHTS = 118, 2279 MGMT_INVALID_PBE_SIZE = 119, 2280 MGMT_INVALID_PBL_ENTRY = 120, 2281 MGMT_INVALID_PBL_OFFSET = 121, 2282 MGMT_ADDR_NON_EXIST = 122, 2283 MGMT_INVALID_VLANID = 123, 2284 MGMT_INVALID_MTU = 124, 2285 MGMT_INVALID_BACKLOG = 125, 2286 MGMT_CONNECTION_INPROGRESS = 126, 2287 MGMT_INVALID_RQE_SIZE = 127, 2288 MGMT_INVALID_RQE_ENTRY = 128 2289 }; 2290 2291 /* Additional Management Status Codes */ 2292 enum MGMT_ADDI_STATUS { 2293 MGMT_ADDI_NO_STATUS = 0, 2294 MGMT_ADDI_INVALID_IPTYPE = 1, 2295 MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9, 2296 MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10, 2297 MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11, 2298 MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16, 2299 MGMT_ADDI_SESSION_ALREADY_OPENED = 17, 2300 MGMT_ADDI_SESSION_ALREADY_CLOSED = 18, 2301 MGMT_ADDI_DEST_HOST_UNREACHABLE = 19, 2302 MGMT_ADDI_LOGIN_IN_PROGRESS = 20, 2303 MGMT_ADDI_TCP_CONNECT_FAILED = 21, 2304 MGMT_ADDI_INSUFFICIENT_RESOURCES = 22, 2305 MGMT_ADDI_LINK_DOWN = 23, 2306 MGMT_ADDI_DHCP_ERROR = 24, 2307 MGMT_ADDI_CONNECTION_OFFLOADED = 25, 2308 MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26, 2309 MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27, 2310 MGMT_ADDI_REQUEST_REJECTED = 28, 2311 MGMT_ADDI_INVALID_SUBSYSTEM = 29, 2312 MGMT_ADDI_INVALID_OPCODE = 30, 2313 MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31, 2314 MGMT_ADDI_INVALID_KEY = 32, 2315 MGMT_ADDI_INVALID_DOMAIN = 35, 2316 MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43, 2317 MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44, 2318 MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45, 2319 MGMT_ADDI_LOGIN_NOT_FOUND = 46, 2320 MGMT_ADDI_LOGIN_TARGET_REMOVED = 47, 2321 MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48, 2322 MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49, 2323 MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50, 2324 MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51, 2325 MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52, 2326 MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53, 2327 MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54, 2328 MGMT_ADDI_LOGIN_TARGET_ERROR = 55, 2329 MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56, 2330 MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57, 2331 MGMT_ADDI_SAME_CHAP_SECRET = 58, 2332 MGMT_ADDI_INVALID_SECRET_LENGTH = 59, 2333 MGMT_ADDI_DUPLICATE_ENTRY = 60, 2334 MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63, 2335 MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64, 2336 MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65, 2337 MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66, 2338 MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67, 2339 MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68, 2340 MGMT_ADDI_INVALID_VLAN_RANGE = 69, 2341 MGMT_ADDI_ERR_SET_VLAN = 70, 2342 MGMT_ADDI_ERR_DEL_VLAN = 71, 2343 MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72, 2344 MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73, 2345 MGMT_ADDI_TOO_MANY_INTERFACES = 74, 2346 MGMT_ADDI_INVALID_REQUEST = 75 2347 }; 2348 2349 enum NIC_SUBSYSTEM_OPCODES { 2350 /** 2351 * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2) 2352 * These opcodes are used for configuring the Ethernet interfaces. 2353 * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code. 2354 */ 2355 NIC_CONFIG_RSS = 1, 2356 NIC_CONFIG_ACPI = 2, 2357 NIC_CONFIG_PROMISCUOUS = 3, 2358 NIC_GET_STATS = 4, 2359 NIC_CREATE_WQ = 7, 2360 NIC_CREATE_RQ = 8, 2361 NIC_DELETE_WQ = 9, 2362 NIC_DELETE_RQ = 10, 2363 NIC_CONFIG_ACPI_WOL_MAGIC = 12, 2364 NIC_GET_NETWORK_STATS = 13, 2365 NIC_CREATE_HDS_RQ = 16, 2366 NIC_DELETE_HDS_RQ = 17, 2367 NIC_GET_PPORT_STATS = 18, 2368 NIC_GET_VPORT_STATS = 19, 2369 NIC_GET_QUEUE_STATS = 20 2370 }; 2371 2372 /* Hash option flags for RSS enable */ 2373 enum RSS_ENABLE_FLAGS { 2374 RSS_ENABLE_NONE = 0x0, /* (No RSS) */ 2375 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */ 2376 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */ 2377 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */ 2378 RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */ 2379 RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */ 2380 RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */ 2381 }; 2382 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4) 2383 #define RSS_DISABLE RSS_ENABLE_NONE 2384 2385 /* NIC header WQE */ 2386 struct oce_nic_hdr_wqe { 2387 union { 2388 struct { 2389 #ifdef _BIG_ENDIAN 2390 /* dw0 */ 2391 uint32_t rsvd0; 2392 2393 /* dw1 */ 2394 uint32_t last_seg_udp_len:14; 2395 uint32_t rsvd1:18; 2396 2397 /* dw2 */ 2398 uint32_t lso_mss:14; 2399 uint32_t num_wqe:5; 2400 uint32_t rsvd4:2; 2401 uint32_t vlan:1; 2402 uint32_t lso:1; 2403 uint32_t tcpcs:1; 2404 uint32_t udpcs:1; 2405 uint32_t ipcs:1; 2406 uint32_t rsvd3:1; 2407 uint32_t rsvd2:1; 2408 uint32_t forward:1; 2409 uint32_t crc:1; 2410 uint32_t event:1; 2411 uint32_t complete:1; 2412 2413 /* dw3 */ 2414 uint32_t vlan_tag:16; 2415 uint32_t total_length:16; 2416 #else 2417 /* dw0 */ 2418 uint32_t rsvd0; 2419 2420 /* dw1 */ 2421 uint32_t rsvd1:18; 2422 uint32_t last_seg_udp_len:14; 2423 2424 /* dw2 */ 2425 uint32_t complete:1; 2426 uint32_t event:1; 2427 uint32_t crc:1; 2428 uint32_t forward:1; 2429 uint32_t rsvd2:1; 2430 uint32_t rsvd3:1; 2431 uint32_t ipcs:1; 2432 uint32_t udpcs:1; 2433 uint32_t tcpcs:1; 2434 uint32_t lso:1; 2435 uint32_t vlan:1; 2436 uint32_t rsvd4:2; 2437 uint32_t num_wqe:5; 2438 uint32_t lso_mss:14; 2439 2440 /* dw3 */ 2441 uint32_t total_length:16; 2442 uint32_t vlan_tag:16; 2443 #endif 2444 } s; 2445 uint32_t dw[4]; 2446 } u0; 2447 }; 2448 2449 /* NIC fragment WQE */ 2450 struct oce_nic_frag_wqe { 2451 union { 2452 struct { 2453 /* dw0 */ 2454 uint32_t frag_pa_hi; 2455 /* dw1 */ 2456 uint32_t frag_pa_lo; 2457 /* dw2 */ 2458 uint32_t rsvd0; 2459 uint32_t frag_len; 2460 } s; 2461 uint32_t dw[4]; 2462 } u0; 2463 }; 2464 2465 /* Ethernet Tx Completion Descriptor */ 2466 struct oce_nic_tx_cqe { 2467 union { 2468 struct { 2469 #ifdef _BIG_ENDIAN 2470 /* dw 0 */ 2471 uint32_t status:4; 2472 uint32_t rsvd0:8; 2473 uint32_t port:2; 2474 uint32_t ct:2; 2475 uint32_t wqe_index:16; 2476 2477 /* dw 1 */ 2478 uint32_t rsvd1:5; 2479 uint32_t cast_enc:2; 2480 uint32_t lso:1; 2481 uint32_t nwh_bytes:8; 2482 uint32_t user_bytes:16; 2483 2484 /* dw 2 */ 2485 uint32_t rsvd2; 2486 2487 /* dw 3 */ 2488 uint32_t valid:1; 2489 uint32_t rsvd3:4; 2490 uint32_t wq_id:11; 2491 uint32_t num_pkts:16; 2492 #else 2493 /* dw 0 */ 2494 uint32_t wqe_index:16; 2495 uint32_t ct:2; 2496 uint32_t port:2; 2497 uint32_t rsvd0:8; 2498 uint32_t status:4; 2499 2500 /* dw 1 */ 2501 uint32_t user_bytes:16; 2502 uint32_t nwh_bytes:8; 2503 uint32_t lso:1; 2504 uint32_t cast_enc:2; 2505 uint32_t rsvd1:5; 2506 /* dw 2 */ 2507 uint32_t rsvd2; 2508 2509 /* dw 3 */ 2510 uint32_t num_pkts:16; 2511 uint32_t wq_id:11; 2512 uint32_t rsvd3:4; 2513 uint32_t valid:1; 2514 #endif 2515 } s; 2516 uint32_t dw[4]; 2517 } u0; 2518 }; 2519 #define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) 2520 #define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) 2521 2522 /* Receive Queue Entry (RQE) */ 2523 struct oce_nic_rqe { 2524 union { 2525 struct { 2526 uint32_t frag_pa_hi; 2527 uint32_t frag_pa_lo; 2528 } s; 2529 uint32_t dw[2]; 2530 } u0; 2531 }; 2532 2533 /* NIC Receive CQE */ 2534 struct oce_nic_rx_cqe { 2535 union { 2536 struct { 2537 #ifdef _BIG_ENDIAN 2538 /* dw 0 */ 2539 uint32_t ip_options:1; 2540 uint32_t port:1; 2541 uint32_t pkt_size:14; 2542 uint32_t vlan_tag:16; 2543 2544 /* dw 1 */ 2545 uint32_t num_fragments:3; 2546 uint32_t switched:1; 2547 uint32_t ct:2; 2548 uint32_t frag_index:10; 2549 uint32_t rsvd0:1; 2550 uint32_t vlan_tag_present:1; 2551 uint32_t mac_dst:6; 2552 uint32_t ip_ver:1; 2553 uint32_t l4_cksum_pass:1; 2554 uint32_t ip_cksum_pass:1; 2555 uint32_t udpframe:1; 2556 uint32_t tcpframe:1; 2557 uint32_t ipframe:1; 2558 uint32_t rss_hp:1; 2559 uint32_t error:1; 2560 2561 /* dw 2 */ 2562 uint32_t valid:1; 2563 uint32_t hds_type:2; 2564 uint32_t lro_pkt:1; 2565 uint32_t rsvd4:1; 2566 uint32_t hds_hdr_size:12; 2567 uint32_t hds_hdr_frag_index:10; 2568 uint32_t rss_bank:1; 2569 uint32_t qnq:1; 2570 uint32_t pkt_type:2; 2571 uint32_t rss_flush:1; 2572 2573 /* dw 3 */ 2574 uint32_t rss_hash_value; 2575 #else 2576 /* dw 0 */ 2577 uint32_t vlan_tag:16; 2578 uint32_t pkt_size:14; 2579 uint32_t port:1; 2580 uint32_t ip_options:1; 2581 /* dw 1 */ 2582 uint32_t error:1; 2583 uint32_t rss_hp:1; 2584 uint32_t ipframe:1; 2585 uint32_t tcpframe:1; 2586 uint32_t udpframe:1; 2587 uint32_t ip_cksum_pass:1; 2588 uint32_t l4_cksum_pass:1; 2589 uint32_t ip_ver:1; 2590 uint32_t mac_dst:6; 2591 uint32_t vlan_tag_present:1; 2592 uint32_t rsvd0:1; 2593 uint32_t frag_index:10; 2594 uint32_t ct:2; 2595 uint32_t switched:1; 2596 uint32_t num_fragments:3; 2597 2598 /* dw 2 */ 2599 uint32_t rss_flush:1; 2600 uint32_t pkt_type:2; 2601 uint32_t qnq:1; 2602 uint32_t rss_bank:1; 2603 uint32_t hds_hdr_frag_index:10; 2604 uint32_t hds_hdr_size:12; 2605 uint32_t rsvd4:1; 2606 uint32_t lro_pkt:1; 2607 uint32_t hds_type:2; 2608 uint32_t valid:1; 2609 /* dw 3 */ 2610 uint32_t rss_hash_value; 2611 #endif 2612 } s; 2613 uint32_t dw[4]; 2614 } u0; 2615 }; 2616 /* NIC Receive CQE_v1 */ 2617 struct oce_nic_rx_cqe_v1 { 2618 union { 2619 struct { 2620 #ifdef _BIG_ENDIAN 2621 /* dw 0 */ 2622 uint32_t ip_options:1; 2623 uint32_t vlan_tag_present:1; 2624 uint32_t pkt_size:14; 2625 uint32_t vlan_tag:16; 2626 2627 /* dw 1 */ 2628 uint32_t num_fragments:3; 2629 uint32_t switched:1; 2630 uint32_t ct:2; 2631 uint32_t frag_index:10; 2632 uint32_t rsvd0:1; 2633 uint32_t mac_dst:7; 2634 uint32_t ip_ver:1; 2635 uint32_t l4_cksum_pass:1; 2636 uint32_t ip_cksum_pass:1; 2637 uint32_t udpframe:1; 2638 uint32_t tcpframe:1; 2639 uint32_t ipframe:1; 2640 uint32_t rss_hp:1; 2641 uint32_t error:1; 2642 2643 /* dw 2 */ 2644 uint32_t valid:1; 2645 uint32_t rsvd4:13; 2646 uint32_t hds_hdr_size: 2647 uint32_t hds_hdr_frag_index:8; 2648 uint32_t vlantag:1; 2649 uint32_t port:2; 2650 uint32_t rss_bank:1; 2651 uint32_t qnq:1; 2652 uint32_t pkt_type:2; 2653 uint32_t rss_flush:1; 2654 2655 /* dw 3 */ 2656 uint32_t rss_hash_value; 2657 #else 2658 /* dw 0 */ 2659 uint32_t vlan_tag:16; 2660 uint32_t pkt_size:14; 2661 uint32_t vlan_tag_present:1; 2662 uint32_t ip_options:1; 2663 /* dw 1 */ 2664 uint32_t error:1; 2665 uint32_t rss_hp:1; 2666 uint32_t ipframe:1; 2667 uint32_t tcpframe:1; 2668 uint32_t udpframe:1; 2669 uint32_t ip_cksum_pass:1; 2670 uint32_t l4_cksum_pass:1; 2671 uint32_t ip_ver:1; 2672 uint32_t mac_dst:7; 2673 uint32_t rsvd0:1; 2674 uint32_t frag_index:10; 2675 uint32_t ct:2; 2676 uint32_t switched:1; 2677 uint32_t num_fragments:3; 2678 2679 /* dw 2 */ 2680 uint32_t rss_flush:1; 2681 uint32_t pkt_type:2; 2682 uint32_t qnq:1; 2683 uint32_t rss_bank:1; 2684 uint32_t port:2; 2685 uint32_t vlantag:1; 2686 uint32_t hds_hdr_frag_index:8; 2687 uint32_t hds_hdr_size:2; 2688 uint32_t rsvd4:13; 2689 uint32_t valid:1; 2690 /* dw 3 */ 2691 uint32_t rss_hash_value; 2692 #endif 2693 } s; 2694 uint32_t dw[4]; 2695 } u0; 2696 }; 2697 2698 #define RQ_CQE_VALID_MASK 0x80 2699 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2]) 2700 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0) 2701 2702 struct mbx_config_nic_promiscuous { 2703 struct mbx_hdr hdr; 2704 union { 2705 struct { 2706 #ifdef _BIG_ENDIAN 2707 uint16_t rsvd0; 2708 uint8_t port1_promisc; 2709 uint8_t port0_promisc; 2710 #else 2711 uint8_t port0_promisc; 2712 uint8_t port1_promisc; 2713 uint16_t rsvd0; 2714 #endif 2715 } req; 2716 2717 struct { 2718 uint32_t rsvd0; 2719 } rsp; 2720 } params; 2721 }; 2722 2723 typedef union oce_wq_ctx_u { 2724 uint32_t dw[17]; 2725 struct { 2726 #ifdef _BIG_ENDIAN 2727 /* dw4 */ 2728 uint32_t dw4rsvd2:8; 2729 uint32_t nic_wq_type:8; 2730 uint32_t dw4rsvd1:8; 2731 uint32_t num_pages:8; 2732 /* dw5 */ 2733 uint32_t dw5rsvd2:12; 2734 uint32_t wq_size:4; 2735 uint32_t dw5rsvd1:16; 2736 /* dw6 */ 2737 uint32_t valid:1; 2738 uint32_t dw6rsvd1:31; 2739 /* dw7 */ 2740 uint32_t dw7rsvd1:16; 2741 uint32_t cq_id:16; 2742 #else 2743 /* dw4 */ 2744 uint32_t num_pages:8; 2745 #if 0 2746 uint32_t dw4rsvd1:8; 2747 #else 2748 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */ 2749 uint32_t ulp_mask:8; 2750 #endif 2751 uint32_t nic_wq_type:8; 2752 uint32_t dw4rsvd2:8; 2753 /* dw5 */ 2754 uint32_t dw5rsvd1:16; 2755 uint32_t wq_size:4; 2756 uint32_t dw5rsvd2:12; 2757 /* dw6 */ 2758 uint32_t dw6rsvd1:31; 2759 uint32_t valid:1; 2760 /* dw7 */ 2761 uint32_t cq_id:16; 2762 uint32_t dw7rsvd1:16; 2763 #endif 2764 /* dw8 - dw20 */ 2765 uint32_t dw8_20rsvd1[13]; 2766 } v0; 2767 struct { 2768 #ifdef _BIG_ENDIAN 2769 /* dw4 */ 2770 uint32_t dw4rsvd2:8; 2771 uint32_t nic_wq_type:8; 2772 uint32_t dw4rsvd1:8; 2773 uint32_t num_pages:8; 2774 /* dw5 */ 2775 uint32_t dw5rsvd2:12; 2776 uint32_t wq_size:4; 2777 uint32_t iface_id:16; 2778 /* dw6 */ 2779 uint32_t valid:1; 2780 uint32_t dw6rsvd1:31; 2781 /* dw7 */ 2782 uint32_t dw7rsvd1:16; 2783 uint32_t cq_id:16; 2784 #else 2785 /* dw4 */ 2786 uint32_t num_pages:8; 2787 uint32_t dw4rsvd1:8; 2788 uint32_t nic_wq_type:8; 2789 uint32_t dw4rsvd2:8; 2790 /* dw5 */ 2791 uint32_t iface_id:16; 2792 uint32_t wq_size:4; 2793 uint32_t dw5rsvd2:12; 2794 /* dw6 */ 2795 uint32_t dw6rsvd1:31; 2796 uint32_t valid:1; 2797 /* dw7 */ 2798 uint32_t cq_id:16; 2799 uint32_t dw7rsvd1:16; 2800 #endif 2801 /* dw8 - dw20 */ 2802 uint32_t dw8_20rsvd1[13]; 2803 } v1; 2804 } oce_wq_ctx_t; 2805 2806 /** 2807 * @brief [07] NIC_CREATE_WQ 2808 * @note 2809 * Lancer requires an InterfaceID to be specified with every WQ. This 2810 * is the basis for NIC IOV where the Interface maps to a vPort and maps 2811 * to both Tx and Rx sides. 2812 */ 2813 #define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */ 2814 #define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */ 2815 struct mbx_create_nic_wq { 2816 struct mbx_hdr hdr; 2817 union { 2818 struct { 2819 uint8_t num_pages; 2820 uint8_t ulp_num; 2821 uint16_t nic_wq_type; 2822 uint16_t if_id; 2823 uint8_t wq_size; 2824 uint8_t rsvd1; 2825 uint32_t rsvd2; 2826 uint16_t cq_id; 2827 uint16_t rsvd3; 2828 uint32_t rsvd4[13]; 2829 struct phys_addr pages[8]; 2830 2831 } req; 2832 2833 struct { 2834 uint16_t wq_id; 2835 uint16_t rid; 2836 uint32_t db_offset; 2837 uint8_t tc_id; 2838 uint8_t rsvd0[3]; 2839 } rsp; 2840 } params; 2841 }; 2842 2843 /* [09] NIC_DELETE_WQ */ 2844 struct mbx_delete_nic_wq { 2845 /* dw0 - dw3 */ 2846 struct mbx_hdr hdr; 2847 union { 2848 struct { 2849 #ifdef _BIG_ENDIAN 2850 /* dw4 */ 2851 uint16_t rsvd0; 2852 uint16_t wq_id; 2853 #else 2854 /* dw4 */ 2855 uint16_t wq_id; 2856 uint16_t rsvd0; 2857 #endif 2858 } req; 2859 struct { 2860 uint32_t rsvd0; 2861 } rsp; 2862 } params; 2863 }; 2864 2865 2866 2867 struct mbx_create_nic_rq { 2868 struct mbx_hdr hdr; 2869 union { 2870 struct { 2871 uint16_t cq_id; 2872 uint8_t frag_size; 2873 uint8_t num_pages; 2874 struct phys_addr pages[2]; 2875 uint32_t if_id; 2876 uint16_t max_frame_size; 2877 uint16_t page_size; 2878 uint32_t is_rss_queue; 2879 } req; 2880 2881 struct { 2882 uint16_t rq_id; 2883 uint8_t rss_cpuid; 2884 uint8_t rsvd0; 2885 } rsp; 2886 2887 } params; 2888 }; 2889 2890 2891 2892 /* [10] NIC_DELETE_RQ */ 2893 struct mbx_delete_nic_rq { 2894 /* dw0 - dw3 */ 2895 struct mbx_hdr hdr; 2896 union { 2897 struct { 2898 #ifdef _BIG_ENDIAN 2899 /* dw4 */ 2900 uint16_t bypass_flush; 2901 uint16_t rq_id; 2902 #else 2903 /* dw4 */ 2904 uint16_t rq_id; 2905 uint16_t bypass_flush; 2906 #endif 2907 } req; 2908 2909 struct { 2910 /* dw4 */ 2911 uint32_t rsvd0; 2912 } rsp; 2913 } params; 2914 }; 2915 2916 2917 2918 2919 struct oce_port_rxf_stats_v0 { 2920 uint32_t rx_bytes_lsd; /* dword 0*/ 2921 uint32_t rx_bytes_msd; /* dword 1*/ 2922 uint32_t rx_total_frames; /* dword 2*/ 2923 uint32_t rx_unicast_frames; /* dword 3*/ 2924 uint32_t rx_multicast_frames; /* dword 4*/ 2925 uint32_t rx_broadcast_frames; /* dword 5*/ 2926 uint32_t rx_crc_errors; /* dword 6*/ 2927 uint32_t rx_alignment_symbol_errors; /* dword 7*/ 2928 uint32_t rx_pause_frames; /* dword 8*/ 2929 uint32_t rx_control_frames; /* dword 9*/ 2930 uint32_t rx_in_range_errors; /* dword 10*/ 2931 uint32_t rx_out_range_errors; /* dword 11*/ 2932 uint32_t rx_frame_too_long; /* dword 12*/ 2933 uint32_t rx_address_match_errors; /* dword 13*/ 2934 uint32_t rx_vlan_mismatch; /* dword 14*/ 2935 uint32_t rx_dropped_too_small; /* dword 15*/ 2936 uint32_t rx_dropped_too_short; /* dword 16*/ 2937 uint32_t rx_dropped_header_too_small; /* dword 17*/ 2938 uint32_t rx_dropped_tcp_length; /* dword 18*/ 2939 uint32_t rx_dropped_runt; /* dword 19*/ 2940 uint32_t rx_64_byte_packets; /* dword 20*/ 2941 uint32_t rx_65_127_byte_packets; /* dword 21*/ 2942 uint32_t rx_128_256_byte_packets; /* dword 22*/ 2943 uint32_t rx_256_511_byte_packets; /* dword 23*/ 2944 uint32_t rx_512_1023_byte_packets; /* dword 24*/ 2945 uint32_t rx_1024_1518_byte_packets; /* dword 25*/ 2946 uint32_t rx_1519_2047_byte_packets; /* dword 26*/ 2947 uint32_t rx_2048_4095_byte_packets; /* dword 27*/ 2948 uint32_t rx_4096_8191_byte_packets; /* dword 28*/ 2949 uint32_t rx_8192_9216_byte_packets; /* dword 29*/ 2950 uint32_t rx_ip_checksum_errs; /* dword 30*/ 2951 uint32_t rx_tcp_checksum_errs; /* dword 31*/ 2952 uint32_t rx_udp_checksum_errs; /* dword 32*/ 2953 uint32_t rx_non_rss_packets; /* dword 33*/ 2954 uint32_t rx_ipv4_packets; /* dword 34*/ 2955 uint32_t rx_ipv6_packets; /* dword 35*/ 2956 uint32_t rx_ipv4_bytes_lsd; /* dword 36*/ 2957 uint32_t rx_ipv4_bytes_msd; /* dword 37*/ 2958 uint32_t rx_ipv6_bytes_lsd; /* dword 38*/ 2959 uint32_t rx_ipv6_bytes_msd; /* dword 39*/ 2960 uint32_t rx_chute1_packets; /* dword 40*/ 2961 uint32_t rx_chute2_packets; /* dword 41*/ 2962 uint32_t rx_chute3_packets; /* dword 42*/ 2963 uint32_t rx_management_packets; /* dword 43*/ 2964 uint32_t rx_switched_unicast_packets; /* dword 44*/ 2965 uint32_t rx_switched_multicast_packets; /* dword 45*/ 2966 uint32_t rx_switched_broadcast_packets; /* dword 46*/ 2967 uint32_t tx_bytes_lsd; /* dword 47*/ 2968 uint32_t tx_bytes_msd; /* dword 48*/ 2969 uint32_t tx_unicastframes; /* dword 49*/ 2970 uint32_t tx_multicastframes; /* dword 50*/ 2971 uint32_t tx_broadcastframes; /* dword 51*/ 2972 uint32_t tx_pauseframes; /* dword 52*/ 2973 uint32_t tx_controlframes; /* dword 53*/ 2974 uint32_t tx_64_byte_packets; /* dword 54*/ 2975 uint32_t tx_65_127_byte_packets; /* dword 55*/ 2976 uint32_t tx_128_256_byte_packets; /* dword 56*/ 2977 uint32_t tx_256_511_byte_packets; /* dword 57*/ 2978 uint32_t tx_512_1023_byte_packets; /* dword 58*/ 2979 uint32_t tx_1024_1518_byte_packets; /* dword 59*/ 2980 uint32_t tx_1519_2047_byte_packets; /* dword 60*/ 2981 uint32_t tx_2048_4095_byte_packets; /* dword 61*/ 2982 uint32_t tx_4096_8191_byte_packets; /* dword 62*/ 2983 uint32_t tx_8192_9216_byte_packets; /* dword 63*/ 2984 uint32_t rxpp_fifo_overflow_drop; /* dword 64*/ 2985 uint32_t rx_input_fifo_overflow_drop; /* dword 65*/ 2986 }; 2987 2988 2989 struct oce_rxf_stats_v0 { 2990 struct oce_port_rxf_stats_v0 port[2]; 2991 uint32_t rx_drops_no_pbuf; /* dword 132*/ 2992 uint32_t rx_drops_no_txpb; /* dword 133*/ 2993 uint32_t rx_drops_no_erx_descr; /* dword 134*/ 2994 uint32_t rx_drops_no_tpre_descr; /* dword 135*/ 2995 uint32_t management_rx_port_packets; /* dword 136*/ 2996 uint32_t management_rx_port_bytes; /* dword 137*/ 2997 uint32_t management_rx_port_pause_frames;/* dword 138*/ 2998 uint32_t management_rx_port_errors; /* dword 139*/ 2999 uint32_t management_tx_port_packets; /* dword 140*/ 3000 uint32_t management_tx_port_bytes; /* dword 141*/ 3001 uint32_t management_tx_port_pause; /* dword 142*/ 3002 uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/ 3003 uint32_t rx_drops_too_many_frags; /* dword 144*/ 3004 uint32_t rx_drops_invalid_ring; /* dword 145*/ 3005 uint32_t forwarded_packets; /* dword 146*/ 3006 uint32_t rx_drops_mtu; /* dword 147*/ 3007 uint32_t rsvd0[7]; 3008 uint32_t port0_jabber_events; 3009 uint32_t port1_jabber_events; 3010 uint32_t rsvd1[6]; 3011 }; 3012 3013 struct oce_port_rxf_stats_v1 { 3014 uint32_t rsvd0[12]; 3015 uint32_t rx_crc_errors; 3016 uint32_t rx_alignment_symbol_errors; 3017 uint32_t rx_pause_frames; 3018 uint32_t rx_priority_pause_frames; 3019 uint32_t rx_control_frames; 3020 uint32_t rx_in_range_errors; 3021 uint32_t rx_out_range_errors; 3022 uint32_t rx_frame_too_long; 3023 uint32_t rx_address_match_errors; 3024 uint32_t rx_dropped_too_small; 3025 uint32_t rx_dropped_too_short; 3026 uint32_t rx_dropped_header_too_small; 3027 uint32_t rx_dropped_tcp_length; 3028 uint32_t rx_dropped_runt; 3029 uint32_t rsvd1[10]; 3030 uint32_t rx_ip_checksum_errs; 3031 uint32_t rx_tcp_checksum_errs; 3032 uint32_t rx_udp_checksum_errs; 3033 uint32_t rsvd2[7]; 3034 uint32_t rx_switched_unicast_packets; 3035 uint32_t rx_switched_multicast_packets; 3036 uint32_t rx_switched_broadcast_packets; 3037 uint32_t rsvd3[3]; 3038 uint32_t tx_pauseframes; 3039 uint32_t tx_priority_pauseframes; 3040 uint32_t tx_controlframes; 3041 uint32_t rsvd4[10]; 3042 uint32_t rxpp_fifo_overflow_drop; 3043 uint32_t rx_input_fifo_overflow_drop; 3044 uint32_t pmem_fifo_overflow_drop; 3045 uint32_t jabber_events; 3046 uint32_t rsvd5[3]; 3047 }; 3048 3049 3050 struct oce_rxf_stats_v1 { 3051 struct oce_port_rxf_stats_v1 port[4]; 3052 uint32_t rsvd0[2]; 3053 uint32_t rx_drops_no_pbuf; 3054 uint32_t rx_drops_no_txpb; 3055 uint32_t rx_drops_no_erx_descr; 3056 uint32_t rx_drops_no_tpre_descr; 3057 uint32_t rsvd1[6]; 3058 uint32_t rx_drops_too_many_frags; 3059 uint32_t rx_drops_invalid_ring; 3060 uint32_t forwarded_packets; 3061 uint32_t rx_drops_mtu; 3062 uint32_t rsvd2[14]; 3063 }; 3064 3065 struct oce_erx_stats_v1 { 3066 uint32_t rx_drops_no_fragments[68]; 3067 uint32_t rsvd[4]; 3068 }; 3069 3070 3071 struct oce_erx_stats_v0 { 3072 uint32_t rx_drops_no_fragments[44]; 3073 uint32_t rsvd[4]; 3074 }; 3075 3076 struct oce_pmem_stats { 3077 uint32_t eth_red_drops; 3078 uint32_t rsvd[5]; 3079 }; 3080 3081 struct oce_hw_stats_v1 { 3082 struct oce_rxf_stats_v1 rxf; 3083 uint32_t rsvd0[OCE_TXP_SW_SZ]; 3084 struct oce_erx_stats_v1 erx; 3085 struct oce_pmem_stats pmem; 3086 uint32_t rsvd1[18]; 3087 }; 3088 3089 struct oce_hw_stats_v0 { 3090 struct oce_rxf_stats_v0 rxf; 3091 uint32_t rsvd[48]; 3092 struct oce_erx_stats_v0 erx; 3093 struct oce_pmem_stats pmem; 3094 }; 3095 3096 struct mbx_get_nic_stats_v0 { 3097 struct mbx_hdr hdr; 3098 union { 3099 struct { 3100 uint32_t rsvd0; 3101 } req; 3102 3103 union { 3104 struct oce_hw_stats_v0 stats; 3105 } rsp; 3106 } params; 3107 }; 3108 3109 struct mbx_get_nic_stats { 3110 struct mbx_hdr hdr; 3111 union { 3112 struct { 3113 uint32_t rsvd0; 3114 } req; 3115 3116 struct { 3117 struct oce_hw_stats_v1 stats; 3118 } rsp; 3119 } params; 3120 }; 3121 3122 3123 /* [18(0x12)] NIC_GET_PPORT_STATS */ 3124 struct pport_stats { 3125 uint64_t tx_pkts; 3126 uint64_t tx_unicast_pkts; 3127 uint64_t tx_multicast_pkts; 3128 uint64_t tx_broadcast_pkts; 3129 uint64_t tx_bytes; 3130 uint64_t tx_unicast_bytes; 3131 uint64_t tx_multicast_bytes; 3132 uint64_t tx_broadcast_bytes; 3133 uint64_t tx_discards; 3134 uint64_t tx_errors; 3135 uint64_t tx_pause_frames; 3136 uint64_t tx_pause_on_frames; 3137 uint64_t tx_pause_off_frames; 3138 uint64_t tx_internal_mac_errors; 3139 uint64_t tx_control_frames; 3140 uint64_t tx_pkts_64_bytes; 3141 uint64_t tx_pkts_65_to_127_bytes; 3142 uint64_t tx_pkts_128_to_255_bytes; 3143 uint64_t tx_pkts_256_to_511_bytes; 3144 uint64_t tx_pkts_512_to_1023_bytes; 3145 uint64_t tx_pkts_1024_to_1518_bytes; 3146 uint64_t tx_pkts_1519_to_2047_bytes; 3147 uint64_t tx_pkts_2048_to_4095_bytes; 3148 uint64_t tx_pkts_4096_to_8191_bytes; 3149 uint64_t tx_pkts_8192_to_9216_bytes; 3150 uint64_t tx_lso_pkts; 3151 uint64_t rx_pkts; 3152 uint64_t rx_unicast_pkts; 3153 uint64_t rx_multicast_pkts; 3154 uint64_t rx_broadcast_pkts; 3155 uint64_t rx_bytes; 3156 uint64_t rx_unicast_bytes; 3157 uint64_t rx_multicast_bytes; 3158 uint64_t rx_broadcast_bytes; 3159 uint32_t rx_unknown_protos; 3160 uint32_t reserved_word69; 3161 uint64_t rx_discards; 3162 uint64_t rx_errors; 3163 uint64_t rx_crc_errors; 3164 uint64_t rx_alignment_errors; 3165 uint64_t rx_symbol_errors; 3166 uint64_t rx_pause_frames; 3167 uint64_t rx_pause_on_frames; 3168 uint64_t rx_pause_off_frames; 3169 uint64_t rx_frames_too_long; 3170 uint64_t rx_internal_mac_errors; 3171 uint32_t rx_undersize_pkts; 3172 uint32_t rx_oversize_pkts; 3173 uint32_t rx_fragment_pkts; 3174 uint32_t rx_jabbers; 3175 uint64_t rx_control_frames; 3176 uint64_t rx_control_frames_unknown_opcode; 3177 uint32_t rx_in_range_errors; 3178 uint32_t rx_out_of_range_errors; 3179 uint32_t rx_address_match_errors; 3180 uint32_t rx_vlan_mismatch_errors; 3181 uint32_t rx_dropped_too_small; 3182 uint32_t rx_dropped_too_short; 3183 uint32_t rx_dropped_header_too_small; 3184 uint32_t rx_dropped_invalid_tcp_length; 3185 uint32_t rx_dropped_runt; 3186 uint32_t rx_ip_checksum_errors; 3187 uint32_t rx_tcp_checksum_errors; 3188 uint32_t rx_udp_checksum_errors; 3189 uint32_t rx_non_rss_pkts; 3190 uint64_t reserved_word111; 3191 uint64_t rx_ipv4_pkts; 3192 uint64_t rx_ipv6_pkts; 3193 uint64_t rx_ipv4_bytes; 3194 uint64_t rx_ipv6_bytes; 3195 uint64_t rx_nic_pkts; 3196 uint64_t rx_tcp_pkts; 3197 uint64_t rx_iscsi_pkts; 3198 uint64_t rx_management_pkts; 3199 uint64_t rx_switched_unicast_pkts; 3200 uint64_t rx_switched_multicast_pkts; 3201 uint64_t rx_switched_broadcast_pkts; 3202 uint64_t num_forwards; 3203 uint32_t rx_fifo_overflow; 3204 uint32_t rx_input_fifo_overflow; 3205 uint64_t rx_drops_too_many_frags; 3206 uint32_t rx_drops_invalid_queue; 3207 uint32_t reserved_word141; 3208 uint64_t rx_drops_mtu; 3209 uint64_t rx_pkts_64_bytes; 3210 uint64_t rx_pkts_65_to_127_bytes; 3211 uint64_t rx_pkts_128_to_255_bytes; 3212 uint64_t rx_pkts_256_to_511_bytes; 3213 uint64_t rx_pkts_512_to_1023_bytes; 3214 uint64_t rx_pkts_1024_to_1518_bytes; 3215 uint64_t rx_pkts_1519_to_2047_bytes; 3216 uint64_t rx_pkts_2048_to_4095_bytes; 3217 uint64_t rx_pkts_4096_to_8191_bytes; 3218 uint64_t rx_pkts_8192_to_9216_bytes; 3219 }; 3220 3221 struct mbx_get_pport_stats { 3222 /* dw0 - dw3 */ 3223 struct mbx_hdr hdr; 3224 union { 3225 struct { 3226 /* dw4 */ 3227 #ifdef _BIG_ENDIAN 3228 uint32_t reset_stats:8; 3229 uint32_t rsvd0:8; 3230 uint32_t port_number:16; 3231 #else 3232 uint32_t port_number:16; 3233 uint32_t rsvd0:8; 3234 uint32_t reset_stats:8; 3235 #endif 3236 } req; 3237 3238 union { 3239 struct pport_stats pps; 3240 uint32_t pport_stats[164 - 4 + 1]; 3241 } rsp; 3242 } params; 3243 }; 3244 3245 /* [19(0x13)] NIC_GET_VPORT_STATS */ 3246 struct vport_stats { 3247 uint64_t tx_pkts; 3248 uint64_t tx_unicast_pkts; 3249 uint64_t tx_multicast_pkts; 3250 uint64_t tx_broadcast_pkts; 3251 uint64_t tx_bytes; 3252 uint64_t tx_unicast_bytes; 3253 uint64_t tx_multicast_bytes; 3254 uint64_t tx_broadcast_bytes; 3255 uint64_t tx_discards; 3256 uint64_t tx_errors; 3257 uint64_t tx_pkts_64_bytes; 3258 uint64_t tx_pkts_65_to_127_bytes; 3259 uint64_t tx_pkts_128_to_255_bytes; 3260 uint64_t tx_pkts_256_to_511_bytes; 3261 uint64_t tx_pkts_512_to_1023_bytes; 3262 uint64_t tx_pkts_1024_to_1518_bytes; 3263 uint64_t tx_pkts_1519_to_9699_bytes; 3264 uint64_t tx_pkts_over_9699_bytes; 3265 uint64_t rx_pkts; 3266 uint64_t rx_unicast_pkts; 3267 uint64_t rx_multicast_pkts; 3268 uint64_t rx_broadcast_pkts; 3269 uint64_t rx_bytes; 3270 uint64_t rx_unicast_bytes; 3271 uint64_t rx_multicast_bytes; 3272 uint64_t rx_broadcast_bytes; 3273 uint64_t rx_discards; 3274 uint64_t rx_errors; 3275 uint64_t rx_pkts_64_bytes; 3276 uint64_t rx_pkts_65_to_127_bytes; 3277 uint64_t rx_pkts_128_to_255_bytes; 3278 uint64_t rx_pkts_256_to_511_bytes; 3279 uint64_t rx_pkts_512_to_1023_bytes; 3280 uint64_t rx_pkts_1024_to_1518_bytes; 3281 uint64_t rx_pkts_1519_to_9699_bytes; 3282 uint64_t rx_pkts_gt_9699_bytes; 3283 }; 3284 struct mbx_get_vport_stats { 3285 /* dw0 - dw3 */ 3286 struct mbx_hdr hdr; 3287 union { 3288 struct { 3289 /* dw4 */ 3290 #ifdef _BIG_ENDIAN 3291 uint32_t reset_stats:8; 3292 uint32_t rsvd0:8; 3293 uint32_t vport_number:16; 3294 #else 3295 uint32_t vport_number:16; 3296 uint32_t rsvd0:8; 3297 uint32_t reset_stats:8; 3298 #endif 3299 } req; 3300 3301 union { 3302 struct vport_stats vps; 3303 uint32_t vport_stats[75 - 4 + 1]; 3304 } rsp; 3305 } params; 3306 }; 3307 3308 /** 3309 * @brief [20(0x14)] NIC_GET_QUEUE_STATS 3310 * The significant difference between vPort and Queue statistics is 3311 * the packet byte counters. 3312 */ 3313 struct queue_stats { 3314 uint64_t packets; 3315 uint64_t bytes; 3316 uint64_t errors; 3317 uint64_t drops; 3318 uint64_t buffer_errors; /* rsvd when tx */ 3319 }; 3320 3321 #define QUEUE_TYPE_WQ 0 3322 #define QUEUE_TYPE_RQ 1 3323 #define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */ 3324 3325 struct mbx_get_queue_stats { 3326 /* dw0 - dw3 */ 3327 struct mbx_hdr hdr; 3328 union { 3329 struct { 3330 /* dw4 */ 3331 #ifdef _BIG_ENDIAN 3332 uint32_t reset_stats:8; 3333 uint32_t queue_type:8; 3334 uint32_t queue_id:16; 3335 #else 3336 uint32_t queue_id:16; 3337 uint32_t queue_type:8; 3338 uint32_t reset_stats:8; 3339 #endif 3340 } req; 3341 3342 union { 3343 struct queue_stats qs; 3344 uint32_t queue_stats[13 - 4 + 1]; 3345 } rsp; 3346 } params; 3347 }; 3348 3349 3350 /* [01] NIC_CONFIG_RSS */ 3351 #define OCE_HASH_TBL_SZ 10 3352 #define OCE_CPU_TBL_SZ 128 3353 #define OCE_FLUSH 1 /* RSS flush completion per CQ port */ 3354 struct mbx_config_nic_rss { 3355 struct mbx_hdr hdr; 3356 union { 3357 struct { 3358 #ifdef _BIG_ENDIAN 3359 uint32_t if_id; 3360 uint16_t cpu_tbl_sz_log2; 3361 uint16_t enable_rss; 3362 uint32_t hash[OCE_HASH_TBL_SZ]; 3363 uint8_t cputable[OCE_CPU_TBL_SZ]; 3364 uint8_t rsvd[3]; 3365 uint8_t flush; 3366 #else 3367 uint32_t if_id; 3368 uint16_t enable_rss; 3369 uint16_t cpu_tbl_sz_log2; 3370 uint32_t hash[OCE_HASH_TBL_SZ]; 3371 uint8_t cputable[OCE_CPU_TBL_SZ]; 3372 uint8_t flush; 3373 uint8_t rsvd[3]; 3374 #endif 3375 } req; 3376 struct { 3377 uint8_t rsvd[3]; 3378 uint8_t rss_bank; 3379 } rsp; 3380 } params; 3381 }; 3382 3383 3384 #pragma pack() 3385 3386 3387 typedef uint32_t oce_stat_t; /* statistic counter */ 3388 3389 enum OCE_RXF_PORT_STATS { 3390 RXF_RX_BYTES_LSD, 3391 RXF_RX_BYTES_MSD, 3392 RXF_RX_TOTAL_FRAMES, 3393 RXF_RX_UNICAST_FRAMES, 3394 RXF_RX_MULTICAST_FRAMES, 3395 RXF_RX_BROADCAST_FRAMES, 3396 RXF_RX_CRC_ERRORS, 3397 RXF_RX_ALIGNMENT_SYMBOL_ERRORS, 3398 RXF_RX_PAUSE_FRAMES, 3399 RXF_RX_CONTROL_FRAMES, 3400 RXF_RX_IN_RANGE_ERRORS, 3401 RXF_RX_OUT_RANGE_ERRORS, 3402 RXF_RX_FRAME_TOO_LONG, 3403 RXF_RX_ADDRESS_MATCH_ERRORS, 3404 RXF_RX_VLAN_MISMATCH, 3405 RXF_RX_DROPPED_TOO_SMALL, 3406 RXF_RX_DROPPED_TOO_SHORT, 3407 RXF_RX_DROPPED_HEADER_TOO_SMALL, 3408 RXF_RX_DROPPED_TCP_LENGTH, 3409 RXF_RX_DROPPED_RUNT, 3410 RXF_RX_64_BYTE_PACKETS, 3411 RXF_RX_65_127_BYTE_PACKETS, 3412 RXF_RX_128_256_BYTE_PACKETS, 3413 RXF_RX_256_511_BYTE_PACKETS, 3414 RXF_RX_512_1023_BYTE_PACKETS, 3415 RXF_RX_1024_1518_BYTE_PACKETS, 3416 RXF_RX_1519_2047_BYTE_PACKETS, 3417 RXF_RX_2048_4095_BYTE_PACKETS, 3418 RXF_RX_4096_8191_BYTE_PACKETS, 3419 RXF_RX_8192_9216_BYTE_PACKETS, 3420 RXF_RX_IP_CHECKSUM_ERRS, 3421 RXF_RX_TCP_CHECKSUM_ERRS, 3422 RXF_RX_UDP_CHECKSUM_ERRS, 3423 RXF_RX_NON_RSS_PACKETS, 3424 RXF_RX_IPV4_PACKETS, 3425 RXF_RX_IPV6_PACKETS, 3426 RXF_RX_IPV4_BYTES_LSD, 3427 RXF_RX_IPV4_BYTES_MSD, 3428 RXF_RX_IPV6_BYTES_LSD, 3429 RXF_RX_IPV6_BYTES_MSD, 3430 RXF_RX_CHUTE1_PACKETS, 3431 RXF_RX_CHUTE2_PACKETS, 3432 RXF_RX_CHUTE3_PACKETS, 3433 RXF_RX_MANAGEMENT_PACKETS, 3434 RXF_RX_SWITCHED_UNICAST_PACKETS, 3435 RXF_RX_SWITCHED_MULTICAST_PACKETS, 3436 RXF_RX_SWITCHED_BROADCAST_PACKETS, 3437 RXF_TX_BYTES_LSD, 3438 RXF_TX_BYTES_MSD, 3439 RXF_TX_UNICAST_FRAMES, 3440 RXF_TX_MULTICAST_FRAMES, 3441 RXF_TX_BROADCAST_FRAMES, 3442 RXF_TX_PAUSE_FRAMES, 3443 RXF_TX_CONTROL_FRAMES, 3444 RXF_TX_64_BYTE_PACKETS, 3445 RXF_TX_65_127_BYTE_PACKETS, 3446 RXF_TX_128_256_BYTE_PACKETS, 3447 RXF_TX_256_511_BYTE_PACKETS, 3448 RXF_TX_512_1023_BYTE_PACKETS, 3449 RXF_TX_1024_1518_BYTE_PACKETS, 3450 RXF_TX_1519_2047_BYTE_PACKETS, 3451 RXF_TX_2048_4095_BYTE_PACKETS, 3452 RXF_TX_4096_8191_BYTE_PACKETS, 3453 RXF_TX_8192_9216_BYTE_PACKETS, 3454 RXF_RX_FIFO_OVERFLOW, 3455 RXF_RX_INPUT_FIFO_OVERFLOW, 3456 RXF_PORT_STATS_N_WORDS 3457 }; 3458 3459 enum OCE_RXF_ADDL_STATS { 3460 RXF_RX_DROPS_NO_PBUF, 3461 RXF_RX_DROPS_NO_TXPB, 3462 RXF_RX_DROPS_NO_ERX_DESCR, 3463 RXF_RX_DROPS_NO_TPRE_DESCR, 3464 RXF_MANAGEMENT_RX_PORT_PACKETS, 3465 RXF_MANAGEMENT_RX_PORT_BYTES, 3466 RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES, 3467 RXF_MANAGEMENT_RX_PORT_ERRORS, 3468 RXF_MANAGEMENT_TX_PORT_PACKETS, 3469 RXF_MANAGEMENT_TX_PORT_BYTES, 3470 RXF_MANAGEMENT_TX_PORT_PAUSE, 3471 RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW, 3472 RXF_RX_DROPS_TOO_MANY_FRAGS, 3473 RXF_RX_DROPS_INVALID_RING, 3474 RXF_FORWARDED_PACKETS, 3475 RXF_RX_DROPS_MTU, 3476 RXF_ADDL_STATS_N_WORDS 3477 }; 3478 3479 enum OCE_TX_CHUTE_PORT_STATS { 3480 CTPT_XMT_IPV4_PKTS, 3481 CTPT_XMT_IPV4_LSD, 3482 CTPT_XMT_IPV4_MSD, 3483 CTPT_XMT_IPV6_PKTS, 3484 CTPT_XMT_IPV6_LSD, 3485 CTPT_XMT_IPV6_MSD, 3486 CTPT_REXMT_IPV4_PKTs, 3487 CTPT_REXMT_IPV4_LSD, 3488 CTPT_REXMT_IPV4_MSD, 3489 CTPT_REXMT_IPV6_PKTs, 3490 CTPT_REXMT_IPV6_LSD, 3491 CTPT_REXMT_IPV6_MSD, 3492 CTPT_N_WORDS, 3493 }; 3494 3495 enum OCE_RX_ERR_STATS { 3496 RX_DROPS_NO_FRAGMENTS_0, 3497 RX_DROPS_NO_FRAGMENTS_1, 3498 RX_DROPS_NO_FRAGMENTS_2, 3499 RX_DROPS_NO_FRAGMENTS_3, 3500 RX_DROPS_NO_FRAGMENTS_4, 3501 RX_DROPS_NO_FRAGMENTS_5, 3502 RX_DROPS_NO_FRAGMENTS_6, 3503 RX_DROPS_NO_FRAGMENTS_7, 3504 RX_DROPS_NO_FRAGMENTS_8, 3505 RX_DROPS_NO_FRAGMENTS_9, 3506 RX_DROPS_NO_FRAGMENTS_10, 3507 RX_DROPS_NO_FRAGMENTS_11, 3508 RX_DROPS_NO_FRAGMENTS_12, 3509 RX_DROPS_NO_FRAGMENTS_13, 3510 RX_DROPS_NO_FRAGMENTS_14, 3511 RX_DROPS_NO_FRAGMENTS_15, 3512 RX_DROPS_NO_FRAGMENTS_16, 3513 RX_DROPS_NO_FRAGMENTS_17, 3514 RX_DROPS_NO_FRAGMENTS_18, 3515 RX_DROPS_NO_FRAGMENTS_19, 3516 RX_DROPS_NO_FRAGMENTS_20, 3517 RX_DROPS_NO_FRAGMENTS_21, 3518 RX_DROPS_NO_FRAGMENTS_22, 3519 RX_DROPS_NO_FRAGMENTS_23, 3520 RX_DROPS_NO_FRAGMENTS_24, 3521 RX_DROPS_NO_FRAGMENTS_25, 3522 RX_DROPS_NO_FRAGMENTS_26, 3523 RX_DROPS_NO_FRAGMENTS_27, 3524 RX_DROPS_NO_FRAGMENTS_28, 3525 RX_DROPS_NO_FRAGMENTS_29, 3526 RX_DROPS_NO_FRAGMENTS_30, 3527 RX_DROPS_NO_FRAGMENTS_31, 3528 RX_DROPS_NO_FRAGMENTS_32, 3529 RX_DROPS_NO_FRAGMENTS_33, 3530 RX_DROPS_NO_FRAGMENTS_34, 3531 RX_DROPS_NO_FRAGMENTS_35, 3532 RX_DROPS_NO_FRAGMENTS_36, 3533 RX_DROPS_NO_FRAGMENTS_37, 3534 RX_DROPS_NO_FRAGMENTS_38, 3535 RX_DROPS_NO_FRAGMENTS_39, 3536 RX_DROPS_NO_FRAGMENTS_40, 3537 RX_DROPS_NO_FRAGMENTS_41, 3538 RX_DROPS_NO_FRAGMENTS_42, 3539 RX_DROPS_NO_FRAGMENTS_43, 3540 RX_DEBUG_WDMA_SENT_HOLD, 3541 RX_DEBUG_WDMA_PBFREE_SENT_HOLD, 3542 RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD, 3543 RX_DEBUG_PMEM_PBUF_DEALLOC, 3544 RX_ERRORS_N_WORDS 3545 }; 3546 3547 enum OCE_PMEM_ERR_STATS { 3548 PMEM_ETH_RED_DROPS, 3549 PMEM_LRO_RED_DROPS, 3550 PMEM_ULP0_RED_DROPS, 3551 PMEM_ULP1_RED_DROPS, 3552 PMEM_GLOBAL_RED_DROPS, 3553 PMEM_ERRORS_N_WORDS 3554 }; 3555 3556 /** 3557 * @brief Statistics for a given Physical Port 3558 * These satisfy all the required BE2 statistics and also the 3559 * following MIB objects: 3560 * 3561 * RFC 2863 - The Interfaces Group MIB 3562 * RFC 2819 - Remote Network Monitoring Management Information Base (RMON) 3563 * RFC 3635 - Managed Objects for the Ethernet-like Interface Types 3564 * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2) 3565 * 3566 */ 3567 enum OCE_PPORT_STATS { 3568 PPORT_TX_PKTS = 0, 3569 PPORT_TX_UNICAST_PKTS = 2, 3570 PPORT_TX_MULTICAST_PKTS = 4, 3571 PPORT_TX_BROADCAST_PKTS = 6, 3572 PPORT_TX_BYTES = 8, 3573 PPORT_TX_UNICAST_BYTES = 10, 3574 PPORT_TX_MULTICAST_BYTES = 12, 3575 PPORT_TX_BROADCAST_BYTES = 14, 3576 PPORT_TX_DISCARDS = 16, 3577 PPORT_TX_ERRORS = 18, 3578 PPORT_TX_PAUSE_FRAMES = 20, 3579 PPORT_TX_PAUSE_ON_FRAMES = 22, 3580 PPORT_TX_PAUSE_OFF_FRAMES = 24, 3581 PPORT_TX_INTERNAL_MAC_ERRORS = 26, 3582 PPORT_TX_CONTROL_FRAMES = 28, 3583 PPORT_TX_PKTS_64_BYTES = 30, 3584 PPORT_TX_PKTS_65_TO_127_BYTES = 32, 3585 PPORT_TX_PKTS_128_TO_255_BYTES = 34, 3586 PPORT_TX_PKTS_256_TO_511_BYTES = 36, 3587 PPORT_TX_PKTS_512_TO_1023_BYTES = 38, 3588 PPORT_TX_PKTS_1024_TO_1518_BYTES = 40, 3589 PPORT_TX_PKTS_1519_TO_2047_BYTES = 42, 3590 PPORT_TX_PKTS_2048_TO_4095_BYTES = 44, 3591 PPORT_TX_PKTS_4096_TO_8191_BYTES = 46, 3592 PPORT_TX_PKTS_8192_TO_9216_BYTES = 48, 3593 PPORT_TX_LSO_PKTS = 50, 3594 PPORT_RX_PKTS = 52, 3595 PPORT_RX_UNICAST_PKTS = 54, 3596 PPORT_RX_MULTICAST_PKTS = 56, 3597 PPORT_RX_BROADCAST_PKTS = 58, 3598 PPORT_RX_BYTES = 60, 3599 PPORT_RX_UNICAST_BYTES = 62, 3600 PPORT_RX_MULTICAST_BYTES = 64, 3601 PPORT_RX_BROADCAST_BYTES = 66, 3602 PPORT_RX_UNKNOWN_PROTOS = 68, 3603 PPORT_RESERVED_WORD69 = 69, 3604 PPORT_RX_DISCARDS = 70, 3605 PPORT_RX_ERRORS = 72, 3606 PPORT_RX_CRC_ERRORS = 74, 3607 PPORT_RX_ALIGNMENT_ERRORS = 76, 3608 PPORT_RX_SYMBOL_ERRORS = 78, 3609 PPORT_RX_PAUSE_FRAMES = 80, 3610 PPORT_RX_PAUSE_ON_FRAMES = 82, 3611 PPORT_RX_PAUSE_OFF_FRAMES = 84, 3612 PPORT_RX_FRAMES_TOO_LONG = 86, 3613 PPORT_RX_INTERNAL_MAC_ERRORS = 88, 3614 PPORT_RX_UNDERSIZE_PKTS = 90, 3615 PPORT_RX_OVERSIZE_PKTS = 91, 3616 PPORT_RX_FRAGMENT_PKTS = 92, 3617 PPORT_RX_JABBERS = 93, 3618 PPORT_RX_CONTROL_FRAMES = 94, 3619 PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96, 3620 PPORT_RX_IN_RANGE_ERRORS = 98, 3621 PPORT_RX_OUT_OF_RANGE_ERRORS = 99, 3622 PPORT_RX_ADDRESS_MATCH_ERRORS = 100, 3623 PPORT_RX_VLAN_MISMATCH_ERRORS = 101, 3624 PPORT_RX_DROPPED_TOO_SMALL = 102, 3625 PPORT_RX_DROPPED_TOO_SHORT = 103, 3626 PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104, 3627 PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105, 3628 PPORT_RX_DROPPED_RUNT = 106, 3629 PPORT_RX_IP_CHECKSUM_ERRORS = 107, 3630 PPORT_RX_TCP_CHECKSUM_ERRORS = 108, 3631 PPORT_RX_UDP_CHECKSUM_ERRORS = 109, 3632 PPORT_RX_NON_RSS_PKTS = 110, 3633 PPORT_RESERVED_WORD111 = 111, 3634 PPORT_RX_IPV4_PKTS = 112, 3635 PPORT_RX_IPV6_PKTS = 114, 3636 PPORT_RX_IPV4_BYTES = 116, 3637 PPORT_RX_IPV6_BYTES = 118, 3638 PPORT_RX_NIC_PKTS = 120, 3639 PPORT_RX_TCP_PKTS = 122, 3640 PPORT_RX_ISCSI_PKTS = 124, 3641 PPORT_RX_MANAGEMENT_PKTS = 126, 3642 PPORT_RX_SWITCHED_UNICAST_PKTS = 128, 3643 PPORT_RX_SWITCHED_MULTICAST_PKTS = 130, 3644 PPORT_RX_SWITCHED_BROADCAST_PKTS = 132, 3645 PPORT_NUM_FORWARDS = 134, 3646 PPORT_RX_FIFO_OVERFLOW = 136, 3647 PPORT_RX_INPUT_FIFO_OVERFLOW = 137, 3648 PPORT_RX_DROPS_TOO_MANY_FRAGS = 138, 3649 PPORT_RX_DROPS_INVALID_QUEUE = 140, 3650 PPORT_RESERVED_WORD141 = 141, 3651 PPORT_RX_DROPS_MTU = 142, 3652 PPORT_RX_PKTS_64_BYTES = 144, 3653 PPORT_RX_PKTS_65_TO_127_BYTES = 146, 3654 PPORT_RX_PKTS_128_TO_255_BYTES = 148, 3655 PPORT_RX_PKTS_256_TO_511_BYTES = 150, 3656 PPORT_RX_PKTS_512_TO_1023_BYTES = 152, 3657 PPORT_RX_PKTS_1024_TO_1518_BYTES = 154, 3658 PPORT_RX_PKTS_1519_TO_2047_BYTES = 156, 3659 PPORT_RX_PKTS_2048_TO_4095_BYTES = 158, 3660 PPORT_RX_PKTS_4096_TO_8191_BYTES = 160, 3661 PPORT_RX_PKTS_8192_TO_9216_BYTES = 162, 3662 PPORT_N_WORDS = 164 3663 }; 3664 3665 /** 3666 * @brief Statistics for a given Virtual Port (vPort) 3667 * The following describes the vPort statistics satisfying 3668 * requirements of Linux/VMWare netdev statistics and 3669 * Microsoft Windows Statistics along with other Operating Systems. 3670 */ 3671 enum OCE_VPORT_STATS { 3672 VPORT_TX_PKTS = 0, 3673 VPORT_TX_UNICAST_PKTS = 2, 3674 VPORT_TX_MULTICAST_PKTS = 4, 3675 VPORT_TX_BROADCAST_PKTS = 6, 3676 VPORT_TX_BYTES = 8, 3677 VPORT_TX_UNICAST_BYTES = 10, 3678 VPORT_TX_MULTICAST_BYTES = 12, 3679 VPORT_TX_BROADCAST_BYTES = 14, 3680 VPORT_TX_DISCARDS = 16, 3681 VPORT_TX_ERRORS = 18, 3682 VPORT_TX_PKTS_64_BYTES = 20, 3683 VPORT_TX_PKTS_65_TO_127_BYTES = 22, 3684 VPORT_TX_PKTS_128_TO_255_BYTES = 24, 3685 VPORT_TX_PKTS_256_TO_511_BYTES = 26, 3686 VPORT_TX_PKTS_512_TO_1023_BYTEs = 28, 3687 VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30, 3688 VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32, 3689 VPORT_TX_PKTS_OVER_9699_BYTES = 34, 3690 VPORT_RX_PKTS = 36, 3691 VPORT_RX_UNICAST_PKTS = 38, 3692 VPORT_RX_MULTICAST_PKTS = 40, 3693 VPORT_RX_BROADCAST_PKTS = 42, 3694 VPORT_RX_BYTES = 44, 3695 VPORT_RX_UNICAST_BYTES = 46, 3696 VPORT_RX_MULTICAST_BYTES = 48, 3697 VPORT_RX_BROADCAST_BYTES = 50, 3698 VPORT_RX_DISCARDS = 52, 3699 VPORT_RX_ERRORS = 54, 3700 VPORT_RX_PKTS_64_BYTES = 56, 3701 VPORT_RX_PKTS_65_TO_127_BYTES = 58, 3702 VPORT_RX_PKTS_128_TO_255_BYTES = 60, 3703 VPORT_RX_PKTS_256_TO_511_BYTES = 62, 3704 VPORT_RX_PKTS_512_TO_1023_BYTEs = 64, 3705 VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66, 3706 VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68, 3707 VPORT_RX_PKTS_OVER_9699_BYTES = 70, 3708 VPORT_N_WORDS = 72 3709 }; 3710 3711 /** 3712 * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ) 3713 * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ 3714 */ 3715 enum OCE_QUEUE_TX_STATS { 3716 QUEUE_TX_PKTS = 0, 3717 QUEUE_TX_BYTES = 2, 3718 QUEUE_TX_ERRORS = 4, 3719 QUEUE_TX_DROPS = 6, 3720 QUEUE_TX_N_WORDS = 8 3721 }; 3722 3723 enum OCE_QUEUE_RX_STATS { 3724 QUEUE_RX_PKTS = 0, 3725 QUEUE_RX_BYTES = 2, 3726 QUEUE_RX_ERRORS = 4, 3727 QUEUE_RX_DROPS = 6, 3728 QUEUE_RX_BUFFER_ERRORS = 8, 3729 QUEUE_RX_N_WORDS = 10 3730 }; 3731