1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2013 Emulex 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the Emulex Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Contact Information: 34 * freebsd-drivers@emulex.com 35 * 36 * Emulex 37 * 3333 Susan Street 38 * Costa Mesa, CA 92626 39 */ 40 41 42 #include <sys/types.h> 43 44 #undef _BIG_ENDIAN /* TODO */ 45 #pragma pack(1) 46 47 #define OC_CNA_GEN2 0x2 48 #define OC_CNA_GEN3 0x3 49 #define DEVID_TIGERSHARK 0x700 50 #define DEVID_TOMCAT 0x710 51 52 /* PCI CSR offsets */ 53 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 54 #define PCICFG_SEMAPHORE 0xbc 55 #define PCICFG_SOFT_RESET 0x5c 56 #define PCICFG_UE_STATUS_HI_MASK 0xac 57 #define PCICFG_UE_STATUS_LO_MASK 0xa8 58 #define PCICFG_ONLINE0 0xb0 59 #define PCICFG_ONLINE1 0xb4 60 #define INTR_EN 0x20000000 61 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 62 63 /********* UE Status and Mask Registers ***/ 64 #define PCICFG_UE_STATUS_LOW 0xA0 65 #define PCICFG_UE_STATUS_HIGH 0xA4 66 #define PCICFG_UE_STATUS_LOW_MASK 0xA8 67 68 /* Lancer SLIPORT registers */ 69 #define SLIPORT_STATUS_OFFSET 0x404 70 #define SLIPORT_CONTROL_OFFSET 0x408 71 #define SLIPORT_ERROR1_OFFSET 0x40C 72 #define SLIPORT_ERROR2_OFFSET 0x410 73 #define PHYSDEV_CONTROL_OFFSET 0x414 74 75 #define SLIPORT_STATUS_ERR_MASK 0x80000000 76 #define SLIPORT_STATUS_DIP_MASK 0x02000000 77 #define SLIPORT_STATUS_RN_MASK 0x01000000 78 #define SLIPORT_STATUS_RDY_MASK 0x00800000 79 #define SLI_PORT_CONTROL_IP_MASK 0x08000000 80 #define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 81 #define PHYSDEV_CONTROL_DD_MASK 0x00000004 82 #define PHYSDEV_CONTROL_INP_MASK 0x40000000 83 84 #define SLIPORT_ERROR_NO_RESOURCE1 0x2 85 #define SLIPORT_ERROR_NO_RESOURCE2 0x9 86 /* CSR register offsets */ 87 #define MPU_EP_CONTROL 0 88 #define MPU_EP_SEMAPHORE_BE3 0xac 89 #define MPU_EP_SEMAPHORE_XE201 0x400 90 #define MPU_EP_SEMAPHORE_SH 0x94 91 #define PCICFG_INTR_CTRL 0xfc 92 #define HOSTINTR_MASK (1 << 29) 93 #define HOSTINTR_PFUNC_SHIFT 26 94 #define HOSTINTR_PFUNC_MASK 7 95 96 /* POST status reg struct */ 97 #define POST_STAGE_POWER_ON_RESET 0x00 98 #define POST_STAGE_AWAITING_HOST_RDY 0x01 99 #define POST_STAGE_HOST_RDY 0x02 100 #define POST_STAGE_CHIP_RESET 0x03 101 #define POST_STAGE_ARMFW_READY 0xc000 102 #define POST_STAGE_ARMFW_UE 0xf000 103 104 /* DOORBELL registers */ 105 #define PD_RXULP_DB 0x0100 106 #define PD_TXULP_DB 0x0060 107 #define DB_RQ_ID_MASK 0x3FF 108 109 #define PD_CQ_DB 0x0120 110 #define PD_EQ_DB PD_CQ_DB 111 #define PD_MPU_MBOX_DB 0x0160 112 #define PD_MQ_DB 0x0140 113 114 #define DB_OFFSET 0xc0 115 #define DB_LRO_RQ_ID_MASK 0x7FF 116 117 /* EQE completion types */ 118 #define EQ_MINOR_CODE_COMPLETION 0x00 119 #define EQ_MINOR_CODE_OTHER 0x01 120 #define EQ_MAJOR_CODE_COMPLETION 0x00 121 122 /* Link Status field values */ 123 #define PHY_LINK_FAULT_NONE 0x0 124 #define PHY_LINK_FAULT_LOCAL 0x01 125 #define PHY_LINK_FAULT_REMOTE 0x02 126 127 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 128 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 129 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 130 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 131 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 132 133 #define PHY_LINK_DUPLEX_NONE 0x0 134 #define PHY_LINK_DUPLEX_HALF 0x1 135 #define PHY_LINK_DUPLEX_FULL 0x2 136 137 #define NTWK_PORT_A 0x0 /* (Port A) */ 138 #define NTWK_PORT_B 0x1 /* (Port B) */ 139 140 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 141 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 142 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 143 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 144 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 145 146 /* Hardware Address types */ 147 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 148 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 149 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 150 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 151 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 152 153 /* CREATE_IFACE capability and cap_en flags */ 154 #define MBX_RX_IFACE_FLAGS_RSS 0x4 155 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 156 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 157 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 158 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 159 #define MBX_RX_IFACE_FLAGS_VLAN 0x100 160 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 161 #define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400 162 #define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800 163 #define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000 164 #define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000 165 #define MBX_RX_IFACE_FLAGS_HDS 0x4000 166 #define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000 167 #define MBX_RX_IFACE_FLAGS_VMQ 0x10000 168 #define MBX_RX_IFACE_FLAGS_NETQ 0x20000 169 #define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000 170 #define MBX_RX_IFACE_FLAGS_LSO 0x80000 171 #define MBX_RX_IFACE_FLAGS_LRO 0x100000 172 173 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 174 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 175 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 176 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 177 178 #define MBX_DB_READY_BIT 0x1 179 #define MBX_DB_HI_BIT 0x2 180 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 181 #define ASYNC_EVENT_LINK_UP 0x1 182 #define ASYNC_EVENT_LINK_DOWN 0x0 183 #define ASYNC_EVENT_GRP5 0x5 184 #define ASYNC_EVENT_CODE_DEBUG 0x6 185 #define ASYNC_EVENT_PVID_STATE 0x3 186 #define ASYNC_EVENT_OS2BMC 0x5 187 #define ASYNC_EVENT_DEBUG_QNQ 0x1 188 #define ASYNC_EVENT_CODE_SLIPORT 0x11 189 #define VLAN_VID_MASK 0x0FFF 190 191 /* port link_status */ 192 #define ASYNC_EVENT_LOGICAL 0x02 193 194 /* Logical Link Status */ 195 #define NTWK_LOGICAL_LINK_DOWN 0 196 #define NTWK_LOGICAL_LINK_UP 1 197 198 /* Rx filter bits */ 199 #define NTWK_RX_FILTER_IP_CKSUM 0x1 200 #define NTWK_RX_FILTER_TCP_CKSUM 0x2 201 #define NTWK_RX_FILTER_UDP_CKSUM 0x4 202 #define NTWK_RX_FILTER_STRIP_CRC 0x8 203 204 /* max SGE per mbx */ 205 #define MAX_MBX_SGE 19 206 207 /* Max multicast filter size*/ 208 #define OCE_MAX_MC_FILTER_SIZE 64 209 210 /* PCI SLI (Service Level Interface) capabilities register */ 211 #define OCE_INTF_REG_OFFSET 0x58 212 #define OCE_INTF_VALID_SIG 6 /* register's signature */ 213 #define OCE_INTF_FUNC_RESET_REQD 1 214 #define OCE_INTF_HINT1_NOHINT 0 215 #define OCE_INTF_HINT1_SEMAINIT 1 216 #define OCE_INTF_HINT1_STATCTRL 2 217 #define OCE_INTF_IF_TYPE_0 0 218 #define OCE_INTF_IF_TYPE_1 1 219 #define OCE_INTF_IF_TYPE_2 2 220 #define OCE_INTF_IF_TYPE_3 3 221 #define OCE_INTF_SLI_REV3 3 /* not supported by driver */ 222 #define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */ 223 #define OCE_INTF_PHYS_FUNC 0 224 #define OCE_INTF_VIRT_FUNC 1 225 #define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */ 226 #define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */ 227 #define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */ 228 #define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */ 229 230 #define NIC_WQE_SIZE 16 231 #define NIC_UNICAST 0x00 232 #define NIC_MULTICAST 0x01 233 #define NIC_BROADCAST 0x02 234 235 #define NIC_HDS_NO_SPLIT 0x00 236 #define NIC_HDS_SPLIT_L3PL 0x01 237 #define NIC_HDS_SPLIT_L4PL 0x02 238 239 #define NIC_WQ_TYPE_FORWARDING 0x01 240 #define NIC_WQ_TYPE_STANDARD 0x02 241 #define NIC_WQ_TYPE_LOW_LATENCY 0x04 242 243 #define OCE_RESET_STATS 1 244 #define OCE_RETAIN_STATS 0 245 #define OCE_TXP_SW_SZ 48 246 247 typedef union pci_sli_intf_u { 248 uint32_t dw0; 249 struct { 250 #ifdef _BIG_ENDIAN 251 uint32_t sli_valid:3; 252 uint32_t sli_hint2:5; 253 uint32_t sli_hint1:8; 254 uint32_t sli_if_type:4; 255 uint32_t sli_family:4; 256 uint32_t sli_rev:4; 257 uint32_t rsv0:3; 258 uint32_t sli_func_type:1; 259 #else 260 uint32_t sli_func_type:1; 261 uint32_t rsv0:3; 262 uint32_t sli_rev:4; 263 uint32_t sli_family:4; 264 uint32_t sli_if_type:4; 265 uint32_t sli_hint1:8; 266 uint32_t sli_hint2:5; 267 uint32_t sli_valid:3; 268 #endif 269 } bits; 270 } pci_sli_intf_t; 271 272 /* physical address structure to be used in MBX */ 273 struct phys_addr { 274 /* dw0 */ 275 uint32_t lo; 276 /* dw1 */ 277 uint32_t hi; 278 }; 279 280 typedef union pcicfg_intr_ctl_u { 281 uint32_t dw0; 282 struct { 283 #ifdef _BIG_ENDIAN 284 uint32_t winselect:2; 285 uint32_t hostintr:1; 286 uint32_t pfnum:3; 287 uint32_t vf_cev_int_line_en:1; 288 uint32_t winaddr:23; 289 uint32_t membarwinen:1; 290 #else 291 uint32_t membarwinen:1; 292 uint32_t winaddr:23; 293 uint32_t vf_cev_int_line_en:1; 294 uint32_t pfnum:3; 295 uint32_t hostintr:1; 296 uint32_t winselect:2; 297 #endif 298 } bits; 299 } pcicfg_intr_ctl_t; 300 301 typedef union pcicfg_semaphore_u { 302 uint32_t dw0; 303 struct { 304 #ifdef _BIG_ENDIAN 305 uint32_t rsvd:31; 306 uint32_t lock:1; 307 #else 308 uint32_t lock:1; 309 uint32_t rsvd:31; 310 #endif 311 } bits; 312 } pcicfg_semaphore_t; 313 314 typedef union pcicfg_soft_reset_u { 315 uint32_t dw0; 316 struct { 317 #ifdef _BIG_ENDIAN 318 uint32_t nec_ll_rcvdetect:8; 319 uint32_t dbg_all_reqs_62_49:14; 320 uint32_t scratchpad0:1; 321 uint32_t exception_oe:1; 322 uint32_t soft_reset:1; 323 uint32_t rsvd0:7; 324 #else 325 uint32_t rsvd0:7; 326 uint32_t soft_reset:1; 327 uint32_t exception_oe:1; 328 uint32_t scratchpad0:1; 329 uint32_t dbg_all_reqs_62_49:14; 330 uint32_t nec_ll_rcvdetect:8; 331 #endif 332 } bits; 333 } pcicfg_soft_reset_t; 334 335 typedef union pcicfg_online1_u { 336 uint32_t dw0; 337 struct { 338 #ifdef _BIG_ENDIAN 339 uint32_t host8_online:1; 340 uint32_t host7_online:1; 341 uint32_t host6_online:1; 342 uint32_t host5_online:1; 343 uint32_t host4_online:1; 344 uint32_t host3_online:1; 345 uint32_t host2_online:1; 346 uint32_t ipc_online:1; 347 uint32_t arm_online:1; 348 uint32_t txp_online:1; 349 uint32_t xaui_online:1; 350 uint32_t rxpp_online:1; 351 uint32_t txpb_online:1; 352 uint32_t rr_online:1; 353 uint32_t pmem_online:1; 354 uint32_t pctl1_online:1; 355 uint32_t pctl0_online:1; 356 uint32_t pcs1online_online:1; 357 uint32_t mpu_iram_online:1; 358 uint32_t pcs0online_online:1; 359 uint32_t mgmt_mac_online:1; 360 uint32_t lpcmemhost_online:1; 361 #else 362 uint32_t lpcmemhost_online:1; 363 uint32_t mgmt_mac_online:1; 364 uint32_t pcs0online_online:1; 365 uint32_t mpu_iram_online:1; 366 uint32_t pcs1online_online:1; 367 uint32_t pctl0_online:1; 368 uint32_t pctl1_online:1; 369 uint32_t pmem_online:1; 370 uint32_t rr_online:1; 371 uint32_t txpb_online:1; 372 uint32_t rxpp_online:1; 373 uint32_t xaui_online:1; 374 uint32_t txp_online:1; 375 uint32_t arm_online:1; 376 uint32_t ipc_online:1; 377 uint32_t host2_online:1; 378 uint32_t host3_online:1; 379 uint32_t host4_online:1; 380 uint32_t host5_online:1; 381 uint32_t host6_online:1; 382 uint32_t host7_online:1; 383 uint32_t host8_online:1; 384 #endif 385 } bits; 386 } pcicfg_online1_t; 387 388 typedef union mpu_ep_semaphore_u { 389 uint32_t dw0; 390 struct { 391 #ifdef _BIG_ENDIAN 392 uint32_t error:1; 393 uint32_t backup_fw:1; 394 uint32_t iscsi_no_ip:1; 395 uint32_t iscsi_ip_conflict:1; 396 uint32_t option_rom_installed:1; 397 uint32_t iscsi_drv_loaded:1; 398 uint32_t rsvd0:10; 399 uint32_t stage:16; 400 #else 401 uint32_t stage:16; 402 uint32_t rsvd0:10; 403 uint32_t iscsi_drv_loaded:1; 404 uint32_t option_rom_installed:1; 405 uint32_t iscsi_ip_conflict:1; 406 uint32_t iscsi_no_ip:1; 407 uint32_t backup_fw:1; 408 uint32_t error:1; 409 #endif 410 } bits; 411 } mpu_ep_semaphore_t; 412 413 typedef union mpu_ep_control_u { 414 uint32_t dw0; 415 struct { 416 #ifdef _BIG_ENDIAN 417 uint32_t cpu_reset:1; 418 uint32_t rsvd1:15; 419 uint32_t ep_ram_init_status:1; 420 uint32_t rsvd0:12; 421 uint32_t m2_rxpbuf:1; 422 uint32_t m1_rxpbuf:1; 423 uint32_t m0_rxpbuf:1; 424 #else 425 uint32_t m0_rxpbuf:1; 426 uint32_t m1_rxpbuf:1; 427 uint32_t m2_rxpbuf:1; 428 uint32_t rsvd0:12; 429 uint32_t ep_ram_init_status:1; 430 uint32_t rsvd1:15; 431 uint32_t cpu_reset:1; 432 #endif 433 } bits; 434 } mpu_ep_control_t; 435 436 /* RX doorbell */ 437 typedef union pd_rxulp_db_u { 438 uint32_t dw0; 439 struct { 440 #ifdef _BIG_ENDIAN 441 uint32_t num_posted:8; 442 uint32_t invalidate:1; 443 uint32_t rsvd1:13; 444 uint32_t qid:10; 445 #else 446 uint32_t qid:10; 447 uint32_t rsvd1:13; 448 uint32_t invalidate:1; 449 uint32_t num_posted:8; 450 #endif 451 } bits; 452 } pd_rxulp_db_t; 453 454 /* TX doorbell */ 455 typedef union pd_txulp_db_u { 456 uint32_t dw0; 457 struct { 458 #ifdef _BIG_ENDIAN 459 uint32_t rsvd1:2; 460 uint32_t num_posted:14; 461 uint32_t rsvd0:6; 462 uint32_t qid:10; 463 #else 464 uint32_t qid:10; 465 uint32_t rsvd0:6; 466 uint32_t num_posted:14; 467 uint32_t rsvd1:2; 468 #endif 469 } bits; 470 } pd_txulp_db_t; 471 472 /* CQ doorbell */ 473 typedef union cq_db_u { 474 uint32_t dw0; 475 struct { 476 #ifdef _BIG_ENDIAN 477 uint32_t rsvd1:2; 478 uint32_t rearm:1; 479 uint32_t num_popped:13; 480 uint32_t rsvd0:5; 481 uint32_t event:1; 482 uint32_t qid:10; 483 #else 484 uint32_t qid:10; 485 uint32_t event:1; 486 uint32_t rsvd0:5; 487 uint32_t num_popped:13; 488 uint32_t rearm:1; 489 uint32_t rsvd1:2; 490 #endif 491 } bits; 492 } cq_db_t; 493 494 /* EQ doorbell */ 495 typedef union eq_db_u { 496 uint32_t dw0; 497 struct { 498 #ifdef _BIG_ENDIAN 499 uint32_t rsvd1:2; 500 uint32_t rearm:1; 501 uint32_t num_popped:13; 502 uint32_t rsvd0:5; 503 uint32_t event:1; 504 uint32_t clrint:1; 505 uint32_t qid:9; 506 #else 507 uint32_t qid:9; 508 uint32_t clrint:1; 509 uint32_t event:1; 510 uint32_t rsvd0:5; 511 uint32_t num_popped:13; 512 uint32_t rearm:1; 513 uint32_t rsvd1:2; 514 #endif 515 } bits; 516 } eq_db_t; 517 518 /* bootstrap mbox doorbell */ 519 typedef union pd_mpu_mbox_db_u { 520 uint32_t dw0; 521 struct { 522 #ifdef _BIG_ENDIAN 523 uint32_t address:30; 524 uint32_t hi:1; 525 uint32_t ready:1; 526 #else 527 uint32_t ready:1; 528 uint32_t hi:1; 529 uint32_t address:30; 530 #endif 531 } bits; 532 } pd_mpu_mbox_db_t; 533 534 /* MQ ring doorbell */ 535 typedef union pd_mq_db_u { 536 uint32_t dw0; 537 struct { 538 #ifdef _BIG_ENDIAN 539 uint32_t rsvd1:2; 540 uint32_t num_posted:14; 541 uint32_t rsvd0:5; 542 uint32_t mq_id:11; 543 #else 544 uint32_t mq_id:11; 545 uint32_t rsvd0:5; 546 uint32_t num_posted:14; 547 uint32_t rsvd1:2; 548 #endif 549 } bits; 550 } pd_mq_db_t; 551 552 /* 553 * Event Queue Entry 554 */ 555 struct oce_eqe { 556 uint32_t evnt; 557 }; 558 559 /* MQ scatter gather entry. Array of these make an SGL */ 560 struct oce_mq_sge { 561 uint32_t pa_lo; 562 uint32_t pa_hi; 563 uint32_t length; 564 }; 565 566 /* 567 * payload can contain an SGL or an embedded array of upto 59 dwords 568 */ 569 struct oce_mbx_payload { 570 union { 571 union { 572 struct oce_mq_sge sgl[MAX_MBX_SGE]; 573 uint32_t embedded[59]; 574 } u1; 575 uint32_t dw[59]; 576 } u0; 577 }; 578 579 /* 580 * MQ MBX structure 581 */ 582 struct oce_mbx { 583 union { 584 struct { 585 #ifdef _BIG_ENDIAN 586 uint32_t special:8; 587 uint32_t rsvd1:16; 588 uint32_t sge_count:5; 589 uint32_t rsvd0:2; 590 uint32_t embedded:1; 591 #else 592 uint32_t embedded:1; 593 uint32_t rsvd0:2; 594 uint32_t sge_count:5; 595 uint32_t rsvd1:16; 596 uint32_t special:8; 597 #endif 598 } s; 599 uint32_t dw0; 600 } u0; 601 602 uint32_t payload_length; 603 uint32_t tag[2]; 604 uint32_t rsvd2[1]; 605 struct oce_mbx_payload payload; 606 }; 607 608 /* completion queue entry for MQ */ 609 struct oce_mq_cqe { 610 union { 611 struct { 612 #ifdef _BIG_ENDIAN 613 /* dw0 */ 614 uint32_t extended_status:16; 615 uint32_t completion_status:16; 616 /* dw1 dw2 */ 617 uint32_t mq_tag[2]; 618 /* dw3 */ 619 uint32_t valid:1; 620 uint32_t async_event:1; 621 uint32_t hpi_buffer_cmpl:1; 622 uint32_t completed:1; 623 uint32_t consumed:1; 624 uint32_t rsvd0:3; 625 uint32_t async_type:8; 626 uint32_t event_type:8; 627 uint32_t rsvd1:8; 628 #else 629 /* dw0 */ 630 uint32_t completion_status:16; 631 uint32_t extended_status:16; 632 /* dw1 dw2 */ 633 uint32_t mq_tag[2]; 634 /* dw3 */ 635 uint32_t rsvd1:8; 636 uint32_t event_type:8; 637 uint32_t async_type:8; 638 uint32_t rsvd0:3; 639 uint32_t consumed:1; 640 uint32_t completed:1; 641 uint32_t hpi_buffer_cmpl:1; 642 uint32_t async_event:1; 643 uint32_t valid:1; 644 #endif 645 } s; 646 uint32_t dw[4]; 647 } u0; 648 }; 649 650 /* Mailbox Completion Status Codes */ 651 enum MBX_COMPLETION_STATUS { 652 MBX_CQE_STATUS_SUCCESS = 0x00, 653 MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01, 654 MBX_CQE_STATUS_INVALID_PARAMETER = 0x02, 655 MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03, 656 MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04, 657 MBX_CQE_STATUS_DMA_FAILED = 0x05 658 }; 659 660 struct oce_async_cqe_link_state { 661 union { 662 struct { 663 #ifdef _BIG_ENDIAN 664 /* dw0 */ 665 uint8_t speed; 666 uint8_t duplex; 667 uint8_t link_status; 668 uint8_t phy_port; 669 /* dw1 */ 670 uint16_t qos_link_speed; 671 uint8_t rsvd0; 672 uint8_t fault; 673 /* dw2 */ 674 uint32_t event_tag; 675 /* dw3 */ 676 uint32_t valid:1; 677 uint32_t async_event:1; 678 uint32_t rsvd2:6; 679 uint32_t event_type:8; 680 uint32_t event_code:8; 681 uint32_t rsvd1:8; 682 #else 683 /* dw0 */ 684 uint8_t phy_port; 685 uint8_t link_status; 686 uint8_t duplex; 687 uint8_t speed; 688 /* dw1 */ 689 uint8_t fault; 690 uint8_t rsvd0; 691 uint16_t qos_link_speed; 692 /* dw2 */ 693 uint32_t event_tag; 694 /* dw3 */ 695 uint32_t rsvd1:8; 696 uint32_t event_code:8; 697 uint32_t event_type:8; 698 uint32_t rsvd2:6; 699 uint32_t async_event:1; 700 uint32_t valid:1; 701 #endif 702 } s; 703 uint32_t dw[4]; 704 } u0; 705 }; 706 707 /* OS2BMC async event */ 708 struct oce_async_evt_grp5_os2bmc { 709 union { 710 struct { 711 uint32_t lrn_enable:1; 712 uint32_t lrn_disable:1; 713 uint32_t mgmt_enable:1; 714 uint32_t mgmt_disable:1; 715 uint32_t rsvd0:12; 716 uint32_t vlan_tag:16; 717 uint32_t arp_filter:1; 718 uint32_t dhcp_client_filt:1; 719 uint32_t dhcp_server_filt:1; 720 uint32_t net_bios_filt:1; 721 uint32_t rsvd1:3; 722 uint32_t bcast_filt:1; 723 uint32_t ipv6_nbr_filt:1; 724 uint32_t ipv6_ra_filt:1; 725 uint32_t ipv6_ras_filt:1; 726 uint32_t rsvd2[4]; 727 uint32_t mcast_filt:1; 728 uint32_t rsvd3:16; 729 uint32_t evt_tag; 730 uint32_t dword3; 731 } s; 732 uint32_t dword[4]; 733 } u; 734 }; 735 736 /* PVID aync event */ 737 struct oce_async_event_grp5_pvid_state { 738 uint8_t enabled; 739 uint8_t rsvd0; 740 uint16_t tag; 741 uint32_t event_tag; 742 uint32_t rsvd1; 743 uint32_t code; 744 }; 745 746 /* async event indicating outer VLAN tag in QnQ */ 747 struct oce_async_event_qnq { 748 uint8_t valid; /* Indicates if outer VLAN is valid */ 749 uint8_t rsvd0; 750 uint16_t vlan_tag; 751 uint32_t event_tag; 752 uint8_t rsvd1[4]; 753 uint32_t code; 754 } ; 755 756 typedef union oce_mq_ext_ctx_u { 757 uint32_t dw[6]; 758 struct { 759 #ifdef _BIG_ENDIAN 760 /* dw0 */ 761 uint32_t dw4rsvd1:16; 762 uint32_t num_pages:16; 763 /* dw1 */ 764 uint32_t async_evt_bitmap; 765 /* dw2 */ 766 uint32_t cq_id:10; 767 uint32_t dw5rsvd2:2; 768 uint32_t ring_size:4; 769 uint32_t dw5rsvd1:16; 770 /* dw3 */ 771 uint32_t valid:1; 772 uint32_t dw6rsvd1:31; 773 /* dw4 */ 774 uint32_t dw7rsvd1:21; 775 uint32_t async_cq_id:10; 776 uint32_t async_cq_valid:1; 777 #else 778 /* dw0 */ 779 uint32_t num_pages:16; 780 uint32_t dw4rsvd1:16; 781 /* dw1 */ 782 uint32_t async_evt_bitmap; 783 /* dw2 */ 784 uint32_t dw5rsvd1:16; 785 uint32_t ring_size:4; 786 uint32_t dw5rsvd2:2; 787 uint32_t cq_id:10; 788 /* dw3 */ 789 uint32_t dw6rsvd1:31; 790 uint32_t valid:1; 791 /* dw4 */ 792 uint32_t async_cq_valid:1; 793 uint32_t async_cq_id:10; 794 uint32_t dw7rsvd1:21; 795 #endif 796 /* dw5 */ 797 uint32_t dw8rsvd1; 798 } v0; 799 struct { 800 #ifdef _BIG_ENDIAN 801 /* dw0 */ 802 uint32_t cq_id:16; 803 uint32_t num_pages:16; 804 /* dw1 */ 805 uint32_t async_evt_bitmap; 806 /* dw2 */ 807 uint32_t dw5rsvd2:12; 808 uint32_t ring_size:4; 809 uint32_t async_cq_id:16; 810 /* dw3 */ 811 uint32_t valid:1; 812 uint32_t dw6rsvd1:31; 813 /* dw4 */ 814 uint32_t dw7rsvd1:31; 815 uint32_t async_cq_valid:1; 816 #else 817 /* dw0 */ 818 uint32_t num_pages:16; 819 uint32_t cq_id:16; 820 /* dw1 */ 821 uint32_t async_evt_bitmap; 822 /* dw2 */ 823 uint32_t async_cq_id:16; 824 uint32_t ring_size:4; 825 uint32_t dw5rsvd2:12; 826 /* dw3 */ 827 uint32_t dw6rsvd1:31; 828 uint32_t valid:1; 829 /* dw4 */ 830 uint32_t async_cq_valid:1; 831 uint32_t dw7rsvd1:31; 832 #endif 833 /* dw5 */ 834 uint32_t dw8rsvd1; 835 } v1; 836 837 } oce_mq_ext_ctx_t; 838 839 /* MQ mailbox structure */ 840 struct oce_bmbx { 841 struct oce_mbx mbx; 842 struct oce_mq_cqe cqe; 843 }; 844 845 /* ---[ MBXs start here ]---------------------------------------------- */ 846 /* MBXs sub system codes */ 847 enum MBX_SUBSYSTEM_CODES { 848 MBX_SUBSYSTEM_RSVD = 0, 849 MBX_SUBSYSTEM_COMMON = 1, 850 MBX_SUBSYSTEM_COMMON_ISCSI = 2, 851 MBX_SUBSYSTEM_NIC = 3, 852 MBX_SUBSYSTEM_TOE = 4, 853 MBX_SUBSYSTEM_PXE_UNDI = 5, 854 MBX_SUBSYSTEM_ISCSI_INI = 6, 855 MBX_SUBSYSTEM_ISCSI_TGT = 7, 856 MBX_SUBSYSTEM_MILI_PTL = 8, 857 MBX_SUBSYSTEM_MILI_TMD = 9, 858 MBX_SUBSYSTEM_RDMA = 10, 859 MBX_SUBSYSTEM_LOWLEVEL = 11, 860 MBX_SUBSYSTEM_LRO = 13, 861 IOCBMBX_SUBSYSTEM_DCBX = 15, 862 IOCBMBX_SUBSYSTEM_DIAG = 16, 863 IOCBMBX_SUBSYSTEM_VENDOR = 17 864 }; 865 866 /* common ioctl opcodes */ 867 enum COMMON_SUBSYSTEM_OPCODES { 868 /* These opcodes are common to both networking and storage PCI functions 869 * They are used to reserve resources and configure CNA. These opcodes 870 * all use the MBX_SUBSYSTEM_COMMON subsystem code. 871 */ 872 OPCODE_COMMON_QUERY_IFACE_MAC = 1, 873 OPCODE_COMMON_SET_IFACE_MAC = 2, 874 OPCODE_COMMON_SET_IFACE_MULTICAST = 3, 875 OPCODE_COMMON_CONFIG_IFACE_VLAN = 4, 876 OPCODE_COMMON_QUERY_LINK_CONFIG = 5, 877 OPCODE_COMMON_READ_FLASHROM = 6, 878 OPCODE_COMMON_WRITE_FLASHROM = 7, 879 OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8, 880 OPCODE_COMMON_CREATE_CQ = 12, 881 OPCODE_COMMON_CREATE_EQ = 13, 882 OPCODE_COMMON_CREATE_MQ = 21, 883 OPCODE_COMMON_GET_QOS = 27, 884 OPCODE_COMMON_SET_QOS = 28, 885 OPCODE_COMMON_READ_EPROM = 30, 886 OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32, 887 OPCODE_COMMON_NOP = 33, 888 OPCODE_COMMON_SET_IFACE_RX_FILTER = 34, 889 OPCODE_COMMON_GET_FW_VERSION = 35, 890 OPCODE_COMMON_SET_FLOW_CONTROL = 36, 891 OPCODE_COMMON_GET_FLOW_CONTROL = 37, 892 OPCODE_COMMON_SET_FRAME_SIZE = 39, 893 OPCODE_COMMON_MODIFY_EQ_DELAY = 41, 894 OPCODE_COMMON_CREATE_IFACE = 50, 895 OPCODE_COMMON_DESTROY_IFACE = 51, 896 OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52, 897 OPCODE_COMMON_DESTROY_MQ = 53, 898 OPCODE_COMMON_DESTROY_CQ = 54, 899 OPCODE_COMMON_DESTROY_EQ = 55, 900 OPCODE_COMMON_UPLOAD_TCP = 56, 901 OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57, 902 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58, 903 OPCODE_COMMON_ADD_IFACE_MAC = 59, 904 OPCODE_COMMON_DEL_IFACE_MAC = 60, 905 OPCODE_COMMON_FUNCTION_RESET = 61, 906 OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62, 907 OPCODE_COMMON_GET_BOOT_CONFIG = 66, 908 OPCPDE_COMMON_SET_BOOT_CONFIG = 67, 909 OPCODE_COMMON_SET_BEACON_CONFIG = 69, 910 OPCODE_COMMON_GET_BEACON_CONFIG = 70, 911 OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71, 912 OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73, 913 OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76, 914 OPCODE_COMMON_GET_PORT_NAME = 77, 915 OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78, 916 OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79, 917 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80, 918 OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81, 919 OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82, 920 OPCODE_COMMON_GET_RESET_NEEDED = 84, 921 OPCODE_COMMON_GET_SERIAL_NUMBER = 85, 922 OPCODE_COMMON_GET_NCSI_CONFIG = 86, 923 OPCODE_COMMON_SET_NCSI_CONFIG = 87, 924 OPCODE_COMMON_CREATE_MQ_EXT = 90, 925 OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100, 926 OPCODE_COMMON_SET_VF_PORT_TYPE = 101, 927 OPCODE_COMMON_GET_PHY_CONFIG = 102, 928 OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103, 929 OPCODE_COMMON_GET_ADAPTER_ID = 110, 930 OPCODE_COMMON_GET_UPGRADE_FEATURES = 111, 931 OPCODE_COMMON_GET_INSTALLED_FEATURES = 112, 932 OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113, 933 OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114, 934 OPCODE_COMMON_SEND_ACTIVATION = 115, 935 OPCODE_COMMON_RESET_LICENSES = 116, 936 OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121, 937 OPCODE_COMMON_QUERY_TCB = 144, 938 OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145, 939 OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146, 940 OPCODE_COMMON_GET_IFACE_MAC_LIST = 147, 941 OPCODE_COMMON_SET_IFACE_MAC_LIST = 148, 942 OPCODE_COMMON_MODIFY_CQ = 149, 943 OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150, 944 OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151, 945 OPCODE_COMMON_GET_HSW_CONFIG = 152, 946 OPCODE_COMMON_SET_HSW_CONFIG = 153, 947 OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154, 948 OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155, 949 OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156, 950 OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157, 951 OPCODE_COMMON_SET_DIAG_REGISTERS = 158, 952 OPCODE_COMMON_GET_FUNCTION_CONFIG = 160, 953 OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161, 954 OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162, 955 OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163, 956 OPCODE_COMMON_GET_PROFILE_CONFIG = 164, 957 OPCODE_COMMON_SET_PROFILE_CONFIG = 165, 958 OPCODE_COMMON_GET_PROFILE_LIST = 166, 959 OPCODE_COMMON_GET_ACTIVE_PROFILE = 167, 960 OPCODE_COMMON_SET_ACTIVE_PROFILE = 168, 961 OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170, 962 OPCODE_COMMON_READ_OBJECT = 171, 963 OPCODE_COMMON_WRITE_OBJECT = 172 964 }; 965 966 /* common ioctl header */ 967 #define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */ 968 #define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */ 969 #define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */ 970 struct mbx_hdr { 971 union { 972 uint32_t dw[4]; 973 struct { 974 #ifdef _BIG_ENDIAN 975 /* dw 0 */ 976 uint32_t domain:8; 977 uint32_t port_number:8; 978 uint32_t subsystem:8; 979 uint32_t opcode:8; 980 /* dw 1 */ 981 uint32_t timeout; 982 /* dw 2 */ 983 uint32_t request_length; 984 /* dw 3 */ 985 uint32_t rsvd0:24; 986 uint32_t version:8; 987 #else 988 /* dw 0 */ 989 uint32_t opcode:8; 990 uint32_t subsystem:8; 991 uint32_t port_number:8; 992 uint32_t domain:8; 993 /* dw 1 */ 994 uint32_t timeout; 995 /* dw 2 */ 996 uint32_t request_length; 997 /* dw 3 */ 998 uint32_t version:8; 999 uint32_t rsvd0:24; 1000 #endif 1001 } req; 1002 struct { 1003 #ifdef _BIG_ENDIAN 1004 /* dw 0 */ 1005 uint32_t domain:8; 1006 uint32_t rsvd0:8; 1007 uint32_t subsystem:8; 1008 uint32_t opcode:8; 1009 /* dw 1 */ 1010 uint32_t rsvd1:16; 1011 uint32_t additional_status:8; 1012 uint32_t status:8; 1013 #else 1014 /* dw 0 */ 1015 uint32_t opcode:8; 1016 uint32_t subsystem:8; 1017 uint32_t rsvd0:8; 1018 uint32_t domain:8; 1019 /* dw 1 */ 1020 uint32_t status:8; 1021 uint32_t additional_status:8; 1022 uint32_t rsvd1:16; 1023 #endif 1024 uint32_t rsp_length; 1025 uint32_t actual_rsp_length; 1026 } rsp; 1027 } u0; 1028 }; 1029 #define OCE_BMBX_RHDR_SZ 20 1030 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 1031 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 1032 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 1033 1034 /* [05] OPCODE_COMMON_QUERY_LINK_CONFIG_V1 */ 1035 struct mbx_query_common_link_config { 1036 struct mbx_hdr hdr; 1037 union { 1038 struct { 1039 uint32_t rsvd0; 1040 } req; 1041 1042 struct { 1043 #ifdef _BIG_ENDIAN 1044 uint32_t physical_port_fault:8; 1045 uint32_t physical_port_speed:8; 1046 uint32_t link_duplex:8; 1047 uint32_t pt:2; 1048 uint32_t port_number:6; 1049 1050 uint16_t qos_link_speed; 1051 uint16_t rsvd0; 1052 1053 uint32_t rsvd1:21; 1054 uint32_t phys_fcv:1; 1055 uint32_t phys_rxf:1; 1056 uint32_t phys_txf:1; 1057 uint32_t logical_link_status:8; 1058 #else 1059 uint32_t port_number:6; 1060 uint32_t pt:2; 1061 uint32_t link_duplex:8; 1062 uint32_t physical_port_speed:8; 1063 uint32_t physical_port_fault:8; 1064 1065 uint16_t rsvd0; 1066 uint16_t qos_link_speed; 1067 1068 uint32_t logical_link_status:8; 1069 uint32_t phys_txf:1; 1070 uint32_t phys_rxf:1; 1071 uint32_t phys_fcv:1; 1072 uint32_t rsvd1:21; 1073 #endif 1074 } rsp; 1075 } params; 1076 }; 1077 1078 /* [57] OPCODE_COMMON_SET_LINK_SPEED */ 1079 struct mbx_set_common_link_speed { 1080 struct mbx_hdr hdr; 1081 union { 1082 struct { 1083 #ifdef _BIG_ENDIAN 1084 uint8_t rsvd0; 1085 uint8_t mac_speed; 1086 uint8_t virtual_port; 1087 uint8_t physical_port; 1088 #else 1089 uint8_t physical_port; 1090 uint8_t virtual_port; 1091 uint8_t mac_speed; 1092 uint8_t rsvd0; 1093 #endif 1094 } req; 1095 1096 struct { 1097 uint32_t rsvd0; 1098 } rsp; 1099 1100 uint32_t dw; 1101 } params; 1102 }; 1103 1104 struct mac_address_format { 1105 uint16_t size_of_struct; 1106 uint8_t mac_addr[6]; 1107 }; 1108 1109 /* [01] OPCODE_COMMON_QUERY_IFACE_MAC */ 1110 struct mbx_query_common_iface_mac { 1111 struct mbx_hdr hdr; 1112 union { 1113 struct { 1114 #ifdef _BIG_ENDIAN 1115 uint16_t if_id; 1116 uint8_t permanent; 1117 uint8_t type; 1118 #else 1119 uint8_t type; 1120 uint8_t permanent; 1121 uint16_t if_id; 1122 #endif 1123 1124 } req; 1125 1126 struct { 1127 struct mac_address_format mac; 1128 } rsp; 1129 } params; 1130 }; 1131 1132 /* [02] OPCODE_COMMON_SET_IFACE_MAC */ 1133 struct mbx_set_common_iface_mac { 1134 struct mbx_hdr hdr; 1135 union { 1136 struct { 1137 #ifdef _BIG_ENDIAN 1138 /* dw 0 */ 1139 uint16_t if_id; 1140 uint8_t invalidate; 1141 uint8_t type; 1142 #else 1143 /* dw 0 */ 1144 uint8_t type; 1145 uint8_t invalidate; 1146 uint16_t if_id; 1147 #endif 1148 /* dw 1 */ 1149 struct mac_address_format mac; 1150 } req; 1151 1152 struct { 1153 uint32_t rsvd0; 1154 } rsp; 1155 1156 uint32_t dw[2]; 1157 } params; 1158 }; 1159 1160 /* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */ 1161 struct mbx_set_common_iface_multicast { 1162 struct mbx_hdr hdr; 1163 union { 1164 struct { 1165 /* dw 0 */ 1166 uint16_t num_mac; 1167 uint8_t promiscuous; 1168 uint8_t if_id; 1169 /* dw 1-48 */ 1170 struct { 1171 uint8_t byte[6]; 1172 } mac[32]; 1173 1174 } req; 1175 1176 struct { 1177 uint32_t rsvd0; 1178 } rsp; 1179 1180 uint32_t dw[49]; 1181 } params; 1182 }; 1183 1184 struct qinq_vlan { 1185 #ifdef _BIG_ENDIAN 1186 uint16_t inner; 1187 uint16_t outer; 1188 #else 1189 uint16_t outer; 1190 uint16_t inner; 1191 #endif 1192 }; 1193 1194 struct normal_vlan { 1195 uint16_t vtag; 1196 }; 1197 1198 struct ntwk_if_vlan_tag { 1199 union { 1200 struct normal_vlan normal; 1201 struct qinq_vlan qinq; 1202 } u0; 1203 }; 1204 1205 /* [50] OPCODE_COMMON_CREATE_IFACE */ 1206 struct mbx_create_common_iface { 1207 struct mbx_hdr hdr; 1208 union { 1209 struct { 1210 uint32_t version; 1211 uint32_t cap_flags; 1212 uint32_t enable_flags; 1213 uint8_t mac_addr[6]; 1214 uint8_t rsvd0; 1215 uint8_t mac_invalid; 1216 struct ntwk_if_vlan_tag vlan_tag; 1217 } req; 1218 1219 struct { 1220 uint32_t if_id; 1221 uint32_t pmac_id; 1222 } rsp; 1223 uint32_t dw[4]; 1224 } params; 1225 }; 1226 1227 /* [51] OPCODE_COMMON_DESTROY_IFACE */ 1228 struct mbx_destroy_common_iface { 1229 struct mbx_hdr hdr; 1230 union { 1231 struct { 1232 uint32_t if_id; 1233 } req; 1234 1235 struct { 1236 uint32_t rsvd0; 1237 } rsp; 1238 1239 uint32_t dw; 1240 } params; 1241 }; 1242 1243 /* event queue context structure */ 1244 struct oce_eq_ctx { 1245 #ifdef _BIG_ENDIAN 1246 uint32_t dw4rsvd1:16; 1247 uint32_t num_pages:16; 1248 1249 uint32_t size:1; 1250 uint32_t dw5rsvd2:1; 1251 uint32_t valid:1; 1252 uint32_t dw5rsvd1:29; 1253 1254 uint32_t armed:1; 1255 uint32_t dw6rsvd2:2; 1256 uint32_t count:3; 1257 uint32_t dw6rsvd1:26; 1258 1259 uint32_t dw7rsvd2:9; 1260 uint32_t delay_mult:10; 1261 uint32_t dw7rsvd1:13; 1262 1263 uint32_t dw8rsvd1; 1264 #else 1265 uint32_t num_pages:16; 1266 uint32_t dw4rsvd1:16; 1267 1268 uint32_t dw5rsvd1:29; 1269 uint32_t valid:1; 1270 uint32_t dw5rsvd2:1; 1271 uint32_t size:1; 1272 1273 uint32_t dw6rsvd1:26; 1274 uint32_t count:3; 1275 uint32_t dw6rsvd2:2; 1276 uint32_t armed:1; 1277 1278 uint32_t dw7rsvd1:13; 1279 uint32_t delay_mult:10; 1280 uint32_t dw7rsvd2:9; 1281 1282 uint32_t dw8rsvd1; 1283 #endif 1284 }; 1285 1286 /* [13] OPCODE_COMMON_CREATE_EQ */ 1287 struct mbx_create_common_eq { 1288 struct mbx_hdr hdr; 1289 union { 1290 struct { 1291 struct oce_eq_ctx ctx; 1292 struct phys_addr pages[8]; 1293 } req; 1294 1295 struct { 1296 uint16_t eq_id; 1297 uint16_t rsvd0; 1298 } rsp; 1299 } params; 1300 }; 1301 1302 /* [55] OPCODE_COMMON_DESTROY_EQ */ 1303 struct mbx_destroy_common_eq { 1304 struct mbx_hdr hdr; 1305 union { 1306 struct { 1307 #ifdef _BIG_ENDIAN 1308 uint16_t rsvd0; 1309 uint16_t id; 1310 #else 1311 uint16_t id; 1312 uint16_t rsvd0; 1313 #endif 1314 } req; 1315 1316 struct { 1317 uint32_t rsvd0; 1318 } rsp; 1319 } params; 1320 }; 1321 1322 /* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */ 1323 typedef union oce_cq_ctx_u { 1324 uint32_t dw[5]; 1325 struct { 1326 #ifdef _BIG_ENDIAN 1327 /* dw4 */ 1328 uint32_t dw4rsvd1:16; 1329 uint32_t num_pages:16; 1330 /* dw5 */ 1331 uint32_t eventable:1; 1332 uint32_t dw5rsvd3:1; 1333 uint32_t valid:1; 1334 uint32_t count:2; 1335 uint32_t dw5rsvd2:12; 1336 uint32_t nodelay:1; 1337 uint32_t coalesce_wm:2; 1338 uint32_t dw5rsvd1:12; 1339 /* dw6 */ 1340 uint32_t armed:1; 1341 uint32_t dw6rsvd2:1; 1342 uint32_t eq_id:8; 1343 uint32_t dw6rsvd1:22; 1344 #else 1345 /* dw4 */ 1346 uint32_t num_pages:16; 1347 uint32_t dw4rsvd1:16; 1348 /* dw5 */ 1349 uint32_t dw5rsvd1:12; 1350 uint32_t coalesce_wm:2; 1351 uint32_t nodelay:1; 1352 uint32_t dw5rsvd2:12; 1353 uint32_t count:2; 1354 uint32_t valid:1; 1355 uint32_t dw5rsvd3:1; 1356 uint32_t eventable:1; 1357 /* dw6 */ 1358 uint32_t dw6rsvd1:22; 1359 uint32_t eq_id:8; 1360 uint32_t dw6rsvd2:1; 1361 uint32_t armed:1; 1362 #endif 1363 /* dw7 */ 1364 uint32_t dw7rsvd1; 1365 /* dw8 */ 1366 uint32_t dw8rsvd1; 1367 } v0; 1368 struct { 1369 #ifdef _BIG_ENDIAN 1370 /* dw4 */ 1371 uint32_t dw4rsvd1:8; 1372 uint32_t page_size:8; 1373 uint32_t num_pages:16; 1374 /* dw5 */ 1375 uint32_t eventable:1; 1376 uint32_t dw5rsvd3:1; 1377 uint32_t valid:1; 1378 uint32_t count:2; 1379 uint32_t dw5rsvd2:11; 1380 uint32_t autovalid:1; 1381 uint32_t nodelay:1; 1382 uint32_t coalesce_wm:2; 1383 uint32_t dw5rsvd1:12; 1384 /* dw6 */ 1385 uint32_t armed:1; 1386 uint32_t dw6rsvd1:15; 1387 uint32_t eq_id:16; 1388 /* dw7 */ 1389 uint32_t dw7rsvd1:16; 1390 uint32_t cqe_count:16; 1391 #else 1392 /* dw4 */ 1393 uint32_t num_pages:16; 1394 uint32_t page_size:8; 1395 uint32_t dw4rsvd1:8; 1396 /* dw5 */ 1397 uint32_t dw5rsvd1:12; 1398 uint32_t coalesce_wm:2; 1399 uint32_t nodelay:1; 1400 uint32_t autovalid:1; 1401 uint32_t dw5rsvd2:11; 1402 uint32_t count:2; 1403 uint32_t valid:1; 1404 uint32_t dw5rsvd3:1; 1405 uint32_t eventable:1; 1406 /* dw6 */ 1407 uint32_t eq_id:16; 1408 uint32_t dw6rsvd1:15; 1409 uint32_t armed:1; 1410 /* dw7 */ 1411 uint32_t cqe_count:16; 1412 uint32_t dw7rsvd1:16; 1413 #endif 1414 /* dw8 */ 1415 uint32_t dw8rsvd1; 1416 } v2; 1417 } oce_cq_ctx_t; 1418 1419 /* [12] OPCODE_COMMON_CREATE_CQ */ 1420 struct mbx_create_common_cq { 1421 struct mbx_hdr hdr; 1422 union { 1423 struct { 1424 oce_cq_ctx_t cq_ctx; 1425 struct phys_addr pages[4]; 1426 } req; 1427 1428 struct { 1429 uint16_t cq_id; 1430 uint16_t rsvd0; 1431 } rsp; 1432 } params; 1433 }; 1434 1435 /* [54] OPCODE_COMMON_DESTROY_CQ */ 1436 struct mbx_destroy_common_cq { 1437 struct mbx_hdr hdr; 1438 union { 1439 struct { 1440 #ifdef _BIG_ENDIAN 1441 uint16_t rsvd0; 1442 uint16_t id; 1443 #else 1444 uint16_t id; 1445 uint16_t rsvd0; 1446 #endif 1447 } req; 1448 1449 struct { 1450 uint32_t rsvd0; 1451 } rsp; 1452 } params; 1453 }; 1454 1455 typedef union oce_mq_ctx_u { 1456 uint32_t dw[5]; 1457 struct { 1458 #ifdef _BIG_ENDIAN 1459 /* dw4 */ 1460 uint32_t dw4rsvd1:16; 1461 uint32_t num_pages:16; 1462 /* dw5 */ 1463 uint32_t cq_id:10; 1464 uint32_t dw5rsvd2:2; 1465 uint32_t ring_size:4; 1466 uint32_t dw5rsvd1:16; 1467 /* dw6 */ 1468 uint32_t valid:1; 1469 uint32_t dw6rsvd1:31; 1470 /* dw7 */ 1471 uint32_t dw7rsvd1:21; 1472 uint32_t async_cq_id:10; 1473 uint32_t async_cq_valid:1; 1474 #else 1475 /* dw4 */ 1476 uint32_t num_pages:16; 1477 uint32_t dw4rsvd1:16; 1478 /* dw5 */ 1479 uint32_t dw5rsvd1:16; 1480 uint32_t ring_size:4; 1481 uint32_t dw5rsvd2:2; 1482 uint32_t cq_id:10; 1483 /* dw6 */ 1484 uint32_t dw6rsvd1:31; 1485 uint32_t valid:1; 1486 /* dw7 */ 1487 uint32_t async_cq_valid:1; 1488 uint32_t async_cq_id:10; 1489 uint32_t dw7rsvd1:21; 1490 #endif 1491 /* dw8 */ 1492 uint32_t dw8rsvd1; 1493 } v0; 1494 } oce_mq_ctx_t; 1495 1496 /** 1497 * @brief [21] OPCODE_COMMON_CREATE_MQ 1498 * A MQ must be at least 16 entries deep (corresponding to 1 page) and 1499 * at most 128 entries deep (corresponding to 8 pages). 1500 */ 1501 struct mbx_create_common_mq { 1502 struct mbx_hdr hdr; 1503 union { 1504 struct { 1505 oce_mq_ctx_t context; 1506 struct phys_addr pages[8]; 1507 } req; 1508 1509 struct { 1510 uint32_t mq_id:16; 1511 uint32_t rsvd0:16; 1512 } rsp; 1513 } params; 1514 }; 1515 1516 struct mbx_create_common_mq_ex { 1517 struct mbx_hdr hdr; 1518 union { 1519 struct { 1520 oce_mq_ext_ctx_t context; 1521 struct phys_addr pages[8]; 1522 } req; 1523 1524 struct { 1525 uint32_t mq_id:16; 1526 uint32_t rsvd0:16; 1527 } rsp; 1528 } params; 1529 }; 1530 1531 /* [53] OPCODE_COMMON_DESTROY_MQ */ 1532 struct mbx_destroy_common_mq { 1533 struct mbx_hdr hdr; 1534 union { 1535 struct { 1536 #ifdef _BIG_ENDIAN 1537 uint16_t rsvd0; 1538 uint16_t id; 1539 #else 1540 uint16_t id; 1541 uint16_t rsvd0; 1542 #endif 1543 } req; 1544 1545 struct { 1546 uint32_t rsvd0; 1547 } rsp; 1548 } params; 1549 }; 1550 1551 /* [35] OPCODE_COMMON_GET_ FW_VERSION */ 1552 struct mbx_get_common_fw_version { 1553 struct mbx_hdr hdr; 1554 union { 1555 struct { 1556 uint32_t rsvd0; 1557 } req; 1558 1559 struct { 1560 uint8_t fw_ver_str[32]; 1561 uint8_t fw_on_flash_ver_str[32]; 1562 } rsp; 1563 } params; 1564 }; 1565 1566 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1567 struct mbx_common_cev_modify_msi_messages { 1568 struct mbx_hdr hdr; 1569 union { 1570 struct { 1571 uint32_t num_msi_msgs; 1572 } req; 1573 1574 struct { 1575 uint32_t rsvd0; 1576 } rsp; 1577 } params; 1578 }; 1579 1580 /* [36] OPCODE_COMMON_SET_FLOW_CONTROL */ 1581 /* [37] OPCODE_COMMON_GET_FLOW_CONTROL */ 1582 struct mbx_common_get_set_flow_control { 1583 struct mbx_hdr hdr; 1584 #ifdef _BIG_ENDIAN 1585 uint16_t tx_flow_control; 1586 uint16_t rx_flow_control; 1587 #else 1588 uint16_t rx_flow_control; 1589 uint16_t tx_flow_control; 1590 #endif 1591 }; 1592 1593 enum e_flash_opcode { 1594 MGMT_FLASHROM_OPCODE_FLASH = 1, 1595 MGMT_FLASHROM_OPCODE_SAVE = 2 1596 }; 1597 1598 /* [06] OPCODE_READ_COMMON_FLASHROM */ 1599 /* [07] OPCODE_WRITE_COMMON_FLASHROM */ 1600 1601 struct mbx_common_read_write_flashrom { 1602 struct mbx_hdr hdr; 1603 uint32_t flash_op_code; 1604 uint32_t flash_op_type; 1605 uint32_t data_buffer_size; 1606 uint32_t data_offset; 1607 uint8_t data_buffer[32768]; /* + IMAGE_TRANSFER_SIZE */ 1608 uint8_t rsvd[4]; 1609 }; 1610 1611 struct oce_phy_info { 1612 uint16_t phy_type; 1613 uint16_t interface_type; 1614 uint32_t misc_params; 1615 uint16_t ext_phy_details; 1616 uint16_t rsvd; 1617 uint16_t auto_speeds_supported; 1618 uint16_t fixed_speeds_supported; 1619 uint32_t future_use[2]; 1620 }; 1621 1622 struct mbx_common_phy_info { 1623 struct mbx_hdr hdr; 1624 union { 1625 struct { 1626 uint32_t rsvd0[4]; 1627 } req; 1628 struct { 1629 struct oce_phy_info phy_info; 1630 } rsp; 1631 } params; 1632 }; 1633 1634 /*Lancer firmware*/ 1635 1636 struct mbx_lancer_common_write_object { 1637 union { 1638 struct { 1639 struct mbx_hdr hdr; 1640 uint32_t write_length: 24; 1641 uint32_t rsvd: 7; 1642 uint32_t eof: 1; 1643 uint32_t write_offset; 1644 uint8_t object_name[104]; 1645 uint32_t descriptor_count; 1646 uint32_t buffer_length; 1647 uint32_t address_lower; 1648 uint32_t address_upper; 1649 } req; 1650 struct { 1651 uint8_t opcode; 1652 uint8_t subsystem; 1653 uint8_t rsvd1[2]; 1654 uint8_t status; 1655 uint8_t additional_status; 1656 uint8_t rsvd2[2]; 1657 uint32_t response_length; 1658 uint32_t actual_response_length; 1659 uint32_t actual_write_length; 1660 } rsp; 1661 } params; 1662 }; 1663 1664 /** 1665 * @brief MBX Common Quiery Firmaware Config 1666 * This command retrieves firmware configuration parameters and adapter 1667 * resources available to the driver originating the request. The firmware 1668 * configuration defines supported protocols by the installed adapter firmware. 1669 * This includes which ULP processors support the specified protocols and 1670 * the number of TCP connections allowed for that protocol. 1671 */ 1672 struct mbx_common_query_fw_config { 1673 struct mbx_hdr hdr; 1674 union { 1675 struct { 1676 uint32_t rsvd0[30]; 1677 } req; 1678 1679 struct { 1680 uint32_t config_number; 1681 uint32_t asic_revision; 1682 uint32_t port_id; /* used for stats retrieval */ 1683 uint32_t function_mode; 1684 struct { 1685 uint32_t ulp_mode; 1686 uint32_t nic_wqid_base; 1687 uint32_t nic_wq_tot; 1688 uint32_t toe_wqid_base; 1689 uint32_t toe_wq_tot; 1690 uint32_t toe_rqid_base; 1691 uint32_t toe_rqid_tot; 1692 uint32_t toe_defrqid_base; 1693 uint32_t toe_defrqid_count; 1694 uint32_t lro_rqid_base; 1695 uint32_t lro_rqid_tot; 1696 uint32_t iscsi_icd_base; 1697 uint32_t iscsi_icd_count; 1698 } ulp[2]; 1699 uint32_t function_caps; 1700 uint32_t cqid_base; 1701 uint32_t cqid_tot; 1702 uint32_t eqid_base; 1703 uint32_t eqid_tot; 1704 } rsp; 1705 } params; 1706 }; 1707 1708 enum CQFW_CONFIG_NUMBER { 1709 FCN_NIC_ISCSI_Initiator = 0x0, 1710 FCN_ISCSI_Target = 0x3, 1711 FCN_FCoE = 0x7, 1712 FCN_ISCSI_Initiator_Target = 0x9, 1713 FCN_NIC_RDMA_TOE = 0xA, 1714 FCN_NIC_RDMA_FCoE = 0xB, 1715 FCN_NIC_RDMA_iSCSI = 0xC, 1716 FCN_NIC_iSCSI_FCoE = 0xD 1717 }; 1718 1719 /** 1720 * @brief Function Capabilites 1721 * This field contains the flags indicating the capabilities of 1722 * the SLI Host’s PCI function. 1723 */ 1724 enum CQFW_FUNCTION_CAPABILITIES { 1725 FNC_UNCLASSIFIED_STATS = 0x1, 1726 FNC_RSS = 0x2, 1727 FNC_PROMISCUOUS = 0x4, 1728 FNC_LEGACY_MODE = 0x8, 1729 FNC_HDS = 0x4000, 1730 FNC_VMQ = 0x10000, 1731 FNC_NETQ = 0x20000, 1732 FNC_QGROUPS = 0x40000, 1733 FNC_LRO = 0x100000, 1734 FNC_VLAN_OFFLOAD = 0x800000 1735 }; 1736 1737 enum CQFW_ULP_MODES_SUPPORTED { 1738 ULP_TOE_MODE = 0x1, 1739 ULP_NIC_MODE = 0x2, 1740 ULP_RDMA_MODE = 0x4, 1741 ULP_ISCSI_INI_MODE = 0x10, 1742 ULP_ISCSI_TGT_MODE = 0x20, 1743 ULP_FCOE_INI_MODE = 0x40, 1744 ULP_FCOE_TGT_MODE = 0x80, 1745 ULP_DAL_MODE = 0x100, 1746 ULP_LRO_MODE = 0x200 1747 }; 1748 1749 /** 1750 * @brief Function Modes Supported 1751 * Valid function modes (or protocol-types) supported on the SLI-Host’s 1752 * PCIe function. This field is a logical OR of the following values: 1753 */ 1754 enum CQFW_FUNCTION_MODES_SUPPORTED { 1755 FNM_TOE_MODE = 0x1, /* TCP offload supported */ 1756 FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */ 1757 FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */ 1758 FNM_VM_MODE = 0x8, /* Virtual Machines supported */ 1759 FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */ 1760 FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 1761 FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */ 1762 FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */ 1763 FNM_DAL_MODE = 0x100, /* DAL supported */ 1764 FNM_LRO_MODE = 0x200, /* LRO supported */ 1765 FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */ 1766 FNM_NCSI_MODE = 0x800, /* NCSI supported */ 1767 FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */ 1768 FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/ 1769 FNM_INVALID_MODE = 0x8000, /* Invalid */ 1770 FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */ 1771 FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */ 1772 FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */ 1773 FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */ 1774 FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */ 1775 FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */ 1776 FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */ 1777 FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */ 1778 }; 1779 1780 struct mbx_common_config_vlan { 1781 struct mbx_hdr hdr; 1782 union { 1783 struct { 1784 #ifdef _BIG_ENDIAN 1785 uint8_t num_vlans; 1786 uint8_t untagged; 1787 uint8_t promisc; 1788 uint8_t if_id; 1789 #else 1790 uint8_t if_id; 1791 uint8_t promisc; 1792 uint8_t untagged; 1793 uint8_t num_vlans; 1794 #endif 1795 union { 1796 struct normal_vlan normal_vlans[64]; 1797 struct qinq_vlan qinq_vlans[32]; 1798 } tags; 1799 } req; 1800 1801 struct { 1802 uint32_t rsvd; 1803 } rsp; 1804 } params; 1805 }; 1806 1807 typedef struct iface_rx_filter_ctx { 1808 uint32_t global_flags_mask; 1809 uint32_t global_flags; 1810 uint32_t iface_flags_mask; 1811 uint32_t iface_flags; 1812 uint32_t if_id; 1813 #define IFACE_RX_NUM_MCAST_MAX 64 1814 uint32_t num_mcast; 1815 struct mbx_mcast_addr { 1816 uint8_t byte[6]; 1817 } mac[IFACE_RX_NUM_MCAST_MAX]; 1818 } iface_rx_filter_ctx_t; 1819 1820 /* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */ 1821 struct mbx_set_common_iface_rx_filter { 1822 struct mbx_hdr hdr; 1823 union { 1824 iface_rx_filter_ctx_t req; 1825 iface_rx_filter_ctx_t rsp; 1826 } params; 1827 }; 1828 1829 struct be_set_eqd { 1830 uint32_t eq_id; 1831 uint32_t phase; 1832 uint32_t dm; 1833 }; 1834 1835 /* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */ 1836 struct mbx_modify_common_eq_delay { 1837 struct mbx_hdr hdr; 1838 union { 1839 struct { 1840 uint32_t num_eq; 1841 struct { 1842 uint32_t eq_id; 1843 uint32_t phase; 1844 uint32_t dm; 1845 } delay[8]; 1846 } req; 1847 1848 struct { 1849 uint32_t rsvd0; 1850 } rsp; 1851 } params; 1852 }; 1853 1854 /* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */ 1855 1856 struct mgmt_hba_attr { 1857 int8_t flashrom_ver_str[32]; 1858 int8_t manufac_name[32]; 1859 uint32_t supp_modes; 1860 int8_t seeprom_ver_lo; 1861 int8_t seeprom_ver_hi; 1862 int8_t rsvd0[2]; 1863 uint32_t ioctl_data_struct_ver; 1864 uint32_t ep_fw_data_struct_ver; 1865 uint8_t ncsi_ver_str[12]; 1866 uint32_t def_ext_to; 1867 int8_t cntl_mod_num[32]; 1868 int8_t cntl_desc[64]; 1869 int8_t cntl_ser_num[32]; 1870 int8_t ip_ver_str[32]; 1871 int8_t fw_ver_str[32]; 1872 int8_t bios_ver_str[32]; 1873 int8_t redboot_ver_str[32]; 1874 int8_t drv_ver_str[32]; 1875 int8_t fw_on_flash_ver_str[32]; 1876 uint32_t funcs_supp; 1877 uint16_t max_cdblen; 1878 uint8_t asic_rev; 1879 uint8_t gen_guid[16]; 1880 uint8_t hba_port_count; 1881 uint16_t default_link_down_timeout; 1882 uint8_t iscsi_ver_min_max; 1883 uint8_t multifunc_dev; 1884 uint8_t cache_valid; 1885 uint8_t hba_status; 1886 uint8_t max_domains_supp; 1887 uint8_t phy_port; 1888 uint32_t fw_post_status; 1889 uint32_t hba_mtu[8]; 1890 uint8_t iSCSI_feat; 1891 uint8_t asic_gen; 1892 uint8_t future_u8[2]; 1893 uint32_t future_u32[3]; 1894 }; 1895 1896 struct mgmt_cntl_attr { 1897 struct mgmt_hba_attr hba_attr; 1898 uint16_t pci_vendor_id; 1899 uint16_t pci_device_id; 1900 uint16_t pci_sub_vendor_id; 1901 uint16_t pci_sub_system_id; 1902 uint8_t pci_bus_num; 1903 uint8_t pci_dev_num; 1904 uint8_t pci_func_num; 1905 uint8_t interface_type; 1906 uint64_t unique_id; 1907 uint8_t netfilters; 1908 uint8_t rsvd0[3]; 1909 uint32_t future_u32[4]; 1910 }; 1911 1912 struct mbx_common_get_cntl_attr { 1913 struct mbx_hdr hdr; 1914 union { 1915 struct { 1916 uint32_t rsvd0; 1917 } req; 1918 struct { 1919 struct mgmt_cntl_attr cntl_attr_info; 1920 } rsp; 1921 } params; 1922 }; 1923 1924 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1925 struct mbx_add_common_iface_mac { 1926 struct mbx_hdr hdr; 1927 union { 1928 struct { 1929 uint32_t if_id; 1930 uint8_t mac_address[6]; 1931 uint8_t rsvd0[2]; 1932 } req; 1933 struct { 1934 uint32_t pmac_id; 1935 } rsp; 1936 } params; 1937 }; 1938 1939 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1940 struct mbx_del_common_iface_mac { 1941 struct mbx_hdr hdr; 1942 union { 1943 struct { 1944 uint32_t if_id; 1945 uint32_t pmac_id; 1946 } req; 1947 struct { 1948 uint32_t rsvd0; 1949 } rsp; 1950 } params; 1951 }; 1952 1953 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1954 struct mbx_query_common_max_mbx_buffer_size { 1955 struct mbx_hdr hdr; 1956 struct { 1957 uint32_t max_ioctl_bufsz; 1958 } rsp; 1959 }; 1960 1961 /* [61] OPCODE_COMMON_FUNCTION_RESET */ 1962 struct ioctl_common_function_reset { 1963 struct mbx_hdr hdr; 1964 }; 1965 1966 /* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */ 1967 struct mbx_read_common_transrecv_data { 1968 struct mbx_hdr hdr; 1969 union { 1970 struct { 1971 uint32_t page_num; 1972 uint32_t port; 1973 } req; 1974 struct { 1975 uint32_t page_num; 1976 uint32_t port; 1977 uint32_t page_data[32]; 1978 } rsp; 1979 } params; 1980 1981 }; 1982 1983 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 1984 struct mbx_common_func_link_cfg { 1985 struct mbx_hdr hdr; 1986 union { 1987 struct { 1988 uint32_t enable; 1989 } req; 1990 struct { 1991 uint32_t rsvd0; 1992 } rsp; 1993 } params; 1994 }; 1995 1996 /* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */ 1997 #define CAP_SW_TIMESTAMPS 2 1998 #define CAP_BE3_NATIVE_ERX_API 4 1999 2000 struct mbx_common_set_function_cap { 2001 struct mbx_hdr hdr; 2002 union { 2003 struct { 2004 uint32_t valid_capability_flags; 2005 uint32_t capability_flags; 2006 uint8_t sbz[212]; 2007 } req; 2008 struct { 2009 uint32_t valid_capability_flags; 2010 uint32_t capability_flags; 2011 uint8_t sbz[212]; 2012 } rsp; 2013 } params; 2014 }; 2015 struct mbx_lowlevel_test_loopback_mode { 2016 struct mbx_hdr hdr; 2017 union { 2018 struct { 2019 uint32_t loopback_type; 2020 uint32_t num_pkts; 2021 uint64_t pattern; 2022 uint32_t src_port; 2023 uint32_t dest_port; 2024 uint32_t pkt_size; 2025 }req; 2026 struct { 2027 uint32_t status; 2028 uint32_t num_txfer; 2029 uint32_t num_rx; 2030 uint32_t miscomp_off; 2031 uint32_t ticks_compl; 2032 }rsp; 2033 } params; 2034 }; 2035 2036 struct mbx_lowlevel_set_loopback_mode { 2037 struct mbx_hdr hdr; 2038 union { 2039 struct { 2040 uint8_t src_port; 2041 uint8_t dest_port; 2042 uint8_t loopback_type; 2043 uint8_t loopback_state; 2044 } req; 2045 struct { 2046 uint8_t rsvd0[4]; 2047 } rsp; 2048 } params; 2049 }; 2050 #define MAX_RESC_DESC 256 2051 #define RESC_DESC_SIZE 88 2052 #define ACTIVE_PROFILE 2 2053 #define NIC_RESC_DESC_TYPE_V0 0x41 2054 #define NIC_RESC_DESC_TYPE_V1 0x51 2055 /* OPCODE_COMMON_GET_FUNCTION_CONFIG */ 2056 struct mbx_common_get_func_config { 2057 struct mbx_hdr hdr; 2058 union { 2059 struct { 2060 uint8_t rsvd; 2061 uint8_t type; 2062 uint16_t rsvd1; 2063 } req; 2064 struct { 2065 uint32_t desc_count; 2066 uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2067 } rsp; 2068 } params; 2069 }; 2070 2071 /* OPCODE_COMMON_GET_PROFILE_CONFIG */ 2072 2073 struct mbx_common_get_profile_config { 2074 struct mbx_hdr hdr; 2075 union { 2076 struct { 2077 uint8_t rsvd; 2078 uint8_t type; 2079 uint16_t rsvd1; 2080 } req; 2081 struct { 2082 uint32_t desc_count; 2083 uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2084 } rsp; 2085 } params; 2086 }; 2087 2088 struct oce_nic_resc_desc { 2089 uint8_t desc_type; 2090 uint8_t desc_len; 2091 uint8_t rsvd1; 2092 uint8_t flags; 2093 uint8_t vf_num; 2094 uint8_t rsvd2; 2095 uint8_t pf_num; 2096 uint8_t rsvd3; 2097 uint16_t unicast_mac_count; 2098 uint8_t rsvd4[6]; 2099 uint16_t mcc_count; 2100 uint16_t vlan_count; 2101 uint16_t mcast_mac_count; 2102 uint16_t txq_count; 2103 uint16_t rq_count; 2104 uint16_t rssq_count; 2105 uint16_t lro_count; 2106 uint16_t cq_count; 2107 uint16_t toe_conn_count; 2108 uint16_t eq_count; 2109 uint32_t rsvd5; 2110 uint32_t cap_flags; 2111 uint8_t link_param; 2112 uint8_t rsvd6[3]; 2113 uint32_t bw_min; 2114 uint32_t bw_max; 2115 uint8_t acpi_params; 2116 uint8_t wol_param; 2117 uint16_t rsvd7; 2118 uint32_t rsvd8[7]; 2119 2120 }; 2121 2122 struct flash_file_hdr { 2123 uint8_t sign[52]; 2124 uint8_t ufi_version[4]; 2125 uint32_t file_len; 2126 uint32_t cksum; 2127 uint32_t antidote; 2128 uint32_t num_imgs; 2129 uint8_t build[24]; 2130 uint8_t asic_type_rev; 2131 uint8_t rsvd[31]; 2132 }; 2133 2134 struct image_hdr { 2135 uint32_t imageid; 2136 uint32_t imageoffset; 2137 uint32_t imagelength; 2138 uint32_t image_checksum; 2139 uint8_t image_version[32]; 2140 }; 2141 2142 struct flash_section_hdr { 2143 uint32_t format_rev; 2144 uint32_t cksum; 2145 uint32_t antidote; 2146 uint32_t num_images; 2147 uint8_t id_string[128]; 2148 uint32_t rsvd[4]; 2149 }; 2150 2151 struct flash_section_entry { 2152 uint32_t type; 2153 uint32_t offset; 2154 uint32_t pad_size; 2155 uint32_t image_size; 2156 uint32_t cksum; 2157 uint32_t entry_point; 2158 uint32_t rsvd0; 2159 uint32_t rsvd1; 2160 uint8_t ver_data[32]; 2161 }; 2162 2163 struct flash_sec_info { 2164 uint8_t cookie[32]; 2165 struct flash_section_hdr fsec_hdr; 2166 struct flash_section_entry fsec_entry[32]; 2167 }; 2168 2169 enum LOWLEVEL_SUBSYSTEM_OPCODES { 2170 /* Opcodes used for lowlevel functions common to many subystems. 2171 * Some of these opcodes are used for diagnostic functions only. 2172 * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code. 2173 */ 2174 OPCODE_LOWLEVEL_TEST_LOOPBACK = 18, 2175 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19, 2176 OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20 2177 }; 2178 2179 enum LLDP_SUBSYSTEM_OPCODES { 2180 /* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */ 2181 OPCODE_LLDP_GET_CFG = 1, 2182 OPCODE_LLDP_SET_CFG = 2, 2183 OPCODE_LLDP_GET_STATS = 3 2184 }; 2185 2186 enum DCBX_SUBSYSTEM_OPCODES { 2187 /* Opcodes used for DCBX. */ 2188 OPCODE_DCBX_GET_CFG = 1, 2189 OPCODE_DCBX_SET_CFG = 2, 2190 OPCODE_DCBX_GET_MIB_INFO = 3, 2191 OPCODE_DCBX_GET_DCBX_MODE = 4, 2192 OPCODE_DCBX_SET_MODE = 5 2193 }; 2194 2195 enum DMTF_SUBSYSTEM_OPCODES { 2196 /* Opcodes used for DCBX subsystem. */ 2197 OPCODE_DMTF_EXEC_CLP_CMD = 1 2198 }; 2199 2200 enum DIAG_SUBSYSTEM_OPCODES { 2201 /* Opcodes used for diag functions common to many subsystems. */ 2202 OPCODE_DIAG_RUN_DMA_TEST = 1, 2203 OPCODE_DIAG_RUN_MDIO_TEST = 2, 2204 OPCODE_DIAG_RUN_NLB_TEST = 3, 2205 OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4, 2206 OPCODE_DIAG_GET_MAC = 5 2207 }; 2208 2209 enum VENDOR_SUBSYSTEM_OPCODES { 2210 /* Opcodes used for Vendor subsystem. */ 2211 OPCODE_VENDOR_SLI = 1 2212 }; 2213 2214 /* Management Status Codes */ 2215 enum MGMT_STATUS_SUCCESS { 2216 MGMT_SUCCESS = 0, 2217 MGMT_FAILED = 1, 2218 MGMT_ILLEGAL_REQUEST = 2, 2219 MGMT_ILLEGAL_FIELD = 3, 2220 MGMT_INSUFFICIENT_BUFFER = 4, 2221 MGMT_UNAUTHORIZED_REQUEST = 5, 2222 MGMT_INVALID_ISNS_ADDRESS = 10, 2223 MGMT_INVALID_IPADDR = 11, 2224 MGMT_INVALID_GATEWAY = 12, 2225 MGMT_INVALID_SUBNETMASK = 13, 2226 MGMT_INVALID_TARGET_IPADDR = 16, 2227 MGMT_TGTTBL_FULL = 20, 2228 MGMT_FLASHROM_SAVE_FAILED = 23, 2229 MGMT_IOCTLHANDLE_ALLOC_FAILED = 27, 2230 MGMT_INVALID_SESSION = 31, 2231 MGMT_INVALID_CONNECTION = 32, 2232 MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33, 2233 MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34, 2234 MGMT_BTL_PATH_TGTID_OCCUPIED = 35, 2235 MGMT_BTL_NO_FREE_SLOT_PATH = 36, 2236 MGMT_BTL_NO_FREE_SLOT_TGTID = 37, 2237 MGMT_POLL_IOCTL_TIMEOUT = 40, 2238 MGMT_ERROR_ACITISCSI = 41, 2239 MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43, 2240 MGMT_REBOOT_REQUIRED = 44, 2241 MGMT_INSUFFICIENT_TIMEOUT = 45, 2242 MGMT_IPADDR_NOT_SET = 46, 2243 MGMT_IPADDR_DUP_DETECTED = 47, 2244 MGMT_CANT_REMOVE_LAST_CONNECTION = 48, 2245 MGMT_TARGET_BUSY = 49, 2246 MGMT_TGT_ERR_LISTEN_SOCKET = 50, 2247 MGMT_TGT_ERR_BIND_SOCKET = 51, 2248 MGMT_TGT_ERR_NO_SOCKET = 52, 2249 MGMT_TGT_ERR_ISNS_COMM_FAILED = 55, 2250 MGMT_CANNOT_DELETE_BOOT_TARGET = 56, 2251 MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57, 2252 MGMT_FCF_IN_USE = 58 , 2253 MGMT_NO_CQE = 59, 2254 MGMT_TARGET_NOT_FOUND = 65, 2255 MGMT_NOT_SUPPORTED = 66, 2256 MGMT_NO_FCF_RECORDS = 67, 2257 MGMT_FEATURE_NOT_SUPPORTED = 68, 2258 MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69, 2259 MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70, 2260 MGMT_INVALID_NON_EMBEDDED_WRB = 71, 2261 MGMT_OOR = 100, 2262 MGMT_INVALID_PD = 101, 2263 MGMT_STATUS_PD_INUSE = 102, 2264 MGMT_INVALID_CQ = 103, 2265 MGMT_INVALID_QP = 104, 2266 MGMT_INVALID_STAG = 105, 2267 MGMT_ORD_EXCEEDS = 106, 2268 MGMT_IRD_EXCEEDS = 107, 2269 MGMT_SENDQ_WQE_EXCEEDS = 108, 2270 MGMT_RECVQ_RQE_EXCEEDS = 109, 2271 MGMT_SGE_SEND_EXCEEDS = 110, 2272 MGMT_SGE_WRITE_EXCEEDS = 111, 2273 MGMT_SGE_RECV_EXCEEDS = 112, 2274 MGMT_INVALID_STATE_CHANGE = 113, 2275 MGMT_MW_BOUND = 114, 2276 MGMT_INVALID_VA = 115, 2277 MGMT_INVALID_LENGTH = 116, 2278 MGMT_INVALID_FBO = 117, 2279 MGMT_INVALID_ACC_RIGHTS = 118, 2280 MGMT_INVALID_PBE_SIZE = 119, 2281 MGMT_INVALID_PBL_ENTRY = 120, 2282 MGMT_INVALID_PBL_OFFSET = 121, 2283 MGMT_ADDR_NON_EXIST = 122, 2284 MGMT_INVALID_VLANID = 123, 2285 MGMT_INVALID_MTU = 124, 2286 MGMT_INVALID_BACKLOG = 125, 2287 MGMT_CONNECTION_INPROGRESS = 126, 2288 MGMT_INVALID_RQE_SIZE = 127, 2289 MGMT_INVALID_RQE_ENTRY = 128 2290 }; 2291 2292 /* Additional Management Status Codes */ 2293 enum MGMT_ADDI_STATUS { 2294 MGMT_ADDI_NO_STATUS = 0, 2295 MGMT_ADDI_INVALID_IPTYPE = 1, 2296 MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9, 2297 MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10, 2298 MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11, 2299 MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16, 2300 MGMT_ADDI_SESSION_ALREADY_OPENED = 17, 2301 MGMT_ADDI_SESSION_ALREADY_CLOSED = 18, 2302 MGMT_ADDI_DEST_HOST_UNREACHABLE = 19, 2303 MGMT_ADDI_LOGIN_IN_PROGRESS = 20, 2304 MGMT_ADDI_TCP_CONNECT_FAILED = 21, 2305 MGMT_ADDI_INSUFFICIENT_RESOURCES = 22, 2306 MGMT_ADDI_LINK_DOWN = 23, 2307 MGMT_ADDI_DHCP_ERROR = 24, 2308 MGMT_ADDI_CONNECTION_OFFLOADED = 25, 2309 MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26, 2310 MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27, 2311 MGMT_ADDI_REQUEST_REJECTED = 28, 2312 MGMT_ADDI_INVALID_SUBSYSTEM = 29, 2313 MGMT_ADDI_INVALID_OPCODE = 30, 2314 MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31, 2315 MGMT_ADDI_INVALID_KEY = 32, 2316 MGMT_ADDI_INVALID_DOMAIN = 35, 2317 MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43, 2318 MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44, 2319 MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45, 2320 MGMT_ADDI_LOGIN_NOT_FOUND = 46, 2321 MGMT_ADDI_LOGIN_TARGET_REMOVED = 47, 2322 MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48, 2323 MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49, 2324 MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50, 2325 MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51, 2326 MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52, 2327 MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53, 2328 MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54, 2329 MGMT_ADDI_LOGIN_TARGET_ERROR = 55, 2330 MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56, 2331 MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57, 2332 MGMT_ADDI_SAME_CHAP_SECRET = 58, 2333 MGMT_ADDI_INVALID_SECRET_LENGTH = 59, 2334 MGMT_ADDI_DUPLICATE_ENTRY = 60, 2335 MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63, 2336 MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64, 2337 MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65, 2338 MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66, 2339 MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67, 2340 MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68, 2341 MGMT_ADDI_INVALID_VLAN_RANGE = 69, 2342 MGMT_ADDI_ERR_SET_VLAN = 70, 2343 MGMT_ADDI_ERR_DEL_VLAN = 71, 2344 MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72, 2345 MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73, 2346 MGMT_ADDI_TOO_MANY_INTERFACES = 74, 2347 MGMT_ADDI_INVALID_REQUEST = 75 2348 }; 2349 2350 enum NIC_SUBSYSTEM_OPCODES { 2351 /** 2352 * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2) 2353 * These opcodes are used for configuring the Ethernet interfaces. 2354 * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code. 2355 */ 2356 NIC_CONFIG_RSS = 1, 2357 NIC_CONFIG_ACPI = 2, 2358 NIC_CONFIG_PROMISCUOUS = 3, 2359 NIC_GET_STATS = 4, 2360 NIC_CREATE_WQ = 7, 2361 NIC_CREATE_RQ = 8, 2362 NIC_DELETE_WQ = 9, 2363 NIC_DELETE_RQ = 10, 2364 NIC_CONFIG_ACPI_WOL_MAGIC = 12, 2365 NIC_GET_NETWORK_STATS = 13, 2366 NIC_CREATE_HDS_RQ = 16, 2367 NIC_DELETE_HDS_RQ = 17, 2368 NIC_GET_PPORT_STATS = 18, 2369 NIC_GET_VPORT_STATS = 19, 2370 NIC_GET_QUEUE_STATS = 20 2371 }; 2372 2373 /* Hash option flags for RSS enable */ 2374 enum RSS_ENABLE_FLAGS { 2375 RSS_ENABLE_NONE = 0x0, /* (No RSS) */ 2376 RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */ 2377 RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */ 2378 RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */ 2379 RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */ 2380 RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */ 2381 RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */ 2382 }; 2383 #define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4) 2384 #define RSS_DISABLE RSS_ENABLE_NONE 2385 2386 /* NIC header WQE */ 2387 struct oce_nic_hdr_wqe { 2388 union { 2389 struct { 2390 #ifdef _BIG_ENDIAN 2391 /* dw0 */ 2392 uint32_t rsvd0; 2393 2394 /* dw1 */ 2395 uint32_t last_seg_udp_len:14; 2396 uint32_t rsvd1:18; 2397 2398 /* dw2 */ 2399 uint32_t lso_mss:14; 2400 uint32_t num_wqe:5; 2401 uint32_t rsvd4:2; 2402 uint32_t vlan:1; 2403 uint32_t lso:1; 2404 uint32_t tcpcs:1; 2405 uint32_t udpcs:1; 2406 uint32_t ipcs:1; 2407 uint32_t mgmt:1; 2408 uint32_t lso6:1; 2409 uint32_t forward:1; 2410 uint32_t crc:1; 2411 uint32_t event:1; 2412 uint32_t complete:1; 2413 2414 /* dw3 */ 2415 uint32_t vlan_tag:16; 2416 uint32_t total_length:16; 2417 #else 2418 /* dw0 */ 2419 uint32_t rsvd0; 2420 2421 /* dw1 */ 2422 uint32_t rsvd1:18; 2423 uint32_t last_seg_udp_len:14; 2424 2425 /* dw2 */ 2426 uint32_t complete:1; 2427 uint32_t event:1; 2428 uint32_t crc:1; 2429 uint32_t forward:1; 2430 uint32_t lso6:1; 2431 uint32_t mgmt:1; 2432 uint32_t ipcs:1; 2433 uint32_t udpcs:1; 2434 uint32_t tcpcs:1; 2435 uint32_t lso:1; 2436 uint32_t vlan:1; 2437 uint32_t rsvd4:2; 2438 uint32_t num_wqe:5; 2439 uint32_t lso_mss:14; 2440 2441 /* dw3 */ 2442 uint32_t total_length:16; 2443 uint32_t vlan_tag:16; 2444 #endif 2445 } s; 2446 uint32_t dw[4]; 2447 } u0; 2448 }; 2449 2450 /* NIC fragment WQE */ 2451 struct oce_nic_frag_wqe { 2452 union { 2453 struct { 2454 /* dw0 */ 2455 uint32_t frag_pa_hi; 2456 /* dw1 */ 2457 uint32_t frag_pa_lo; 2458 /* dw2 */ 2459 uint32_t rsvd0; 2460 uint32_t frag_len; 2461 } s; 2462 uint32_t dw[4]; 2463 } u0; 2464 }; 2465 2466 /* Ethernet Tx Completion Descriptor */ 2467 struct oce_nic_tx_cqe { 2468 union { 2469 struct { 2470 #ifdef _BIG_ENDIAN 2471 /* dw 0 */ 2472 uint32_t status:4; 2473 uint32_t rsvd0:8; 2474 uint32_t port:2; 2475 uint32_t ct:2; 2476 uint32_t wqe_index:16; 2477 2478 /* dw 1 */ 2479 uint32_t rsvd1:5; 2480 uint32_t cast_enc:2; 2481 uint32_t lso:1; 2482 uint32_t nwh_bytes:8; 2483 uint32_t user_bytes:16; 2484 2485 /* dw 2 */ 2486 uint32_t rsvd2; 2487 2488 /* dw 3 */ 2489 uint32_t valid:1; 2490 uint32_t rsvd3:4; 2491 uint32_t wq_id:11; 2492 uint32_t num_pkts:16; 2493 #else 2494 /* dw 0 */ 2495 uint32_t wqe_index:16; 2496 uint32_t ct:2; 2497 uint32_t port:2; 2498 uint32_t rsvd0:8; 2499 uint32_t status:4; 2500 2501 /* dw 1 */ 2502 uint32_t user_bytes:16; 2503 uint32_t nwh_bytes:8; 2504 uint32_t lso:1; 2505 uint32_t cast_enc:2; 2506 uint32_t rsvd1:5; 2507 /* dw 2 */ 2508 uint32_t rsvd2; 2509 2510 /* dw 3 */ 2511 uint32_t num_pkts:16; 2512 uint32_t wq_id:11; 2513 uint32_t rsvd3:4; 2514 uint32_t valid:1; 2515 #endif 2516 } s; 2517 uint32_t dw[4]; 2518 } u0; 2519 }; 2520 #define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) 2521 #define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) 2522 2523 /* Receive Queue Entry (RQE) */ 2524 struct oce_nic_rqe { 2525 union { 2526 struct { 2527 uint32_t frag_pa_hi; 2528 uint32_t frag_pa_lo; 2529 } s; 2530 uint32_t dw[2]; 2531 } u0; 2532 }; 2533 2534 /* NIC Receive CQE */ 2535 struct oce_nic_rx_cqe { 2536 union { 2537 struct { 2538 #ifdef _BIG_ENDIAN 2539 /* dw 0 */ 2540 uint32_t ip_options:1; 2541 uint32_t port:1; 2542 uint32_t pkt_size:14; 2543 uint32_t vlan_tag:16; 2544 2545 /* dw 1 */ 2546 uint32_t num_fragments:3; 2547 uint32_t switched:1; 2548 uint32_t ct:2; 2549 uint32_t frag_index:10; 2550 uint32_t rsvd0:1; 2551 uint32_t vlan_tag_present:1; 2552 uint32_t mac_dst:6; 2553 uint32_t ip_ver:1; 2554 uint32_t l4_cksum_pass:1; 2555 uint32_t ip_cksum_pass:1; 2556 uint32_t udpframe:1; 2557 uint32_t tcpframe:1; 2558 uint32_t ipframe:1; 2559 uint32_t rss_hp:1; 2560 uint32_t error:1; 2561 2562 /* dw 2 */ 2563 uint32_t valid:1; 2564 uint32_t hds_type:2; 2565 uint32_t lro_pkt:1; 2566 uint32_t rsvd4:1; 2567 uint32_t hds_hdr_size:12; 2568 uint32_t hds_hdr_frag_index:10; 2569 uint32_t rss_bank:1; 2570 uint32_t qnq:1; 2571 uint32_t pkt_type:2; 2572 uint32_t rss_flush:1; 2573 2574 /* dw 3 */ 2575 uint32_t rss_hash_value; 2576 #else 2577 /* dw 0 */ 2578 uint32_t vlan_tag:16; 2579 uint32_t pkt_size:14; 2580 uint32_t port:1; 2581 uint32_t ip_options:1; 2582 /* dw 1 */ 2583 uint32_t error:1; 2584 uint32_t rss_hp:1; 2585 uint32_t ipframe:1; 2586 uint32_t tcpframe:1; 2587 uint32_t udpframe:1; 2588 uint32_t ip_cksum_pass:1; 2589 uint32_t l4_cksum_pass:1; 2590 uint32_t ip_ver:1; 2591 uint32_t mac_dst:6; 2592 uint32_t vlan_tag_present:1; 2593 uint32_t rsvd0:1; 2594 uint32_t frag_index:10; 2595 uint32_t ct:2; 2596 uint32_t switched:1; 2597 uint32_t num_fragments:3; 2598 2599 /* dw 2 */ 2600 uint32_t rss_flush:1; 2601 uint32_t pkt_type:2; 2602 uint32_t qnq:1; 2603 uint32_t rss_bank:1; 2604 uint32_t hds_hdr_frag_index:10; 2605 uint32_t hds_hdr_size:12; 2606 uint32_t rsvd4:1; 2607 uint32_t lro_pkt:1; 2608 uint32_t hds_type:2; 2609 uint32_t valid:1; 2610 /* dw 3 */ 2611 uint32_t rss_hash_value; 2612 #endif 2613 } s; 2614 uint32_t dw[4]; 2615 } u0; 2616 }; 2617 /* NIC Receive CQE_v1 */ 2618 struct oce_nic_rx_cqe_v1 { 2619 union { 2620 struct { 2621 #ifdef _BIG_ENDIAN 2622 /* dw 0 */ 2623 uint32_t ip_options:1; 2624 uint32_t vlan_tag_present:1; 2625 uint32_t pkt_size:14; 2626 uint32_t vlan_tag:16; 2627 2628 /* dw 1 */ 2629 uint32_t num_fragments:3; 2630 uint32_t switched:1; 2631 uint32_t ct:2; 2632 uint32_t frag_index:10; 2633 uint32_t rsvd0:1; 2634 uint32_t mac_dst:7; 2635 uint32_t ip_ver:1; 2636 uint32_t l4_cksum_pass:1; 2637 uint32_t ip_cksum_pass:1; 2638 uint32_t udpframe:1; 2639 uint32_t tcpframe:1; 2640 uint32_t ipframe:1; 2641 uint32_t rss_hp:1; 2642 uint32_t error:1; 2643 2644 /* dw 2 */ 2645 uint32_t valid:1; 2646 uint32_t rsvd4:13; 2647 uint32_t hds_hdr_size: 2648 uint32_t hds_hdr_frag_index:8; 2649 uint32_t vlantag:1; 2650 uint32_t port:2; 2651 uint32_t rss_bank:1; 2652 uint32_t qnq:1; 2653 uint32_t pkt_type:2; 2654 uint32_t rss_flush:1; 2655 2656 /* dw 3 */ 2657 uint32_t rss_hash_value; 2658 #else 2659 /* dw 0 */ 2660 uint32_t vlan_tag:16; 2661 uint32_t pkt_size:14; 2662 uint32_t vlan_tag_present:1; 2663 uint32_t ip_options:1; 2664 /* dw 1 */ 2665 uint32_t error:1; 2666 uint32_t rss_hp:1; 2667 uint32_t ipframe:1; 2668 uint32_t tcpframe:1; 2669 uint32_t udpframe:1; 2670 uint32_t ip_cksum_pass:1; 2671 uint32_t l4_cksum_pass:1; 2672 uint32_t ip_ver:1; 2673 uint32_t mac_dst:7; 2674 uint32_t rsvd0:1; 2675 uint32_t frag_index:10; 2676 uint32_t ct:2; 2677 uint32_t switched:1; 2678 uint32_t num_fragments:3; 2679 2680 /* dw 2 */ 2681 uint32_t rss_flush:1; 2682 uint32_t pkt_type:2; 2683 uint32_t qnq:1; 2684 uint32_t rss_bank:1; 2685 uint32_t port:2; 2686 uint32_t vlantag:1; 2687 uint32_t hds_hdr_frag_index:8; 2688 uint32_t hds_hdr_size:2; 2689 uint32_t rsvd4:13; 2690 uint32_t valid:1; 2691 /* dw 3 */ 2692 uint32_t rss_hash_value; 2693 #endif 2694 } s; 2695 uint32_t dw[4]; 2696 } u0; 2697 }; 2698 2699 #define RQ_CQE_VALID_MASK 0x80 2700 #define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2]) 2701 #define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0) 2702 2703 struct mbx_config_nic_promiscuous { 2704 struct mbx_hdr hdr; 2705 union { 2706 struct { 2707 #ifdef _BIG_ENDIAN 2708 uint16_t rsvd0; 2709 uint8_t port1_promisc; 2710 uint8_t port0_promisc; 2711 #else 2712 uint8_t port0_promisc; 2713 uint8_t port1_promisc; 2714 uint16_t rsvd0; 2715 #endif 2716 } req; 2717 2718 struct { 2719 uint32_t rsvd0; 2720 } rsp; 2721 } params; 2722 }; 2723 2724 typedef union oce_wq_ctx_u { 2725 uint32_t dw[17]; 2726 struct { 2727 #ifdef _BIG_ENDIAN 2728 /* dw4 */ 2729 uint32_t dw4rsvd2:8; 2730 uint32_t nic_wq_type:8; 2731 uint32_t dw4rsvd1:8; 2732 uint32_t num_pages:8; 2733 /* dw5 */ 2734 uint32_t dw5rsvd2:12; 2735 uint32_t wq_size:4; 2736 uint32_t dw5rsvd1:16; 2737 /* dw6 */ 2738 uint32_t valid:1; 2739 uint32_t dw6rsvd1:31; 2740 /* dw7 */ 2741 uint32_t dw7rsvd1:16; 2742 uint32_t cq_id:16; 2743 #else 2744 /* dw4 */ 2745 uint32_t num_pages:8; 2746 #if 0 2747 uint32_t dw4rsvd1:8; 2748 #else 2749 /* PSP: this workaround is not documented: fill 0x01 for ulp_mask */ 2750 uint32_t ulp_mask:8; 2751 #endif 2752 uint32_t nic_wq_type:8; 2753 uint32_t dw4rsvd2:8; 2754 /* dw5 */ 2755 uint32_t dw5rsvd1:16; 2756 uint32_t wq_size:4; 2757 uint32_t dw5rsvd2:12; 2758 /* dw6 */ 2759 uint32_t dw6rsvd1:31; 2760 uint32_t valid:1; 2761 /* dw7 */ 2762 uint32_t cq_id:16; 2763 uint32_t dw7rsvd1:16; 2764 #endif 2765 /* dw8 - dw20 */ 2766 uint32_t dw8_20rsvd1[13]; 2767 } v0; 2768 struct { 2769 #ifdef _BIG_ENDIAN 2770 /* dw4 */ 2771 uint32_t dw4rsvd2:8; 2772 uint32_t nic_wq_type:8; 2773 uint32_t dw4rsvd1:8; 2774 uint32_t num_pages:8; 2775 /* dw5 */ 2776 uint32_t dw5rsvd2:12; 2777 uint32_t wq_size:4; 2778 uint32_t iface_id:16; 2779 /* dw6 */ 2780 uint32_t valid:1; 2781 uint32_t dw6rsvd1:31; 2782 /* dw7 */ 2783 uint32_t dw7rsvd1:16; 2784 uint32_t cq_id:16; 2785 #else 2786 /* dw4 */ 2787 uint32_t num_pages:8; 2788 uint32_t dw4rsvd1:8; 2789 uint32_t nic_wq_type:8; 2790 uint32_t dw4rsvd2:8; 2791 /* dw5 */ 2792 uint32_t iface_id:16; 2793 uint32_t wq_size:4; 2794 uint32_t dw5rsvd2:12; 2795 /* dw6 */ 2796 uint32_t dw6rsvd1:31; 2797 uint32_t valid:1; 2798 /* dw7 */ 2799 uint32_t cq_id:16; 2800 uint32_t dw7rsvd1:16; 2801 #endif 2802 /* dw8 - dw20 */ 2803 uint32_t dw8_20rsvd1[13]; 2804 } v1; 2805 } oce_wq_ctx_t; 2806 2807 /** 2808 * @brief [07] NIC_CREATE_WQ 2809 * @note 2810 * Lancer requires an InterfaceID to be specified with every WQ. This 2811 * is the basis for NIC IOV where the Interface maps to a vPort and maps 2812 * to both Tx and Rx sides. 2813 */ 2814 #define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */ 2815 #define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */ 2816 struct mbx_create_nic_wq { 2817 struct mbx_hdr hdr; 2818 union { 2819 struct { 2820 uint8_t num_pages; 2821 uint8_t ulp_num; 2822 uint16_t nic_wq_type; 2823 uint16_t if_id; 2824 uint8_t wq_size; 2825 uint8_t rsvd1; 2826 uint32_t rsvd2; 2827 uint16_t cq_id; 2828 uint16_t rsvd3; 2829 uint32_t rsvd4[13]; 2830 struct phys_addr pages[8]; 2831 2832 } req; 2833 2834 struct { 2835 uint16_t wq_id; 2836 uint16_t rid; 2837 uint32_t db_offset; 2838 uint8_t tc_id; 2839 uint8_t rsvd0[3]; 2840 } rsp; 2841 } params; 2842 }; 2843 2844 /* [09] NIC_DELETE_WQ */ 2845 struct mbx_delete_nic_wq { 2846 /* dw0 - dw3 */ 2847 struct mbx_hdr hdr; 2848 union { 2849 struct { 2850 #ifdef _BIG_ENDIAN 2851 /* dw4 */ 2852 uint16_t rsvd0; 2853 uint16_t wq_id; 2854 #else 2855 /* dw4 */ 2856 uint16_t wq_id; 2857 uint16_t rsvd0; 2858 #endif 2859 } req; 2860 struct { 2861 uint32_t rsvd0; 2862 } rsp; 2863 } params; 2864 }; 2865 2866 struct mbx_create_nic_rq { 2867 struct mbx_hdr hdr; 2868 union { 2869 struct { 2870 uint16_t cq_id; 2871 uint8_t frag_size; 2872 uint8_t num_pages; 2873 struct phys_addr pages[2]; 2874 uint32_t if_id; 2875 uint16_t max_frame_size; 2876 uint16_t page_size; 2877 uint32_t is_rss_queue; 2878 } req; 2879 2880 struct { 2881 uint16_t rq_id; 2882 uint8_t rss_cpuid; 2883 uint8_t rsvd0; 2884 } rsp; 2885 2886 } params; 2887 }; 2888 2889 /* [10] NIC_DELETE_RQ */ 2890 struct mbx_delete_nic_rq { 2891 /* dw0 - dw3 */ 2892 struct mbx_hdr hdr; 2893 union { 2894 struct { 2895 #ifdef _BIG_ENDIAN 2896 /* dw4 */ 2897 uint16_t bypass_flush; 2898 uint16_t rq_id; 2899 #else 2900 /* dw4 */ 2901 uint16_t rq_id; 2902 uint16_t bypass_flush; 2903 #endif 2904 } req; 2905 2906 struct { 2907 /* dw4 */ 2908 uint32_t rsvd0; 2909 } rsp; 2910 } params; 2911 }; 2912 2913 struct oce_port_rxf_stats_v0 { 2914 uint32_t rx_bytes_lsd; /* dword 0*/ 2915 uint32_t rx_bytes_msd; /* dword 1*/ 2916 uint32_t rx_total_frames; /* dword 2*/ 2917 uint32_t rx_unicast_frames; /* dword 3*/ 2918 uint32_t rx_multicast_frames; /* dword 4*/ 2919 uint32_t rx_broadcast_frames; /* dword 5*/ 2920 uint32_t rx_crc_errors; /* dword 6*/ 2921 uint32_t rx_alignment_symbol_errors; /* dword 7*/ 2922 uint32_t rx_pause_frames; /* dword 8*/ 2923 uint32_t rx_control_frames; /* dword 9*/ 2924 uint32_t rx_in_range_errors; /* dword 10*/ 2925 uint32_t rx_out_range_errors; /* dword 11*/ 2926 uint32_t rx_frame_too_long; /* dword 12*/ 2927 uint32_t rx_address_match_errors; /* dword 13*/ 2928 uint32_t rx_vlan_mismatch; /* dword 14*/ 2929 uint32_t rx_dropped_too_small; /* dword 15*/ 2930 uint32_t rx_dropped_too_short; /* dword 16*/ 2931 uint32_t rx_dropped_header_too_small; /* dword 17*/ 2932 uint32_t rx_dropped_tcp_length; /* dword 18*/ 2933 uint32_t rx_dropped_runt; /* dword 19*/ 2934 uint32_t rx_64_byte_packets; /* dword 20*/ 2935 uint32_t rx_65_127_byte_packets; /* dword 21*/ 2936 uint32_t rx_128_256_byte_packets; /* dword 22*/ 2937 uint32_t rx_256_511_byte_packets; /* dword 23*/ 2938 uint32_t rx_512_1023_byte_packets; /* dword 24*/ 2939 uint32_t rx_1024_1518_byte_packets; /* dword 25*/ 2940 uint32_t rx_1519_2047_byte_packets; /* dword 26*/ 2941 uint32_t rx_2048_4095_byte_packets; /* dword 27*/ 2942 uint32_t rx_4096_8191_byte_packets; /* dword 28*/ 2943 uint32_t rx_8192_9216_byte_packets; /* dword 29*/ 2944 uint32_t rx_ip_checksum_errs; /* dword 30*/ 2945 uint32_t rx_tcp_checksum_errs; /* dword 31*/ 2946 uint32_t rx_udp_checksum_errs; /* dword 32*/ 2947 uint32_t rx_non_rss_packets; /* dword 33*/ 2948 uint32_t rx_ipv4_packets; /* dword 34*/ 2949 uint32_t rx_ipv6_packets; /* dword 35*/ 2950 uint32_t rx_ipv4_bytes_lsd; /* dword 36*/ 2951 uint32_t rx_ipv4_bytes_msd; /* dword 37*/ 2952 uint32_t rx_ipv6_bytes_lsd; /* dword 38*/ 2953 uint32_t rx_ipv6_bytes_msd; /* dword 39*/ 2954 uint32_t rx_chute1_packets; /* dword 40*/ 2955 uint32_t rx_chute2_packets; /* dword 41*/ 2956 uint32_t rx_chute3_packets; /* dword 42*/ 2957 uint32_t rx_management_packets; /* dword 43*/ 2958 uint32_t rx_switched_unicast_packets; /* dword 44*/ 2959 uint32_t rx_switched_multicast_packets; /* dword 45*/ 2960 uint32_t rx_switched_broadcast_packets; /* dword 46*/ 2961 uint32_t tx_bytes_lsd; /* dword 47*/ 2962 uint32_t tx_bytes_msd; /* dword 48*/ 2963 uint32_t tx_unicastframes; /* dword 49*/ 2964 uint32_t tx_multicastframes; /* dword 50*/ 2965 uint32_t tx_broadcastframes; /* dword 51*/ 2966 uint32_t tx_pauseframes; /* dword 52*/ 2967 uint32_t tx_controlframes; /* dword 53*/ 2968 uint32_t tx_64_byte_packets; /* dword 54*/ 2969 uint32_t tx_65_127_byte_packets; /* dword 55*/ 2970 uint32_t tx_128_256_byte_packets; /* dword 56*/ 2971 uint32_t tx_256_511_byte_packets; /* dword 57*/ 2972 uint32_t tx_512_1023_byte_packets; /* dword 58*/ 2973 uint32_t tx_1024_1518_byte_packets; /* dword 59*/ 2974 uint32_t tx_1519_2047_byte_packets; /* dword 60*/ 2975 uint32_t tx_2048_4095_byte_packets; /* dword 61*/ 2976 uint32_t tx_4096_8191_byte_packets; /* dword 62*/ 2977 uint32_t tx_8192_9216_byte_packets; /* dword 63*/ 2978 uint32_t rxpp_fifo_overflow_drop; /* dword 64*/ 2979 uint32_t rx_input_fifo_overflow_drop; /* dword 65*/ 2980 }; 2981 2982 struct oce_rxf_stats_v0 { 2983 struct oce_port_rxf_stats_v0 port[2]; 2984 uint32_t rx_drops_no_pbuf; /* dword 132*/ 2985 uint32_t rx_drops_no_txpb; /* dword 133*/ 2986 uint32_t rx_drops_no_erx_descr; /* dword 134*/ 2987 uint32_t rx_drops_no_tpre_descr; /* dword 135*/ 2988 uint32_t management_rx_port_packets; /* dword 136*/ 2989 uint32_t management_rx_port_bytes; /* dword 137*/ 2990 uint32_t management_rx_port_pause_frames;/* dword 138*/ 2991 uint32_t management_rx_port_errors; /* dword 139*/ 2992 uint32_t management_tx_port_packets; /* dword 140*/ 2993 uint32_t management_tx_port_bytes; /* dword 141*/ 2994 uint32_t management_tx_port_pause; /* dword 142*/ 2995 uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/ 2996 uint32_t rx_drops_too_many_frags; /* dword 144*/ 2997 uint32_t rx_drops_invalid_ring; /* dword 145*/ 2998 uint32_t forwarded_packets; /* dword 146*/ 2999 uint32_t rx_drops_mtu; /* dword 147*/ 3000 uint32_t rsvd0[7]; 3001 uint32_t port0_jabber_events; 3002 uint32_t port1_jabber_events; 3003 uint32_t rsvd1[6]; 3004 }; 3005 3006 struct oce_port_rxf_stats_v2 { 3007 uint32_t rsvd0[10]; 3008 uint32_t roce_bytes_received_lsd; 3009 uint32_t roce_bytes_received_msd; 3010 uint32_t rsvd1[5]; 3011 uint32_t roce_frames_received; 3012 uint32_t rx_crc_errors; 3013 uint32_t rx_alignment_symbol_errors; 3014 uint32_t rx_pause_frames; 3015 uint32_t rx_priority_pause_frames; 3016 uint32_t rx_control_frames; 3017 uint32_t rx_in_range_errors; 3018 uint32_t rx_out_range_errors; 3019 uint32_t rx_frame_too_long; 3020 uint32_t rx_address_match_errors; 3021 uint32_t rx_dropped_too_small; 3022 uint32_t rx_dropped_too_short; 3023 uint32_t rx_dropped_header_too_small; 3024 uint32_t rx_dropped_tcp_length; 3025 uint32_t rx_dropped_runt; 3026 uint32_t rsvd2[10]; 3027 uint32_t rx_ip_checksum_errs; 3028 uint32_t rx_tcp_checksum_errs; 3029 uint32_t rx_udp_checksum_errs; 3030 uint32_t rsvd3[7]; 3031 uint32_t rx_switched_unicast_packets; 3032 uint32_t rx_switched_multicast_packets; 3033 uint32_t rx_switched_broadcast_packets; 3034 uint32_t rsvd4[3]; 3035 uint32_t tx_pauseframes; 3036 uint32_t tx_priority_pauseframes; 3037 uint32_t tx_controlframes; 3038 uint32_t rsvd5[10]; 3039 uint32_t rxpp_fifo_overflow_drop; 3040 uint32_t rx_input_fifo_overflow_drop; 3041 uint32_t pmem_fifo_overflow_drop; 3042 uint32_t jabber_events; 3043 uint32_t rsvd6[3]; 3044 uint32_t rx_drops_payload_size; 3045 uint32_t rx_drops_clipped_header; 3046 uint32_t rx_drops_crc; 3047 uint32_t roce_drops_payload_len; 3048 uint32_t roce_drops_crc; 3049 uint32_t rsvd7[19]; 3050 }; 3051 3052 struct oce_port_rxf_stats_v1 { 3053 uint32_t rsvd0[12]; 3054 uint32_t rx_crc_errors; 3055 uint32_t rx_alignment_symbol_errors; 3056 uint32_t rx_pause_frames; 3057 uint32_t rx_priority_pause_frames; 3058 uint32_t rx_control_frames; 3059 uint32_t rx_in_range_errors; 3060 uint32_t rx_out_range_errors; 3061 uint32_t rx_frame_too_long; 3062 uint32_t rx_address_match_errors; 3063 uint32_t rx_dropped_too_small; 3064 uint32_t rx_dropped_too_short; 3065 uint32_t rx_dropped_header_too_small; 3066 uint32_t rx_dropped_tcp_length; 3067 uint32_t rx_dropped_runt; 3068 uint32_t rsvd1[10]; 3069 uint32_t rx_ip_checksum_errs; 3070 uint32_t rx_tcp_checksum_errs; 3071 uint32_t rx_udp_checksum_errs; 3072 uint32_t rsvd2[7]; 3073 uint32_t rx_switched_unicast_packets; 3074 uint32_t rx_switched_multicast_packets; 3075 uint32_t rx_switched_broadcast_packets; 3076 uint32_t rsvd3[3]; 3077 uint32_t tx_pauseframes; 3078 uint32_t tx_priority_pauseframes; 3079 uint32_t tx_controlframes; 3080 uint32_t rsvd4[10]; 3081 uint32_t rxpp_fifo_overflow_drop; 3082 uint32_t rx_input_fifo_overflow_drop; 3083 uint32_t pmem_fifo_overflow_drop; 3084 uint32_t jabber_events; 3085 uint32_t rsvd5[3]; 3086 }; 3087 3088 struct oce_rxf_stats_v2 { 3089 struct oce_port_rxf_stats_v2 port[4]; 3090 uint32_t rsvd0[2]; 3091 uint32_t rx_drops_no_pbuf; 3092 uint32_t rx_drops_no_txpb; 3093 uint32_t rx_drops_no_erx_descr; 3094 uint32_t rx_drops_no_tpre_descr; 3095 uint32_t rsvd1[6]; 3096 uint32_t rx_drops_too_many_frags; 3097 uint32_t rx_drops_invalid_ring; 3098 uint32_t forwarded_packets; 3099 uint32_t rx_drops_mtu; 3100 uint32_t rsvd2[35]; 3101 }; 3102 3103 struct oce_rxf_stats_v1 { 3104 struct oce_port_rxf_stats_v1 port[4]; 3105 uint32_t rsvd0[2]; 3106 uint32_t rx_drops_no_pbuf; 3107 uint32_t rx_drops_no_txpb; 3108 uint32_t rx_drops_no_erx_descr; 3109 uint32_t rx_drops_no_tpre_descr; 3110 uint32_t rsvd1[6]; 3111 uint32_t rx_drops_too_many_frags; 3112 uint32_t rx_drops_invalid_ring; 3113 uint32_t forwarded_packets; 3114 uint32_t rx_drops_mtu; 3115 uint32_t rsvd2[14]; 3116 }; 3117 3118 struct oce_erx_stats_v2 { 3119 uint32_t rx_drops_no_fragments[136]; 3120 uint32_t rsvd[3]; 3121 }; 3122 3123 struct oce_erx_stats_v1 { 3124 uint32_t rx_drops_no_fragments[68]; 3125 uint32_t rsvd[4]; 3126 }; 3127 3128 struct oce_erx_stats_v0 { 3129 uint32_t rx_drops_no_fragments[44]; 3130 uint32_t rsvd[4]; 3131 }; 3132 3133 struct oce_pmem_stats { 3134 uint32_t eth_red_drops; 3135 uint32_t rsvd[5]; 3136 }; 3137 3138 struct oce_hw_stats_v2 { 3139 struct oce_rxf_stats_v2 rxf; 3140 uint32_t rsvd0[OCE_TXP_SW_SZ]; 3141 struct oce_erx_stats_v2 erx; 3142 struct oce_pmem_stats pmem; 3143 uint32_t rsvd1[18]; 3144 }; 3145 3146 struct oce_hw_stats_v1 { 3147 struct oce_rxf_stats_v1 rxf; 3148 uint32_t rsvd0[OCE_TXP_SW_SZ]; 3149 struct oce_erx_stats_v1 erx; 3150 struct oce_pmem_stats pmem; 3151 uint32_t rsvd1[18]; 3152 }; 3153 3154 struct oce_hw_stats_v0 { 3155 struct oce_rxf_stats_v0 rxf; 3156 uint32_t rsvd[48]; 3157 struct oce_erx_stats_v0 erx; 3158 struct oce_pmem_stats pmem; 3159 }; 3160 3161 #define MBX_GET_NIC_STATS(version) \ 3162 struct mbx_get_nic_stats_v##version { \ 3163 struct mbx_hdr hdr; \ 3164 union { \ 3165 struct { \ 3166 uint32_t rsvd0; \ 3167 } req; \ 3168 union { \ 3169 struct oce_hw_stats_v##version stats; \ 3170 } rsp; \ 3171 } params; \ 3172 } 3173 3174 MBX_GET_NIC_STATS(0); 3175 MBX_GET_NIC_STATS(1); 3176 MBX_GET_NIC_STATS(2); 3177 3178 /* [18(0x12)] NIC_GET_PPORT_STATS */ 3179 struct pport_stats { 3180 uint64_t tx_pkts; 3181 uint64_t tx_unicast_pkts; 3182 uint64_t tx_multicast_pkts; 3183 uint64_t tx_broadcast_pkts; 3184 uint64_t tx_bytes; 3185 uint64_t tx_unicast_bytes; 3186 uint64_t tx_multicast_bytes; 3187 uint64_t tx_broadcast_bytes; 3188 uint64_t tx_discards; 3189 uint64_t tx_errors; 3190 uint64_t tx_pause_frames; 3191 uint64_t tx_pause_on_frames; 3192 uint64_t tx_pause_off_frames; 3193 uint64_t tx_internal_mac_errors; 3194 uint64_t tx_control_frames; 3195 uint64_t tx_pkts_64_bytes; 3196 uint64_t tx_pkts_65_to_127_bytes; 3197 uint64_t tx_pkts_128_to_255_bytes; 3198 uint64_t tx_pkts_256_to_511_bytes; 3199 uint64_t tx_pkts_512_to_1023_bytes; 3200 uint64_t tx_pkts_1024_to_1518_bytes; 3201 uint64_t tx_pkts_1519_to_2047_bytes; 3202 uint64_t tx_pkts_2048_to_4095_bytes; 3203 uint64_t tx_pkts_4096_to_8191_bytes; 3204 uint64_t tx_pkts_8192_to_9216_bytes; 3205 uint64_t tx_lso_pkts; 3206 uint64_t rx_pkts; 3207 uint64_t rx_unicast_pkts; 3208 uint64_t rx_multicast_pkts; 3209 uint64_t rx_broadcast_pkts; 3210 uint64_t rx_bytes; 3211 uint64_t rx_unicast_bytes; 3212 uint64_t rx_multicast_bytes; 3213 uint64_t rx_broadcast_bytes; 3214 uint32_t rx_unknown_protos; 3215 uint32_t reserved_word69; 3216 uint64_t rx_discards; 3217 uint64_t rx_errors; 3218 uint64_t rx_crc_errors; 3219 uint64_t rx_alignment_errors; 3220 uint64_t rx_symbol_errors; 3221 uint64_t rx_pause_frames; 3222 uint64_t rx_pause_on_frames; 3223 uint64_t rx_pause_off_frames; 3224 uint64_t rx_frames_too_long; 3225 uint64_t rx_internal_mac_errors; 3226 uint32_t rx_undersize_pkts; 3227 uint32_t rx_oversize_pkts; 3228 uint32_t rx_fragment_pkts; 3229 uint32_t rx_jabbers; 3230 uint64_t rx_control_frames; 3231 uint64_t rx_control_frames_unknown_opcode; 3232 uint32_t rx_in_range_errors; 3233 uint32_t rx_out_of_range_errors; 3234 uint32_t rx_address_match_errors; 3235 uint32_t rx_vlan_mismatch_errors; 3236 uint32_t rx_dropped_too_small; 3237 uint32_t rx_dropped_too_short; 3238 uint32_t rx_dropped_header_too_small; 3239 uint32_t rx_dropped_invalid_tcp_length; 3240 uint32_t rx_dropped_runt; 3241 uint32_t rx_ip_checksum_errors; 3242 uint32_t rx_tcp_checksum_errors; 3243 uint32_t rx_udp_checksum_errors; 3244 uint32_t rx_non_rss_pkts; 3245 uint64_t reserved_word111; 3246 uint64_t rx_ipv4_pkts; 3247 uint64_t rx_ipv6_pkts; 3248 uint64_t rx_ipv4_bytes; 3249 uint64_t rx_ipv6_bytes; 3250 uint64_t rx_nic_pkts; 3251 uint64_t rx_tcp_pkts; 3252 uint64_t rx_iscsi_pkts; 3253 uint64_t rx_management_pkts; 3254 uint64_t rx_switched_unicast_pkts; 3255 uint64_t rx_switched_multicast_pkts; 3256 uint64_t rx_switched_broadcast_pkts; 3257 uint64_t num_forwards; 3258 uint32_t rx_fifo_overflow; 3259 uint32_t rx_input_fifo_overflow; 3260 uint64_t rx_drops_too_many_frags; 3261 uint32_t rx_drops_invalid_queue; 3262 uint32_t reserved_word141; 3263 uint64_t rx_drops_mtu; 3264 uint64_t rx_pkts_64_bytes; 3265 uint64_t rx_pkts_65_to_127_bytes; 3266 uint64_t rx_pkts_128_to_255_bytes; 3267 uint64_t rx_pkts_256_to_511_bytes; 3268 uint64_t rx_pkts_512_to_1023_bytes; 3269 uint64_t rx_pkts_1024_to_1518_bytes; 3270 uint64_t rx_pkts_1519_to_2047_bytes; 3271 uint64_t rx_pkts_2048_to_4095_bytes; 3272 uint64_t rx_pkts_4096_to_8191_bytes; 3273 uint64_t rx_pkts_8192_to_9216_bytes; 3274 }; 3275 3276 struct mbx_get_pport_stats { 3277 /* dw0 - dw3 */ 3278 struct mbx_hdr hdr; 3279 union { 3280 struct { 3281 /* dw4 */ 3282 #ifdef _BIG_ENDIAN 3283 uint32_t reset_stats:8; 3284 uint32_t rsvd0:8; 3285 uint32_t port_number:16; 3286 #else 3287 uint32_t port_number:16; 3288 uint32_t rsvd0:8; 3289 uint32_t reset_stats:8; 3290 #endif 3291 } req; 3292 3293 union { 3294 struct pport_stats pps; 3295 uint32_t pport_stats[164 - 4 + 1]; 3296 } rsp; 3297 } params; 3298 }; 3299 3300 /* [19(0x13)] NIC_GET_VPORT_STATS */ 3301 struct vport_stats { 3302 uint64_t tx_pkts; 3303 uint64_t tx_unicast_pkts; 3304 uint64_t tx_multicast_pkts; 3305 uint64_t tx_broadcast_pkts; 3306 uint64_t tx_bytes; 3307 uint64_t tx_unicast_bytes; 3308 uint64_t tx_multicast_bytes; 3309 uint64_t tx_broadcast_bytes; 3310 uint64_t tx_discards; 3311 uint64_t tx_errors; 3312 uint64_t tx_pkts_64_bytes; 3313 uint64_t tx_pkts_65_to_127_bytes; 3314 uint64_t tx_pkts_128_to_255_bytes; 3315 uint64_t tx_pkts_256_to_511_bytes; 3316 uint64_t tx_pkts_512_to_1023_bytes; 3317 uint64_t tx_pkts_1024_to_1518_bytes; 3318 uint64_t tx_pkts_1519_to_9699_bytes; 3319 uint64_t tx_pkts_over_9699_bytes; 3320 uint64_t rx_pkts; 3321 uint64_t rx_unicast_pkts; 3322 uint64_t rx_multicast_pkts; 3323 uint64_t rx_broadcast_pkts; 3324 uint64_t rx_bytes; 3325 uint64_t rx_unicast_bytes; 3326 uint64_t rx_multicast_bytes; 3327 uint64_t rx_broadcast_bytes; 3328 uint64_t rx_discards; 3329 uint64_t rx_errors; 3330 uint64_t rx_pkts_64_bytes; 3331 uint64_t rx_pkts_65_to_127_bytes; 3332 uint64_t rx_pkts_128_to_255_bytes; 3333 uint64_t rx_pkts_256_to_511_bytes; 3334 uint64_t rx_pkts_512_to_1023_bytes; 3335 uint64_t rx_pkts_1024_to_1518_bytes; 3336 uint64_t rx_pkts_1519_to_9699_bytes; 3337 uint64_t rx_pkts_gt_9699_bytes; 3338 }; 3339 struct mbx_get_vport_stats { 3340 /* dw0 - dw3 */ 3341 struct mbx_hdr hdr; 3342 union { 3343 struct { 3344 /* dw4 */ 3345 #ifdef _BIG_ENDIAN 3346 uint32_t reset_stats:8; 3347 uint32_t rsvd0:8; 3348 uint32_t vport_number:16; 3349 #else 3350 uint32_t vport_number:16; 3351 uint32_t rsvd0:8; 3352 uint32_t reset_stats:8; 3353 #endif 3354 } req; 3355 3356 union { 3357 struct vport_stats vps; 3358 uint32_t vport_stats[75 - 4 + 1]; 3359 } rsp; 3360 } params; 3361 }; 3362 3363 /** 3364 * @brief [20(0x14)] NIC_GET_QUEUE_STATS 3365 * The significant difference between vPort and Queue statistics is 3366 * the packet byte counters. 3367 */ 3368 struct queue_stats { 3369 uint64_t packets; 3370 uint64_t bytes; 3371 uint64_t errors; 3372 uint64_t drops; 3373 uint64_t buffer_errors; /* rsvd when tx */ 3374 }; 3375 3376 #define QUEUE_TYPE_WQ 0 3377 #define QUEUE_TYPE_RQ 1 3378 #define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */ 3379 3380 struct mbx_get_queue_stats { 3381 /* dw0 - dw3 */ 3382 struct mbx_hdr hdr; 3383 union { 3384 struct { 3385 /* dw4 */ 3386 #ifdef _BIG_ENDIAN 3387 uint32_t reset_stats:8; 3388 uint32_t queue_type:8; 3389 uint32_t queue_id:16; 3390 #else 3391 uint32_t queue_id:16; 3392 uint32_t queue_type:8; 3393 uint32_t reset_stats:8; 3394 #endif 3395 } req; 3396 3397 union { 3398 struct queue_stats qs; 3399 uint32_t queue_stats[13 - 4 + 1]; 3400 } rsp; 3401 } params; 3402 }; 3403 3404 /* [01] NIC_CONFIG_RSS */ 3405 #define OCE_HASH_TBL_SZ 10 3406 #define OCE_CPU_TBL_SZ 128 3407 #define OCE_FLUSH 1 /* RSS flush completion per CQ port */ 3408 struct mbx_config_nic_rss { 3409 struct mbx_hdr hdr; 3410 union { 3411 struct { 3412 #ifdef _BIG_ENDIAN 3413 uint32_t if_id; 3414 uint16_t cpu_tbl_sz_log2; 3415 uint16_t enable_rss; 3416 uint32_t hash[OCE_HASH_TBL_SZ]; 3417 uint8_t cputable[OCE_CPU_TBL_SZ]; 3418 uint8_t rsvd[3]; 3419 uint8_t flush; 3420 #else 3421 uint32_t if_id; 3422 uint16_t enable_rss; 3423 uint16_t cpu_tbl_sz_log2; 3424 uint32_t hash[OCE_HASH_TBL_SZ]; 3425 uint8_t cputable[OCE_CPU_TBL_SZ]; 3426 uint8_t flush; 3427 uint8_t rsvd[3]; 3428 #endif 3429 } req; 3430 struct { 3431 uint8_t rsvd[3]; 3432 uint8_t rss_bank; 3433 } rsp; 3434 } params; 3435 }; 3436 3437 #pragma pack() 3438 3439 typedef uint32_t oce_stat_t; /* statistic counter */ 3440 3441 enum OCE_RXF_PORT_STATS { 3442 RXF_RX_BYTES_LSD, 3443 RXF_RX_BYTES_MSD, 3444 RXF_RX_TOTAL_FRAMES, 3445 RXF_RX_UNICAST_FRAMES, 3446 RXF_RX_MULTICAST_FRAMES, 3447 RXF_RX_BROADCAST_FRAMES, 3448 RXF_RX_CRC_ERRORS, 3449 RXF_RX_ALIGNMENT_SYMBOL_ERRORS, 3450 RXF_RX_PAUSE_FRAMES, 3451 RXF_RX_CONTROL_FRAMES, 3452 RXF_RX_IN_RANGE_ERRORS, 3453 RXF_RX_OUT_RANGE_ERRORS, 3454 RXF_RX_FRAME_TOO_LONG, 3455 RXF_RX_ADDRESS_MATCH_ERRORS, 3456 RXF_RX_VLAN_MISMATCH, 3457 RXF_RX_DROPPED_TOO_SMALL, 3458 RXF_RX_DROPPED_TOO_SHORT, 3459 RXF_RX_DROPPED_HEADER_TOO_SMALL, 3460 RXF_RX_DROPPED_TCP_LENGTH, 3461 RXF_RX_DROPPED_RUNT, 3462 RXF_RX_64_BYTE_PACKETS, 3463 RXF_RX_65_127_BYTE_PACKETS, 3464 RXF_RX_128_256_BYTE_PACKETS, 3465 RXF_RX_256_511_BYTE_PACKETS, 3466 RXF_RX_512_1023_BYTE_PACKETS, 3467 RXF_RX_1024_1518_BYTE_PACKETS, 3468 RXF_RX_1519_2047_BYTE_PACKETS, 3469 RXF_RX_2048_4095_BYTE_PACKETS, 3470 RXF_RX_4096_8191_BYTE_PACKETS, 3471 RXF_RX_8192_9216_BYTE_PACKETS, 3472 RXF_RX_IP_CHECKSUM_ERRS, 3473 RXF_RX_TCP_CHECKSUM_ERRS, 3474 RXF_RX_UDP_CHECKSUM_ERRS, 3475 RXF_RX_NON_RSS_PACKETS, 3476 RXF_RX_IPV4_PACKETS, 3477 RXF_RX_IPV6_PACKETS, 3478 RXF_RX_IPV4_BYTES_LSD, 3479 RXF_RX_IPV4_BYTES_MSD, 3480 RXF_RX_IPV6_BYTES_LSD, 3481 RXF_RX_IPV6_BYTES_MSD, 3482 RXF_RX_CHUTE1_PACKETS, 3483 RXF_RX_CHUTE2_PACKETS, 3484 RXF_RX_CHUTE3_PACKETS, 3485 RXF_RX_MANAGEMENT_PACKETS, 3486 RXF_RX_SWITCHED_UNICAST_PACKETS, 3487 RXF_RX_SWITCHED_MULTICAST_PACKETS, 3488 RXF_RX_SWITCHED_BROADCAST_PACKETS, 3489 RXF_TX_BYTES_LSD, 3490 RXF_TX_BYTES_MSD, 3491 RXF_TX_UNICAST_FRAMES, 3492 RXF_TX_MULTICAST_FRAMES, 3493 RXF_TX_BROADCAST_FRAMES, 3494 RXF_TX_PAUSE_FRAMES, 3495 RXF_TX_CONTROL_FRAMES, 3496 RXF_TX_64_BYTE_PACKETS, 3497 RXF_TX_65_127_BYTE_PACKETS, 3498 RXF_TX_128_256_BYTE_PACKETS, 3499 RXF_TX_256_511_BYTE_PACKETS, 3500 RXF_TX_512_1023_BYTE_PACKETS, 3501 RXF_TX_1024_1518_BYTE_PACKETS, 3502 RXF_TX_1519_2047_BYTE_PACKETS, 3503 RXF_TX_2048_4095_BYTE_PACKETS, 3504 RXF_TX_4096_8191_BYTE_PACKETS, 3505 RXF_TX_8192_9216_BYTE_PACKETS, 3506 RXF_RX_FIFO_OVERFLOW, 3507 RXF_RX_INPUT_FIFO_OVERFLOW, 3508 RXF_PORT_STATS_N_WORDS 3509 }; 3510 3511 enum OCE_RXF_ADDL_STATS { 3512 RXF_RX_DROPS_NO_PBUF, 3513 RXF_RX_DROPS_NO_TXPB, 3514 RXF_RX_DROPS_NO_ERX_DESCR, 3515 RXF_RX_DROPS_NO_TPRE_DESCR, 3516 RXF_MANAGEMENT_RX_PORT_PACKETS, 3517 RXF_MANAGEMENT_RX_PORT_BYTES, 3518 RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES, 3519 RXF_MANAGEMENT_RX_PORT_ERRORS, 3520 RXF_MANAGEMENT_TX_PORT_PACKETS, 3521 RXF_MANAGEMENT_TX_PORT_BYTES, 3522 RXF_MANAGEMENT_TX_PORT_PAUSE, 3523 RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW, 3524 RXF_RX_DROPS_TOO_MANY_FRAGS, 3525 RXF_RX_DROPS_INVALID_RING, 3526 RXF_FORWARDED_PACKETS, 3527 RXF_RX_DROPS_MTU, 3528 RXF_ADDL_STATS_N_WORDS 3529 }; 3530 3531 enum OCE_TX_CHUTE_PORT_STATS { 3532 CTPT_XMT_IPV4_PKTS, 3533 CTPT_XMT_IPV4_LSD, 3534 CTPT_XMT_IPV4_MSD, 3535 CTPT_XMT_IPV6_PKTS, 3536 CTPT_XMT_IPV6_LSD, 3537 CTPT_XMT_IPV6_MSD, 3538 CTPT_REXMT_IPV4_PKTs, 3539 CTPT_REXMT_IPV4_LSD, 3540 CTPT_REXMT_IPV4_MSD, 3541 CTPT_REXMT_IPV6_PKTs, 3542 CTPT_REXMT_IPV6_LSD, 3543 CTPT_REXMT_IPV6_MSD, 3544 CTPT_N_WORDS, 3545 }; 3546 3547 enum OCE_RX_ERR_STATS { 3548 RX_DROPS_NO_FRAGMENTS_0, 3549 RX_DROPS_NO_FRAGMENTS_1, 3550 RX_DROPS_NO_FRAGMENTS_2, 3551 RX_DROPS_NO_FRAGMENTS_3, 3552 RX_DROPS_NO_FRAGMENTS_4, 3553 RX_DROPS_NO_FRAGMENTS_5, 3554 RX_DROPS_NO_FRAGMENTS_6, 3555 RX_DROPS_NO_FRAGMENTS_7, 3556 RX_DROPS_NO_FRAGMENTS_8, 3557 RX_DROPS_NO_FRAGMENTS_9, 3558 RX_DROPS_NO_FRAGMENTS_10, 3559 RX_DROPS_NO_FRAGMENTS_11, 3560 RX_DROPS_NO_FRAGMENTS_12, 3561 RX_DROPS_NO_FRAGMENTS_13, 3562 RX_DROPS_NO_FRAGMENTS_14, 3563 RX_DROPS_NO_FRAGMENTS_15, 3564 RX_DROPS_NO_FRAGMENTS_16, 3565 RX_DROPS_NO_FRAGMENTS_17, 3566 RX_DROPS_NO_FRAGMENTS_18, 3567 RX_DROPS_NO_FRAGMENTS_19, 3568 RX_DROPS_NO_FRAGMENTS_20, 3569 RX_DROPS_NO_FRAGMENTS_21, 3570 RX_DROPS_NO_FRAGMENTS_22, 3571 RX_DROPS_NO_FRAGMENTS_23, 3572 RX_DROPS_NO_FRAGMENTS_24, 3573 RX_DROPS_NO_FRAGMENTS_25, 3574 RX_DROPS_NO_FRAGMENTS_26, 3575 RX_DROPS_NO_FRAGMENTS_27, 3576 RX_DROPS_NO_FRAGMENTS_28, 3577 RX_DROPS_NO_FRAGMENTS_29, 3578 RX_DROPS_NO_FRAGMENTS_30, 3579 RX_DROPS_NO_FRAGMENTS_31, 3580 RX_DROPS_NO_FRAGMENTS_32, 3581 RX_DROPS_NO_FRAGMENTS_33, 3582 RX_DROPS_NO_FRAGMENTS_34, 3583 RX_DROPS_NO_FRAGMENTS_35, 3584 RX_DROPS_NO_FRAGMENTS_36, 3585 RX_DROPS_NO_FRAGMENTS_37, 3586 RX_DROPS_NO_FRAGMENTS_38, 3587 RX_DROPS_NO_FRAGMENTS_39, 3588 RX_DROPS_NO_FRAGMENTS_40, 3589 RX_DROPS_NO_FRAGMENTS_41, 3590 RX_DROPS_NO_FRAGMENTS_42, 3591 RX_DROPS_NO_FRAGMENTS_43, 3592 RX_DEBUG_WDMA_SENT_HOLD, 3593 RX_DEBUG_WDMA_PBFREE_SENT_HOLD, 3594 RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD, 3595 RX_DEBUG_PMEM_PBUF_DEALLOC, 3596 RX_ERRORS_N_WORDS 3597 }; 3598 3599 enum OCE_PMEM_ERR_STATS { 3600 PMEM_ETH_RED_DROPS, 3601 PMEM_LRO_RED_DROPS, 3602 PMEM_ULP0_RED_DROPS, 3603 PMEM_ULP1_RED_DROPS, 3604 PMEM_GLOBAL_RED_DROPS, 3605 PMEM_ERRORS_N_WORDS 3606 }; 3607 3608 /** 3609 * @brief Statistics for a given Physical Port 3610 * These satisfy all the required BE2 statistics and also the 3611 * following MIB objects: 3612 * 3613 * RFC 2863 - The Interfaces Group MIB 3614 * RFC 2819 - Remote Network Monitoring Management Information Base (RMON) 3615 * RFC 3635 - Managed Objects for the Ethernet-like Interface Types 3616 * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2) 3617 * 3618 */ 3619 enum OCE_PPORT_STATS { 3620 PPORT_TX_PKTS = 0, 3621 PPORT_TX_UNICAST_PKTS = 2, 3622 PPORT_TX_MULTICAST_PKTS = 4, 3623 PPORT_TX_BROADCAST_PKTS = 6, 3624 PPORT_TX_BYTES = 8, 3625 PPORT_TX_UNICAST_BYTES = 10, 3626 PPORT_TX_MULTICAST_BYTES = 12, 3627 PPORT_TX_BROADCAST_BYTES = 14, 3628 PPORT_TX_DISCARDS = 16, 3629 PPORT_TX_ERRORS = 18, 3630 PPORT_TX_PAUSE_FRAMES = 20, 3631 PPORT_TX_PAUSE_ON_FRAMES = 22, 3632 PPORT_TX_PAUSE_OFF_FRAMES = 24, 3633 PPORT_TX_INTERNAL_MAC_ERRORS = 26, 3634 PPORT_TX_CONTROL_FRAMES = 28, 3635 PPORT_TX_PKTS_64_BYTES = 30, 3636 PPORT_TX_PKTS_65_TO_127_BYTES = 32, 3637 PPORT_TX_PKTS_128_TO_255_BYTES = 34, 3638 PPORT_TX_PKTS_256_TO_511_BYTES = 36, 3639 PPORT_TX_PKTS_512_TO_1023_BYTES = 38, 3640 PPORT_TX_PKTS_1024_TO_1518_BYTES = 40, 3641 PPORT_TX_PKTS_1519_TO_2047_BYTES = 42, 3642 PPORT_TX_PKTS_2048_TO_4095_BYTES = 44, 3643 PPORT_TX_PKTS_4096_TO_8191_BYTES = 46, 3644 PPORT_TX_PKTS_8192_TO_9216_BYTES = 48, 3645 PPORT_TX_LSO_PKTS = 50, 3646 PPORT_RX_PKTS = 52, 3647 PPORT_RX_UNICAST_PKTS = 54, 3648 PPORT_RX_MULTICAST_PKTS = 56, 3649 PPORT_RX_BROADCAST_PKTS = 58, 3650 PPORT_RX_BYTES = 60, 3651 PPORT_RX_UNICAST_BYTES = 62, 3652 PPORT_RX_MULTICAST_BYTES = 64, 3653 PPORT_RX_BROADCAST_BYTES = 66, 3654 PPORT_RX_UNKNOWN_PROTOS = 68, 3655 PPORT_RESERVED_WORD69 = 69, 3656 PPORT_RX_DISCARDS = 70, 3657 PPORT_RX_ERRORS = 72, 3658 PPORT_RX_CRC_ERRORS = 74, 3659 PPORT_RX_ALIGNMENT_ERRORS = 76, 3660 PPORT_RX_SYMBOL_ERRORS = 78, 3661 PPORT_RX_PAUSE_FRAMES = 80, 3662 PPORT_RX_PAUSE_ON_FRAMES = 82, 3663 PPORT_RX_PAUSE_OFF_FRAMES = 84, 3664 PPORT_RX_FRAMES_TOO_LONG = 86, 3665 PPORT_RX_INTERNAL_MAC_ERRORS = 88, 3666 PPORT_RX_UNDERSIZE_PKTS = 90, 3667 PPORT_RX_OVERSIZE_PKTS = 91, 3668 PPORT_RX_FRAGMENT_PKTS = 92, 3669 PPORT_RX_JABBERS = 93, 3670 PPORT_RX_CONTROL_FRAMES = 94, 3671 PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96, 3672 PPORT_RX_IN_RANGE_ERRORS = 98, 3673 PPORT_RX_OUT_OF_RANGE_ERRORS = 99, 3674 PPORT_RX_ADDRESS_MATCH_ERRORS = 100, 3675 PPORT_RX_VLAN_MISMATCH_ERRORS = 101, 3676 PPORT_RX_DROPPED_TOO_SMALL = 102, 3677 PPORT_RX_DROPPED_TOO_SHORT = 103, 3678 PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104, 3679 PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105, 3680 PPORT_RX_DROPPED_RUNT = 106, 3681 PPORT_RX_IP_CHECKSUM_ERRORS = 107, 3682 PPORT_RX_TCP_CHECKSUM_ERRORS = 108, 3683 PPORT_RX_UDP_CHECKSUM_ERRORS = 109, 3684 PPORT_RX_NON_RSS_PKTS = 110, 3685 PPORT_RESERVED_WORD111 = 111, 3686 PPORT_RX_IPV4_PKTS = 112, 3687 PPORT_RX_IPV6_PKTS = 114, 3688 PPORT_RX_IPV4_BYTES = 116, 3689 PPORT_RX_IPV6_BYTES = 118, 3690 PPORT_RX_NIC_PKTS = 120, 3691 PPORT_RX_TCP_PKTS = 122, 3692 PPORT_RX_ISCSI_PKTS = 124, 3693 PPORT_RX_MANAGEMENT_PKTS = 126, 3694 PPORT_RX_SWITCHED_UNICAST_PKTS = 128, 3695 PPORT_RX_SWITCHED_MULTICAST_PKTS = 130, 3696 PPORT_RX_SWITCHED_BROADCAST_PKTS = 132, 3697 PPORT_NUM_FORWARDS = 134, 3698 PPORT_RX_FIFO_OVERFLOW = 136, 3699 PPORT_RX_INPUT_FIFO_OVERFLOW = 137, 3700 PPORT_RX_DROPS_TOO_MANY_FRAGS = 138, 3701 PPORT_RX_DROPS_INVALID_QUEUE = 140, 3702 PPORT_RESERVED_WORD141 = 141, 3703 PPORT_RX_DROPS_MTU = 142, 3704 PPORT_RX_PKTS_64_BYTES = 144, 3705 PPORT_RX_PKTS_65_TO_127_BYTES = 146, 3706 PPORT_RX_PKTS_128_TO_255_BYTES = 148, 3707 PPORT_RX_PKTS_256_TO_511_BYTES = 150, 3708 PPORT_RX_PKTS_512_TO_1023_BYTES = 152, 3709 PPORT_RX_PKTS_1024_TO_1518_BYTES = 154, 3710 PPORT_RX_PKTS_1519_TO_2047_BYTES = 156, 3711 PPORT_RX_PKTS_2048_TO_4095_BYTES = 158, 3712 PPORT_RX_PKTS_4096_TO_8191_BYTES = 160, 3713 PPORT_RX_PKTS_8192_TO_9216_BYTES = 162, 3714 PPORT_N_WORDS = 164 3715 }; 3716 3717 /** 3718 * @brief Statistics for a given Virtual Port (vPort) 3719 * The following describes the vPort statistics satisfying 3720 * requirements of Linux/VMWare netdev statistics and 3721 * Microsoft Windows Statistics along with other Operating Systems. 3722 */ 3723 enum OCE_VPORT_STATS { 3724 VPORT_TX_PKTS = 0, 3725 VPORT_TX_UNICAST_PKTS = 2, 3726 VPORT_TX_MULTICAST_PKTS = 4, 3727 VPORT_TX_BROADCAST_PKTS = 6, 3728 VPORT_TX_BYTES = 8, 3729 VPORT_TX_UNICAST_BYTES = 10, 3730 VPORT_TX_MULTICAST_BYTES = 12, 3731 VPORT_TX_BROADCAST_BYTES = 14, 3732 VPORT_TX_DISCARDS = 16, 3733 VPORT_TX_ERRORS = 18, 3734 VPORT_TX_PKTS_64_BYTES = 20, 3735 VPORT_TX_PKTS_65_TO_127_BYTES = 22, 3736 VPORT_TX_PKTS_128_TO_255_BYTES = 24, 3737 VPORT_TX_PKTS_256_TO_511_BYTES = 26, 3738 VPORT_TX_PKTS_512_TO_1023_BYTEs = 28, 3739 VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30, 3740 VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32, 3741 VPORT_TX_PKTS_OVER_9699_BYTES = 34, 3742 VPORT_RX_PKTS = 36, 3743 VPORT_RX_UNICAST_PKTS = 38, 3744 VPORT_RX_MULTICAST_PKTS = 40, 3745 VPORT_RX_BROADCAST_PKTS = 42, 3746 VPORT_RX_BYTES = 44, 3747 VPORT_RX_UNICAST_BYTES = 46, 3748 VPORT_RX_MULTICAST_BYTES = 48, 3749 VPORT_RX_BROADCAST_BYTES = 50, 3750 VPORT_RX_DISCARDS = 52, 3751 VPORT_RX_ERRORS = 54, 3752 VPORT_RX_PKTS_64_BYTES = 56, 3753 VPORT_RX_PKTS_65_TO_127_BYTES = 58, 3754 VPORT_RX_PKTS_128_TO_255_BYTES = 60, 3755 VPORT_RX_PKTS_256_TO_511_BYTES = 62, 3756 VPORT_RX_PKTS_512_TO_1023_BYTEs = 64, 3757 VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66, 3758 VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68, 3759 VPORT_RX_PKTS_OVER_9699_BYTES = 70, 3760 VPORT_N_WORDS = 72 3761 }; 3762 3763 /** 3764 * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ) 3765 * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ 3766 */ 3767 enum OCE_QUEUE_TX_STATS { 3768 QUEUE_TX_PKTS = 0, 3769 QUEUE_TX_BYTES = 2, 3770 QUEUE_TX_ERRORS = 4, 3771 QUEUE_TX_DROPS = 6, 3772 QUEUE_TX_N_WORDS = 8 3773 }; 3774 3775 enum OCE_QUEUE_RX_STATS { 3776 QUEUE_RX_PKTS = 0, 3777 QUEUE_RX_BYTES = 2, 3778 QUEUE_RX_ERRORS = 4, 3779 QUEUE_RX_DROPS = 6, 3780 QUEUE_RX_BUFFER_ERRORS = 8, 3781 QUEUE_RX_N_WORDS = 10 3782 }; 3783 3784 /* HW LRO structures */ 3785 struct mbx_nic_query_lro_capabilities { 3786 struct mbx_hdr hdr; 3787 union { 3788 struct { 3789 uint32_t rsvd[6]; 3790 } req; 3791 struct { 3792 #ifdef _BIG_ENDIAN 3793 uint32_t lro_flags; 3794 uint16_t lro_rq_cnt; 3795 uint16_t plro_max_offload; 3796 uint32_t rsvd[4]; 3797 #else 3798 uint32_t lro_flags; 3799 uint16_t plro_max_offload; 3800 uint16_t lro_rq_cnt; 3801 uint32_t rsvd[4]; 3802 #endif 3803 } rsp; 3804 } params; 3805 }; 3806 3807 struct mbx_nic_set_iface_lro_config { 3808 struct mbx_hdr hdr; 3809 union { 3810 struct { 3811 #ifdef _BIG_ENDIAN 3812 uint32_t lro_flags; 3813 uint32_t iface_id; 3814 uint32_t max_clsc_byte_cnt; 3815 uint32_t max_clsc_seg_cnt; 3816 uint32_t max_clsc_usec_delay; 3817 uint32_t min_clsc_frame_byte_cnt; 3818 uint32_t rsvd[2]; 3819 #else 3820 uint32_t lro_flags; 3821 uint32_t iface_id; 3822 uint32_t max_clsc_byte_cnt; 3823 uint32_t max_clsc_seg_cnt; 3824 uint32_t max_clsc_usec_delay; 3825 uint32_t min_clsc_frame_byte_cnt; 3826 uint32_t rsvd[2]; 3827 #endif 3828 } req; 3829 struct { 3830 #ifdef _BIG_ENDIAN 3831 uint32_t lro_flags; 3832 uint32_t rsvd[7]; 3833 #else 3834 uint32_t lro_flags; 3835 uint32_t rsvd[7]; 3836 #endif 3837 } rsp; 3838 } params; 3839 }; 3840 3841 struct mbx_create_nic_rq_v2 { 3842 struct mbx_hdr hdr; 3843 union { 3844 struct { 3845 #ifdef _BIG_ENDIAN 3846 uint8_t num_pages; 3847 uint8_t frag_size; 3848 uint16_t cq_id; 3849 3850 uint32_t if_id; 3851 3852 uint16_t page_size; 3853 uint16_t max_frame_size; 3854 3855 uint16_t rsvd; 3856 uint16_t pd_id; 3857 3858 uint16_t rsvd1; 3859 uint16_t rq_flags; 3860 3861 uint16_t hds_fixed_offset; 3862 uint8_t hds_start; 3863 uint8_t hds_frag; 3864 3865 uint16_t hds_backfill_size; 3866 uint16_t hds_frag_size; 3867 3868 uint32_t rbq_id; 3869 3870 uint32_t rsvd2[8]; 3871 3872 struct phys_addr pages[2]; 3873 #else 3874 uint16_t cq_id; 3875 uint8_t frag_size; 3876 uint8_t num_pages; 3877 3878 uint32_t if_id; 3879 3880 uint16_t max_frame_size; 3881 uint16_t page_size; 3882 3883 uint16_t pd_id; 3884 uint16_t rsvd; 3885 3886 uint16_t rq_flags; 3887 uint16_t rsvd1; 3888 3889 uint8_t hds_frag; 3890 uint8_t hds_start; 3891 uint16_t hds_fixed_offset; 3892 3893 uint16_t hds_frag_size; 3894 uint16_t hds_backfill_size; 3895 3896 uint32_t rbq_id; 3897 3898 uint32_t rsvd2[8]; 3899 3900 struct phys_addr pages[2]; 3901 #endif 3902 } req; 3903 struct { 3904 #ifdef _BIG_ENDIAN 3905 uint8_t rsvd0; 3906 uint8_t rss_cpuid; 3907 uint16_t rq_id; 3908 3909 uint8_t db_format; 3910 uint8_t db_reg_set; 3911 uint16_t rsvd1; 3912 3913 uint32_t db_offset; 3914 3915 uint32_t rsvd2; 3916 3917 uint16_t rsvd3; 3918 uint16_t rq_flags; 3919 3920 #else 3921 uint16_t rq_id; 3922 uint8_t rss_cpuid; 3923 uint8_t rsvd0; 3924 3925 uint16_t rsvd1; 3926 uint8_t db_reg_set; 3927 uint8_t db_format; 3928 3929 uint32_t db_offset; 3930 3931 uint32_t rsvd2; 3932 3933 uint16_t rq_flags; 3934 uint16_t rsvd3; 3935 #endif 3936 } rsp; 3937 3938 } params; 3939 }; 3940 3941 struct mbx_delete_nic_rq_v1 { 3942 struct mbx_hdr hdr; 3943 union { 3944 struct { 3945 #ifdef _BIG_ENDIAN 3946 uint16_t bypass_flush; 3947 uint16_t rq_id; 3948 uint16_t rsvd; 3949 uint16_t rq_flags; 3950 #else 3951 uint16_t rq_id; 3952 uint16_t bypass_flush; 3953 uint16_t rq_flags; 3954 uint16_t rsvd; 3955 #endif 3956 } req; 3957 struct { 3958 uint32_t rsvd[2]; 3959 } rsp; 3960 } params; 3961 }; 3962 3963 struct nic_hwlro_singleton_cqe { 3964 #ifdef _BIG_ENDIAN 3965 /* dw 0 */ 3966 uint32_t ip_opt:1; 3967 uint32_t vtp:1; 3968 uint32_t pkt_size:14; 3969 uint32_t vlan_tag:16; 3970 3971 /* dw 1 */ 3972 uint32_t num_frags:3; 3973 uint32_t rsvd1:3; 3974 uint32_t frag_index:10; 3975 uint32_t rsvd:8; 3976 uint32_t ipv6_frame:1; 3977 uint32_t l4_cksum_pass:1; 3978 uint32_t ip_cksum_pass:1; 3979 uint32_t udpframe:1; 3980 uint32_t tcpframe:1; 3981 uint32_t ipframe:1; 3982 uint32_t rss_hp:1; 3983 uint32_t error:1; 3984 3985 /* dw 2 */ 3986 uint32_t valid:1; 3987 uint32_t cqe_type:2; 3988 uint32_t debug:7; 3989 uint32_t rsvd4:6; 3990 uint32_t data_offset:8; 3991 uint32_t rsvd3:3; 3992 uint32_t rss_bank:1; 3993 uint32_t qnq:1; 3994 uint32_t rsvd2:3; 3995 3996 /* dw 3 */ 3997 uint32_t rss_hash_value; 3998 #else 3999 /* dw 0 */ 4000 uint32_t vlan_tag:16; 4001 uint32_t pkt_size:14; 4002 uint32_t vtp:1; 4003 uint32_t ip_opt:1; 4004 4005 /* dw 1 */ 4006 uint32_t error:1; 4007 uint32_t rss_hp:1; 4008 uint32_t ipframe:1; 4009 uint32_t tcpframe:1; 4010 uint32_t udpframe:1; 4011 uint32_t ip_cksum_pass:1; 4012 uint32_t l4_cksum_pass:1; 4013 uint32_t ipv6_frame:1; 4014 uint32_t rsvd:8; 4015 uint32_t frag_index:10; 4016 uint32_t rsvd1:3; 4017 uint32_t num_frags:3; 4018 4019 /* dw 2 */ 4020 uint32_t rsvd2:3; 4021 uint32_t qnq:1; 4022 uint32_t rss_bank:1; 4023 uint32_t rsvd3:3; 4024 uint32_t data_offset:8; 4025 uint32_t rsvd4:6; 4026 uint32_t debug:7; 4027 uint32_t cqe_type:2; 4028 uint32_t valid:1; 4029 4030 /* dw 3 */ 4031 uint32_t rss_hash_value; 4032 #endif 4033 }; 4034 4035 struct nic_hwlro_cqe_part1 { 4036 #ifdef _BIG_ENDIAN 4037 /* dw 0 */ 4038 uint32_t tcp_timestamp_val; 4039 4040 /* dw 1 */ 4041 uint32_t tcp_timestamp_ecr; 4042 4043 /* dw 2 */ 4044 uint32_t valid:1; 4045 uint32_t cqe_type:2; 4046 uint32_t rsvd3:7; 4047 uint32_t rss_policy:4; 4048 uint32_t rsvd2:2; 4049 uint32_t data_offset:8; 4050 uint32_t rsvd1:1; 4051 uint32_t lro_desc:1; 4052 uint32_t lro_timer_pop:1; 4053 uint32_t rss_bank:1; 4054 uint32_t qnq:1; 4055 uint32_t rsvd:2; 4056 uint32_t rss_flush:1; 4057 4058 /* dw 3 */ 4059 uint32_t rss_hash_value; 4060 #else 4061 /* dw 0 */ 4062 uint32_t tcp_timestamp_val; 4063 4064 /* dw 1 */ 4065 uint32_t tcp_timestamp_ecr; 4066 4067 /* dw 2 */ 4068 uint32_t rss_flush:1; 4069 uint32_t rsvd:2; 4070 uint32_t qnq:1; 4071 uint32_t rss_bank:1; 4072 uint32_t lro_timer_pop:1; 4073 uint32_t lro_desc:1; 4074 uint32_t rsvd1:1; 4075 uint32_t data_offset:8; 4076 uint32_t rsvd2:2; 4077 uint32_t rss_policy:4; 4078 uint32_t rsvd3:7; 4079 uint32_t cqe_type:2; 4080 uint32_t valid:1; 4081 4082 /* dw 3 */ 4083 uint32_t rss_hash_value; 4084 #endif 4085 }; 4086 4087 struct nic_hwlro_cqe_part2 { 4088 #ifdef _BIG_ENDIAN 4089 /* dw 0 */ 4090 uint32_t ip_opt:1; 4091 uint32_t vtp:1; 4092 uint32_t pkt_size:14; 4093 uint32_t vlan_tag:16; 4094 4095 /* dw 1 */ 4096 uint32_t tcp_window:16; 4097 uint32_t coalesced_size:16; 4098 4099 /* dw 2 */ 4100 uint32_t valid:1; 4101 uint32_t cqe_type:2; 4102 uint32_t rsvd:2; 4103 uint32_t push:1; 4104 uint32_t ts_opt:1; 4105 uint32_t threshold:1; 4106 uint32_t seg_cnt:8; 4107 uint32_t frame_lifespan:8; 4108 uint32_t ipv6_frame:1; 4109 uint32_t l4_cksum_pass:1; 4110 uint32_t ip_cksum_pass:1; 4111 uint32_t udpframe:1; 4112 uint32_t tcpframe:1; 4113 uint32_t ipframe:1; 4114 uint32_t rss_hp:1; 4115 uint32_t error:1; 4116 4117 /* dw 3 */ 4118 uint32_t tcp_ack_num; 4119 #else 4120 /* dw 0 */ 4121 uint32_t vlan_tag:16; 4122 uint32_t pkt_size:14; 4123 uint32_t vtp:1; 4124 uint32_t ip_opt:1; 4125 4126 /* dw 1 */ 4127 uint32_t coalesced_size:16; 4128 uint32_t tcp_window:16; 4129 4130 /* dw 2 */ 4131 uint32_t error:1; 4132 uint32_t rss_hp:1; 4133 uint32_t ipframe:1; 4134 uint32_t tcpframe:1; 4135 uint32_t udpframe:1; 4136 uint32_t ip_cksum_pass:1; 4137 uint32_t l4_cksum_pass:1; 4138 uint32_t ipv6_frame:1; 4139 uint32_t frame_lifespan:8; 4140 uint32_t seg_cnt:8; 4141 uint32_t threshold:1; 4142 uint32_t ts_opt:1; 4143 uint32_t push:1; 4144 uint32_t rsvd:2; 4145 uint32_t cqe_type:2; 4146 uint32_t valid:1; 4147 4148 /* dw 3 */ 4149 uint32_t tcp_ack_num; 4150 #endif 4151 }; 4152