1 /*- 2 * Copyright (c) 2016 Netflix, Inc 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/ioccom.h> 36 #include <sys/malloc.h> 37 #include <sys/proc.h> 38 #include <sys/smp.h> 39 40 #include <cam/cam.h> 41 #include <cam/cam_ccb.h> 42 #include <cam/cam_sim.h> 43 #include <cam/cam_xpt_sim.h> 44 #include <cam/cam_xpt_internal.h> // Yes, this is wrong. 45 #include <cam/cam_debug.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include "nvme_private.h" 51 52 #define ccb_accb_ptr spriv_ptr0 53 #define ccb_ctrlr_ptr spriv_ptr1 54 static void nvme_sim_action(struct cam_sim *sim, union ccb *ccb); 55 static void nvme_sim_poll(struct cam_sim *sim); 56 57 #define sim2softc(sim) ((struct nvme_sim_softc *)cam_sim_softc(sim)) 58 #define sim2ns(sim) (sim2softc(sim)->s_ns) 59 #define sim2ctrlr(sim) (sim2softc(sim)->s_ctrlr) 60 61 struct nvme_sim_softc 62 { 63 struct nvme_controller *s_ctrlr; 64 struct nvme_namespace *s_ns; 65 struct cam_sim *s_sim; 66 struct cam_path *s_path; 67 }; 68 69 static void 70 nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl) 71 { 72 union ccb *ccb = (union ccb *)ccb_arg; 73 74 /* 75 * Let the periph know the completion, and let it sort out what 76 * it means. Make our best guess, though for the status code. 77 */ 78 memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl)); 79 if (nvme_completion_is_error(cpl)) { 80 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 81 xpt_done(ccb); 82 } else { 83 ccb->ccb_h.status = CAM_REQ_CMP; 84 xpt_done_direct(ccb); 85 } 86 } 87 88 static void 89 nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb) 90 { 91 struct ccb_nvmeio *nvmeio = &ccb->nvmeio; 92 struct nvme_request *req; 93 void *payload; 94 uint32_t size; 95 struct nvme_controller *ctrlr; 96 97 ctrlr = sim2ctrlr(sim); 98 payload = nvmeio->data_ptr; 99 size = nvmeio->dxfer_len; 100 /* SG LIST ??? */ 101 if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) 102 req = nvme_allocate_request_bio((struct bio *)payload, 103 nvme_sim_nvmeio_done, ccb); 104 else if ((nvmeio->ccb_h.flags & CAM_DATA_SG) == CAM_DATA_SG) 105 req = nvme_allocate_request_ccb(ccb, nvme_sim_nvmeio_done, ccb); 106 else if (payload == NULL) 107 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb); 108 else 109 req = nvme_allocate_request_vaddr(payload, size, 110 nvme_sim_nvmeio_done, ccb); 111 112 if (req == NULL) { 113 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL; 114 xpt_done(ccb); 115 return; 116 } 117 118 memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd)); 119 120 if (ccb->ccb_h.func_code == XPT_NVME_IO) 121 nvme_ctrlr_submit_io_request(ctrlr, req); 122 else 123 nvme_ctrlr_submit_admin_request(ctrlr, req); 124 125 ccb->ccb_h.status |= CAM_SIM_QUEUED; 126 } 127 128 static uint32_t 129 nvme_link_kBps(struct nvme_controller *ctrlr) 130 { 131 uint32_t speed, lanes, link[] = { 1, 250000, 500000, 985000, 1970000 }; 132 133 speed = pcie_link_status(ctrlr->dev) & PCIEM_LINK_STA_SPEED; 134 lanes = (pcie_link_status(ctrlr->dev) & PCIEM_LINK_STA_WIDTH) >> 4; 135 /* 136 * Failsafe on link speed indicator. If it is insane report the number of 137 * lanes as the speed. Not 100% accurate, but may be diagnostic. 138 */ 139 if (speed >= nitems(link)) 140 speed = 0; 141 return link[speed] * lanes; 142 } 143 144 static void 145 nvme_sim_action(struct cam_sim *sim, union ccb *ccb) 146 { 147 struct nvme_controller *ctrlr; 148 struct nvme_namespace *ns; 149 150 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 151 ("nvme_sim_action: func= %#x\n", 152 ccb->ccb_h.func_code)); 153 154 /* 155 * XXX when we support multiple namespaces in the base driver we'll need 156 * to revisit how all this gets stored and saved in the periph driver's 157 * reserved areas. Right now we store all three in the softc of the sim. 158 */ 159 ns = sim2ns(sim); 160 ctrlr = sim2ctrlr(sim); 161 162 mtx_assert(&ctrlr->lock, MA_OWNED); 163 164 switch (ccb->ccb_h.func_code) { 165 case XPT_CALC_GEOMETRY: /* Calculate Geometry Totally nuts ? XXX */ 166 /* 167 * Only meaningful for old-school SCSI disks since only the SCSI 168 * da driver generates them. Reject all these that slip through. 169 */ 170 /*FALLTHROUGH*/ 171 case XPT_ABORT: /* Abort the specified CCB */ 172 ccb->ccb_h.status = CAM_REQ_INVALID; 173 break; 174 case XPT_SET_TRAN_SETTINGS: 175 /* 176 * NVMe doesn't really have different transfer settings, but 177 * other parts of CAM think failure here is a big deal. 178 */ 179 ccb->ccb_h.status = CAM_REQ_CMP; 180 break; 181 case XPT_PATH_INQ: /* Path routing inquiry */ 182 { 183 struct ccb_pathinq *cpi = &ccb->cpi; 184 185 /* 186 * NVMe may have multiple LUNs on the same path. Current generation 187 * of NVMe devives support only a single name space. Multiple name 188 * space drives are coming, but it's unclear how we should report 189 * them up the stack. 190 */ 191 cpi->version_num = 1; 192 cpi->hba_inquiry = 0; 193 cpi->target_sprt = 0; 194 cpi->hba_misc = PIM_UNMAPPED /* | PIM_NOSCAN */; 195 cpi->hba_eng_cnt = 0; 196 cpi->max_target = 0; 197 cpi->max_lun = ctrlr->cdata.nn; 198 cpi->maxio = nvme_ns_get_max_io_xfer_size(ns); 199 cpi->initiator_id = 0; 200 cpi->bus_id = cam_sim_bus(sim); 201 cpi->base_transfer_speed = nvme_link_kBps(ctrlr); 202 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 203 strlcpy(cpi->hba_vid, "NVMe", HBA_IDLEN); 204 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 205 cpi->unit_number = cam_sim_unit(sim); 206 cpi->transport = XPORT_NVME; /* XXX XPORT_PCIE ? */ 207 cpi->transport_version = nvme_mmio_read_4(ctrlr, vs); 208 cpi->protocol = PROTO_NVME; 209 cpi->protocol_version = nvme_mmio_read_4(ctrlr, vs); 210 cpi->xport_specific.nvme.nsid = ns->id; 211 cpi->ccb_h.status = CAM_REQ_CMP; 212 break; 213 } 214 case XPT_GET_TRAN_SETTINGS: /* Get transport settings */ 215 { 216 struct ccb_trans_settings *cts; 217 struct ccb_trans_settings_nvme *nvmep; 218 struct ccb_trans_settings_nvme *nvmex; 219 device_t dev; 220 221 dev = ctrlr->dev; 222 cts = &ccb->cts; 223 nvmex = &cts->xport_specific.nvme; 224 nvmep = &cts->proto_specific.nvme; 225 226 nvmex->valid = CTS_NVME_VALID_SPEC | CTS_NVME_VALID_LINK; 227 nvmex->spec = nvme_mmio_read_4(ctrlr, vs); 228 nvmex->speed = pcie_link_status(dev) & PCIEM_LINK_STA_SPEED; 229 nvmex->lanes = (pcie_link_status(dev) & PCIEM_LINK_STA_WIDTH) >> 4; 230 nvmex->max_speed = pcie_link_caps(dev) & PCIEM_LINK_CAP_MAX_SPEED; 231 nvmex->max_lanes = (pcie_link_caps(dev) & PCIEM_LINK_CAP_MAX_WIDTH) >> 4; 232 233 /* XXX these should be something else maybe ? */ 234 nvmep->valid = 1; 235 nvmep->spec = nvmex->spec; 236 237 cts->transport = XPORT_NVME; 238 cts->protocol = PROTO_NVME; 239 cts->ccb_h.status = CAM_REQ_CMP; 240 break; 241 } 242 case XPT_TERM_IO: /* Terminate the I/O process */ 243 /* 244 * every driver handles this, but nothing generates it. Assume 245 * it's OK to just say 'that worked'. 246 */ 247 /*FALLTHROUGH*/ 248 case XPT_RESET_DEV: /* Bus Device Reset the specified device */ 249 case XPT_RESET_BUS: /* Reset the specified bus */ 250 /* 251 * NVMe doesn't really support physically resetting the bus. It's part 252 * of the bus scanning dance, so return sucess to tell the process to 253 * proceed. 254 */ 255 ccb->ccb_h.status = CAM_REQ_CMP; 256 break; 257 case XPT_NVME_IO: /* Execute the requested I/O operation */ 258 case XPT_NVME_ADMIN: /* or Admin operation */ 259 nvme_sim_nvmeio(sim, ccb); 260 return; /* no done */ 261 default: 262 ccb->ccb_h.status = CAM_REQ_INVALID; 263 break; 264 } 265 xpt_done(ccb); 266 } 267 268 static void 269 nvme_sim_poll(struct cam_sim *sim) 270 { 271 272 nvme_ctrlr_poll(sim2ctrlr(sim)); 273 } 274 275 static void * 276 nvme_sim_new_controller(struct nvme_controller *ctrlr) 277 { 278 struct cam_devq *devq; 279 int max_trans; 280 int unit; 281 struct nvme_sim_softc *sc = NULL; 282 283 max_trans = ctrlr->max_hw_pend_io; 284 unit = device_get_unit(ctrlr->dev); 285 devq = cam_simq_alloc(max_trans); 286 if (devq == NULL) 287 return NULL; 288 289 sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK); 290 291 sc->s_ctrlr = ctrlr; 292 293 sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll, 294 "nvme", sc, unit, &ctrlr->lock, max_trans, max_trans, devq); 295 if (sc->s_sim == NULL) { 296 printf("Failed to allocate a sim\n"); 297 cam_simq_free(devq); 298 free(sc, M_NVME); 299 return NULL; 300 } 301 302 return sc; 303 } 304 305 static void 306 nvme_sim_rescan_target(struct nvme_controller *ctrlr, struct cam_path *path) 307 { 308 union ccb *ccb; 309 310 ccb = xpt_alloc_ccb_nowait(); 311 if (ccb == NULL) { 312 printf("unable to alloc CCB for rescan\n"); 313 return; 314 } 315 316 if (xpt_clone_path(&ccb->ccb_h.path, path) != CAM_REQ_CMP) { 317 printf("unable to copy path for rescan\n"); 318 xpt_free_ccb(ccb); 319 return; 320 } 321 322 xpt_rescan(ccb); 323 } 324 325 static void * 326 nvme_sim_new_ns(struct nvme_namespace *ns, void *sc_arg) 327 { 328 struct nvme_sim_softc *sc = sc_arg; 329 struct nvme_controller *ctrlr = sc->s_ctrlr; 330 int i; 331 332 sc->s_ns = ns; 333 334 /* 335 * XXX this is creating one bus per ns, but it should be one 336 * XXX target per controller, and one LUN per namespace. 337 * XXX Current drives only support one NS, so there's time 338 * XXX to fix it later when new drives arrive. 339 * 340 * XXX I'm pretty sure the xpt_bus_register() call below is 341 * XXX like super lame and it really belongs in the sim_new_ctrlr 342 * XXX callback. Then the create_path below would be pretty close 343 * XXX to being right. Except we should be per-ns not per-ctrlr 344 * XXX data. 345 */ 346 347 mtx_lock(&ctrlr->lock); 348 /* Create bus */ 349 350 /* 351 * XXX do I need to lock ctrlr->lock ? 352 * XXX do I need to lock the path? 353 * ata and scsi seem to in their code, but their discovery is 354 * somewhat more asynchronous. We're only every called one at a 355 * time, and nothing is in parallel. 356 */ 357 358 i = 0; 359 if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS) 360 goto error; 361 i++; 362 if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim), 363 1, ns->id) != CAM_REQ_CMP) 364 goto error; 365 i++; 366 367 sc->s_path->device->nvme_data = nvme_ns_get_data(ns); 368 sc->s_path->device->nvme_cdata = nvme_ctrlr_get_data(ns->ctrlr); 369 370 /* Scan bus */ 371 nvme_sim_rescan_target(ctrlr, sc->s_path); 372 373 mtx_unlock(&ctrlr->lock); 374 375 return ns; 376 377 error: 378 switch (i) { 379 case 2: 380 xpt_free_path(sc->s_path); 381 case 1: 382 xpt_bus_deregister(cam_sim_path(sc->s_sim)); 383 case 0: 384 cam_sim_free(sc->s_sim, /*free_devq*/TRUE); 385 } 386 mtx_unlock(&ctrlr->lock); 387 return NULL; 388 } 389 390 static void 391 nvme_sim_controller_fail(void *ctrlr_arg) 392 { 393 /* XXX cleanup XXX */ 394 } 395 396 struct nvme_consumer *consumer_cookie; 397 398 static void 399 nvme_sim_init(void) 400 { 401 if (nvme_use_nvd) 402 return; 403 404 consumer_cookie = nvme_register_consumer(nvme_sim_new_ns, 405 nvme_sim_new_controller, NULL, nvme_sim_controller_fail); 406 } 407 408 SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY, 409 nvme_sim_init, NULL); 410 411 static void 412 nvme_sim_uninit(void) 413 { 414 if (nvme_use_nvd) 415 return; 416 /* XXX Cleanup */ 417 418 nvme_unregister_consumer(consumer_cookie); 419 } 420 421 SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY, 422 nvme_sim_uninit, NULL); 423