1 /*- 2 * Copyright (c) 2016 Netflix, Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer, 9 * without modification, immediately at the beginning of the file. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/buf.h> 30 #include <sys/bus.h> 31 #include <sys/conf.h> 32 #include <sys/ioccom.h> 33 #include <sys/malloc.h> 34 #include <sys/proc.h> 35 #include <sys/smp.h> 36 37 #include <cam/cam.h> 38 #include <cam/cam_ccb.h> 39 #include <cam/cam_sim.h> 40 #include <cam/cam_xpt_sim.h> 41 #include <cam/cam_debug.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcireg.h> 45 46 #include "nvme_private.h" 47 48 #define ccb_accb_ptr spriv_ptr0 49 #define ccb_ctrlr_ptr spriv_ptr1 50 static void nvme_sim_action(struct cam_sim *sim, union ccb *ccb); 51 static void nvme_sim_poll(struct cam_sim *sim); 52 53 #define sim2softc(sim) ((struct nvme_sim_softc *)cam_sim_softc(sim)) 54 #define sim2ctrlr(sim) (sim2softc(sim)->s_ctrlr) 55 56 struct nvme_sim_softc 57 { 58 struct nvme_controller *s_ctrlr; 59 struct cam_sim *s_sim; 60 struct cam_path *s_path; 61 }; 62 63 static void 64 nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl) 65 { 66 union ccb *ccb = (union ccb *)ccb_arg; 67 68 /* 69 * Let the periph know the completion, and let it sort out what 70 * it means. Report an error or success based on SC and SCT. 71 * We do not try to fetch additional data from the error log, 72 * though maybe we should in the future. 73 */ 74 memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl)); 75 ccb->ccb_h.status &= ~CAM_SIM_QUEUED; 76 if (nvme_completion_is_error(cpl)) { 77 ccb->ccb_h.status = CAM_NVME_STATUS_ERROR; 78 xpt_done(ccb); 79 } else { 80 ccb->ccb_h.status = CAM_REQ_CMP; 81 xpt_done_direct(ccb); 82 } 83 } 84 85 static void 86 nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb) 87 { 88 struct ccb_nvmeio *nvmeio = &ccb->nvmeio; 89 struct nvme_request *req; 90 void *payload; 91 uint32_t size; 92 struct nvme_controller *ctrlr; 93 94 ctrlr = sim2ctrlr(sim); 95 payload = nvmeio->data_ptr; 96 size = nvmeio->dxfer_len; 97 /* SG LIST ??? */ 98 if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) 99 req = nvme_allocate_request_bio((struct bio *)payload, 100 nvme_sim_nvmeio_done, ccb); 101 else if ((nvmeio->ccb_h.flags & CAM_DATA_SG) == CAM_DATA_SG) 102 req = nvme_allocate_request_ccb(ccb, nvme_sim_nvmeio_done, ccb); 103 else if (payload == NULL) 104 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb); 105 else 106 req = nvme_allocate_request_vaddr(payload, size, 107 nvme_sim_nvmeio_done, ccb); 108 109 if (req == NULL) { 110 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL; 111 xpt_done(ccb); 112 return; 113 } 114 ccb->ccb_h.status |= CAM_SIM_QUEUED; 115 116 memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd)); 117 118 if (ccb->ccb_h.func_code == XPT_NVME_IO) 119 nvme_ctrlr_submit_io_request(ctrlr, req); 120 else 121 nvme_ctrlr_submit_admin_request(ctrlr, req); 122 } 123 124 static uint32_t 125 nvme_link_kBps(struct nvme_controller *ctrlr) 126 { 127 uint32_t speed, lanes, link[] = { 1, 250000, 500000, 985000, 1970000 }; 128 uint32_t status; 129 130 status = pcie_read_config(ctrlr->dev, PCIER_LINK_STA, 2); 131 speed = status & PCIEM_LINK_STA_SPEED; 132 lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4; 133 /* 134 * Failsafe on link speed indicator. If it is insane report the number of 135 * lanes as the speed. Not 100% accurate, but may be diagnostic. 136 */ 137 if (speed >= nitems(link)) 138 speed = 0; 139 return link[speed] * lanes; 140 } 141 142 static void 143 nvme_sim_action(struct cam_sim *sim, union ccb *ccb) 144 { 145 struct nvme_controller *ctrlr; 146 147 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 148 ("nvme_sim_action: func= %#x\n", 149 ccb->ccb_h.func_code)); 150 151 ctrlr = sim2ctrlr(sim); 152 153 switch (ccb->ccb_h.func_code) { 154 case XPT_CALC_GEOMETRY: /* Calculate Geometry Totally nuts ? XXX */ 155 /* 156 * Only meaningful for old-school SCSI disks since only the SCSI 157 * da driver generates them. Reject all these that slip through. 158 */ 159 /*FALLTHROUGH*/ 160 case XPT_ABORT: /* Abort the specified CCB */ 161 ccb->ccb_h.status = CAM_REQ_INVALID; 162 break; 163 case XPT_SET_TRAN_SETTINGS: 164 /* 165 * NVMe doesn't really have different transfer settings, but 166 * other parts of CAM think failure here is a big deal. 167 */ 168 ccb->ccb_h.status = CAM_REQ_CMP; 169 break; 170 case XPT_PATH_INQ: /* Path routing inquiry */ 171 { 172 struct ccb_pathinq *cpi = &ccb->cpi; 173 device_t dev = ctrlr->dev; 174 175 /* 176 * For devices that are reported as children of the AHCI 177 * controller, which has no access to the config space for this 178 * controller, report the AHCI controller's data. 179 */ 180 if (ctrlr->quirks & QUIRK_AHCI) 181 dev = device_get_parent(dev); 182 cpi->version_num = 1; 183 cpi->hba_inquiry = 0; 184 cpi->target_sprt = 0; 185 cpi->hba_misc = PIM_UNMAPPED | PIM_NOSCAN; 186 cpi->hba_eng_cnt = 0; 187 cpi->max_target = 0; 188 cpi->max_lun = ctrlr->cdata.nn; 189 cpi->maxio = ctrlr->max_xfer_size; 190 cpi->initiator_id = 0; 191 cpi->bus_id = cam_sim_bus(sim); 192 cpi->base_transfer_speed = nvme_link_kBps(ctrlr); 193 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 194 strlcpy(cpi->hba_vid, "NVMe", HBA_IDLEN); 195 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 196 cpi->unit_number = cam_sim_unit(sim); 197 cpi->transport = XPORT_NVME; /* XXX XPORT_PCIE ? */ 198 cpi->transport_version = nvme_mmio_read_4(ctrlr, vs); 199 cpi->protocol = PROTO_NVME; 200 cpi->protocol_version = nvme_mmio_read_4(ctrlr, vs); 201 cpi->xport_specific.nvme.nsid = xpt_path_lun_id(ccb->ccb_h.path); 202 cpi->xport_specific.nvme.domain = pci_get_domain(dev); 203 cpi->xport_specific.nvme.bus = pci_get_bus(dev); 204 cpi->xport_specific.nvme.slot = pci_get_slot(dev); 205 cpi->xport_specific.nvme.function = pci_get_function(dev); 206 cpi->xport_specific.nvme.extra = 0; 207 strncpy(cpi->xport_specific.nvme.dev_name, device_get_nameunit(dev), 208 sizeof(cpi->xport_specific.nvme.dev_name)); 209 cpi->hba_vendor = pci_get_vendor(dev); 210 cpi->hba_device = pci_get_device(dev); 211 cpi->hba_subvendor = pci_get_subvendor(dev); 212 cpi->hba_subdevice = pci_get_subdevice(dev); 213 cpi->ccb_h.status = CAM_REQ_CMP; 214 break; 215 } 216 case XPT_GET_TRAN_SETTINGS: /* Get transport settings */ 217 { 218 struct ccb_trans_settings *cts; 219 struct ccb_trans_settings_nvme *nvmep; 220 struct ccb_trans_settings_nvme *nvmex; 221 device_t dev; 222 uint32_t status, caps, flags; 223 224 dev = ctrlr->dev; 225 cts = &ccb->cts; 226 nvmex = &cts->xport_specific.nvme; 227 nvmep = &cts->proto_specific.nvme; 228 229 nvmex->spec = nvme_mmio_read_4(ctrlr, vs); 230 nvmex->valid = CTS_NVME_VALID_SPEC; 231 if ((ctrlr->quirks & QUIRK_AHCI) == 0) { 232 /* AHCI redirect makes it impossible to query */ 233 status = pcie_read_config(dev, PCIER_LINK_STA, 2); 234 caps = pcie_read_config(dev, PCIER_LINK_CAP, 2); 235 flags = pcie_read_config(dev, PCIER_FLAGS, 2); 236 if ((flags & PCIEM_FLAGS_TYPE) == PCIEM_TYPE_ENDPOINT) { 237 nvmex->valid |= CTS_NVME_VALID_LINK; 238 nvmex->speed = status & PCIEM_LINK_STA_SPEED; 239 nvmex->lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4; 240 nvmex->max_speed = caps & PCIEM_LINK_CAP_MAX_SPEED; 241 nvmex->max_lanes = (caps & PCIEM_LINK_CAP_MAX_WIDTH) >> 4; 242 } 243 } 244 245 /* XXX these should be something else maybe ? */ 246 nvmep->valid = CTS_NVME_VALID_SPEC; 247 nvmep->spec = nvmex->spec; 248 249 cts->transport = XPORT_NVME; 250 cts->transport_version = nvmex->spec; 251 cts->protocol = PROTO_NVME; 252 cts->protocol_version = nvmex->spec; 253 cts->ccb_h.status = CAM_REQ_CMP; 254 break; 255 } 256 case XPT_TERM_IO: /* Terminate the I/O process */ 257 /* 258 * every driver handles this, but nothing generates it. Assume 259 * it's OK to just say 'that worked'. 260 */ 261 /*FALLTHROUGH*/ 262 case XPT_RESET_DEV: /* Bus Device Reset the specified device */ 263 case XPT_RESET_BUS: /* Reset the specified bus */ 264 /* 265 * NVMe doesn't really support physically resetting the bus. It's part 266 * of the bus scanning dance, so return sucess to tell the process to 267 * proceed. 268 */ 269 ccb->ccb_h.status = CAM_REQ_CMP; 270 break; 271 case XPT_NVME_IO: /* Execute the requested I/O operation */ 272 case XPT_NVME_ADMIN: /* or Admin operation */ 273 if (ctrlr->is_failed) { 274 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 275 break; 276 } 277 nvme_sim_nvmeio(sim, ccb); 278 return; /* no done */ 279 default: 280 ccb->ccb_h.status = CAM_REQ_INVALID; 281 break; 282 } 283 xpt_done(ccb); 284 } 285 286 static void 287 nvme_sim_poll(struct cam_sim *sim) 288 { 289 290 nvme_ctrlr_poll(sim2ctrlr(sim)); 291 } 292 293 static void * 294 nvme_sim_new_controller(struct nvme_controller *ctrlr) 295 { 296 struct nvme_sim_softc *sc; 297 struct cam_devq *devq; 298 int max_trans; 299 300 max_trans = ctrlr->max_hw_pend_io; 301 devq = cam_simq_alloc(max_trans); 302 if (devq == NULL) 303 return (NULL); 304 305 sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK); 306 sc->s_ctrlr = ctrlr; 307 308 sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll, 309 "nvme", sc, device_get_unit(ctrlr->dev), 310 NULL, max_trans, max_trans, devq); 311 if (sc->s_sim == NULL) { 312 printf("Failed to allocate a sim\n"); 313 cam_simq_free(devq); 314 goto err1; 315 } 316 if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS) { 317 printf("Failed to create a bus\n"); 318 goto err2; 319 } 320 if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim), 321 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 322 printf("Failed to create a path\n"); 323 goto err3; 324 } 325 326 return (sc); 327 328 err3: 329 xpt_bus_deregister(cam_sim_path(sc->s_sim)); 330 err2: 331 cam_sim_free(sc->s_sim, /*free_devq*/TRUE); 332 err1: 333 free(sc, M_NVME); 334 return (NULL); 335 } 336 337 static void * 338 nvme_sim_ns_change(struct nvme_namespace *ns, void *sc_arg) 339 { 340 struct nvme_sim_softc *sc = sc_arg; 341 union ccb *ccb; 342 343 ccb = xpt_alloc_ccb_nowait(); 344 if (ccb == NULL) { 345 printf("unable to alloc CCB for rescan\n"); 346 return (NULL); 347 } 348 349 /* 350 * We map the NVMe namespace idea onto the CAM unit LUN. For 351 * each new namespace, we create a new CAM path for it. We then 352 * rescan the path to get it to enumerate. 353 */ 354 if (xpt_create_path(&ccb->ccb_h.path, /*periph*/NULL, 355 cam_sim_path(sc->s_sim), 0, ns->id) != CAM_REQ_CMP) { 356 printf("unable to create path for rescan\n"); 357 xpt_free_ccb(ccb); 358 return (NULL); 359 } 360 xpt_rescan(ccb); 361 362 return (sc_arg); 363 } 364 365 static void 366 nvme_sim_controller_fail(void *ctrlr_arg) 367 { 368 struct nvme_sim_softc *sc = ctrlr_arg; 369 370 xpt_async(AC_LOST_DEVICE, sc->s_path, NULL); 371 xpt_free_path(sc->s_path); 372 xpt_bus_deregister(cam_sim_path(sc->s_sim)); 373 cam_sim_free(sc->s_sim, /*free_devq*/TRUE); 374 free(sc, M_NVME); 375 } 376 377 struct nvme_consumer *consumer_cookie; 378 379 static void 380 nvme_sim_init(void) 381 { 382 if (nvme_use_nvd) 383 return; 384 385 consumer_cookie = nvme_register_consumer(nvme_sim_ns_change, 386 nvme_sim_new_controller, NULL, nvme_sim_controller_fail); 387 } 388 389 SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY, 390 nvme_sim_init, NULL); 391 392 static void 393 nvme_sim_uninit(void) 394 { 395 if (nvme_use_nvd) 396 return; 397 /* XXX Cleanup */ 398 399 nvme_unregister_consumer(consumer_cookie); 400 } 401 402 SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY, 403 nvme_sim_uninit, NULL); 404