1 /*- 2 * Copyright (c) 2016 Netflix, Inc 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/ioccom.h> 36 #include <sys/malloc.h> 37 #include <sys/proc.h> 38 #include <sys/smp.h> 39 40 #include <cam/cam.h> 41 #include <cam/cam_ccb.h> 42 #include <cam/cam_sim.h> 43 #include <cam/cam_xpt_sim.h> 44 #include <cam/cam_xpt_internal.h> // Yes, this is wrong. 45 #include <cam/cam_debug.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 50 #include "nvme_private.h" 51 52 #define ccb_accb_ptr spriv_ptr0 53 #define ccb_ctrlr_ptr spriv_ptr1 54 static void nvme_sim_action(struct cam_sim *sim, union ccb *ccb); 55 static void nvme_sim_poll(struct cam_sim *sim); 56 57 #define sim2softc(sim) ((struct nvme_sim_softc *)cam_sim_softc(sim)) 58 #define sim2ns(sim) (sim2softc(sim)->s_ns) 59 #define sim2ctrlr(sim) (sim2softc(sim)->s_ctrlr) 60 61 struct nvme_sim_softc 62 { 63 struct nvme_controller *s_ctrlr; 64 struct nvme_namespace *s_ns; 65 struct cam_sim *s_sim; 66 struct cam_path *s_path; 67 }; 68 69 static void 70 nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl) 71 { 72 union ccb *ccb = (union ccb *)ccb_arg; 73 74 /* 75 * Let the periph know the completion, and let it sort out what 76 * it means. Make our best guess, though for the status code. 77 */ 78 memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl)); 79 if (nvme_completion_is_error(cpl)) { 80 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 81 xpt_done(ccb); 82 } else { 83 ccb->ccb_h.status = CAM_REQ_CMP; 84 xpt_done_direct(ccb); 85 } 86 } 87 88 static void 89 nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb) 90 { 91 struct ccb_nvmeio *nvmeio = &ccb->nvmeio; 92 struct nvme_request *req; 93 void *payload; 94 uint32_t size; 95 struct nvme_controller *ctrlr; 96 97 ctrlr = sim2ctrlr(sim); 98 payload = nvmeio->data_ptr; 99 size = nvmeio->dxfer_len; 100 /* SG LIST ??? */ 101 if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) 102 req = nvme_allocate_request_bio((struct bio *)payload, 103 nvme_sim_nvmeio_done, ccb); 104 else if ((nvmeio->ccb_h.flags & CAM_DATA_SG) == CAM_DATA_SG) 105 req = nvme_allocate_request_ccb(ccb, nvme_sim_nvmeio_done, ccb); 106 else if (payload == NULL) 107 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb); 108 else 109 req = nvme_allocate_request_vaddr(payload, size, 110 nvme_sim_nvmeio_done, ccb); 111 112 if (req == NULL) { 113 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL; 114 xpt_done(ccb); 115 return; 116 } 117 118 memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd)); 119 120 if (ccb->ccb_h.func_code == XPT_NVME_IO) 121 nvme_ctrlr_submit_io_request(ctrlr, req); 122 else 123 nvme_ctrlr_submit_admin_request(ctrlr, req); 124 125 ccb->ccb_h.status |= CAM_SIM_QUEUED; 126 } 127 128 static uint32_t 129 nvme_link_kBps(struct nvme_controller *ctrlr) 130 { 131 uint32_t speed, lanes, link[] = { 1, 250000, 500000, 985000, 1970000 }; 132 uint32_t status; 133 134 status = pcie_read_config(ctrlr->dev, PCIER_LINK_STA, 2); 135 speed = status & PCIEM_LINK_STA_SPEED; 136 lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4; 137 /* 138 * Failsafe on link speed indicator. If it is insane report the number of 139 * lanes as the speed. Not 100% accurate, but may be diagnostic. 140 */ 141 if (speed >= nitems(link)) 142 speed = 0; 143 return link[speed] * lanes; 144 } 145 146 static void 147 nvme_sim_action(struct cam_sim *sim, union ccb *ccb) 148 { 149 struct nvme_controller *ctrlr; 150 struct nvme_namespace *ns; 151 152 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 153 ("nvme_sim_action: func= %#x\n", 154 ccb->ccb_h.func_code)); 155 156 /* 157 * XXX when we support multiple namespaces in the base driver we'll need 158 * to revisit how all this gets stored and saved in the periph driver's 159 * reserved areas. Right now we store all three in the softc of the sim. 160 */ 161 ns = sim2ns(sim); 162 ctrlr = sim2ctrlr(sim); 163 164 mtx_assert(&ctrlr->lock, MA_OWNED); 165 166 switch (ccb->ccb_h.func_code) { 167 case XPT_CALC_GEOMETRY: /* Calculate Geometry Totally nuts ? XXX */ 168 /* 169 * Only meaningful for old-school SCSI disks since only the SCSI 170 * da driver generates them. Reject all these that slip through. 171 */ 172 /*FALLTHROUGH*/ 173 case XPT_ABORT: /* Abort the specified CCB */ 174 ccb->ccb_h.status = CAM_REQ_INVALID; 175 break; 176 case XPT_SET_TRAN_SETTINGS: 177 /* 178 * NVMe doesn't really have different transfer settings, but 179 * other parts of CAM think failure here is a big deal. 180 */ 181 ccb->ccb_h.status = CAM_REQ_CMP; 182 break; 183 case XPT_PATH_INQ: /* Path routing inquiry */ 184 { 185 struct ccb_pathinq *cpi = &ccb->cpi; 186 187 /* 188 * NVMe may have multiple LUNs on the same path. Current generation 189 * of NVMe devives support only a single name space. Multiple name 190 * space drives are coming, but it's unclear how we should report 191 * them up the stack. 192 */ 193 cpi->version_num = 1; 194 cpi->hba_inquiry = 0; 195 cpi->target_sprt = 0; 196 cpi->hba_misc = PIM_UNMAPPED /* | PIM_NOSCAN */; 197 cpi->hba_eng_cnt = 0; 198 cpi->max_target = 0; 199 cpi->max_lun = ctrlr->cdata.nn; 200 cpi->maxio = nvme_ns_get_max_io_xfer_size(ns); 201 cpi->initiator_id = 0; 202 cpi->bus_id = cam_sim_bus(sim); 203 cpi->base_transfer_speed = nvme_link_kBps(ctrlr); 204 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 205 strlcpy(cpi->hba_vid, "NVMe", HBA_IDLEN); 206 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 207 cpi->unit_number = cam_sim_unit(sim); 208 cpi->transport = XPORT_NVME; /* XXX XPORT_PCIE ? */ 209 cpi->transport_version = nvme_mmio_read_4(ctrlr, vs); 210 cpi->protocol = PROTO_NVME; 211 cpi->protocol_version = nvme_mmio_read_4(ctrlr, vs); 212 cpi->xport_specific.nvme.nsid = ns->id; 213 cpi->ccb_h.status = CAM_REQ_CMP; 214 break; 215 } 216 case XPT_GET_TRAN_SETTINGS: /* Get transport settings */ 217 { 218 struct ccb_trans_settings *cts; 219 struct ccb_trans_settings_nvme *nvmep; 220 struct ccb_trans_settings_nvme *nvmex; 221 device_t dev; 222 uint32_t status, caps; 223 224 dev = ctrlr->dev; 225 cts = &ccb->cts; 226 nvmex = &cts->xport_specific.nvme; 227 nvmep = &cts->proto_specific.nvme; 228 229 status = pcie_read_config(dev, PCIER_LINK_STA, 2); 230 caps = pcie_read_config(dev, PCIER_LINK_CAP, 2); 231 nvmex->valid = CTS_NVME_VALID_SPEC | CTS_NVME_VALID_LINK; 232 nvmex->spec = nvme_mmio_read_4(ctrlr, vs); 233 nvmex->speed = status & PCIEM_LINK_STA_SPEED; 234 nvmex->lanes = (status & PCIEM_LINK_STA_WIDTH) >> 4; 235 nvmex->max_speed = caps & PCIEM_LINK_CAP_MAX_SPEED; 236 nvmex->max_lanes = (caps & PCIEM_LINK_CAP_MAX_WIDTH) >> 4; 237 238 /* XXX these should be something else maybe ? */ 239 nvmep->valid = 1; 240 nvmep->spec = nvmex->spec; 241 242 cts->transport = XPORT_NVME; 243 cts->protocol = PROTO_NVME; 244 cts->ccb_h.status = CAM_REQ_CMP; 245 break; 246 } 247 case XPT_TERM_IO: /* Terminate the I/O process */ 248 /* 249 * every driver handles this, but nothing generates it. Assume 250 * it's OK to just say 'that worked'. 251 */ 252 /*FALLTHROUGH*/ 253 case XPT_RESET_DEV: /* Bus Device Reset the specified device */ 254 case XPT_RESET_BUS: /* Reset the specified bus */ 255 /* 256 * NVMe doesn't really support physically resetting the bus. It's part 257 * of the bus scanning dance, so return sucess to tell the process to 258 * proceed. 259 */ 260 ccb->ccb_h.status = CAM_REQ_CMP; 261 break; 262 case XPT_NVME_IO: /* Execute the requested I/O operation */ 263 case XPT_NVME_ADMIN: /* or Admin operation */ 264 nvme_sim_nvmeio(sim, ccb); 265 return; /* no done */ 266 default: 267 ccb->ccb_h.status = CAM_REQ_INVALID; 268 break; 269 } 270 xpt_done(ccb); 271 } 272 273 static void 274 nvme_sim_poll(struct cam_sim *sim) 275 { 276 277 nvme_ctrlr_poll(sim2ctrlr(sim)); 278 } 279 280 static void * 281 nvme_sim_new_controller(struct nvme_controller *ctrlr) 282 { 283 struct cam_devq *devq; 284 int max_trans; 285 int unit; 286 struct nvme_sim_softc *sc = NULL; 287 288 max_trans = ctrlr->max_hw_pend_io; 289 unit = device_get_unit(ctrlr->dev); 290 devq = cam_simq_alloc(max_trans); 291 if (devq == NULL) 292 return NULL; 293 294 sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK); 295 296 sc->s_ctrlr = ctrlr; 297 298 sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll, 299 "nvme", sc, unit, &ctrlr->lock, max_trans, max_trans, devq); 300 if (sc->s_sim == NULL) { 301 printf("Failed to allocate a sim\n"); 302 cam_simq_free(devq); 303 free(sc, M_NVME); 304 return NULL; 305 } 306 307 return sc; 308 } 309 310 static void 311 nvme_sim_rescan_target(struct nvme_controller *ctrlr, struct cam_path *path) 312 { 313 union ccb *ccb; 314 315 ccb = xpt_alloc_ccb_nowait(); 316 if (ccb == NULL) { 317 printf("unable to alloc CCB for rescan\n"); 318 return; 319 } 320 321 if (xpt_clone_path(&ccb->ccb_h.path, path) != CAM_REQ_CMP) { 322 printf("unable to copy path for rescan\n"); 323 xpt_free_ccb(ccb); 324 return; 325 } 326 327 xpt_rescan(ccb); 328 } 329 330 static void * 331 nvme_sim_new_ns(struct nvme_namespace *ns, void *sc_arg) 332 { 333 struct nvme_sim_softc *sc = sc_arg; 334 struct nvme_controller *ctrlr = sc->s_ctrlr; 335 int i; 336 337 sc->s_ns = ns; 338 339 /* 340 * XXX this is creating one bus per ns, but it should be one 341 * XXX target per controller, and one LUN per namespace. 342 * XXX Current drives only support one NS, so there's time 343 * XXX to fix it later when new drives arrive. 344 * 345 * XXX I'm pretty sure the xpt_bus_register() call below is 346 * XXX like super lame and it really belongs in the sim_new_ctrlr 347 * XXX callback. Then the create_path below would be pretty close 348 * XXX to being right. Except we should be per-ns not per-ctrlr 349 * XXX data. 350 */ 351 352 mtx_lock(&ctrlr->lock); 353 /* Create bus */ 354 355 /* 356 * XXX do I need to lock ctrlr->lock ? 357 * XXX do I need to lock the path? 358 * ata and scsi seem to in their code, but their discovery is 359 * somewhat more asynchronous. We're only every called one at a 360 * time, and nothing is in parallel. 361 */ 362 363 i = 0; 364 if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS) 365 goto error; 366 i++; 367 if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim), 368 1, ns->id) != CAM_REQ_CMP) 369 goto error; 370 i++; 371 372 sc->s_path->device->nvme_data = nvme_ns_get_data(ns); 373 sc->s_path->device->nvme_cdata = nvme_ctrlr_get_data(ns->ctrlr); 374 375 /* Scan bus */ 376 nvme_sim_rescan_target(ctrlr, sc->s_path); 377 378 mtx_unlock(&ctrlr->lock); 379 380 return ns; 381 382 error: 383 switch (i) { 384 case 2: 385 xpt_free_path(sc->s_path); 386 case 1: 387 xpt_bus_deregister(cam_sim_path(sc->s_sim)); 388 case 0: 389 cam_sim_free(sc->s_sim, /*free_devq*/TRUE); 390 } 391 mtx_unlock(&ctrlr->lock); 392 return NULL; 393 } 394 395 static void 396 nvme_sim_controller_fail(void *ctrlr_arg) 397 { 398 /* XXX cleanup XXX */ 399 } 400 401 struct nvme_consumer *consumer_cookie; 402 403 static void 404 nvme_sim_init(void) 405 { 406 if (nvme_use_nvd) 407 return; 408 409 consumer_cookie = nvme_register_consumer(nvme_sim_new_ns, 410 nvme_sim_new_controller, NULL, nvme_sim_controller_fail); 411 } 412 413 SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY, 414 nvme_sim_init, NULL); 415 416 static void 417 nvme_sim_uninit(void) 418 { 419 if (nvme_use_nvd) 420 return; 421 /* XXX Cleanup */ 422 423 nvme_unregister_consumer(consumer_cookie); 424 } 425 426 SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY, 427 nvme_sim_uninit, NULL); 428