1 /*- 2 * Copyright (c) 2016 Netflix, Inc 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/ioccom.h> 36 #include <sys/malloc.h> 37 #include <sys/proc.h> 38 #include <sys/smp.h> 39 40 #include <cam/cam.h> 41 #include <cam/cam_ccb.h> 42 #include <cam/cam_sim.h> 43 #include <cam/cam_xpt_sim.h> 44 #include <cam/cam_xpt_internal.h> // Yes, this is wrong. 45 #include <cam/cam_debug.h> 46 47 #include "nvme_private.h" 48 49 #define ccb_accb_ptr spriv_ptr0 50 #define ccb_ctrlr_ptr spriv_ptr1 51 static void nvme_sim_action(struct cam_sim *sim, union ccb *ccb); 52 static void nvme_sim_poll(struct cam_sim *sim); 53 54 #define sim2softc(sim) ((struct nvme_sim_softc *)cam_sim_softc(sim)) 55 #define sim2ns(sim) (sim2softc(sim)->s_ns) 56 #define sim2ctrlr(sim) (sim2softc(sim)->s_ctrlr) 57 58 struct nvme_sim_softc 59 { 60 struct nvme_controller *s_ctrlr; 61 struct nvme_namespace *s_ns; 62 struct cam_sim *s_sim; 63 struct cam_path *s_path; 64 }; 65 66 static void 67 nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl) 68 { 69 union ccb *ccb = (union ccb *)ccb_arg; 70 71 /* 72 * Let the periph know the completion, and let it sort out what 73 * it means. Make our best guess, though for the status code. 74 */ 75 memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl)); 76 if (nvme_completion_is_error(cpl)) 77 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 78 else 79 ccb->ccb_h.status = CAM_REQ_CMP; 80 xpt_done(ccb); 81 } 82 83 static void 84 nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb) 85 { 86 struct ccb_nvmeio *nvmeio = &ccb->nvmeio; 87 struct nvme_request *req; 88 void *payload; 89 uint32_t size; 90 struct nvme_controller *ctrlr; 91 92 ctrlr = sim2ctrlr(sim); 93 payload = nvmeio->data_ptr; 94 size = nvmeio->dxfer_len; 95 /* SG LIST ??? */ 96 if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) 97 req = nvme_allocate_request_bio((struct bio *)payload, 98 nvme_sim_nvmeio_done, ccb); 99 else if (payload == NULL) 100 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb); 101 else 102 req = nvme_allocate_request_vaddr(payload, size, 103 nvme_sim_nvmeio_done, ccb); 104 105 if (req == NULL) { 106 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL; 107 xpt_done(ccb); 108 return; 109 } 110 111 memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd)); 112 113 if (ccb->ccb_h.func_code == XPT_NVME_IO) 114 nvme_ctrlr_submit_io_request(ctrlr, req); 115 else 116 nvme_ctrlr_submit_admin_request(ctrlr, req); 117 118 ccb->ccb_h.status |= CAM_SIM_QUEUED; 119 } 120 121 static void 122 nvme_sim_action(struct cam_sim *sim, union ccb *ccb) 123 { 124 struct nvme_controller *ctrlr; 125 struct nvme_namespace *ns; 126 127 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 128 ("nvme_sim_action: func= %#x\n", 129 ccb->ccb_h.func_code)); 130 131 /* 132 * XXX when we support multiple namespaces in the base driver we'll need 133 * to revisit how all this gets stored and saved in the periph driver's 134 * reserved areas. Right now we store all three in the softc of the sim. 135 */ 136 ns = sim2ns(sim); 137 ctrlr = sim2ctrlr(sim); 138 139 mtx_assert(&ctrlr->lock, MA_OWNED); 140 141 switch (ccb->ccb_h.func_code) { 142 case XPT_CALC_GEOMETRY: /* Calculate Geometry Totally nuts ? XXX */ 143 /* 144 * Only meaningful for old-school SCSI disks since only the SCSI 145 * da driver generates them. Reject all these that slip through. 146 */ 147 /*FALLTHROUGH*/ 148 case XPT_ABORT: /* Abort the specified CCB */ 149 ccb->ccb_h.status = CAM_REQ_INVALID; 150 break; 151 case XPT_SET_TRAN_SETTINGS: 152 /* 153 * NVMe doesn't really have different transfer settings, but 154 * other parts of CAM think failure here is a big deal. 155 */ 156 ccb->ccb_h.status = CAM_REQ_CMP; 157 break; 158 case XPT_PATH_INQ: /* Path routing inquiry */ 159 { 160 struct ccb_pathinq *cpi = &ccb->cpi; 161 162 /* 163 * NVMe may have multiple LUNs on the same path. Current generation 164 * of NVMe devives support only a single name space. Multiple name 165 * space drives are coming, but it's unclear how we should report 166 * them up the stack. 167 */ 168 cpi->version_num = 1; 169 cpi->hba_inquiry = 0; 170 cpi->target_sprt = 0; 171 cpi->hba_misc = PIM_UNMAPPED /* | PIM_NOSCAN */; 172 cpi->hba_eng_cnt = 0; 173 cpi->max_target = 0; 174 cpi->max_lun = ctrlr->cdata.nn; 175 cpi->maxio = nvme_ns_get_max_io_xfer_size(ns); 176 cpi->initiator_id = 0; 177 cpi->bus_id = cam_sim_bus(sim); 178 cpi->base_transfer_speed = 4000000; /* 4 GB/s 4 lanes pcie 3 */ 179 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 180 strlcpy(cpi->hba_vid, "NVMe", HBA_IDLEN); 181 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 182 cpi->unit_number = cam_sim_unit(sim); 183 cpi->transport = XPORT_NVME; /* XXX XPORT_PCIE ? */ 184 cpi->transport_version = 1; /* XXX Get PCIe spec ? */ 185 cpi->protocol = PROTO_NVME; 186 cpi->protocol_version = NVME_REV_1; /* Groks all 1.x NVMe cards */ 187 cpi->xport_specific.nvme.nsid = ns->id; 188 cpi->ccb_h.status = CAM_REQ_CMP; 189 break; 190 } 191 case XPT_GET_TRAN_SETTINGS: /* Get transport settings */ 192 { 193 struct ccb_trans_settings *cts; 194 struct ccb_trans_settings_nvme *nvmep; 195 struct ccb_trans_settings_nvme *nvmex; 196 197 cts = &ccb->cts; 198 nvmex = &cts->xport_specific.nvme; 199 nvmep = &cts->proto_specific.nvme; 200 201 nvmex->valid = CTS_NVME_VALID_SPEC; 202 nvmex->spec_major = 1; /* XXX read from card */ 203 nvmex->spec_minor = 2; 204 nvmex->spec_tiny = 0; 205 206 nvmep->valid = CTS_NVME_VALID_SPEC; 207 nvmep->spec_major = 1; /* XXX read from card */ 208 nvmep->spec_minor = 2; 209 nvmep->spec_tiny = 0; 210 cts->transport = XPORT_NVME; 211 cts->protocol = PROTO_NVME; 212 cts->ccb_h.status = CAM_REQ_CMP; 213 break; 214 } 215 case XPT_TERM_IO: /* Terminate the I/O process */ 216 /* 217 * every driver handles this, but nothing generates it. Assume 218 * it's OK to just say 'that worked'. 219 */ 220 /*FALLTHROUGH*/ 221 case XPT_RESET_DEV: /* Bus Device Reset the specified device */ 222 case XPT_RESET_BUS: /* Reset the specified bus */ 223 /* 224 * NVMe doesn't really support physically resetting the bus. It's part 225 * of the bus scanning dance, so return sucess to tell the process to 226 * proceed. 227 */ 228 ccb->ccb_h.status = CAM_REQ_CMP; 229 break; 230 case XPT_NVME_IO: /* Execute the requested I/O operation */ 231 case XPT_NVME_ADMIN: /* or Admin operation */ 232 nvme_sim_nvmeio(sim, ccb); 233 return; /* no done */ 234 default: 235 ccb->ccb_h.status = CAM_REQ_INVALID; 236 break; 237 } 238 xpt_done(ccb); 239 } 240 241 static void 242 nvme_sim_poll(struct cam_sim *sim) 243 { 244 245 nvme_ctrlr_intx_handler(sim2ctrlr(sim)); 246 } 247 248 static void * 249 nvme_sim_new_controller(struct nvme_controller *ctrlr) 250 { 251 struct cam_devq *devq; 252 int max_trans; 253 int unit; 254 struct nvme_sim_softc *sc = NULL; 255 256 max_trans = 256;/* XXX not so simple -- must match queues */ 257 unit = device_get_unit(ctrlr->dev); 258 devq = cam_simq_alloc(max_trans); 259 if (devq == NULL) 260 return NULL; 261 262 sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK); 263 264 sc->s_ctrlr = ctrlr; 265 266 sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll, 267 "nvme", sc, unit, &ctrlr->lock, max_trans, max_trans, devq); 268 if (sc->s_sim == NULL) { 269 printf("Failed to allocate a sim\n"); 270 cam_simq_free(devq); 271 free(sc, M_NVME); 272 return NULL; 273 } 274 275 return sc; 276 } 277 278 static void 279 nvme_sim_rescan_target(struct nvme_controller *ctrlr, struct cam_path *path) 280 { 281 union ccb *ccb; 282 283 ccb = xpt_alloc_ccb_nowait(); 284 if (ccb == NULL) { 285 printf("unable to alloc CCB for rescan\n"); 286 return; 287 } 288 289 if (xpt_clone_path(&ccb->ccb_h.path, path) != CAM_REQ_CMP) { 290 printf("unable to copy path for rescan\n"); 291 xpt_free_ccb(ccb); 292 return; 293 } 294 295 xpt_rescan(ccb); 296 } 297 298 static void * 299 nvme_sim_new_ns(struct nvme_namespace *ns, void *sc_arg) 300 { 301 struct nvme_sim_softc *sc = sc_arg; 302 struct nvme_controller *ctrlr = sc->s_ctrlr; 303 int i; 304 305 sc->s_ns = ns; 306 307 /* 308 * XXX this is creating one bus per ns, but it should be one 309 * XXX target per controller, and one LUN per namespace. 310 * XXX Current drives only support one NS, so there's time 311 * XXX to fix it later when new drives arrive. 312 * 313 * XXX I'm pretty sure the xpt_bus_register() call below is 314 * XXX like super lame and it really belongs in the sim_new_ctrlr 315 * XXX callback. Then the create_path below would be pretty close 316 * XXX to being right. Except we should be per-ns not per-ctrlr 317 * XXX data. 318 */ 319 320 mtx_lock(&ctrlr->lock); 321 /* Create bus */ 322 323 /* 324 * XXX do I need to lock ctrlr->lock ? 325 * XXX do I need to lock the path? 326 * ata and scsi seem to in their code, but their discovery is 327 * somewhat more asynchronous. We're only every called one at a 328 * time, and nothing is in parallel. 329 */ 330 331 i = 0; 332 if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS) 333 goto error; 334 i++; 335 if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim), 336 1, ns->id) != CAM_REQ_CMP) 337 goto error; 338 i++; 339 340 sc->s_path->device->nvme_data = nvme_ns_get_data(ns); 341 sc->s_path->device->nvme_cdata = nvme_ctrlr_get_data(ns->ctrlr); 342 343 /* Scan bus */ 344 nvme_sim_rescan_target(ctrlr, sc->s_path); 345 346 mtx_unlock(&ctrlr->lock); 347 348 return ns; 349 350 error: 351 switch (i) { 352 case 2: 353 xpt_free_path(sc->s_path); 354 case 1: 355 xpt_bus_deregister(cam_sim_path(sc->s_sim)); 356 case 0: 357 cam_sim_free(sc->s_sim, /*free_devq*/TRUE); 358 } 359 mtx_unlock(&ctrlr->lock); 360 return NULL; 361 } 362 363 static void 364 nvme_sim_controller_fail(void *ctrlr_arg) 365 { 366 /* XXX cleanup XXX */ 367 } 368 369 struct nvme_consumer *consumer_cookie; 370 371 static void 372 nvme_sim_init(void) 373 { 374 375 consumer_cookie = nvme_register_consumer(nvme_sim_new_ns, 376 nvme_sim_new_controller, NULL, nvme_sim_controller_fail); 377 } 378 379 SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY, 380 nvme_sim_init, NULL); 381 382 static void 383 nvme_sim_uninit(void) 384 { 385 /* XXX Cleanup */ 386 387 nvme_unregister_consumer(consumer_cookie); 388 } 389 390 SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY, 391 nvme_sim_uninit, NULL); 392