1 /*- 2 * Copyright (c) 2016 Netflix, Inc 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/ioccom.h> 36 #include <sys/malloc.h> 37 #include <sys/proc.h> 38 #include <sys/smp.h> 39 40 #include <cam/cam.h> 41 #include <cam/cam_ccb.h> 42 #include <cam/cam_sim.h> 43 #include <cam/cam_xpt_sim.h> 44 #include <cam/cam_xpt_internal.h> // Yes, this is wrong. 45 #include <cam/cam_debug.h> 46 47 #include "nvme_private.h" 48 49 #define ccb_accb_ptr spriv_ptr0 50 #define ccb_ctrlr_ptr spriv_ptr1 51 static void nvme_sim_action(struct cam_sim *sim, union ccb *ccb); 52 static void nvme_sim_poll(struct cam_sim *sim); 53 54 #define sim2softc(sim) ((struct nvme_sim_softc *)cam_sim_softc(sim)) 55 #define sim2ns(sim) (sim2softc(sim)->s_ns) 56 #define sim2ctrlr(sim) (sim2softc(sim)->s_ctrlr) 57 58 struct nvme_sim_softc 59 { 60 struct nvme_controller *s_ctrlr; 61 struct nvme_namespace *s_ns; 62 struct cam_sim *s_sim; 63 struct cam_path *s_path; 64 }; 65 66 static void 67 nvme_sim_nvmeio_done(void *ccb_arg, const struct nvme_completion *cpl) 68 { 69 union ccb *ccb = (union ccb *)ccb_arg; 70 71 /* 72 * Let the periph know the completion, and let it sort out what 73 * it means. Make our best guess, though for the status code. 74 */ 75 memcpy(&ccb->nvmeio.cpl, cpl, sizeof(*cpl)); 76 if (nvme_completion_is_error(cpl)) 77 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 78 else 79 ccb->ccb_h.status = CAM_REQ_CMP; 80 xpt_done(ccb); 81 } 82 83 static void 84 nvme_sim_nvmeio(struct cam_sim *sim, union ccb *ccb) 85 { 86 struct ccb_nvmeio *nvmeio = &ccb->nvmeio; 87 struct nvme_request *req; 88 void *payload; 89 uint32_t size; 90 struct nvme_controller *ctrlr; 91 92 ctrlr = sim2ctrlr(sim); 93 payload = nvmeio->data_ptr; 94 size = nvmeio->dxfer_len; 95 /* SG LIST ??? */ 96 if ((nvmeio->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_BIO) 97 req = nvme_allocate_request_bio((struct bio *)payload, 98 nvme_sim_nvmeio_done, ccb); 99 else if (payload == NULL) 100 req = nvme_allocate_request_null(nvme_sim_nvmeio_done, ccb); 101 else 102 req = nvme_allocate_request_vaddr(payload, size, 103 nvme_sim_nvmeio_done, ccb); 104 105 if (req == NULL) { 106 nvmeio->ccb_h.status = CAM_RESRC_UNAVAIL; 107 xpt_done(ccb); 108 return; 109 } 110 111 memcpy(&req->cmd, &ccb->nvmeio.cmd, sizeof(ccb->nvmeio.cmd)); 112 113 nvme_ctrlr_submit_io_request(ctrlr, req); 114 115 ccb->ccb_h.status |= CAM_SIM_QUEUED; 116 } 117 118 static void 119 nvme_sim_action(struct cam_sim *sim, union ccb *ccb) 120 { 121 struct nvme_controller *ctrlr; 122 struct nvme_namespace *ns; 123 124 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, 125 ("nvme_sim_action: func= %#x\n", 126 ccb->ccb_h.func_code)); 127 128 /* 129 * XXX when we support multiple namespaces in the base driver we'll need 130 * to revisit how all this gets stored and saved in the periph driver's 131 * reserved areas. Right now we store all three in the softc of the sim. 132 */ 133 ns = sim2ns(sim); 134 ctrlr = sim2ctrlr(sim); 135 136 mtx_assert(&ctrlr->lock, MA_OWNED); 137 138 switch (ccb->ccb_h.func_code) { 139 case XPT_CALC_GEOMETRY: /* Calculate Geometry Totally nuts ? XXX */ 140 /* 141 * Only meaningful for old-school SCSI disks since only the SCSI 142 * da driver generates them. Reject all these that slip through. 143 */ 144 /*FALLTHROUGH*/ 145 case XPT_ABORT: /* Abort the specified CCB */ 146 case XPT_EN_LUN: /* Enable LUN as a target */ 147 case XPT_TARGET_IO: /* Execute target I/O request */ 148 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 149 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 150 /* 151 * Only target mode generates these, and only for SCSI. They are 152 * all invalid/unsupported for NVMe. 153 */ 154 ccb->ccb_h.status = CAM_REQ_INVALID; 155 break; 156 case XPT_SET_TRAN_SETTINGS: 157 /* 158 * NVMe doesn't really have different transfer settings, but 159 * other parts of CAM think failure here is a big deal. 160 */ 161 ccb->ccb_h.status = CAM_REQ_CMP; 162 break; 163 case XPT_PATH_INQ: /* Path routing inquiry */ 164 { 165 struct ccb_pathinq *cpi = &ccb->cpi; 166 167 /* 168 * NVMe may have multiple LUNs on the same path. Current generation 169 * of NVMe devives support only a single name space. Multiple name 170 * space drives are coming, but it's unclear how we should report 171 * them up the stack. 172 */ 173 cpi->version_num = 1; 174 cpi->hba_inquiry = 0; 175 cpi->target_sprt = 0; 176 cpi->hba_misc = PIM_UNMAPPED /* | PIM_NOSCAN */; 177 cpi->hba_eng_cnt = 0; 178 cpi->max_target = 0; 179 cpi->max_lun = ctrlr->cdata.nn; 180 cpi->maxio = nvme_ns_get_max_io_xfer_size(ns); 181 cpi->initiator_id = 0; 182 cpi->bus_id = cam_sim_bus(sim); 183 cpi->base_transfer_speed = 4000000; /* 4 GB/s 4 lanes pcie 3 */ 184 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 185 strncpy(cpi->hba_vid, "NVMe", HBA_IDLEN); 186 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 187 cpi->unit_number = cam_sim_unit(sim); 188 cpi->transport = XPORT_NVME; /* XXX XPORT_PCIE ? */ 189 cpi->transport_version = 1; /* XXX Get PCIe spec ? */ 190 cpi->protocol = PROTO_NVME; 191 cpi->protocol_version = NVME_REV_1; /* Groks all 1.x NVMe cards */ 192 cpi->xport_specific.nvme.nsid = ns->id; 193 cpi->ccb_h.status = CAM_REQ_CMP; 194 break; 195 } 196 case XPT_GET_TRAN_SETTINGS: /* Get transport settings */ 197 { 198 struct ccb_trans_settings *cts; 199 struct ccb_trans_settings_nvme *nvmep; 200 struct ccb_trans_settings_nvme *nvmex; 201 202 cts = &ccb->cts; 203 nvmex = &cts->xport_specific.nvme; 204 nvmep = &cts->proto_specific.nvme; 205 206 nvmex->valid = CTS_NVME_VALID_SPEC; 207 nvmex->spec_major = 1; /* XXX read from card */ 208 nvmex->spec_minor = 2; 209 nvmex->spec_tiny = 0; 210 211 nvmep->valid = CTS_NVME_VALID_SPEC; 212 nvmep->spec_major = 1; /* XXX read from card */ 213 nvmep->spec_minor = 2; 214 nvmep->spec_tiny = 0; 215 cts->transport = XPORT_NVME; 216 cts->protocol = PROTO_NVME; 217 cts->ccb_h.status = CAM_REQ_CMP; 218 break; 219 } 220 case XPT_TERM_IO: /* Terminate the I/O process */ 221 /* 222 * every driver handles this, but nothing generates it. Assume 223 * it's OK to just say 'that worked'. 224 */ 225 /*FALLTHROUGH*/ 226 case XPT_RESET_DEV: /* Bus Device Reset the specified device */ 227 case XPT_RESET_BUS: /* Reset the specified bus */ 228 /* 229 * NVMe doesn't really support physically resetting the bus. It's part 230 * of the bus scanning dance, so return sucess to tell the process to 231 * proceed. 232 */ 233 ccb->ccb_h.status = CAM_REQ_CMP; 234 break; 235 case XPT_NVME_IO: /* Execute the requested I/O operation */ 236 nvme_sim_nvmeio(sim, ccb); 237 return; /* no done */ 238 default: 239 ccb->ccb_h.status = CAM_REQ_INVALID; 240 break; 241 } 242 xpt_done(ccb); 243 } 244 245 static void 246 nvme_sim_poll(struct cam_sim *sim) 247 { 248 249 nvme_ctrlr_intx_handler(sim2ctrlr(sim)); 250 } 251 252 static void * 253 nvme_sim_new_controller(struct nvme_controller *ctrlr) 254 { 255 struct cam_devq *devq; 256 int max_trans; 257 int unit; 258 struct nvme_sim_softc *sc = NULL; 259 260 max_trans = 256;/* XXX not so simple -- must match queues */ 261 unit = device_get_unit(ctrlr->dev); 262 devq = cam_simq_alloc(max_trans); 263 if (devq == NULL) 264 return NULL; 265 266 sc = malloc(sizeof(*sc), M_NVME, M_ZERO | M_WAITOK); 267 268 sc->s_ctrlr = ctrlr; 269 270 sc->s_sim = cam_sim_alloc(nvme_sim_action, nvme_sim_poll, 271 "nvme", sc, unit, &ctrlr->lock, max_trans, max_trans, devq); 272 if (sc->s_sim == NULL) { 273 printf("Failed to allocate a sim\n"); 274 cam_simq_free(devq); 275 free(sc, M_NVME); 276 return NULL; 277 } 278 279 return sc; 280 } 281 282 static void 283 nvme_sim_rescan_target(struct nvme_controller *ctrlr, struct cam_path *path) 284 { 285 union ccb *ccb; 286 287 ccb = xpt_alloc_ccb_nowait(); 288 if (ccb == NULL) { 289 printf("unable to alloc CCB for rescan\n"); 290 return; 291 } 292 293 if (xpt_clone_path(&ccb->ccb_h.path, path) != CAM_REQ_CMP) { 294 printf("unable to copy path for rescan\n"); 295 xpt_free_ccb(ccb); 296 return; 297 } 298 299 xpt_rescan(ccb); 300 } 301 302 static void * 303 nvme_sim_new_ns(struct nvme_namespace *ns, void *sc_arg) 304 { 305 struct nvme_sim_softc *sc = sc_arg; 306 struct nvme_controller *ctrlr = sc->s_ctrlr; 307 int i; 308 309 sc->s_ns = ns; 310 311 /* 312 * XXX this is creating one bus per ns, but it should be one 313 * XXX target per controller, and one LUN per namespace. 314 * XXX Current drives only support one NS, so there's time 315 * XXX to fix it later when new drives arrive. 316 * 317 * XXX I'm pretty sure the xpt_bus_register() call below is 318 * XXX like super lame and it really belongs in the sim_new_ctrlr 319 * XXX callback. Then the create_path below would be pretty close 320 * XXX to being right. Except we should be per-ns not per-ctrlr 321 * XXX data. 322 */ 323 324 mtx_lock(&ctrlr->lock); 325 /* Create bus */ 326 327 /* 328 * XXX do I need to lock ctrlr->lock ? 329 * XXX do I need to lock the path? 330 * ata and scsi seem to in their code, but their discovery is 331 * somewhat more asynchronous. We're only every called one at a 332 * time, and nothing is in parallel. 333 */ 334 335 i = 0; 336 if (xpt_bus_register(sc->s_sim, ctrlr->dev, 0) != CAM_SUCCESS) 337 goto error; 338 i++; 339 if (xpt_create_path(&sc->s_path, /*periph*/NULL, cam_sim_path(sc->s_sim), 340 1, ns->id) != CAM_REQ_CMP) 341 goto error; 342 i++; 343 344 sc->s_path->device->nvme_data = nvme_ns_get_data(ns); 345 sc->s_path->device->nvme_cdata = nvme_ctrlr_get_data(ns->ctrlr); 346 347 /* Scan bus */ 348 nvme_sim_rescan_target(ctrlr, sc->s_path); 349 350 mtx_unlock(&ctrlr->lock); 351 352 return ns; 353 354 error: 355 switch (i) { 356 case 2: 357 xpt_free_path(sc->s_path); 358 case 1: 359 xpt_bus_deregister(cam_sim_path(sc->s_sim)); 360 case 0: 361 cam_sim_free(sc->s_sim, /*free_devq*/TRUE); 362 } 363 mtx_unlock(&ctrlr->lock); 364 return NULL; 365 } 366 367 static void 368 nvme_sim_controller_fail(void *ctrlr_arg) 369 { 370 /* XXX cleanup XXX */ 371 } 372 373 struct nvme_consumer *consumer_cookie; 374 375 static void 376 nvme_sim_init(void) 377 { 378 379 consumer_cookie = nvme_register_consumer(nvme_sim_new_ns, 380 nvme_sim_new_controller, NULL, nvme_sim_controller_fail); 381 } 382 383 SYSINIT(nvme_sim_register, SI_SUB_DRIVERS, SI_ORDER_ANY, 384 nvme_sim_init, NULL); 385 386 static void 387 nvme_sim_uninit(void) 388 { 389 /* XXX Cleanup */ 390 391 nvme_unregister_consumer(consumer_cookie); 392 } 393 394 SYSUNINIT(nvme_sim_unregister, SI_SUB_DRIVERS, SI_ORDER_ANY, 395 nvme_sim_uninit, NULL); 396