1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/domainset.h> 36 #include <sys/proc.h> 37 38 #include <dev/pci/pcivar.h> 39 40 #include "nvme_private.h" 41 42 typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t; 43 #define DO_NOT_RETRY 1 44 45 static void _nvme_qpair_submit_request(struct nvme_qpair *qpair, 46 struct nvme_request *req); 47 static void nvme_qpair_destroy(struct nvme_qpair *qpair); 48 49 struct nvme_opcode_string { 50 uint16_t opc; 51 const char * str; 52 }; 53 54 static struct nvme_opcode_string admin_opcode[] = { 55 { NVME_OPC_DELETE_IO_SQ, "DELETE IO SQ" }, 56 { NVME_OPC_CREATE_IO_SQ, "CREATE IO SQ" }, 57 { NVME_OPC_GET_LOG_PAGE, "GET LOG PAGE" }, 58 { NVME_OPC_DELETE_IO_CQ, "DELETE IO CQ" }, 59 { NVME_OPC_CREATE_IO_CQ, "CREATE IO CQ" }, 60 { NVME_OPC_IDENTIFY, "IDENTIFY" }, 61 { NVME_OPC_ABORT, "ABORT" }, 62 { NVME_OPC_SET_FEATURES, "SET FEATURES" }, 63 { NVME_OPC_GET_FEATURES, "GET FEATURES" }, 64 { NVME_OPC_ASYNC_EVENT_REQUEST, "ASYNC EVENT REQUEST" }, 65 { NVME_OPC_NAMESPACE_MANAGEMENT, "NAMESPACE MANAGEMENT" }, 66 { NVME_OPC_FIRMWARE_ACTIVATE, "FIRMWARE ACTIVATE" }, 67 { NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD, "FIRMWARE IMAGE DOWNLOAD" }, 68 { NVME_OPC_DEVICE_SELF_TEST, "DEVICE SELF-TEST" }, 69 { NVME_OPC_NAMESPACE_ATTACHMENT, "NAMESPACE ATTACHMENT" }, 70 { NVME_OPC_KEEP_ALIVE, "KEEP ALIVE" }, 71 { NVME_OPC_DIRECTIVE_SEND, "DIRECTIVE SEND" }, 72 { NVME_OPC_DIRECTIVE_RECEIVE, "DIRECTIVE RECEIVE" }, 73 { NVME_OPC_VIRTUALIZATION_MANAGEMENT, "VIRTUALIZATION MANAGEMENT" }, 74 { NVME_OPC_NVME_MI_SEND, "NVME-MI SEND" }, 75 { NVME_OPC_NVME_MI_RECEIVE, "NVME-MI RECEIVE" }, 76 { NVME_OPC_DOORBELL_BUFFER_CONFIG, "DOORBELL BUFFER CONFIG" }, 77 { NVME_OPC_FORMAT_NVM, "FORMAT NVM" }, 78 { NVME_OPC_SECURITY_SEND, "SECURITY SEND" }, 79 { NVME_OPC_SECURITY_RECEIVE, "SECURITY RECEIVE" }, 80 { NVME_OPC_SANITIZE, "SANITIZE" }, 81 { NVME_OPC_GET_LBA_STATUS, "GET LBA STATUS" }, 82 { 0xFFFF, "ADMIN COMMAND" } 83 }; 84 85 static struct nvme_opcode_string io_opcode[] = { 86 { NVME_OPC_FLUSH, "FLUSH" }, 87 { NVME_OPC_WRITE, "WRITE" }, 88 { NVME_OPC_READ, "READ" }, 89 { NVME_OPC_WRITE_UNCORRECTABLE, "WRITE UNCORRECTABLE" }, 90 { NVME_OPC_COMPARE, "COMPARE" }, 91 { NVME_OPC_WRITE_ZEROES, "WRITE ZEROES" }, 92 { NVME_OPC_DATASET_MANAGEMENT, "DATASET MANAGEMENT" }, 93 { NVME_OPC_VERIFY, "VERIFY" }, 94 { NVME_OPC_RESERVATION_REGISTER, "RESERVATION REGISTER" }, 95 { NVME_OPC_RESERVATION_REPORT, "RESERVATION REPORT" }, 96 { NVME_OPC_RESERVATION_ACQUIRE, "RESERVATION ACQUIRE" }, 97 { NVME_OPC_RESERVATION_RELEASE, "RESERVATION RELEASE" }, 98 { 0xFFFF, "IO COMMAND" } 99 }; 100 101 static const char * 102 get_admin_opcode_string(uint16_t opc) 103 { 104 struct nvme_opcode_string *entry; 105 106 entry = admin_opcode; 107 108 while (entry->opc != 0xFFFF) { 109 if (entry->opc == opc) 110 return (entry->str); 111 entry++; 112 } 113 return (entry->str); 114 } 115 116 static const char * 117 get_io_opcode_string(uint16_t opc) 118 { 119 struct nvme_opcode_string *entry; 120 121 entry = io_opcode; 122 123 while (entry->opc != 0xFFFF) { 124 if (entry->opc == opc) 125 return (entry->str); 126 entry++; 127 } 128 return (entry->str); 129 } 130 131 static void 132 nvme_admin_qpair_print_command(struct nvme_qpair *qpair, 133 struct nvme_command *cmd) 134 { 135 136 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x " 137 "cdw10:%08x cdw11:%08x\n", 138 get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid, 139 le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11)); 140 } 141 142 static void 143 nvme_io_qpair_print_command(struct nvme_qpair *qpair, 144 struct nvme_command *cmd) 145 { 146 147 switch (cmd->opc) { 148 case NVME_OPC_WRITE: 149 case NVME_OPC_READ: 150 case NVME_OPC_WRITE_UNCORRECTABLE: 151 case NVME_OPC_COMPARE: 152 case NVME_OPC_WRITE_ZEROES: 153 case NVME_OPC_VERIFY: 154 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d " 155 "lba:%llu len:%d\n", 156 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid), 157 ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10), 158 (le32toh(cmd->cdw12) & 0xFFFF) + 1); 159 break; 160 case NVME_OPC_FLUSH: 161 case NVME_OPC_DATASET_MANAGEMENT: 162 case NVME_OPC_RESERVATION_REGISTER: 163 case NVME_OPC_RESERVATION_REPORT: 164 case NVME_OPC_RESERVATION_ACQUIRE: 165 case NVME_OPC_RESERVATION_RELEASE: 166 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n", 167 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid)); 168 break; 169 default: 170 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n", 171 get_io_opcode_string(cmd->opc), cmd->opc, qpair->id, 172 cmd->cid, le32toh(cmd->nsid)); 173 break; 174 } 175 } 176 177 static void 178 nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd) 179 { 180 if (qpair->id == 0) 181 nvme_admin_qpair_print_command(qpair, cmd); 182 else 183 nvme_io_qpair_print_command(qpair, cmd); 184 if (nvme_verbose_cmd_dump) { 185 nvme_printf(qpair->ctrlr, 186 "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n", 187 cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr, 188 (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2); 189 nvme_printf(qpair->ctrlr, 190 "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n", 191 cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14, 192 cmd->cdw15); 193 } 194 } 195 196 struct nvme_status_string { 197 uint16_t sc; 198 const char * str; 199 }; 200 201 static struct nvme_status_string generic_status[] = { 202 { NVME_SC_SUCCESS, "SUCCESS" }, 203 { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" }, 204 { NVME_SC_INVALID_FIELD, "INVALID_FIELD" }, 205 { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" }, 206 { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" }, 207 { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" }, 208 { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" }, 209 { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" }, 210 { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" }, 211 { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" }, 212 { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" }, 213 { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" }, 214 { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" }, 215 { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" }, 216 { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" }, 217 { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" }, 218 { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" }, 219 { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" }, 220 { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" }, 221 { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" }, 222 { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" }, 223 { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" }, 224 { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" }, 225 { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" }, 226 { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" }, 227 { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" }, 228 { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" }, 229 { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" }, 230 { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" }, 231 { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" }, 232 { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" }, 233 { NVME_SC_NAMESPACE_IS_WRITE_PROTECTED, "NAMESPACE IS WRITE PROTECTED" }, 234 { NVME_SC_COMMAND_INTERRUPTED, "COMMAND INTERRUPTED" }, 235 { NVME_SC_TRANSIENT_TRANSPORT_ERROR, "TRANSIENT TRANSPORT ERROR" }, 236 237 { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" }, 238 { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" }, 239 { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" }, 240 { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" }, 241 { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" }, 242 { 0xFFFF, "GENERIC" } 243 }; 244 245 static struct nvme_status_string command_specific_status[] = { 246 { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" }, 247 { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" }, 248 { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" }, 249 { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" }, 250 { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" }, 251 { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" }, 252 { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" }, 253 { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" }, 254 { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" }, 255 { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" }, 256 { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" }, 257 { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" }, 258 { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" }, 259 { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" }, 260 { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" }, 261 { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" }, 262 { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" }, 263 { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" }, 264 { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" }, 265 { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" }, 266 { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" }, 267 { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" }, 268 { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" }, 269 { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" }, 270 { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" }, 271 { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" }, 272 { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" }, 273 { NVME_SC_SELF_TEST_IN_PROGRESS, "DEVICE SELF-TEST IN PROGRESS" }, 274 { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" }, 275 { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" }, 276 { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" }, 277 { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" }, 278 { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" }, 279 { NVME_SC_SANITIZE_PROHIBITED_WPMRE, "SANITIZE PROHIBITED WRITE PERSISTENT MEMORY REGION ENABLED" }, 280 { NVME_SC_ANA_GROUP_ID_INVALID, "ANA GROUP IDENTIFIED INVALID" }, 281 { NVME_SC_ANA_ATTACH_FAILED, "ANA ATTACH FAILED" }, 282 283 { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" }, 284 { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" }, 285 { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" }, 286 { 0xFFFF, "COMMAND SPECIFIC" } 287 }; 288 289 static struct nvme_status_string media_error_status[] = { 290 { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" }, 291 { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" }, 292 { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" }, 293 { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" }, 294 { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" }, 295 { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" }, 296 { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" }, 297 { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" }, 298 { 0xFFFF, "MEDIA ERROR" } 299 }; 300 301 static struct nvme_status_string path_related_status[] = { 302 { NVME_SC_INTERNAL_PATH_ERROR, "INTERNAL PATH ERROR" }, 303 { NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS, "ASYMMETRIC ACCESS PERSISTENT LOSS" }, 304 { NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE, "ASYMMETRIC ACCESS INACCESSIBLE" }, 305 { NVME_SC_ASYMMETRIC_ACCESS_TRANSITION, "ASYMMETRIC ACCESS TRANSITION" }, 306 { NVME_SC_CONTROLLER_PATHING_ERROR, "CONTROLLER PATHING ERROR" }, 307 { NVME_SC_HOST_PATHING_ERROR, "HOST PATHING ERROR" }, 308 { NVME_SC_COMMAND_ABOTHED_BY_HOST, "COMMAND ABOTHED BY HOST" }, 309 { 0xFFFF, "PATH RELATED" }, 310 }; 311 312 static const char * 313 get_status_string(uint16_t sct, uint16_t sc) 314 { 315 struct nvme_status_string *entry; 316 317 switch (sct) { 318 case NVME_SCT_GENERIC: 319 entry = generic_status; 320 break; 321 case NVME_SCT_COMMAND_SPECIFIC: 322 entry = command_specific_status; 323 break; 324 case NVME_SCT_MEDIA_ERROR: 325 entry = media_error_status; 326 break; 327 case NVME_SCT_PATH_RELATED: 328 entry = path_related_status; 329 break; 330 case NVME_SCT_VENDOR_SPECIFIC: 331 return ("VENDOR SPECIFIC"); 332 default: 333 return ("RESERVED"); 334 } 335 336 while (entry->sc != 0xFFFF) { 337 if (entry->sc == sc) 338 return (entry->str); 339 entry++; 340 } 341 return (entry->str); 342 } 343 344 static void 345 nvme_qpair_print_completion(struct nvme_qpair *qpair, 346 struct nvme_completion *cpl) 347 { 348 uint8_t sct, sc, crd, m, dnr; 349 350 sct = NVME_STATUS_GET_SCT(cpl->status); 351 sc = NVME_STATUS_GET_SC(cpl->status); 352 crd = NVME_STATUS_GET_CRD(cpl->status); 353 m = NVME_STATUS_GET_M(cpl->status); 354 dnr = NVME_STATUS_GET_DNR(cpl->status); 355 356 nvme_printf(qpair->ctrlr, "%s (%02x/%02x) crd:%x m:%x dnr:%x " 357 "sqid:%d cid:%d cdw0:%x\n", 358 get_status_string(sct, sc), sct, sc, crd, m, dnr, 359 cpl->sqid, cpl->cid, cpl->cdw0); 360 } 361 362 static bool 363 nvme_completion_is_retry(const struct nvme_completion *cpl) 364 { 365 uint8_t sct, sc, dnr; 366 367 sct = NVME_STATUS_GET_SCT(cpl->status); 368 sc = NVME_STATUS_GET_SC(cpl->status); 369 dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */ 370 371 /* 372 * TODO: spec is not clear how commands that are aborted due 373 * to TLER will be marked. So for now, it seems 374 * NAMESPACE_NOT_READY is the only case where we should 375 * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST 376 * set the DNR bit correctly since the driver controls that. 377 */ 378 switch (sct) { 379 case NVME_SCT_GENERIC: 380 switch (sc) { 381 case NVME_SC_ABORTED_BY_REQUEST: 382 case NVME_SC_NAMESPACE_NOT_READY: 383 if (dnr) 384 return (0); 385 else 386 return (1); 387 case NVME_SC_INVALID_OPCODE: 388 case NVME_SC_INVALID_FIELD: 389 case NVME_SC_COMMAND_ID_CONFLICT: 390 case NVME_SC_DATA_TRANSFER_ERROR: 391 case NVME_SC_ABORTED_POWER_LOSS: 392 case NVME_SC_INTERNAL_DEVICE_ERROR: 393 case NVME_SC_ABORTED_SQ_DELETION: 394 case NVME_SC_ABORTED_FAILED_FUSED: 395 case NVME_SC_ABORTED_MISSING_FUSED: 396 case NVME_SC_INVALID_NAMESPACE_OR_FORMAT: 397 case NVME_SC_COMMAND_SEQUENCE_ERROR: 398 case NVME_SC_LBA_OUT_OF_RANGE: 399 case NVME_SC_CAPACITY_EXCEEDED: 400 default: 401 return (0); 402 } 403 case NVME_SCT_COMMAND_SPECIFIC: 404 case NVME_SCT_MEDIA_ERROR: 405 return (0); 406 case NVME_SCT_PATH_RELATED: 407 switch (sc) { 408 case NVME_SC_INTERNAL_PATH_ERROR: 409 if (dnr) 410 return (0); 411 else 412 return (1); 413 default: 414 return (0); 415 } 416 case NVME_SCT_VENDOR_SPECIFIC: 417 default: 418 return (0); 419 } 420 } 421 422 static void 423 nvme_qpair_complete_tracker(struct nvme_tracker *tr, 424 struct nvme_completion *cpl, error_print_t print_on_error) 425 { 426 struct nvme_qpair * qpair = tr->qpair; 427 struct nvme_request *req; 428 bool retry, error, retriable; 429 430 req = tr->req; 431 error = nvme_completion_is_error(cpl); 432 retriable = nvme_completion_is_retry(cpl); 433 retry = error && retriable && req->retries < nvme_retry_count; 434 if (retry) 435 qpair->num_retries++; 436 if (error && req->retries >= nvme_retry_count && retriable) 437 qpair->num_failures++; 438 439 if (error && (print_on_error == ERROR_PRINT_ALL || 440 (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) { 441 nvme_qpair_print_command(qpair, &req->cmd); 442 nvme_qpair_print_completion(qpair, cpl); 443 } 444 445 qpair->act_tr[cpl->cid] = NULL; 446 447 KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n")); 448 449 if (!retry) { 450 if (req->type != NVME_REQUEST_NULL) { 451 bus_dmamap_sync(qpair->dma_tag_payload, 452 tr->payload_dma_map, 453 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 454 } 455 if (req->cb_fn) 456 req->cb_fn(req->cb_arg, cpl); 457 } 458 459 mtx_lock(&qpair->lock); 460 461 if (retry) { 462 req->retries++; 463 nvme_qpair_submit_tracker(qpair, tr); 464 } else { 465 if (req->type != NVME_REQUEST_NULL) { 466 bus_dmamap_unload(qpair->dma_tag_payload, 467 tr->payload_dma_map); 468 } 469 470 nvme_free_request(req); 471 tr->req = NULL; 472 473 TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq); 474 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 475 476 /* 477 * If the controller is in the middle of resetting, don't 478 * try to submit queued requests here - let the reset logic 479 * handle that instead. 480 */ 481 if (!STAILQ_EMPTY(&qpair->queued_req) && 482 !qpair->ctrlr->is_resetting) { 483 req = STAILQ_FIRST(&qpair->queued_req); 484 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 485 _nvme_qpair_submit_request(qpair, req); 486 } 487 } 488 489 mtx_unlock(&qpair->lock); 490 } 491 492 static void 493 nvme_qpair_manual_complete_tracker( 494 struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr, 495 error_print_t print_on_error) 496 { 497 struct nvme_completion cpl; 498 499 memset(&cpl, 0, sizeof(cpl)); 500 501 struct nvme_qpair * qpair = tr->qpair; 502 503 cpl.sqid = qpair->id; 504 cpl.cid = tr->cid; 505 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 506 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 507 cpl.status |= (dnr & NVME_STATUS_DNR_MASK) << NVME_STATUS_DNR_SHIFT; 508 nvme_qpair_complete_tracker(tr, &cpl, print_on_error); 509 } 510 511 void 512 nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 513 struct nvme_request *req, uint32_t sct, uint32_t sc) 514 { 515 struct nvme_completion cpl; 516 bool error; 517 518 memset(&cpl, 0, sizeof(cpl)); 519 cpl.sqid = qpair->id; 520 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 521 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 522 523 error = nvme_completion_is_error(&cpl); 524 525 if (error) { 526 nvme_qpair_print_command(qpair, &req->cmd); 527 nvme_qpair_print_completion(qpair, &cpl); 528 } 529 530 if (req->cb_fn) 531 req->cb_fn(req->cb_arg, &cpl); 532 533 nvme_free_request(req); 534 } 535 536 bool 537 nvme_qpair_process_completions(struct nvme_qpair *qpair) 538 { 539 struct nvme_tracker *tr; 540 struct nvme_completion cpl; 541 int done = 0; 542 bool in_panic = dumping || SCHEDULER_STOPPED(); 543 544 /* 545 * qpair is not enabled, likely because a controller reset is in 546 * progress. Ignore the interrupt - any I/O that was associated with 547 * this interrupt will get retried when the reset is complete. Any 548 * pending completions for when we're in startup will be completed 549 * as soon as initialization is complete and we start sending commands 550 * to the device. 551 */ 552 if (qpair->recovery_state != RECOVERY_NONE) { 553 qpair->num_ignored++; 554 return (false); 555 } 556 557 /* 558 * Sanity check initialization. After we reset the hardware, the phase 559 * is defined to be 1. So if we get here with zero prior calls and the 560 * phase is 0, it means that we've lost a race between the 561 * initialization and the ISR running. With the phase wrong, we'll 562 * process a bunch of completions that aren't really completions leading 563 * to a KASSERT below. 564 */ 565 KASSERT(!(qpair->num_intr_handler_calls == 0 && qpair->phase == 0), 566 ("%s: Phase wrong for first interrupt call.", 567 device_get_nameunit(qpair->ctrlr->dev))); 568 569 qpair->num_intr_handler_calls++; 570 571 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 572 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 573 /* 574 * A panic can stop the CPU this routine is running on at any point. If 575 * we're called during a panic, complete the sq_head wrap protocol for 576 * the case where we are interrupted just after the increment at 1 577 * below, but before we can reset cq_head to zero at 2. Also cope with 578 * the case where we do the zero at 2, but may or may not have done the 579 * phase adjustment at step 3. The panic machinery flushes all pending 580 * memory writes, so we can make these strong ordering assumptions 581 * that would otherwise be unwise if we were racing in real time. 582 */ 583 if (__predict_false(in_panic)) { 584 if (qpair->cq_head == qpair->num_entries) { 585 /* 586 * Here we know that we need to zero cq_head and then negate 587 * the phase, which hasn't been assigned if cq_head isn't 588 * zero due to the atomic_store_rel. 589 */ 590 qpair->cq_head = 0; 591 qpair->phase = !qpair->phase; 592 } else if (qpair->cq_head == 0) { 593 /* 594 * In this case, we know that the assignment at 2 595 * happened below, but we don't know if it 3 happened or 596 * not. To do this, we look at the last completion 597 * entry and set the phase to the opposite phase 598 * that it has. This gets us back in sync 599 */ 600 cpl = qpair->cpl[qpair->num_entries - 1]; 601 nvme_completion_swapbytes(&cpl); 602 qpair->phase = !NVME_STATUS_GET_P(cpl.status); 603 } 604 } 605 606 while (1) { 607 uint16_t status; 608 609 /* 610 * We need to do this dance to avoid a race between the host and 611 * the device where the device overtakes the host while the host 612 * is reading this record, leaving the status field 'new' and 613 * the sqhd and cid fields potentially stale. If the phase 614 * doesn't match, that means status hasn't yet been updated and 615 * we'll get any pending changes next time. It also means that 616 * the phase must be the same the second time. We have to sync 617 * before reading to ensure any bouncing completes. 618 */ 619 status = le16toh(qpair->cpl[qpair->cq_head].status); 620 if (NVME_STATUS_GET_P(status) != qpair->phase) 621 break; 622 623 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 624 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 625 cpl = qpair->cpl[qpair->cq_head]; 626 nvme_completion_swapbytes(&cpl); 627 628 KASSERT( 629 NVME_STATUS_GET_P(status) == NVME_STATUS_GET_P(cpl.status), 630 ("Phase unexpectedly inconsistent")); 631 632 if (cpl.cid < qpair->num_trackers) 633 tr = qpair->act_tr[cpl.cid]; 634 else 635 tr = NULL; 636 637 done++; 638 if (tr != NULL) { 639 nvme_qpair_complete_tracker(tr, &cpl, ERROR_PRINT_ALL); 640 qpair->sq_head = cpl.sqhd; 641 } else if (!in_panic) { 642 /* 643 * A missing tracker is normally an error. However, a 644 * panic can stop the CPU this routine is running on 645 * after completing an I/O but before updating 646 * qpair->cq_head at 1 below. Later, we re-enter this 647 * routine to poll I/O associated with the kernel 648 * dump. We find that the tr has been set to null before 649 * calling the completion routine. If it hasn't 650 * completed (or it triggers a panic), then '1' below 651 * won't have updated cq_head. Rather than panic again, 652 * ignore this condition because it's not unexpected. 653 */ 654 nvme_printf(qpair->ctrlr, 655 "cpl (cid = %u) does not map to outstanding cmd\n", 656 cpl.cid); 657 /* nvme_dump_completion expects device endianess */ 658 nvme_dump_completion(&qpair->cpl[qpair->cq_head]); 659 KASSERT(0, ("received completion for unknown cmd")); 660 } 661 662 /* 663 * There's a number of races with the following (see above) when 664 * the system panics. We compensate for each one of them by 665 * using the atomic store to force strong ordering (at least when 666 * viewed in the aftermath of a panic). 667 */ 668 if (++qpair->cq_head == qpair->num_entries) { /* 1 */ 669 atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */ 670 qpair->phase = !qpair->phase; /* 3 */ 671 } 672 } 673 674 if (done != 0) { 675 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 676 qpair->cq_hdbl_off, qpair->cq_head); 677 } 678 679 return (done != 0); 680 } 681 682 static void 683 nvme_qpair_msi_handler(void *arg) 684 { 685 struct nvme_qpair *qpair = arg; 686 687 nvme_qpair_process_completions(qpair); 688 } 689 690 int 691 nvme_qpair_construct(struct nvme_qpair *qpair, 692 uint32_t num_entries, uint32_t num_trackers, 693 struct nvme_controller *ctrlr) 694 { 695 struct nvme_tracker *tr; 696 size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz; 697 uint64_t queuemem_phys, prpmem_phys, list_phys; 698 uint8_t *queuemem, *prpmem, *prp_list; 699 int i, err; 700 701 qpair->vector = ctrlr->msi_count > 1 ? qpair->id : 0; 702 qpair->num_entries = num_entries; 703 qpair->num_trackers = num_trackers; 704 qpair->ctrlr = ctrlr; 705 706 mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF); 707 708 /* Note: NVMe PRP format is restricted to 4-byte alignment. */ 709 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 710 4, ctrlr->page_size, BUS_SPACE_MAXADDR, 711 BUS_SPACE_MAXADDR, NULL, NULL, ctrlr->max_xfer_size, 712 howmany(ctrlr->max_xfer_size, ctrlr->page_size) + 1, 713 ctrlr->page_size, 0, 714 NULL, NULL, &qpair->dma_tag_payload); 715 if (err != 0) { 716 nvme_printf(ctrlr, "payload tag create failed %d\n", err); 717 goto out; 718 } 719 720 /* 721 * Each component must be page aligned, and individual PRP lists 722 * cannot cross a page boundary. 723 */ 724 cmdsz = qpair->num_entries * sizeof(struct nvme_command); 725 cmdsz = roundup2(cmdsz, ctrlr->page_size); 726 cplsz = qpair->num_entries * sizeof(struct nvme_completion); 727 cplsz = roundup2(cplsz, ctrlr->page_size); 728 /* 729 * For commands requiring more than 2 PRP entries, one PRP will be 730 * embedded in the command (prp1), and the rest of the PRP entries 731 * will be in a list pointed to by the command (prp2). 732 */ 733 prpsz = sizeof(uint64_t) * 734 howmany(ctrlr->max_xfer_size, ctrlr->page_size); 735 prpmemsz = qpair->num_trackers * prpsz; 736 allocsz = cmdsz + cplsz + prpmemsz; 737 738 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 739 ctrlr->page_size, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 740 allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag); 741 if (err != 0) { 742 nvme_printf(ctrlr, "tag create failed %d\n", err); 743 goto out; 744 } 745 bus_dma_tag_set_domain(qpair->dma_tag, qpair->domain); 746 747 if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem, 748 BUS_DMA_COHERENT | BUS_DMA_NOWAIT, &qpair->queuemem_map)) { 749 nvme_printf(ctrlr, "failed to alloc qpair memory\n"); 750 goto out; 751 } 752 753 if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map, 754 queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) { 755 nvme_printf(ctrlr, "failed to load qpair memory\n"); 756 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 757 qpair->queuemem_map); 758 goto out; 759 } 760 761 qpair->num_cmds = 0; 762 qpair->num_intr_handler_calls = 0; 763 qpair->num_retries = 0; 764 qpair->num_failures = 0; 765 qpair->num_ignored = 0; 766 qpair->cmd = (struct nvme_command *)queuemem; 767 qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz); 768 prpmem = (uint8_t *)(queuemem + cmdsz + cplsz); 769 qpair->cmd_bus_addr = queuemem_phys; 770 qpair->cpl_bus_addr = queuemem_phys + cmdsz; 771 prpmem_phys = queuemem_phys + cmdsz + cplsz; 772 773 callout_init(&qpair->timer, 1); 774 qpair->timer_armed = false; 775 qpair->recovery_state = RECOVERY_WAITING; 776 777 /* 778 * Calcuate the stride of the doorbell register. Many emulators set this 779 * value to correspond to a cache line. However, some hardware has set 780 * it to various small values. 781 */ 782 qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[0]) + 783 (qpair->id << (ctrlr->dstrd + 1)); 784 qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[0]) + 785 (qpair->id << (ctrlr->dstrd + 1)) + (1 << ctrlr->dstrd); 786 787 TAILQ_INIT(&qpair->free_tr); 788 TAILQ_INIT(&qpair->outstanding_tr); 789 STAILQ_INIT(&qpair->queued_req); 790 791 list_phys = prpmem_phys; 792 prp_list = prpmem; 793 for (i = 0; i < qpair->num_trackers; i++) { 794 if (list_phys + prpsz > prpmem_phys + prpmemsz) { 795 qpair->num_trackers = i; 796 break; 797 } 798 799 /* 800 * Make sure that the PRP list for this tracker doesn't 801 * overflow to another nvme page. 802 */ 803 if (trunc_page(list_phys) != 804 trunc_page(list_phys + prpsz - 1)) { 805 list_phys = roundup2(list_phys, ctrlr->page_size); 806 prp_list = 807 (uint8_t *)roundup2((uintptr_t)prp_list, ctrlr->page_size); 808 } 809 810 tr = malloc_domainset(sizeof(*tr), M_NVME, 811 DOMAINSET_PREF(qpair->domain), M_ZERO | M_WAITOK); 812 bus_dmamap_create(qpair->dma_tag_payload, 0, 813 &tr->payload_dma_map); 814 tr->cid = i; 815 tr->qpair = qpair; 816 tr->prp = (uint64_t *)prp_list; 817 tr->prp_bus_addr = list_phys; 818 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 819 list_phys += prpsz; 820 prp_list += prpsz; 821 } 822 823 if (qpair->num_trackers == 0) { 824 nvme_printf(ctrlr, "failed to allocate enough trackers\n"); 825 goto out; 826 } 827 828 qpair->act_tr = malloc_domainset(sizeof(struct nvme_tracker *) * 829 qpair->num_entries, M_NVME, DOMAINSET_PREF(qpair->domain), 830 M_ZERO | M_WAITOK); 831 832 if (ctrlr->msi_count > 1) { 833 /* 834 * MSI-X vector resource IDs start at 1, so we add one to 835 * the queue's vector to get the corresponding rid to use. 836 */ 837 qpair->rid = qpair->vector + 1; 838 839 qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 840 &qpair->rid, RF_ACTIVE); 841 if (qpair->res == NULL) { 842 nvme_printf(ctrlr, "unable to allocate MSI\n"); 843 goto out; 844 } 845 if (bus_setup_intr(ctrlr->dev, qpair->res, 846 INTR_TYPE_MISC | INTR_MPSAFE, NULL, 847 nvme_qpair_msi_handler, qpair, &qpair->tag) != 0) { 848 nvme_printf(ctrlr, "unable to setup MSI\n"); 849 goto out; 850 } 851 if (qpair->id == 0) { 852 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 853 "admin"); 854 } else { 855 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 856 "io%d", qpair->id - 1); 857 } 858 } 859 860 return (0); 861 862 out: 863 nvme_qpair_destroy(qpair); 864 return (ENOMEM); 865 } 866 867 static void 868 nvme_qpair_destroy(struct nvme_qpair *qpair) 869 { 870 struct nvme_tracker *tr; 871 872 callout_drain(&qpair->timer); 873 874 if (qpair->tag) { 875 bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag); 876 qpair->tag = NULL; 877 } 878 879 if (qpair->act_tr) { 880 free(qpair->act_tr, M_NVME); 881 qpair->act_tr = NULL; 882 } 883 884 while (!TAILQ_EMPTY(&qpair->free_tr)) { 885 tr = TAILQ_FIRST(&qpair->free_tr); 886 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 887 bus_dmamap_destroy(qpair->dma_tag_payload, 888 tr->payload_dma_map); 889 free(tr, M_NVME); 890 } 891 892 if (qpair->cmd != NULL) { 893 bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map); 894 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 895 qpair->queuemem_map); 896 qpair->cmd = NULL; 897 } 898 899 if (qpair->dma_tag) { 900 bus_dma_tag_destroy(qpair->dma_tag); 901 qpair->dma_tag = NULL; 902 } 903 904 if (qpair->dma_tag_payload) { 905 bus_dma_tag_destroy(qpair->dma_tag_payload); 906 qpair->dma_tag_payload = NULL; 907 } 908 909 if (mtx_initialized(&qpair->lock)) 910 mtx_destroy(&qpair->lock); 911 912 if (qpair->res) { 913 bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ, 914 rman_get_rid(qpair->res), qpair->res); 915 qpair->res = NULL; 916 } 917 } 918 919 static void 920 nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair) 921 { 922 struct nvme_tracker *tr; 923 924 tr = TAILQ_FIRST(&qpair->outstanding_tr); 925 while (tr != NULL) { 926 if (tr->req->cmd.opc == NVME_OPC_ASYNC_EVENT_REQUEST) { 927 nvme_qpair_manual_complete_tracker(tr, 928 NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0, 929 ERROR_PRINT_NONE); 930 tr = TAILQ_FIRST(&qpair->outstanding_tr); 931 } else { 932 tr = TAILQ_NEXT(tr, tailq); 933 } 934 } 935 } 936 937 void 938 nvme_admin_qpair_destroy(struct nvme_qpair *qpair) 939 { 940 941 nvme_admin_qpair_abort_aers(qpair); 942 nvme_qpair_destroy(qpair); 943 } 944 945 void 946 nvme_io_qpair_destroy(struct nvme_qpair *qpair) 947 { 948 949 nvme_qpair_destroy(qpair); 950 } 951 952 static void 953 nvme_qpair_timeout(void *arg) 954 { 955 struct nvme_qpair *qpair = arg; 956 struct nvme_controller *ctrlr = qpair->ctrlr; 957 struct nvme_tracker *tr; 958 sbintime_t now; 959 bool idle; 960 uint32_t csts; 961 uint8_t cfs; 962 963 mtx_lock(&qpair->lock); 964 idle = TAILQ_EMPTY(&qpair->outstanding_tr); 965 again: 966 switch (qpair->recovery_state) { 967 case RECOVERY_NONE: 968 if (idle) 969 break; 970 now = getsbinuptime(); 971 idle = true; 972 TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) { 973 if (tr->deadline == SBT_MAX) 974 continue; 975 idle = false; 976 if (now > tr->deadline) { 977 /* 978 * We're now passed our earliest deadline. We 979 * need to do expensive things to cope, but next 980 * time. Flag that and close the door to any 981 * further processing. 982 */ 983 qpair->recovery_state = RECOVERY_START; 984 nvme_printf(ctrlr, "RECOVERY_START %jd vs %jd\n", 985 (uintmax_t)now, (uintmax_t)tr->deadline); 986 break; 987 } 988 } 989 break; 990 case RECOVERY_START: 991 /* 992 * Read csts to get value of cfs - controller fatal status. 993 * If no fatal status, try to call the completion routine, and 994 * if completes transactions, report a missed interrupt and 995 * return (this may need to be rate limited). Otherwise, if 996 * aborts are enabled and the controller is not reporting 997 * fatal status, abort the command. Otherwise, just reset the 998 * controller and hope for the best. 999 */ 1000 csts = nvme_mmio_read_4(ctrlr, csts); 1001 cfs = (csts >> NVME_CSTS_REG_CFS_SHIFT) & NVME_CSTS_REG_CFS_MASK; 1002 if (cfs) { 1003 nvme_printf(ctrlr, "Controller in fatal status, resetting\n"); 1004 qpair->recovery_state = RECOVERY_RESET; 1005 goto again; 1006 } 1007 mtx_unlock(&qpair->lock); 1008 if (nvme_qpair_process_completions(qpair)) { 1009 nvme_printf(ctrlr, "Completions present in output without an interrupt\n"); 1010 qpair->recovery_state = RECOVERY_NONE; 1011 } else { 1012 nvme_printf(ctrlr, "timeout with nothing complete, resetting\n"); 1013 qpair->recovery_state = RECOVERY_RESET; 1014 mtx_lock(&qpair->lock); 1015 goto again; 1016 } 1017 mtx_lock(&qpair->lock); 1018 break; 1019 case RECOVERY_RESET: 1020 /* 1021 * If we get here due to a possible surprise hot-unplug event, 1022 * then we let nvme_ctrlr_reset confirm and fail the 1023 * controller. 1024 */ 1025 nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n", 1026 (csts == 0xffffffff) ? " and possible hot unplug" : 1027 (cfs ? " and fatal error status" : "")); 1028 nvme_printf(ctrlr, "RECOVERY_WAITING\n"); 1029 qpair->recovery_state = RECOVERY_WAITING; 1030 nvme_ctrlr_reset(ctrlr); 1031 break; 1032 case RECOVERY_WAITING: 1033 nvme_printf(ctrlr, "waiting\n"); 1034 break; 1035 } 1036 1037 /* 1038 * Rearm the timeout. 1039 */ 1040 if (!idle) { 1041 callout_schedule_sbt(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 0); 1042 } else { 1043 qpair->timer_armed = false; 1044 } 1045 mtx_unlock(&qpair->lock); 1046 } 1047 1048 /* 1049 * Submit the tracker to the hardware. Must already be in the 1050 * outstanding queue when called. 1051 */ 1052 void 1053 nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr) 1054 { 1055 struct nvme_request *req; 1056 struct nvme_controller *ctrlr; 1057 int timeout; 1058 1059 mtx_assert(&qpair->lock, MA_OWNED); 1060 1061 req = tr->req; 1062 req->cmd.cid = tr->cid; 1063 qpair->act_tr[tr->cid] = tr; 1064 ctrlr = qpair->ctrlr; 1065 1066 if (req->timeout) { 1067 if (req->cb_fn == nvme_completion_poll_cb) 1068 timeout = 1; 1069 else 1070 timeout = ctrlr->timeout_period; 1071 tr->deadline = getsbinuptime() + timeout * SBT_1S; 1072 if (!qpair->timer_armed) { 1073 qpair->timer_armed = true; 1074 callout_reset_sbt_on(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 1075 nvme_qpair_timeout, qpair, qpair->cpu, 0); 1076 } 1077 } else 1078 tr->deadline = SBT_MAX; 1079 1080 /* Copy the command from the tracker to the submission queue. */ 1081 memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd)); 1082 1083 if (++qpair->sq_tail == qpair->num_entries) 1084 qpair->sq_tail = 0; 1085 1086 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 1087 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1088 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 1089 qpair->sq_tdbl_off, qpair->sq_tail); 1090 qpair->num_cmds++; 1091 } 1092 1093 static void 1094 nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 1095 { 1096 struct nvme_tracker *tr = arg; 1097 uint32_t cur_nseg; 1098 1099 /* 1100 * If the mapping operation failed, return immediately. The caller 1101 * is responsible for detecting the error status and failing the 1102 * tracker manually. 1103 */ 1104 if (error != 0) { 1105 nvme_printf(tr->qpair->ctrlr, 1106 "nvme_payload_map err %d\n", error); 1107 return; 1108 } 1109 1110 /* 1111 * Note that we specified ctrlr->page_size for alignment and max 1112 * segment size when creating the bus dma tags. So here we can safely 1113 * just transfer each segment to its associated PRP entry. 1114 */ 1115 tr->req->cmd.prp1 = htole64(seg[0].ds_addr); 1116 1117 if (nseg == 2) { 1118 tr->req->cmd.prp2 = htole64(seg[1].ds_addr); 1119 } else if (nseg > 2) { 1120 cur_nseg = 1; 1121 tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr); 1122 while (cur_nseg < nseg) { 1123 tr->prp[cur_nseg-1] = 1124 htole64((uint64_t)seg[cur_nseg].ds_addr); 1125 cur_nseg++; 1126 } 1127 } else { 1128 /* 1129 * prp2 should not be used by the controller 1130 * since there is only one segment, but set 1131 * to 0 just to be safe. 1132 */ 1133 tr->req->cmd.prp2 = 0; 1134 } 1135 1136 bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map, 1137 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1138 nvme_qpair_submit_tracker(tr->qpair, tr); 1139 } 1140 1141 static void 1142 _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1143 { 1144 struct nvme_tracker *tr; 1145 int err = 0; 1146 1147 mtx_assert(&qpair->lock, MA_OWNED); 1148 1149 tr = TAILQ_FIRST(&qpair->free_tr); 1150 req->qpair = qpair; 1151 1152 if (tr == NULL || qpair->recovery_state != RECOVERY_NONE) { 1153 /* 1154 * No tracker is available, or the qpair is disabled due to 1155 * an in-progress controller-level reset or controller 1156 * failure. 1157 */ 1158 1159 if (qpair->ctrlr->is_failed) { 1160 /* 1161 * The controller has failed, so fail the request. 1162 */ 1163 nvme_qpair_manual_complete_request(qpair, req, 1164 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST); 1165 } else { 1166 /* 1167 * Put the request on the qpair's request queue to be 1168 * processed when a tracker frees up via a command 1169 * completion or when the controller reset is 1170 * completed. 1171 */ 1172 STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq); 1173 } 1174 return; 1175 } 1176 1177 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 1178 TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq); 1179 tr->deadline = SBT_MAX; 1180 tr->req = req; 1181 1182 switch (req->type) { 1183 case NVME_REQUEST_VADDR: 1184 KASSERT(req->payload_size <= qpair->ctrlr->max_xfer_size, 1185 ("payload_size (%d) exceeds max_xfer_size (%d)\n", 1186 req->payload_size, qpair->ctrlr->max_xfer_size)); 1187 err = bus_dmamap_load(tr->qpair->dma_tag_payload, 1188 tr->payload_dma_map, req->u.payload, req->payload_size, 1189 nvme_payload_map, tr, 0); 1190 if (err != 0) 1191 nvme_printf(qpair->ctrlr, 1192 "bus_dmamap_load returned 0x%x!\n", err); 1193 break; 1194 case NVME_REQUEST_NULL: 1195 nvme_qpair_submit_tracker(tr->qpair, tr); 1196 break; 1197 case NVME_REQUEST_BIO: 1198 KASSERT(req->u.bio->bio_bcount <= qpair->ctrlr->max_xfer_size, 1199 ("bio->bio_bcount (%jd) exceeds max_xfer_size (%d)\n", 1200 (intmax_t)req->u.bio->bio_bcount, 1201 qpair->ctrlr->max_xfer_size)); 1202 err = bus_dmamap_load_bio(tr->qpair->dma_tag_payload, 1203 tr->payload_dma_map, req->u.bio, nvme_payload_map, tr, 0); 1204 if (err != 0) 1205 nvme_printf(qpair->ctrlr, 1206 "bus_dmamap_load_bio returned 0x%x!\n", err); 1207 break; 1208 case NVME_REQUEST_CCB: 1209 err = bus_dmamap_load_ccb(tr->qpair->dma_tag_payload, 1210 tr->payload_dma_map, req->u.payload, 1211 nvme_payload_map, tr, 0); 1212 if (err != 0) 1213 nvme_printf(qpair->ctrlr, 1214 "bus_dmamap_load_ccb returned 0x%x!\n", err); 1215 break; 1216 default: 1217 panic("unknown nvme request type 0x%x\n", req->type); 1218 break; 1219 } 1220 1221 if (err != 0) { 1222 /* 1223 * The dmamap operation failed, so we manually fail the 1224 * tracker here with DATA_TRANSFER_ERROR status. 1225 * 1226 * nvme_qpair_manual_complete_tracker must not be called 1227 * with the qpair lock held. 1228 */ 1229 mtx_unlock(&qpair->lock); 1230 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1231 NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL); 1232 mtx_lock(&qpair->lock); 1233 } 1234 } 1235 1236 void 1237 nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1238 { 1239 1240 mtx_lock(&qpair->lock); 1241 _nvme_qpair_submit_request(qpair, req); 1242 mtx_unlock(&qpair->lock); 1243 } 1244 1245 static void 1246 nvme_qpair_enable(struct nvme_qpair *qpair) 1247 { 1248 mtx_assert(&qpair->lock, MA_OWNED); 1249 1250 qpair->recovery_state = RECOVERY_NONE; 1251 } 1252 1253 void 1254 nvme_qpair_reset(struct nvme_qpair *qpair) 1255 { 1256 1257 qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0; 1258 1259 /* 1260 * First time through the completion queue, HW will set phase 1261 * bit on completions to 1. So set this to 1 here, indicating 1262 * we're looking for a 1 to know which entries have completed. 1263 * we'll toggle the bit each time when the completion queue 1264 * rolls over. 1265 */ 1266 qpair->phase = 1; 1267 1268 memset(qpair->cmd, 0, 1269 qpair->num_entries * sizeof(struct nvme_command)); 1270 memset(qpair->cpl, 0, 1271 qpair->num_entries * sizeof(struct nvme_completion)); 1272 } 1273 1274 void 1275 nvme_admin_qpair_enable(struct nvme_qpair *qpair) 1276 { 1277 struct nvme_tracker *tr; 1278 struct nvme_tracker *tr_temp; 1279 1280 /* 1281 * Manually abort each outstanding admin command. Do not retry 1282 * admin commands found here, since they will be left over from 1283 * a controller reset and its likely the context in which the 1284 * command was issued no longer applies. 1285 */ 1286 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1287 nvme_printf(qpair->ctrlr, 1288 "aborting outstanding admin command\n"); 1289 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1290 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1291 } 1292 1293 mtx_lock(&qpair->lock); 1294 nvme_qpair_enable(qpair); 1295 mtx_unlock(&qpair->lock); 1296 } 1297 1298 void 1299 nvme_io_qpair_enable(struct nvme_qpair *qpair) 1300 { 1301 STAILQ_HEAD(, nvme_request) temp; 1302 struct nvme_tracker *tr; 1303 struct nvme_tracker *tr_temp; 1304 struct nvme_request *req; 1305 1306 /* 1307 * Manually abort each outstanding I/O. This normally results in a 1308 * retry, unless the retry count on the associated request has 1309 * reached its limit. 1310 */ 1311 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1312 nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n"); 1313 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1314 NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY); 1315 } 1316 1317 mtx_lock(&qpair->lock); 1318 1319 nvme_qpair_enable(qpair); 1320 1321 STAILQ_INIT(&temp); 1322 STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request); 1323 1324 while (!STAILQ_EMPTY(&temp)) { 1325 req = STAILQ_FIRST(&temp); 1326 STAILQ_REMOVE_HEAD(&temp, stailq); 1327 nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n"); 1328 nvme_qpair_print_command(qpair, &req->cmd); 1329 _nvme_qpair_submit_request(qpair, req); 1330 } 1331 1332 mtx_unlock(&qpair->lock); 1333 } 1334 1335 static void 1336 nvme_qpair_disable(struct nvme_qpair *qpair) 1337 { 1338 struct nvme_tracker *tr, *tr_temp; 1339 1340 mtx_lock(&qpair->lock); 1341 qpair->recovery_state = RECOVERY_WAITING; 1342 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1343 tr->deadline = SBT_MAX; 1344 } 1345 mtx_unlock(&qpair->lock); 1346 } 1347 1348 void 1349 nvme_admin_qpair_disable(struct nvme_qpair *qpair) 1350 { 1351 1352 nvme_qpair_disable(qpair); 1353 nvme_admin_qpair_abort_aers(qpair); 1354 } 1355 1356 void 1357 nvme_io_qpair_disable(struct nvme_qpair *qpair) 1358 { 1359 1360 nvme_qpair_disable(qpair); 1361 } 1362 1363 void 1364 nvme_qpair_fail(struct nvme_qpair *qpair) 1365 { 1366 struct nvme_tracker *tr; 1367 struct nvme_request *req; 1368 1369 if (!mtx_initialized(&qpair->lock)) 1370 return; 1371 1372 mtx_lock(&qpair->lock); 1373 1374 while (!STAILQ_EMPTY(&qpair->queued_req)) { 1375 req = STAILQ_FIRST(&qpair->queued_req); 1376 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 1377 nvme_printf(qpair->ctrlr, "failing queued i/o\n"); 1378 mtx_unlock(&qpair->lock); 1379 nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC, 1380 NVME_SC_ABORTED_BY_REQUEST); 1381 mtx_lock(&qpair->lock); 1382 } 1383 1384 /* Manually abort each outstanding I/O. */ 1385 while (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1386 tr = TAILQ_FIRST(&qpair->outstanding_tr); 1387 /* 1388 * Do not remove the tracker. The abort_tracker path will 1389 * do that for us. 1390 */ 1391 nvme_printf(qpair->ctrlr, "failing outstanding i/o\n"); 1392 mtx_unlock(&qpair->lock); 1393 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1394 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1395 mtx_lock(&qpair->lock); 1396 } 1397 1398 mtx_unlock(&qpair->lock); 1399 } 1400