1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/domainset.h> 36 #include <sys/proc.h> 37 38 #include <dev/pci/pcivar.h> 39 40 #include "nvme_private.h" 41 42 typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t; 43 #define DO_NOT_RETRY 1 44 45 static void _nvme_qpair_submit_request(struct nvme_qpair *qpair, 46 struct nvme_request *req); 47 static void nvme_qpair_destroy(struct nvme_qpair *qpair); 48 49 struct nvme_opcode_string { 50 uint16_t opc; 51 const char * str; 52 }; 53 54 static struct nvme_opcode_string admin_opcode[] = { 55 { NVME_OPC_DELETE_IO_SQ, "DELETE IO SQ" }, 56 { NVME_OPC_CREATE_IO_SQ, "CREATE IO SQ" }, 57 { NVME_OPC_GET_LOG_PAGE, "GET LOG PAGE" }, 58 { NVME_OPC_DELETE_IO_CQ, "DELETE IO CQ" }, 59 { NVME_OPC_CREATE_IO_CQ, "CREATE IO CQ" }, 60 { NVME_OPC_IDENTIFY, "IDENTIFY" }, 61 { NVME_OPC_ABORT, "ABORT" }, 62 { NVME_OPC_SET_FEATURES, "SET FEATURES" }, 63 { NVME_OPC_GET_FEATURES, "GET FEATURES" }, 64 { NVME_OPC_ASYNC_EVENT_REQUEST, "ASYNC EVENT REQUEST" }, 65 { NVME_OPC_FIRMWARE_ACTIVATE, "FIRMWARE ACTIVATE" }, 66 { NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD, "FIRMWARE IMAGE DOWNLOAD" }, 67 { NVME_OPC_DEVICE_SELF_TEST, "DEVICE SELF-TEST" }, 68 { NVME_OPC_NAMESPACE_ATTACHMENT, "NAMESPACE ATTACHMENT" }, 69 { NVME_OPC_KEEP_ALIVE, "KEEP ALIVE" }, 70 { NVME_OPC_DIRECTIVE_SEND, "DIRECTIVE SEND" }, 71 { NVME_OPC_DIRECTIVE_RECEIVE, "DIRECTIVE RECEIVE" }, 72 { NVME_OPC_VIRTUALIZATION_MANAGEMENT, "VIRTUALIZATION MANAGEMENT" }, 73 { NVME_OPC_NVME_MI_SEND, "NVME-MI SEND" }, 74 { NVME_OPC_NVME_MI_RECEIVE, "NVME-MI RECEIVE" }, 75 { NVME_OPC_DOORBELL_BUFFER_CONFIG, "DOORBELL BUFFER CONFIG" }, 76 { NVME_OPC_FORMAT_NVM, "FORMAT NVM" }, 77 { NVME_OPC_SECURITY_SEND, "SECURITY SEND" }, 78 { NVME_OPC_SECURITY_RECEIVE, "SECURITY RECEIVE" }, 79 { NVME_OPC_SANITIZE, "SANITIZE" }, 80 { NVME_OPC_GET_LBA_STATUS, "GET LBA STATUS" }, 81 { 0xFFFF, "ADMIN COMMAND" } 82 }; 83 84 static struct nvme_opcode_string io_opcode[] = { 85 { NVME_OPC_FLUSH, "FLUSH" }, 86 { NVME_OPC_WRITE, "WRITE" }, 87 { NVME_OPC_READ, "READ" }, 88 { NVME_OPC_WRITE_UNCORRECTABLE, "WRITE UNCORRECTABLE" }, 89 { NVME_OPC_COMPARE, "COMPARE" }, 90 { NVME_OPC_WRITE_ZEROES, "WRITE ZEROES" }, 91 { NVME_OPC_DATASET_MANAGEMENT, "DATASET MANAGEMENT" }, 92 { NVME_OPC_VERIFY, "VERIFY" }, 93 { NVME_OPC_RESERVATION_REGISTER, "RESERVATION REGISTER" }, 94 { NVME_OPC_RESERVATION_REPORT, "RESERVATION REPORT" }, 95 { NVME_OPC_RESERVATION_ACQUIRE, "RESERVATION ACQUIRE" }, 96 { NVME_OPC_RESERVATION_RELEASE, "RESERVATION RELEASE" }, 97 { 0xFFFF, "IO COMMAND" } 98 }; 99 100 static const char * 101 get_admin_opcode_string(uint16_t opc) 102 { 103 struct nvme_opcode_string *entry; 104 105 entry = admin_opcode; 106 107 while (entry->opc != 0xFFFF) { 108 if (entry->opc == opc) 109 return (entry->str); 110 entry++; 111 } 112 return (entry->str); 113 } 114 115 static const char * 116 get_io_opcode_string(uint16_t opc) 117 { 118 struct nvme_opcode_string *entry; 119 120 entry = io_opcode; 121 122 while (entry->opc != 0xFFFF) { 123 if (entry->opc == opc) 124 return (entry->str); 125 entry++; 126 } 127 return (entry->str); 128 } 129 130 static void 131 nvme_admin_qpair_print_command(struct nvme_qpair *qpair, 132 struct nvme_command *cmd) 133 { 134 135 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x " 136 "cdw10:%08x cdw11:%08x\n", 137 get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid, 138 le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11)); 139 } 140 141 static void 142 nvme_io_qpair_print_command(struct nvme_qpair *qpair, 143 struct nvme_command *cmd) 144 { 145 146 switch (cmd->opc) { 147 case NVME_OPC_WRITE: 148 case NVME_OPC_READ: 149 case NVME_OPC_WRITE_UNCORRECTABLE: 150 case NVME_OPC_COMPARE: 151 case NVME_OPC_WRITE_ZEROES: 152 case NVME_OPC_VERIFY: 153 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d " 154 "lba:%llu len:%d\n", 155 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid), 156 ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10), 157 (le32toh(cmd->cdw12) & 0xFFFF) + 1); 158 break; 159 case NVME_OPC_FLUSH: 160 case NVME_OPC_DATASET_MANAGEMENT: 161 case NVME_OPC_RESERVATION_REGISTER: 162 case NVME_OPC_RESERVATION_REPORT: 163 case NVME_OPC_RESERVATION_ACQUIRE: 164 case NVME_OPC_RESERVATION_RELEASE: 165 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n", 166 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid)); 167 break; 168 default: 169 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n", 170 get_io_opcode_string(cmd->opc), cmd->opc, qpair->id, 171 cmd->cid, le32toh(cmd->nsid)); 172 break; 173 } 174 } 175 176 static void 177 nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd) 178 { 179 if (qpair->id == 0) 180 nvme_admin_qpair_print_command(qpair, cmd); 181 else 182 nvme_io_qpair_print_command(qpair, cmd); 183 if (nvme_verbose_cmd_dump) { 184 nvme_printf(qpair->ctrlr, 185 "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n", 186 cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr, 187 (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2); 188 nvme_printf(qpair->ctrlr, 189 "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n", 190 cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14, 191 cmd->cdw15); 192 } 193 } 194 195 struct nvme_status_string { 196 uint16_t sc; 197 const char * str; 198 }; 199 200 static struct nvme_status_string generic_status[] = { 201 { NVME_SC_SUCCESS, "SUCCESS" }, 202 { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" }, 203 { NVME_SC_INVALID_FIELD, "INVALID_FIELD" }, 204 { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" }, 205 { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" }, 206 { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" }, 207 { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" }, 208 { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" }, 209 { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" }, 210 { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" }, 211 { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" }, 212 { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" }, 213 { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" }, 214 { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" }, 215 { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" }, 216 { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" }, 217 { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" }, 218 { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" }, 219 { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" }, 220 { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" }, 221 { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" }, 222 { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" }, 223 { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" }, 224 { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" }, 225 { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" }, 226 { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" }, 227 { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" }, 228 { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" }, 229 { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" }, 230 { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" }, 231 { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" }, 232 { NVME_SC_NAMESPACE_IS_WRITE_PROTECTED, "NAMESPACE IS WRITE PROTECTED" }, 233 { NVME_SC_COMMAND_INTERRUPTED, "COMMAND INTERRUPTED" }, 234 { NVME_SC_TRANSIENT_TRANSPORT_ERROR, "TRANSIENT TRANSPORT ERROR" }, 235 236 { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" }, 237 { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" }, 238 { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" }, 239 { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" }, 240 { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" }, 241 { 0xFFFF, "GENERIC" } 242 }; 243 244 static struct nvme_status_string command_specific_status[] = { 245 { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" }, 246 { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" }, 247 { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" }, 248 { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" }, 249 { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" }, 250 { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" }, 251 { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" }, 252 { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" }, 253 { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" }, 254 { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" }, 255 { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" }, 256 { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" }, 257 { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" }, 258 { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" }, 259 { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" }, 260 { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" }, 261 { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" }, 262 { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" }, 263 { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" }, 264 { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" }, 265 { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" }, 266 { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" }, 267 { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" }, 268 { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" }, 269 { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" }, 270 { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" }, 271 { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" }, 272 { NVME_SC_SELF_TEST_IN_PROGRESS, "DEVICE SELF-TEST IN PROGRESS" }, 273 { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" }, 274 { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" }, 275 { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" }, 276 { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" }, 277 { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" }, 278 { NVME_SC_SANITIZE_PROHIBITED_WPMRE, "SANITIZE PROHIBITED WRITE PERSISTENT MEMORY REGION ENABLED" }, 279 { NVME_SC_ANA_GROUP_ID_INVALID, "ANA GROUP IDENTIFIED INVALID" }, 280 { NVME_SC_ANA_ATTACH_FAILED, "ANA ATTACH FAILED" }, 281 282 { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" }, 283 { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" }, 284 { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" }, 285 { 0xFFFF, "COMMAND SPECIFIC" } 286 }; 287 288 static struct nvme_status_string media_error_status[] = { 289 { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" }, 290 { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" }, 291 { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" }, 292 { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" }, 293 { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" }, 294 { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" }, 295 { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" }, 296 { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" }, 297 { 0xFFFF, "MEDIA ERROR" } 298 }; 299 300 static struct nvme_status_string path_related_status[] = { 301 { NVME_SC_INTERNAL_PATH_ERROR, "INTERNAL PATH ERROR" }, 302 { NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS, "ASYMMETRIC ACCESS PERSISTENT LOSS" }, 303 { NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE, "ASYMMETRIC ACCESS INACCESSIBLE" }, 304 { NVME_SC_ASYMMETRIC_ACCESS_TRANSITION, "ASYMMETRIC ACCESS TRANSITION" }, 305 { NVME_SC_CONTROLLER_PATHING_ERROR, "CONTROLLER PATHING ERROR" }, 306 { NVME_SC_HOST_PATHING_ERROR, "HOST PATHING ERROR" }, 307 { NVME_SC_COMMAND_ABOTHED_BY_HOST, "COMMAND ABOTHED BY HOST" }, 308 { 0xFFFF, "PATH RELATED" }, 309 }; 310 311 static const char * 312 get_status_string(uint16_t sct, uint16_t sc) 313 { 314 struct nvme_status_string *entry; 315 316 switch (sct) { 317 case NVME_SCT_GENERIC: 318 entry = generic_status; 319 break; 320 case NVME_SCT_COMMAND_SPECIFIC: 321 entry = command_specific_status; 322 break; 323 case NVME_SCT_MEDIA_ERROR: 324 entry = media_error_status; 325 break; 326 case NVME_SCT_PATH_RELATED: 327 entry = path_related_status; 328 break; 329 case NVME_SCT_VENDOR_SPECIFIC: 330 return ("VENDOR SPECIFIC"); 331 default: 332 return ("RESERVED"); 333 } 334 335 while (entry->sc != 0xFFFF) { 336 if (entry->sc == sc) 337 return (entry->str); 338 entry++; 339 } 340 return (entry->str); 341 } 342 343 static void 344 nvme_qpair_print_completion(struct nvme_qpair *qpair, 345 struct nvme_completion *cpl) 346 { 347 uint16_t sct, sc; 348 349 sct = NVME_STATUS_GET_SCT(cpl->status); 350 sc = NVME_STATUS_GET_SC(cpl->status); 351 352 nvme_printf(qpair->ctrlr, "%s (%02x/%02x) sqid:%d cid:%d cdw0:%x\n", 353 get_status_string(sct, sc), sct, sc, cpl->sqid, cpl->cid, 354 cpl->cdw0); 355 } 356 357 static bool 358 nvme_completion_is_retry(const struct nvme_completion *cpl) 359 { 360 uint8_t sct, sc, dnr; 361 362 sct = NVME_STATUS_GET_SCT(cpl->status); 363 sc = NVME_STATUS_GET_SC(cpl->status); 364 dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */ 365 366 /* 367 * TODO: spec is not clear how commands that are aborted due 368 * to TLER will be marked. So for now, it seems 369 * NAMESPACE_NOT_READY is the only case where we should 370 * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST 371 * set the DNR bit correctly since the driver controls that. 372 */ 373 switch (sct) { 374 case NVME_SCT_GENERIC: 375 switch (sc) { 376 case NVME_SC_ABORTED_BY_REQUEST: 377 case NVME_SC_NAMESPACE_NOT_READY: 378 if (dnr) 379 return (0); 380 else 381 return (1); 382 case NVME_SC_INVALID_OPCODE: 383 case NVME_SC_INVALID_FIELD: 384 case NVME_SC_COMMAND_ID_CONFLICT: 385 case NVME_SC_DATA_TRANSFER_ERROR: 386 case NVME_SC_ABORTED_POWER_LOSS: 387 case NVME_SC_INTERNAL_DEVICE_ERROR: 388 case NVME_SC_ABORTED_SQ_DELETION: 389 case NVME_SC_ABORTED_FAILED_FUSED: 390 case NVME_SC_ABORTED_MISSING_FUSED: 391 case NVME_SC_INVALID_NAMESPACE_OR_FORMAT: 392 case NVME_SC_COMMAND_SEQUENCE_ERROR: 393 case NVME_SC_LBA_OUT_OF_RANGE: 394 case NVME_SC_CAPACITY_EXCEEDED: 395 default: 396 return (0); 397 } 398 case NVME_SCT_COMMAND_SPECIFIC: 399 case NVME_SCT_MEDIA_ERROR: 400 return (0); 401 case NVME_SCT_PATH_RELATED: 402 switch (sc) { 403 case NVME_SC_INTERNAL_PATH_ERROR: 404 if (dnr) 405 return (0); 406 else 407 return (1); 408 default: 409 return (0); 410 } 411 case NVME_SCT_VENDOR_SPECIFIC: 412 default: 413 return (0); 414 } 415 } 416 417 static void 418 nvme_qpair_complete_tracker(struct nvme_tracker *tr, 419 struct nvme_completion *cpl, error_print_t print_on_error) 420 { 421 struct nvme_qpair * qpair = tr->qpair; 422 struct nvme_request *req; 423 bool retry, error, retriable; 424 425 req = tr->req; 426 error = nvme_completion_is_error(cpl); 427 retriable = nvme_completion_is_retry(cpl); 428 retry = error && retriable && req->retries < nvme_retry_count; 429 if (retry) 430 qpair->num_retries++; 431 if (error && req->retries >= nvme_retry_count && retriable) 432 qpair->num_failures++; 433 434 if (error && (print_on_error == ERROR_PRINT_ALL || 435 (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) { 436 nvme_qpair_print_command(qpair, &req->cmd); 437 nvme_qpair_print_completion(qpair, cpl); 438 } 439 440 qpair->act_tr[cpl->cid] = NULL; 441 442 KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n")); 443 444 if (!retry) { 445 if (req->type != NVME_REQUEST_NULL) { 446 bus_dmamap_sync(qpair->dma_tag_payload, 447 tr->payload_dma_map, 448 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 449 } 450 if (req->cb_fn) 451 req->cb_fn(req->cb_arg, cpl); 452 } 453 454 mtx_lock(&qpair->lock); 455 456 if (retry) { 457 req->retries++; 458 nvme_qpair_submit_tracker(qpair, tr); 459 } else { 460 if (req->type != NVME_REQUEST_NULL) { 461 bus_dmamap_unload(qpair->dma_tag_payload, 462 tr->payload_dma_map); 463 } 464 465 nvme_free_request(req); 466 tr->req = NULL; 467 468 TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq); 469 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 470 471 /* 472 * If the controller is in the middle of resetting, don't 473 * try to submit queued requests here - let the reset logic 474 * handle that instead. 475 */ 476 if (!STAILQ_EMPTY(&qpair->queued_req) && 477 !qpair->ctrlr->is_resetting) { 478 req = STAILQ_FIRST(&qpair->queued_req); 479 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 480 _nvme_qpair_submit_request(qpair, req); 481 } 482 } 483 484 mtx_unlock(&qpair->lock); 485 } 486 487 static void 488 nvme_qpair_manual_complete_tracker( 489 struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr, 490 error_print_t print_on_error) 491 { 492 struct nvme_completion cpl; 493 494 memset(&cpl, 0, sizeof(cpl)); 495 496 struct nvme_qpair * qpair = tr->qpair; 497 498 cpl.sqid = qpair->id; 499 cpl.cid = tr->cid; 500 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 501 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 502 cpl.status |= (dnr & NVME_STATUS_DNR_MASK) << NVME_STATUS_DNR_SHIFT; 503 nvme_qpair_complete_tracker(tr, &cpl, print_on_error); 504 } 505 506 void 507 nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 508 struct nvme_request *req, uint32_t sct, uint32_t sc) 509 { 510 struct nvme_completion cpl; 511 bool error; 512 513 memset(&cpl, 0, sizeof(cpl)); 514 cpl.sqid = qpair->id; 515 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 516 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 517 518 error = nvme_completion_is_error(&cpl); 519 520 if (error) { 521 nvme_qpair_print_command(qpair, &req->cmd); 522 nvme_qpair_print_completion(qpair, &cpl); 523 } 524 525 if (req->cb_fn) 526 req->cb_fn(req->cb_arg, &cpl); 527 528 nvme_free_request(req); 529 } 530 531 bool 532 nvme_qpair_process_completions(struct nvme_qpair *qpair) 533 { 534 struct nvme_tracker *tr; 535 struct nvme_completion cpl; 536 int done = 0; 537 bool in_panic = dumping || SCHEDULER_STOPPED(); 538 539 /* 540 * qpair is not enabled, likely because a controller reset is is in 541 * progress. Ignore the interrupt - any I/O that was associated with 542 * this interrupt will get retried when the reset is complete. Any 543 * pending completions for when we're in startup will be completed 544 * as soon as initialization is complete and we start sending commands 545 * to the device. 546 */ 547 if (qpair->recovery_state != RECOVERY_NONE) { 548 qpair->num_ignored++; 549 return (false); 550 } 551 552 /* 553 * Sanity check initialization. After we reset the hardware, the phase 554 * is defined to be 1. So if we get here with zero prior calls and the 555 * phase is 0, it means that we've lost a race between the 556 * initialization and the ISR running. With the phase wrong, we'll 557 * process a bunch of completions that aren't really completions leading 558 * to a KASSERT below. 559 */ 560 KASSERT(!(qpair->num_intr_handler_calls == 0 && qpair->phase == 0), 561 ("%s: Phase wrong for first interrupt call.", 562 device_get_nameunit(qpair->ctrlr->dev))); 563 564 qpair->num_intr_handler_calls++; 565 566 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 567 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 568 /* 569 * A panic can stop the CPU this routine is running on at any point. If 570 * we're called during a panic, complete the sq_head wrap protocol for 571 * the case where we are interrupted just after the increment at 1 572 * below, but before we can reset cq_head to zero at 2. Also cope with 573 * the case where we do the zero at 2, but may or may not have done the 574 * phase adjustment at step 3. The panic machinery flushes all pending 575 * memory writes, so we can make these strong ordering assumptions 576 * that would otherwise be unwise if we were racing in real time. 577 */ 578 if (__predict_false(in_panic)) { 579 if (qpair->cq_head == qpair->num_entries) { 580 /* 581 * Here we know that we need to zero cq_head and then negate 582 * the phase, which hasn't been assigned if cq_head isn't 583 * zero due to the atomic_store_rel. 584 */ 585 qpair->cq_head = 0; 586 qpair->phase = !qpair->phase; 587 } else if (qpair->cq_head == 0) { 588 /* 589 * In this case, we know that the assignment at 2 590 * happened below, but we don't know if it 3 happened or 591 * not. To do this, we look at the last completion 592 * entry and set the phase to the opposite phase 593 * that it has. This gets us back in sync 594 */ 595 cpl = qpair->cpl[qpair->num_entries - 1]; 596 nvme_completion_swapbytes(&cpl); 597 qpair->phase = !NVME_STATUS_GET_P(cpl.status); 598 } 599 } 600 601 while (1) { 602 uint16_t status; 603 604 /* 605 * We need to do this dance to avoid a race between the host and 606 * the device where the device overtakes the host while the host 607 * is reading this record, leaving the status field 'new' and 608 * the sqhd and cid fields potentially stale. If the phase 609 * doesn't match, that means status hasn't yet been updated and 610 * we'll get any pending changes next time. It also means that 611 * the phase must be the same the second time. We have to sync 612 * before reading to ensure any bouncing completes. 613 */ 614 status = le16toh(qpair->cpl[qpair->cq_head].status); 615 if (NVME_STATUS_GET_P(status) != qpair->phase) 616 break; 617 618 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 619 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 620 cpl = qpair->cpl[qpair->cq_head]; 621 nvme_completion_swapbytes(&cpl); 622 623 KASSERT( 624 NVME_STATUS_GET_P(status) == NVME_STATUS_GET_P(cpl.status), 625 ("Phase unexpectedly inconsistent")); 626 627 if (cpl.cid < qpair->num_trackers) 628 tr = qpair->act_tr[cpl.cid]; 629 else 630 tr = NULL; 631 632 done++; 633 if (tr != NULL) { 634 nvme_qpair_complete_tracker(tr, &cpl, ERROR_PRINT_ALL); 635 qpair->sq_head = cpl.sqhd; 636 } else if (!in_panic) { 637 /* 638 * A missing tracker is normally an error. However, a 639 * panic can stop the CPU this routine is running on 640 * after completing an I/O but before updating 641 * qpair->cq_head at 1 below. Later, we re-enter this 642 * routine to poll I/O associated with the kernel 643 * dump. We find that the tr has been set to null before 644 * calling the completion routine. If it hasn't 645 * completed (or it triggers a panic), then '1' below 646 * won't have updated cq_head. Rather than panic again, 647 * ignore this condition because it's not unexpected. 648 */ 649 nvme_printf(qpair->ctrlr, 650 "cpl (cid = %u) does not map to outstanding cmd\n", 651 cpl.cid); 652 /* nvme_dump_completion expects device endianess */ 653 nvme_dump_completion(&qpair->cpl[qpair->cq_head]); 654 KASSERT(0, ("received completion for unknown cmd")); 655 } 656 657 /* 658 * There's a number of races with the following (see above) when 659 * the system panics. We compensate for each one of them by 660 * using the atomic store to force strong ordering (at least when 661 * viewed in the aftermath of a panic). 662 */ 663 if (++qpair->cq_head == qpair->num_entries) { /* 1 */ 664 atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */ 665 qpair->phase = !qpair->phase; /* 3 */ 666 } 667 } 668 669 if (done != 0) { 670 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 671 qpair->cq_hdbl_off, qpair->cq_head); 672 } 673 674 return (done != 0); 675 } 676 677 static void 678 nvme_qpair_msi_handler(void *arg) 679 { 680 struct nvme_qpair *qpair = arg; 681 682 nvme_qpair_process_completions(qpair); 683 } 684 685 int 686 nvme_qpair_construct(struct nvme_qpair *qpair, 687 uint32_t num_entries, uint32_t num_trackers, 688 struct nvme_controller *ctrlr) 689 { 690 struct nvme_tracker *tr; 691 size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz; 692 uint64_t queuemem_phys, prpmem_phys, list_phys; 693 uint8_t *queuemem, *prpmem, *prp_list; 694 int i, err; 695 696 qpair->vector = ctrlr->msi_count > 1 ? qpair->id : 0; 697 qpair->num_entries = num_entries; 698 qpair->num_trackers = num_trackers; 699 qpair->ctrlr = ctrlr; 700 701 mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF); 702 703 /* Note: NVMe PRP format is restricted to 4-byte alignment. */ 704 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 705 4, PAGE_SIZE, BUS_SPACE_MAXADDR, 706 BUS_SPACE_MAXADDR, NULL, NULL, ctrlr->max_xfer_size, 707 btoc(ctrlr->max_xfer_size) + 1, PAGE_SIZE, 0, 708 NULL, NULL, &qpair->dma_tag_payload); 709 if (err != 0) { 710 nvme_printf(ctrlr, "payload tag create failed %d\n", err); 711 goto out; 712 } 713 714 /* 715 * Each component must be page aligned, and individual PRP lists 716 * cannot cross a page boundary. 717 */ 718 cmdsz = qpair->num_entries * sizeof(struct nvme_command); 719 cmdsz = roundup2(cmdsz, PAGE_SIZE); 720 cplsz = qpair->num_entries * sizeof(struct nvme_completion); 721 cplsz = roundup2(cplsz, PAGE_SIZE); 722 /* 723 * For commands requiring more than 2 PRP entries, one PRP will be 724 * embedded in the command (prp1), and the rest of the PRP entries 725 * will be in a list pointed to by the command (prp2). 726 */ 727 prpsz = sizeof(uint64_t) * btoc(ctrlr->max_xfer_size); 728 prpmemsz = qpair->num_trackers * prpsz; 729 allocsz = cmdsz + cplsz + prpmemsz; 730 731 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 732 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 733 allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag); 734 if (err != 0) { 735 nvme_printf(ctrlr, "tag create failed %d\n", err); 736 goto out; 737 } 738 bus_dma_tag_set_domain(qpair->dma_tag, qpair->domain); 739 740 if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem, 741 BUS_DMA_COHERENT | BUS_DMA_NOWAIT, &qpair->queuemem_map)) { 742 nvme_printf(ctrlr, "failed to alloc qpair memory\n"); 743 goto out; 744 } 745 746 if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map, 747 queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) { 748 nvme_printf(ctrlr, "failed to load qpair memory\n"); 749 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 750 qpair->queuemem_map); 751 goto out; 752 } 753 754 qpair->num_cmds = 0; 755 qpair->num_intr_handler_calls = 0; 756 qpair->num_retries = 0; 757 qpair->num_failures = 0; 758 qpair->num_ignored = 0; 759 qpair->cmd = (struct nvme_command *)queuemem; 760 qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz); 761 prpmem = (uint8_t *)(queuemem + cmdsz + cplsz); 762 qpair->cmd_bus_addr = queuemem_phys; 763 qpair->cpl_bus_addr = queuemem_phys + cmdsz; 764 prpmem_phys = queuemem_phys + cmdsz + cplsz; 765 766 callout_init(&qpair->timer, 1); 767 qpair->timer_armed = false; 768 qpair->recovery_state = RECOVERY_WAITING; 769 770 /* 771 * Calcuate the stride of the doorbell register. Many emulators set this 772 * value to correspond to a cache line. However, some hardware has set 773 * it to various small values. 774 */ 775 qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[0]) + 776 (qpair->id << (ctrlr->dstrd + 1)); 777 qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[0]) + 778 (qpair->id << (ctrlr->dstrd + 1)) + (1 << ctrlr->dstrd); 779 780 TAILQ_INIT(&qpair->free_tr); 781 TAILQ_INIT(&qpair->outstanding_tr); 782 STAILQ_INIT(&qpair->queued_req); 783 784 list_phys = prpmem_phys; 785 prp_list = prpmem; 786 for (i = 0; i < qpair->num_trackers; i++) { 787 if (list_phys + prpsz > prpmem_phys + prpmemsz) { 788 qpair->num_trackers = i; 789 break; 790 } 791 792 /* 793 * Make sure that the PRP list for this tracker doesn't 794 * overflow to another page. 795 */ 796 if (trunc_page(list_phys) != 797 trunc_page(list_phys + prpsz - 1)) { 798 list_phys = roundup2(list_phys, PAGE_SIZE); 799 prp_list = 800 (uint8_t *)roundup2((uintptr_t)prp_list, PAGE_SIZE); 801 } 802 803 tr = malloc_domainset(sizeof(*tr), M_NVME, 804 DOMAINSET_PREF(qpair->domain), M_ZERO | M_WAITOK); 805 bus_dmamap_create(qpair->dma_tag_payload, 0, 806 &tr->payload_dma_map); 807 tr->cid = i; 808 tr->qpair = qpair; 809 tr->prp = (uint64_t *)prp_list; 810 tr->prp_bus_addr = list_phys; 811 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 812 list_phys += prpsz; 813 prp_list += prpsz; 814 } 815 816 if (qpair->num_trackers == 0) { 817 nvme_printf(ctrlr, "failed to allocate enough trackers\n"); 818 goto out; 819 } 820 821 qpair->act_tr = malloc_domainset(sizeof(struct nvme_tracker *) * 822 qpair->num_entries, M_NVME, DOMAINSET_PREF(qpair->domain), 823 M_ZERO | M_WAITOK); 824 825 if (ctrlr->msi_count > 1) { 826 /* 827 * MSI-X vector resource IDs start at 1, so we add one to 828 * the queue's vector to get the corresponding rid to use. 829 */ 830 qpair->rid = qpair->vector + 1; 831 832 qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 833 &qpair->rid, RF_ACTIVE); 834 if (qpair->res == NULL) { 835 nvme_printf(ctrlr, "unable to allocate MSI\n"); 836 goto out; 837 } 838 if (bus_setup_intr(ctrlr->dev, qpair->res, 839 INTR_TYPE_MISC | INTR_MPSAFE, NULL, 840 nvme_qpair_msi_handler, qpair, &qpair->tag) != 0) { 841 nvme_printf(ctrlr, "unable to setup MSI\n"); 842 goto out; 843 } 844 if (qpair->id == 0) { 845 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 846 "admin"); 847 } else { 848 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 849 "io%d", qpair->id - 1); 850 } 851 } 852 853 return (0); 854 855 out: 856 nvme_qpair_destroy(qpair); 857 return (ENOMEM); 858 } 859 860 static void 861 nvme_qpair_destroy(struct nvme_qpair *qpair) 862 { 863 struct nvme_tracker *tr; 864 865 callout_drain(&qpair->timer); 866 867 if (qpair->tag) { 868 bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag); 869 qpair->tag = NULL; 870 } 871 872 if (qpair->act_tr) { 873 free(qpair->act_tr, M_NVME); 874 qpair->act_tr = NULL; 875 } 876 877 while (!TAILQ_EMPTY(&qpair->free_tr)) { 878 tr = TAILQ_FIRST(&qpair->free_tr); 879 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 880 bus_dmamap_destroy(qpair->dma_tag_payload, 881 tr->payload_dma_map); 882 free(tr, M_NVME); 883 } 884 885 if (qpair->cmd != NULL) { 886 bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map); 887 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 888 qpair->queuemem_map); 889 qpair->cmd = NULL; 890 } 891 892 if (qpair->dma_tag) { 893 bus_dma_tag_destroy(qpair->dma_tag); 894 qpair->dma_tag = NULL; 895 } 896 897 if (qpair->dma_tag_payload) { 898 bus_dma_tag_destroy(qpair->dma_tag_payload); 899 qpair->dma_tag_payload = NULL; 900 } 901 902 if (mtx_initialized(&qpair->lock)) 903 mtx_destroy(&qpair->lock); 904 905 if (qpair->res) { 906 bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ, 907 rman_get_rid(qpair->res), qpair->res); 908 qpair->res = NULL; 909 } 910 } 911 912 static void 913 nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair) 914 { 915 struct nvme_tracker *tr; 916 917 tr = TAILQ_FIRST(&qpair->outstanding_tr); 918 while (tr != NULL) { 919 if (tr->req->cmd.opc == NVME_OPC_ASYNC_EVENT_REQUEST) { 920 nvme_qpair_manual_complete_tracker(tr, 921 NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0, 922 ERROR_PRINT_NONE); 923 tr = TAILQ_FIRST(&qpair->outstanding_tr); 924 } else { 925 tr = TAILQ_NEXT(tr, tailq); 926 } 927 } 928 } 929 930 void 931 nvme_admin_qpair_destroy(struct nvme_qpair *qpair) 932 { 933 934 nvme_admin_qpair_abort_aers(qpair); 935 nvme_qpair_destroy(qpair); 936 } 937 938 void 939 nvme_io_qpair_destroy(struct nvme_qpair *qpair) 940 { 941 942 nvme_qpair_destroy(qpair); 943 } 944 945 static void 946 nvme_qpair_timeout(void *arg) 947 { 948 struct nvme_qpair *qpair = arg; 949 struct nvme_controller *ctrlr = qpair->ctrlr; 950 struct nvme_tracker *tr; 951 sbintime_t now; 952 bool idle; 953 uint32_t csts; 954 uint8_t cfs; 955 956 mtx_lock(&qpair->lock); 957 idle = TAILQ_EMPTY(&qpair->outstanding_tr); 958 again: 959 switch (qpair->recovery_state) { 960 case RECOVERY_NONE: 961 if (idle) 962 break; 963 now = getsbinuptime(); 964 idle = true; 965 TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) { 966 if (tr->deadline == SBT_MAX) 967 continue; 968 idle = false; 969 if (now > tr->deadline) { 970 /* 971 * We're now passed our earliest deadline. We 972 * need to do expensive things to cope, but next 973 * time. Flag that and close the door to any 974 * further processing. 975 */ 976 qpair->recovery_state = RECOVERY_START; 977 nvme_printf(ctrlr, "RECOVERY_START %jd vs %jd\n", 978 (uintmax_t)now, (uintmax_t)tr->deadline); 979 break; 980 } 981 } 982 break; 983 case RECOVERY_START: 984 /* 985 * Read csts to get value of cfs - controller fatal status. 986 * If no fatal status, try to call the completion routine, and 987 * if completes transactions, report a missed interrupt and 988 * return (this may need to be rate limited). Otherwise, if 989 * aborts are enabled and the controller is not reporting 990 * fatal status, abort the command. Otherwise, just reset the 991 * controller and hope for the best. 992 */ 993 csts = nvme_mmio_read_4(ctrlr, csts); 994 cfs = (csts >> NVME_CSTS_REG_CFS_SHIFT) & NVME_CSTS_REG_CFS_MASK; 995 if (cfs) { 996 nvme_printf(ctrlr, "Controller in fatal status, resetting\n"); 997 qpair->recovery_state = RECOVERY_RESET; 998 goto again; 999 } 1000 mtx_unlock(&qpair->lock); 1001 if (nvme_qpair_process_completions(qpair)) { 1002 nvme_printf(ctrlr, "Completions present in output without an interrupt\n"); 1003 qpair->recovery_state = RECOVERY_NONE; 1004 } else { 1005 nvme_printf(ctrlr, "timeout with nothing complete, resetting\n"); 1006 qpair->recovery_state = RECOVERY_RESET; 1007 mtx_lock(&qpair->lock); 1008 goto again; 1009 } 1010 mtx_lock(&qpair->lock); 1011 break; 1012 case RECOVERY_RESET: 1013 /* 1014 * If we get here due to a possible surprise hot-unplug event, 1015 * then we let nvme_ctrlr_reset confirm and fail the 1016 * controller. 1017 */ 1018 nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n", 1019 (csts == 0xffffffff) ? " and possible hot unplug" : 1020 (cfs ? " and fatal error status" : "")); 1021 nvme_printf(ctrlr, "RECOVERY_WAITING\n"); 1022 qpair->recovery_state = RECOVERY_WAITING; 1023 nvme_ctrlr_reset(ctrlr); 1024 break; 1025 case RECOVERY_WAITING: 1026 nvme_printf(ctrlr, "waiting\n"); 1027 break; 1028 } 1029 1030 /* 1031 * Rearm the timeout. 1032 */ 1033 if (!idle) { 1034 callout_schedule_sbt(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 0); 1035 } else { 1036 qpair->timer_armed = false; 1037 } 1038 mtx_unlock(&qpair->lock); 1039 } 1040 1041 /* 1042 * Submit the tracker to the hardware. Must already be in the 1043 * outstanding queue when called. 1044 */ 1045 void 1046 nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr) 1047 { 1048 struct nvme_request *req; 1049 struct nvme_controller *ctrlr; 1050 int timeout; 1051 1052 mtx_assert(&qpair->lock, MA_OWNED); 1053 1054 req = tr->req; 1055 req->cmd.cid = tr->cid; 1056 qpair->act_tr[tr->cid] = tr; 1057 ctrlr = qpair->ctrlr; 1058 1059 if (req->timeout) { 1060 if (req->cb_fn == nvme_completion_poll_cb) 1061 timeout = 1; 1062 else 1063 timeout = ctrlr->timeout_period; 1064 tr->deadline = getsbinuptime() + timeout * SBT_1S; 1065 if (!qpair->timer_armed) { 1066 qpair->timer_armed = true; 1067 callout_reset_sbt_on(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 1068 nvme_qpair_timeout, qpair, qpair->cpu, 0); 1069 } 1070 } else 1071 tr->deadline = SBT_MAX; 1072 1073 /* Copy the command from the tracker to the submission queue. */ 1074 memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd)); 1075 1076 if (++qpair->sq_tail == qpair->num_entries) 1077 qpair->sq_tail = 0; 1078 1079 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 1080 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1081 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 1082 qpair->sq_tdbl_off, qpair->sq_tail); 1083 qpair->num_cmds++; 1084 } 1085 1086 static void 1087 nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 1088 { 1089 struct nvme_tracker *tr = arg; 1090 uint32_t cur_nseg; 1091 1092 /* 1093 * If the mapping operation failed, return immediately. The caller 1094 * is responsible for detecting the error status and failing the 1095 * tracker manually. 1096 */ 1097 if (error != 0) { 1098 nvme_printf(tr->qpair->ctrlr, 1099 "nvme_payload_map err %d\n", error); 1100 return; 1101 } 1102 1103 /* 1104 * Note that we specified PAGE_SIZE for alignment and max 1105 * segment size when creating the bus dma tags. So here 1106 * we can safely just transfer each segment to its 1107 * associated PRP entry. 1108 */ 1109 tr->req->cmd.prp1 = htole64(seg[0].ds_addr); 1110 1111 if (nseg == 2) { 1112 tr->req->cmd.prp2 = htole64(seg[1].ds_addr); 1113 } else if (nseg > 2) { 1114 cur_nseg = 1; 1115 tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr); 1116 while (cur_nseg < nseg) { 1117 tr->prp[cur_nseg-1] = 1118 htole64((uint64_t)seg[cur_nseg].ds_addr); 1119 cur_nseg++; 1120 } 1121 } else { 1122 /* 1123 * prp2 should not be used by the controller 1124 * since there is only one segment, but set 1125 * to 0 just to be safe. 1126 */ 1127 tr->req->cmd.prp2 = 0; 1128 } 1129 1130 bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map, 1131 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1132 nvme_qpair_submit_tracker(tr->qpair, tr); 1133 } 1134 1135 static void 1136 _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1137 { 1138 struct nvme_tracker *tr; 1139 int err = 0; 1140 1141 mtx_assert(&qpair->lock, MA_OWNED); 1142 1143 tr = TAILQ_FIRST(&qpair->free_tr); 1144 req->qpair = qpair; 1145 1146 if (tr == NULL || qpair->recovery_state != RECOVERY_NONE) { 1147 /* 1148 * No tracker is available, or the qpair is disabled due to 1149 * an in-progress controller-level reset or controller 1150 * failure. 1151 */ 1152 1153 if (qpair->ctrlr->is_failed) { 1154 /* 1155 * The controller has failed, so fail the request. 1156 */ 1157 nvme_qpair_manual_complete_request(qpair, req, 1158 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST); 1159 } else { 1160 /* 1161 * Put the request on the qpair's request queue to be 1162 * processed when a tracker frees up via a command 1163 * completion or when the controller reset is 1164 * completed. 1165 */ 1166 STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq); 1167 } 1168 return; 1169 } 1170 1171 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 1172 TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq); 1173 if (!qpair->timer_armed) 1174 tr->deadline = SBT_MAX; 1175 tr->req = req; 1176 1177 switch (req->type) { 1178 case NVME_REQUEST_VADDR: 1179 KASSERT(req->payload_size <= qpair->ctrlr->max_xfer_size, 1180 ("payload_size (%d) exceeds max_xfer_size (%d)\n", 1181 req->payload_size, qpair->ctrlr->max_xfer_size)); 1182 err = bus_dmamap_load(tr->qpair->dma_tag_payload, 1183 tr->payload_dma_map, req->u.payload, req->payload_size, 1184 nvme_payload_map, tr, 0); 1185 if (err != 0) 1186 nvme_printf(qpair->ctrlr, 1187 "bus_dmamap_load returned 0x%x!\n", err); 1188 break; 1189 case NVME_REQUEST_NULL: 1190 nvme_qpair_submit_tracker(tr->qpair, tr); 1191 break; 1192 case NVME_REQUEST_BIO: 1193 KASSERT(req->u.bio->bio_bcount <= qpair->ctrlr->max_xfer_size, 1194 ("bio->bio_bcount (%jd) exceeds max_xfer_size (%d)\n", 1195 (intmax_t)req->u.bio->bio_bcount, 1196 qpair->ctrlr->max_xfer_size)); 1197 err = bus_dmamap_load_bio(tr->qpair->dma_tag_payload, 1198 tr->payload_dma_map, req->u.bio, nvme_payload_map, tr, 0); 1199 if (err != 0) 1200 nvme_printf(qpair->ctrlr, 1201 "bus_dmamap_load_bio returned 0x%x!\n", err); 1202 break; 1203 case NVME_REQUEST_CCB: 1204 err = bus_dmamap_load_ccb(tr->qpair->dma_tag_payload, 1205 tr->payload_dma_map, req->u.payload, 1206 nvme_payload_map, tr, 0); 1207 if (err != 0) 1208 nvme_printf(qpair->ctrlr, 1209 "bus_dmamap_load_ccb returned 0x%x!\n", err); 1210 break; 1211 default: 1212 panic("unknown nvme request type 0x%x\n", req->type); 1213 break; 1214 } 1215 1216 if (err != 0) { 1217 /* 1218 * The dmamap operation failed, so we manually fail the 1219 * tracker here with DATA_TRANSFER_ERROR status. 1220 * 1221 * nvme_qpair_manual_complete_tracker must not be called 1222 * with the qpair lock held. 1223 */ 1224 mtx_unlock(&qpair->lock); 1225 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1226 NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL); 1227 mtx_lock(&qpair->lock); 1228 } 1229 } 1230 1231 void 1232 nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1233 { 1234 1235 mtx_lock(&qpair->lock); 1236 _nvme_qpair_submit_request(qpair, req); 1237 mtx_unlock(&qpair->lock); 1238 } 1239 1240 static void 1241 nvme_qpair_enable(struct nvme_qpair *qpair) 1242 { 1243 mtx_assert(&qpair->lock, MA_OWNED); 1244 1245 qpair->recovery_state = RECOVERY_NONE; 1246 } 1247 1248 void 1249 nvme_qpair_reset(struct nvme_qpair *qpair) 1250 { 1251 1252 qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0; 1253 1254 /* 1255 * First time through the completion queue, HW will set phase 1256 * bit on completions to 1. So set this to 1 here, indicating 1257 * we're looking for a 1 to know which entries have completed. 1258 * we'll toggle the bit each time when the completion queue 1259 * rolls over. 1260 */ 1261 qpair->phase = 1; 1262 1263 memset(qpair->cmd, 0, 1264 qpair->num_entries * sizeof(struct nvme_command)); 1265 memset(qpair->cpl, 0, 1266 qpair->num_entries * sizeof(struct nvme_completion)); 1267 } 1268 1269 void 1270 nvme_admin_qpair_enable(struct nvme_qpair *qpair) 1271 { 1272 struct nvme_tracker *tr; 1273 struct nvme_tracker *tr_temp; 1274 1275 /* 1276 * Manually abort each outstanding admin command. Do not retry 1277 * admin commands found here, since they will be left over from 1278 * a controller reset and its likely the context in which the 1279 * command was issued no longer applies. 1280 */ 1281 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1282 nvme_printf(qpair->ctrlr, 1283 "aborting outstanding admin command\n"); 1284 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1285 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1286 } 1287 1288 mtx_lock(&qpair->lock); 1289 nvme_qpair_enable(qpair); 1290 mtx_unlock(&qpair->lock); 1291 } 1292 1293 void 1294 nvme_io_qpair_enable(struct nvme_qpair *qpair) 1295 { 1296 STAILQ_HEAD(, nvme_request) temp; 1297 struct nvme_tracker *tr; 1298 struct nvme_tracker *tr_temp; 1299 struct nvme_request *req; 1300 1301 /* 1302 * Manually abort each outstanding I/O. This normally results in a 1303 * retry, unless the retry count on the associated request has 1304 * reached its limit. 1305 */ 1306 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1307 nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n"); 1308 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1309 NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY); 1310 } 1311 1312 mtx_lock(&qpair->lock); 1313 1314 nvme_qpair_enable(qpair); 1315 1316 STAILQ_INIT(&temp); 1317 STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request); 1318 1319 while (!STAILQ_EMPTY(&temp)) { 1320 req = STAILQ_FIRST(&temp); 1321 STAILQ_REMOVE_HEAD(&temp, stailq); 1322 nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n"); 1323 nvme_qpair_print_command(qpair, &req->cmd); 1324 _nvme_qpair_submit_request(qpair, req); 1325 } 1326 1327 mtx_unlock(&qpair->lock); 1328 } 1329 1330 static void 1331 nvme_qpair_disable(struct nvme_qpair *qpair) 1332 { 1333 struct nvme_tracker *tr, *tr_temp; 1334 1335 mtx_lock(&qpair->lock); 1336 qpair->recovery_state = RECOVERY_WAITING; 1337 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1338 tr->deadline = SBT_MAX; 1339 } 1340 mtx_unlock(&qpair->lock); 1341 } 1342 1343 void 1344 nvme_admin_qpair_disable(struct nvme_qpair *qpair) 1345 { 1346 1347 nvme_qpair_disable(qpair); 1348 nvme_admin_qpair_abort_aers(qpair); 1349 } 1350 1351 void 1352 nvme_io_qpair_disable(struct nvme_qpair *qpair) 1353 { 1354 1355 nvme_qpair_disable(qpair); 1356 } 1357 1358 void 1359 nvme_qpair_fail(struct nvme_qpair *qpair) 1360 { 1361 struct nvme_tracker *tr; 1362 struct nvme_request *req; 1363 1364 if (!mtx_initialized(&qpair->lock)) 1365 return; 1366 1367 mtx_lock(&qpair->lock); 1368 1369 while (!STAILQ_EMPTY(&qpair->queued_req)) { 1370 req = STAILQ_FIRST(&qpair->queued_req); 1371 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 1372 nvme_printf(qpair->ctrlr, "failing queued i/o\n"); 1373 mtx_unlock(&qpair->lock); 1374 nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC, 1375 NVME_SC_ABORTED_BY_REQUEST); 1376 mtx_lock(&qpair->lock); 1377 } 1378 1379 /* Manually abort each outstanding I/O. */ 1380 while (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1381 tr = TAILQ_FIRST(&qpair->outstanding_tr); 1382 /* 1383 * Do not remove the tracker. The abort_tracker path will 1384 * do that for us. 1385 */ 1386 nvme_printf(qpair->ctrlr, "failing outstanding i/o\n"); 1387 mtx_unlock(&qpair->lock); 1388 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1389 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1390 mtx_lock(&qpair->lock); 1391 } 1392 1393 mtx_unlock(&qpair->lock); 1394 } 1395