1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/proc.h> 36 37 #include <dev/pci/pcivar.h> 38 39 #include "nvme_private.h" 40 41 typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t; 42 #define DO_NOT_RETRY 1 43 44 static void _nvme_qpair_submit_request(struct nvme_qpair *qpair, 45 struct nvme_request *req); 46 static void nvme_qpair_destroy(struct nvme_qpair *qpair); 47 48 struct nvme_opcode_string { 49 50 uint16_t opc; 51 const char * str; 52 }; 53 54 static struct nvme_opcode_string admin_opcode[] = { 55 { NVME_OPC_DELETE_IO_SQ, "DELETE IO SQ" }, 56 { NVME_OPC_CREATE_IO_SQ, "CREATE IO SQ" }, 57 { NVME_OPC_GET_LOG_PAGE, "GET LOG PAGE" }, 58 { NVME_OPC_DELETE_IO_CQ, "DELETE IO CQ" }, 59 { NVME_OPC_CREATE_IO_CQ, "CREATE IO CQ" }, 60 { NVME_OPC_IDENTIFY, "IDENTIFY" }, 61 { NVME_OPC_ABORT, "ABORT" }, 62 { NVME_OPC_SET_FEATURES, "SET FEATURES" }, 63 { NVME_OPC_GET_FEATURES, "GET FEATURES" }, 64 { NVME_OPC_ASYNC_EVENT_REQUEST, "ASYNC EVENT REQUEST" }, 65 { NVME_OPC_FIRMWARE_ACTIVATE, "FIRMWARE ACTIVATE" }, 66 { NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD, "FIRMWARE IMAGE DOWNLOAD" }, 67 { NVME_OPC_DEVICE_SELF_TEST, "DEVICE SELF-TEST" }, 68 { NVME_OPC_NAMESPACE_ATTACHMENT, "NAMESPACE ATTACHMENT" }, 69 { NVME_OPC_KEEP_ALIVE, "KEEP ALIVE" }, 70 { NVME_OPC_DIRECTIVE_SEND, "DIRECTIVE SEND" }, 71 { NVME_OPC_DIRECTIVE_RECEIVE, "DIRECTIVE RECEIVE" }, 72 { NVME_OPC_VIRTUALIZATION_MANAGEMENT, "VIRTUALIZATION MANAGEMENT" }, 73 { NVME_OPC_NVME_MI_SEND, "NVME-MI SEND" }, 74 { NVME_OPC_NVME_MI_RECEIVE, "NVME-MI RECEIVE" }, 75 { NVME_OPC_DOORBELL_BUFFER_CONFIG, "DOORBELL BUFFER CONFIG" }, 76 { NVME_OPC_FORMAT_NVM, "FORMAT NVM" }, 77 { NVME_OPC_SECURITY_SEND, "SECURITY SEND" }, 78 { NVME_OPC_SECURITY_RECEIVE, "SECURITY RECEIVE" }, 79 { NVME_OPC_SANITIZE, "SANITIZE" }, 80 { NVME_OPC_GET_LBA_STATUS, "GET LBA STATUS" }, 81 { 0xFFFF, "ADMIN COMMAND" } 82 }; 83 84 static struct nvme_opcode_string io_opcode[] = { 85 { NVME_OPC_FLUSH, "FLUSH" }, 86 { NVME_OPC_WRITE, "WRITE" }, 87 { NVME_OPC_READ, "READ" }, 88 { NVME_OPC_WRITE_UNCORRECTABLE, "WRITE UNCORRECTABLE" }, 89 { NVME_OPC_COMPARE, "COMPARE" }, 90 { NVME_OPC_WRITE_ZEROES, "WRITE ZEROES" }, 91 { NVME_OPC_DATASET_MANAGEMENT, "DATASET MANAGEMENT" }, 92 { NVME_OPC_VERIFY, "VERIFY" }, 93 { NVME_OPC_RESERVATION_REGISTER, "RESERVATION REGISTER" }, 94 { NVME_OPC_RESERVATION_REPORT, "RESERVATION REPORT" }, 95 { NVME_OPC_RESERVATION_ACQUIRE, "RESERVATION ACQUIRE" }, 96 { NVME_OPC_RESERVATION_RELEASE, "RESERVATION RELEASE" }, 97 { 0xFFFF, "IO COMMAND" } 98 }; 99 100 static const char * 101 get_admin_opcode_string(uint16_t opc) 102 { 103 struct nvme_opcode_string *entry; 104 105 entry = admin_opcode; 106 107 while (entry->opc != 0xFFFF) { 108 if (entry->opc == opc) 109 return (entry->str); 110 entry++; 111 } 112 return (entry->str); 113 } 114 115 static const char * 116 get_io_opcode_string(uint16_t opc) 117 { 118 struct nvme_opcode_string *entry; 119 120 entry = io_opcode; 121 122 while (entry->opc != 0xFFFF) { 123 if (entry->opc == opc) 124 return (entry->str); 125 entry++; 126 } 127 return (entry->str); 128 } 129 130 131 static void 132 nvme_admin_qpair_print_command(struct nvme_qpair *qpair, 133 struct nvme_command *cmd) 134 { 135 136 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x " 137 "cdw10:%08x cdw11:%08x\n", 138 get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid, 139 le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11)); 140 } 141 142 static void 143 nvme_io_qpair_print_command(struct nvme_qpair *qpair, 144 struct nvme_command *cmd) 145 { 146 147 switch (cmd->opc) { 148 case NVME_OPC_WRITE: 149 case NVME_OPC_READ: 150 case NVME_OPC_WRITE_UNCORRECTABLE: 151 case NVME_OPC_COMPARE: 152 case NVME_OPC_WRITE_ZEROES: 153 case NVME_OPC_VERIFY: 154 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d " 155 "lba:%llu len:%d\n", 156 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid), 157 ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10), 158 (le32toh(cmd->cdw12) & 0xFFFF) + 1); 159 break; 160 case NVME_OPC_FLUSH: 161 case NVME_OPC_DATASET_MANAGEMENT: 162 case NVME_OPC_RESERVATION_REGISTER: 163 case NVME_OPC_RESERVATION_REPORT: 164 case NVME_OPC_RESERVATION_ACQUIRE: 165 case NVME_OPC_RESERVATION_RELEASE: 166 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n", 167 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid)); 168 break; 169 default: 170 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n", 171 get_io_opcode_string(cmd->opc), cmd->opc, qpair->id, 172 cmd->cid, le32toh(cmd->nsid)); 173 break; 174 } 175 } 176 177 static void 178 nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd) 179 { 180 if (qpair->id == 0) 181 nvme_admin_qpair_print_command(qpair, cmd); 182 else 183 nvme_io_qpair_print_command(qpair, cmd); 184 if (nvme_verbose_cmd_dump) { 185 nvme_printf(qpair->ctrlr, 186 "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n", 187 cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr, 188 (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2); 189 nvme_printf(qpair->ctrlr, 190 "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n", 191 cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14, 192 cmd->cdw15); 193 } 194 } 195 196 struct nvme_status_string { 197 198 uint16_t sc; 199 const char * str; 200 }; 201 202 static struct nvme_status_string generic_status[] = { 203 { NVME_SC_SUCCESS, "SUCCESS" }, 204 { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" }, 205 { NVME_SC_INVALID_FIELD, "INVALID_FIELD" }, 206 { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" }, 207 { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" }, 208 { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" }, 209 { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" }, 210 { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" }, 211 { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" }, 212 { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" }, 213 { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" }, 214 { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" }, 215 { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" }, 216 { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" }, 217 { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" }, 218 { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" }, 219 { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" }, 220 { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" }, 221 { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" }, 222 { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" }, 223 { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" }, 224 { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" }, 225 { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" }, 226 { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" }, 227 { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" }, 228 { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" }, 229 { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" }, 230 { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" }, 231 { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" }, 232 { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" }, 233 { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" }, 234 { NVME_SC_NAMESPACE_IS_WRITE_PROTECTED, "NAMESPACE IS WRITE PROTECTED" }, 235 { NVME_SC_COMMAND_INTERRUPTED, "COMMAND INTERRUPTED" }, 236 { NVME_SC_TRANSIENT_TRANSPORT_ERROR, "TRANSIENT TRANSPORT ERROR" }, 237 238 { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" }, 239 { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" }, 240 { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" }, 241 { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" }, 242 { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" }, 243 { 0xFFFF, "GENERIC" } 244 }; 245 246 static struct nvme_status_string command_specific_status[] = { 247 { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" }, 248 { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" }, 249 { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" }, 250 { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" }, 251 { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" }, 252 { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" }, 253 { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" }, 254 { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" }, 255 { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" }, 256 { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" }, 257 { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" }, 258 { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" }, 259 { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" }, 260 { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" }, 261 { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" }, 262 { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" }, 263 { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" }, 264 { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" }, 265 { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" }, 266 { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" }, 267 { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" }, 268 { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" }, 269 { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" }, 270 { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" }, 271 { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" }, 272 { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" }, 273 { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" }, 274 { NVME_SC_SELT_TEST_IN_PROGRESS, "DEVICE SELT-TEST IN PROGRESS" }, 275 { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" }, 276 { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" }, 277 { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" }, 278 { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" }, 279 { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" }, 280 { NVME_SC_SANITIZE_PROHIBITED_WPMRE, "SANITIZE PROHIBITED WRITE PERSISTENT MEMORY REGION ENABLED" }, 281 { NVME_SC_ANA_GROUP_ID_INVALID, "ANA GROUP IDENTIFIED INVALID" }, 282 { NVME_SC_ANA_ATTACH_FAILED, "ANA ATTACH FAILED" }, 283 284 { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" }, 285 { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" }, 286 { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" }, 287 { 0xFFFF, "COMMAND SPECIFIC" } 288 }; 289 290 static struct nvme_status_string media_error_status[] = { 291 { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" }, 292 { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" }, 293 { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" }, 294 { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" }, 295 { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" }, 296 { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" }, 297 { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" }, 298 { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" }, 299 { 0xFFFF, "MEDIA ERROR" } 300 }; 301 302 static struct nvme_status_string path_related_status[] = { 303 { NVME_SC_INTERNAL_PATH_ERROR, "INTERNAL PATH ERROR" }, 304 { NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS, "ASYMMETRIC ACCESS PERSISTENT LOSS" }, 305 { NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE, "ASYMMETRIC ACCESS INACCESSIBLE" }, 306 { NVME_SC_ASYMMETRIC_ACCESS_TRANSITION, "ASYMMETRIC ACCESS TRANSITION" }, 307 { NVME_SC_CONTROLLER_PATHING_ERROR, "CONTROLLER PATHING ERROR" }, 308 { NVME_SC_HOST_PATHING_ERROR, "HOST PATHING ERROR" }, 309 { NVME_SC_COMMAND_ABOTHED_BY_HOST, "COMMAND ABOTHED BY HOST" }, 310 { 0xFFFF, "PATH RELATED" }, 311 }; 312 313 static const char * 314 get_status_string(uint16_t sct, uint16_t sc) 315 { 316 struct nvme_status_string *entry; 317 318 switch (sct) { 319 case NVME_SCT_GENERIC: 320 entry = generic_status; 321 break; 322 case NVME_SCT_COMMAND_SPECIFIC: 323 entry = command_specific_status; 324 break; 325 case NVME_SCT_MEDIA_ERROR: 326 entry = media_error_status; 327 break; 328 case NVME_SCT_PATH_RELATED: 329 entry = path_related_status; 330 break; 331 case NVME_SCT_VENDOR_SPECIFIC: 332 return ("VENDOR SPECIFIC"); 333 default: 334 return ("RESERVED"); 335 } 336 337 while (entry->sc != 0xFFFF) { 338 if (entry->sc == sc) 339 return (entry->str); 340 entry++; 341 } 342 return (entry->str); 343 } 344 345 static void 346 nvme_qpair_print_completion(struct nvme_qpair *qpair, 347 struct nvme_completion *cpl) 348 { 349 uint16_t sct, sc; 350 351 sct = NVME_STATUS_GET_SCT(cpl->status); 352 sc = NVME_STATUS_GET_SC(cpl->status); 353 354 nvme_printf(qpair->ctrlr, "%s (%02x/%02x) sqid:%d cid:%d cdw0:%x\n", 355 get_status_string(sct, sc), sct, sc, cpl->sqid, cpl->cid, 356 cpl->cdw0); 357 } 358 359 static boolean_t 360 nvme_completion_is_retry(const struct nvme_completion *cpl) 361 { 362 uint8_t sct, sc, dnr; 363 364 sct = NVME_STATUS_GET_SCT(cpl->status); 365 sc = NVME_STATUS_GET_SC(cpl->status); 366 dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */ 367 368 /* 369 * TODO: spec is not clear how commands that are aborted due 370 * to TLER will be marked. So for now, it seems 371 * NAMESPACE_NOT_READY is the only case where we should 372 * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST 373 * set the DNR bit correctly since the driver controls that. 374 */ 375 switch (sct) { 376 case NVME_SCT_GENERIC: 377 switch (sc) { 378 case NVME_SC_ABORTED_BY_REQUEST: 379 case NVME_SC_NAMESPACE_NOT_READY: 380 if (dnr) 381 return (0); 382 else 383 return (1); 384 case NVME_SC_INVALID_OPCODE: 385 case NVME_SC_INVALID_FIELD: 386 case NVME_SC_COMMAND_ID_CONFLICT: 387 case NVME_SC_DATA_TRANSFER_ERROR: 388 case NVME_SC_ABORTED_POWER_LOSS: 389 case NVME_SC_INTERNAL_DEVICE_ERROR: 390 case NVME_SC_ABORTED_SQ_DELETION: 391 case NVME_SC_ABORTED_FAILED_FUSED: 392 case NVME_SC_ABORTED_MISSING_FUSED: 393 case NVME_SC_INVALID_NAMESPACE_OR_FORMAT: 394 case NVME_SC_COMMAND_SEQUENCE_ERROR: 395 case NVME_SC_LBA_OUT_OF_RANGE: 396 case NVME_SC_CAPACITY_EXCEEDED: 397 default: 398 return (0); 399 } 400 case NVME_SCT_COMMAND_SPECIFIC: 401 case NVME_SCT_MEDIA_ERROR: 402 return (0); 403 case NVME_SCT_PATH_RELATED: 404 switch (sc) { 405 case NVME_SC_INTERNAL_PATH_ERROR: 406 if (dnr) 407 return (0); 408 else 409 return (1); 410 default: 411 return (0); 412 } 413 case NVME_SCT_VENDOR_SPECIFIC: 414 default: 415 return (0); 416 } 417 } 418 419 static void 420 nvme_qpair_complete_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr, 421 struct nvme_completion *cpl, error_print_t print_on_error) 422 { 423 struct nvme_request *req; 424 boolean_t retry, error, retriable; 425 426 req = tr->req; 427 error = nvme_completion_is_error(cpl); 428 retriable = nvme_completion_is_retry(cpl); 429 retry = error && retriable && req->retries < nvme_retry_count; 430 if (retry) 431 qpair->num_retries++; 432 if (error && req->retries >= nvme_retry_count && retriable) 433 qpair->num_failures++; 434 435 if (error && (print_on_error == ERROR_PRINT_ALL || 436 (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) { 437 nvme_qpair_print_command(qpair, &req->cmd); 438 nvme_qpair_print_completion(qpair, cpl); 439 } 440 441 qpair->act_tr[cpl->cid] = NULL; 442 443 KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n")); 444 445 if (req->cb_fn && !retry) 446 req->cb_fn(req->cb_arg, cpl); 447 448 mtx_lock(&qpair->lock); 449 callout_stop(&tr->timer); 450 451 if (retry) { 452 req->retries++; 453 nvme_qpair_submit_tracker(qpair, tr); 454 } else { 455 if (req->type != NVME_REQUEST_NULL) { 456 bus_dmamap_sync(qpair->dma_tag_payload, 457 tr->payload_dma_map, 458 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 459 bus_dmamap_unload(qpair->dma_tag_payload, 460 tr->payload_dma_map); 461 } 462 463 nvme_free_request(req); 464 tr->req = NULL; 465 466 TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq); 467 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 468 469 /* 470 * If the controller is in the middle of resetting, don't 471 * try to submit queued requests here - let the reset logic 472 * handle that instead. 473 */ 474 if (!STAILQ_EMPTY(&qpair->queued_req) && 475 !qpair->ctrlr->is_resetting) { 476 req = STAILQ_FIRST(&qpair->queued_req); 477 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 478 _nvme_qpair_submit_request(qpair, req); 479 } 480 } 481 482 mtx_unlock(&qpair->lock); 483 } 484 485 static void 486 nvme_qpair_manual_complete_tracker(struct nvme_qpair *qpair, 487 struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr, 488 error_print_t print_on_error) 489 { 490 struct nvme_completion cpl; 491 492 memset(&cpl, 0, sizeof(cpl)); 493 cpl.sqid = qpair->id; 494 cpl.cid = tr->cid; 495 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 496 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 497 cpl.status |= (dnr & NVME_STATUS_DNR_MASK) << NVME_STATUS_DNR_SHIFT; 498 nvme_qpair_complete_tracker(qpair, tr, &cpl, print_on_error); 499 } 500 501 void 502 nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 503 struct nvme_request *req, uint32_t sct, uint32_t sc) 504 { 505 struct nvme_completion cpl; 506 boolean_t error; 507 508 memset(&cpl, 0, sizeof(cpl)); 509 cpl.sqid = qpair->id; 510 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 511 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 512 513 error = nvme_completion_is_error(&cpl); 514 515 if (error) { 516 nvme_qpair_print_command(qpair, &req->cmd); 517 nvme_qpair_print_completion(qpair, &cpl); 518 } 519 520 if (req->cb_fn) 521 req->cb_fn(req->cb_arg, &cpl); 522 523 nvme_free_request(req); 524 } 525 526 bool 527 nvme_qpair_process_completions(struct nvme_qpair *qpair) 528 { 529 struct nvme_tracker *tr; 530 struct nvme_completion cpl; 531 int done = 0; 532 bool in_panic = dumping || SCHEDULER_STOPPED(); 533 534 qpair->num_intr_handler_calls++; 535 536 /* 537 * qpair is not enabled, likely because a controller reset is is in 538 * progress. Ignore the interrupt - any I/O that was associated with 539 * this interrupt will get retried when the reset is complete. 540 */ 541 if (!qpair->is_enabled) 542 return (false); 543 544 /* 545 * A panic can stop the CPU this routine is running on at any point. If 546 * we're called during a panic, complete the sq_head wrap protocol for 547 * the case where we are interrupted just after the increment at 1 548 * below, but before we can reset cq_head to zero at 2. Also cope with 549 * the case where we do the zero at 2, but may or may not have done the 550 * phase adjustment at step 3. The panic machinery flushes all pending 551 * memory writes, so we can make these strong ordering assumptions 552 * that would otherwise be unwise if we were racing in real time. 553 */ 554 if (__predict_false(in_panic)) { 555 if (qpair->cq_head == qpair->num_entries) { 556 /* 557 * Here we know that we need to zero cq_head and then negate 558 * the phase, which hasn't been assigned if cq_head isn't 559 * zero due to the atomic_store_rel. 560 */ 561 qpair->cq_head = 0; 562 qpair->phase = !qpair->phase; 563 } else if (qpair->cq_head == 0) { 564 /* 565 * In this case, we know that the assignment at 2 566 * happened below, but we don't know if it 3 happened or 567 * not. To do this, we look at the last completion 568 * entry and set the phase to the opposite phase 569 * that it has. This gets us back in sync 570 */ 571 cpl = qpair->cpl[qpair->num_entries - 1]; 572 nvme_completion_swapbytes(&cpl); 573 qpair->phase = !NVME_STATUS_GET_P(cpl.status); 574 } 575 } 576 577 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 578 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 579 while (1) { 580 cpl = qpair->cpl[qpair->cq_head]; 581 582 /* Convert to host endian */ 583 nvme_completion_swapbytes(&cpl); 584 585 if (NVME_STATUS_GET_P(cpl.status) != qpair->phase) 586 break; 587 588 tr = qpair->act_tr[cpl.cid]; 589 590 if (tr != NULL) { 591 nvme_qpair_complete_tracker(qpair, tr, &cpl, ERROR_PRINT_ALL); 592 qpair->sq_head = cpl.sqhd; 593 done++; 594 } else if (!in_panic) { 595 /* 596 * A missing tracker is normally an error. However, a 597 * panic can stop the CPU this routine is running on 598 * after completing an I/O but before updating 599 * qpair->cq_head at 1 below. Later, we re-enter this 600 * routine to poll I/O associated with the kernel 601 * dump. We find that the tr has been set to null before 602 * calling the completion routine. If it hasn't 603 * completed (or it triggers a panic), then '1' below 604 * won't have updated cq_head. Rather than panic again, 605 * ignore this condition because it's not unexpected. 606 */ 607 nvme_printf(qpair->ctrlr, 608 "cpl does not map to outstanding cmd\n"); 609 /* nvme_dump_completion expects device endianess */ 610 nvme_dump_completion(&qpair->cpl[qpair->cq_head]); 611 KASSERT(0, ("received completion for unknown cmd")); 612 } 613 614 /* 615 * There's a number of races with the following (see above) when 616 * the system panics. We compensate for each one of them by 617 * using the atomic store to force strong ordering (at least when 618 * viewed in the aftermath of a panic). 619 */ 620 if (++qpair->cq_head == qpair->num_entries) { /* 1 */ 621 atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */ 622 qpair->phase = !qpair->phase; /* 3 */ 623 } 624 625 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 626 qpair->cq_hdbl_off, qpair->cq_head); 627 } 628 return (done != 0); 629 } 630 631 static void 632 nvme_qpair_msix_handler(void *arg) 633 { 634 struct nvme_qpair *qpair = arg; 635 636 nvme_qpair_process_completions(qpair); 637 } 638 639 int 640 nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 641 uint16_t vector, uint32_t num_entries, uint32_t num_trackers, 642 struct nvme_controller *ctrlr) 643 { 644 struct nvme_tracker *tr; 645 size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz; 646 uint64_t queuemem_phys, prpmem_phys, list_phys; 647 uint8_t *queuemem, *prpmem, *prp_list; 648 int i, err; 649 650 qpair->id = id; 651 qpair->vector = vector; 652 qpair->num_entries = num_entries; 653 qpair->num_trackers = num_trackers; 654 qpair->ctrlr = ctrlr; 655 656 if (ctrlr->msix_enabled) { 657 658 /* 659 * MSI-X vector resource IDs start at 1, so we add one to 660 * the queue's vector to get the corresponding rid to use. 661 */ 662 qpair->rid = vector + 1; 663 664 qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 665 &qpair->rid, RF_ACTIVE); 666 bus_setup_intr(ctrlr->dev, qpair->res, 667 INTR_TYPE_MISC | INTR_MPSAFE, NULL, 668 nvme_qpair_msix_handler, qpair, &qpair->tag); 669 if (id == 0) { 670 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 671 "admin"); 672 } else { 673 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 674 "io%d", id - 1); 675 } 676 } 677 678 mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF); 679 680 /* Note: NVMe PRP format is restricted to 4-byte alignment. */ 681 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 682 4, PAGE_SIZE, BUS_SPACE_MAXADDR, 683 BUS_SPACE_MAXADDR, NULL, NULL, NVME_MAX_XFER_SIZE, 684 (NVME_MAX_XFER_SIZE/PAGE_SIZE)+1, PAGE_SIZE, 0, 685 NULL, NULL, &qpair->dma_tag_payload); 686 if (err != 0) { 687 nvme_printf(ctrlr, "payload tag create failed %d\n", err); 688 goto out; 689 } 690 691 /* 692 * Each component must be page aligned, and individual PRP lists 693 * cannot cross a page boundary. 694 */ 695 cmdsz = qpair->num_entries * sizeof(struct nvme_command); 696 cmdsz = roundup2(cmdsz, PAGE_SIZE); 697 cplsz = qpair->num_entries * sizeof(struct nvme_completion); 698 cplsz = roundup2(cplsz, PAGE_SIZE); 699 prpsz = sizeof(uint64_t) * NVME_MAX_PRP_LIST_ENTRIES;; 700 prpmemsz = qpair->num_trackers * prpsz; 701 allocsz = cmdsz + cplsz + prpmemsz; 702 703 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 704 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 705 allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag); 706 if (err != 0) { 707 nvme_printf(ctrlr, "tag create failed %d\n", err); 708 goto out; 709 } 710 711 if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem, 712 BUS_DMA_NOWAIT, &qpair->queuemem_map)) { 713 nvme_printf(ctrlr, "failed to alloc qpair memory\n"); 714 goto out; 715 } 716 717 if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map, 718 queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) { 719 nvme_printf(ctrlr, "failed to load qpair memory\n"); 720 goto out; 721 } 722 723 qpair->num_cmds = 0; 724 qpair->num_intr_handler_calls = 0; 725 qpair->num_retries = 0; 726 qpair->num_failures = 0; 727 qpair->cmd = (struct nvme_command *)queuemem; 728 qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz); 729 prpmem = (uint8_t *)(queuemem + cmdsz + cplsz); 730 qpair->cmd_bus_addr = queuemem_phys; 731 qpair->cpl_bus_addr = queuemem_phys + cmdsz; 732 prpmem_phys = queuemem_phys + cmdsz + cplsz; 733 734 /* 735 * Calcuate the stride of the doorbell register. Many emulators set this 736 * value to correspond to a cache line. However, some hardware has set 737 * it to various small values. 738 */ 739 qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[0]) + 740 (id << (ctrlr->dstrd + 1)); 741 qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[0]) + 742 (id << (ctrlr->dstrd + 1)) + (1 << ctrlr->dstrd); 743 744 TAILQ_INIT(&qpair->free_tr); 745 TAILQ_INIT(&qpair->outstanding_tr); 746 STAILQ_INIT(&qpair->queued_req); 747 748 list_phys = prpmem_phys; 749 prp_list = prpmem; 750 for (i = 0; i < qpair->num_trackers; i++) { 751 752 if (list_phys + prpsz > prpmem_phys + prpmemsz) { 753 qpair->num_trackers = i; 754 break; 755 } 756 757 /* 758 * Make sure that the PRP list for this tracker doesn't 759 * overflow to another page. 760 */ 761 if (trunc_page(list_phys) != 762 trunc_page(list_phys + prpsz - 1)) { 763 list_phys = roundup2(list_phys, PAGE_SIZE); 764 prp_list = 765 (uint8_t *)roundup2((uintptr_t)prp_list, PAGE_SIZE); 766 } 767 768 tr = malloc(sizeof(*tr), M_NVME, M_ZERO | M_WAITOK); 769 bus_dmamap_create(qpair->dma_tag_payload, 0, 770 &tr->payload_dma_map); 771 callout_init(&tr->timer, 1); 772 tr->cid = i; 773 tr->qpair = qpair; 774 tr->prp = (uint64_t *)prp_list; 775 tr->prp_bus_addr = list_phys; 776 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 777 list_phys += prpsz; 778 prp_list += prpsz; 779 } 780 781 if (qpair->num_trackers == 0) { 782 nvme_printf(ctrlr, "failed to allocate enough trackers\n"); 783 goto out; 784 } 785 786 qpair->act_tr = malloc(sizeof(struct nvme_tracker *) * 787 qpair->num_entries, M_NVME, M_ZERO | M_WAITOK); 788 return (0); 789 790 out: 791 nvme_qpair_destroy(qpair); 792 return (ENOMEM); 793 } 794 795 static void 796 nvme_qpair_destroy(struct nvme_qpair *qpair) 797 { 798 struct nvme_tracker *tr; 799 800 if (qpair->tag) 801 bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag); 802 803 if (mtx_initialized(&qpair->lock)) 804 mtx_destroy(&qpair->lock); 805 806 if (qpair->res) 807 bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ, 808 rman_get_rid(qpair->res), qpair->res); 809 810 if (qpair->cmd != NULL) { 811 bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map); 812 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 813 qpair->queuemem_map); 814 } 815 816 if (qpair->act_tr) 817 free(qpair->act_tr, M_NVME); 818 819 while (!TAILQ_EMPTY(&qpair->free_tr)) { 820 tr = TAILQ_FIRST(&qpair->free_tr); 821 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 822 bus_dmamap_destroy(qpair->dma_tag_payload, 823 tr->payload_dma_map); 824 free(tr, M_NVME); 825 } 826 827 if (qpair->dma_tag) 828 bus_dma_tag_destroy(qpair->dma_tag); 829 830 if (qpair->dma_tag_payload) 831 bus_dma_tag_destroy(qpair->dma_tag_payload); 832 } 833 834 static void 835 nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair) 836 { 837 struct nvme_tracker *tr; 838 839 tr = TAILQ_FIRST(&qpair->outstanding_tr); 840 while (tr != NULL) { 841 if (tr->req->cmd.opc == NVME_OPC_ASYNC_EVENT_REQUEST) { 842 nvme_qpair_manual_complete_tracker(qpair, tr, 843 NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0, 844 ERROR_PRINT_NONE); 845 tr = TAILQ_FIRST(&qpair->outstanding_tr); 846 } else { 847 tr = TAILQ_NEXT(tr, tailq); 848 } 849 } 850 } 851 852 void 853 nvme_admin_qpair_destroy(struct nvme_qpair *qpair) 854 { 855 856 nvme_admin_qpair_abort_aers(qpair); 857 nvme_qpair_destroy(qpair); 858 } 859 860 void 861 nvme_io_qpair_destroy(struct nvme_qpair *qpair) 862 { 863 864 nvme_qpair_destroy(qpair); 865 } 866 867 static void 868 nvme_abort_complete(void *arg, const struct nvme_completion *status) 869 { 870 struct nvme_tracker *tr = arg; 871 872 /* 873 * If cdw0 == 1, the controller was not able to abort the command 874 * we requested. We still need to check the active tracker array, 875 * to cover race where I/O timed out at same time controller was 876 * completing the I/O. 877 */ 878 if (status->cdw0 == 1 && tr->qpair->act_tr[tr->cid] != NULL) { 879 /* 880 * An I/O has timed out, and the controller was unable to 881 * abort it for some reason. Construct a fake completion 882 * status, and then complete the I/O's tracker manually. 883 */ 884 nvme_printf(tr->qpair->ctrlr, 885 "abort command failed, aborting command manually\n"); 886 nvme_qpair_manual_complete_tracker(tr->qpair, tr, 887 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_ALL); 888 } 889 } 890 891 static void 892 nvme_timeout(void *arg) 893 { 894 struct nvme_tracker *tr = arg; 895 struct nvme_qpair *qpair = tr->qpair; 896 struct nvme_controller *ctrlr = qpair->ctrlr; 897 uint32_t csts; 898 uint8_t cfs; 899 900 /* 901 * Read csts to get value of cfs - controller fatal status. 902 * If no fatal status, try to call the completion routine, and 903 * if completes transactions, report a missed interrupt and 904 * return (this may need to be rate limited). Otherwise, if 905 * aborts are enabled and the controller is not reporting 906 * fatal status, abort the command. Otherwise, just reset the 907 * controller and hope for the best. 908 */ 909 csts = nvme_mmio_read_4(ctrlr, csts); 910 cfs = (csts >> NVME_CSTS_REG_CFS_SHIFT) & NVME_CSTS_REG_CFS_MASK; 911 if (cfs == 0 && nvme_qpair_process_completions(qpair)) { 912 nvme_printf(ctrlr, "Missing interrupt\n"); 913 return; 914 } 915 if (ctrlr->enable_aborts && cfs == 0) { 916 nvme_printf(ctrlr, "Aborting command due to a timeout.\n"); 917 nvme_ctrlr_cmd_abort(ctrlr, tr->cid, qpair->id, 918 nvme_abort_complete, tr); 919 } else { 920 nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n", 921 (csts == 0xffffffff) ? " and possible hot unplug" : 922 (cfs ? " and fatal error status" : "")); 923 nvme_ctrlr_reset(ctrlr); 924 } 925 } 926 927 void 928 nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr) 929 { 930 struct nvme_request *req; 931 struct nvme_controller *ctrlr; 932 933 mtx_assert(&qpair->lock, MA_OWNED); 934 935 req = tr->req; 936 req->cmd.cid = tr->cid; 937 qpair->act_tr[tr->cid] = tr; 938 ctrlr = qpair->ctrlr; 939 940 if (req->timeout) 941 callout_reset_curcpu(&tr->timer, ctrlr->timeout_period * hz, 942 nvme_timeout, tr); 943 944 /* Copy the command from the tracker to the submission queue. */ 945 memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd)); 946 947 if (++qpair->sq_tail == qpair->num_entries) 948 qpair->sq_tail = 0; 949 950 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 952 #ifndef __powerpc__ 953 /* 954 * powerpc's bus_dmamap_sync() already includes a heavyweight sync, but 955 * no other archs do. 956 */ 957 wmb(); 958 #endif 959 960 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 961 qpair->sq_tdbl_off, qpair->sq_tail); 962 qpair->num_cmds++; 963 } 964 965 static void 966 nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 967 { 968 struct nvme_tracker *tr = arg; 969 uint32_t cur_nseg; 970 971 /* 972 * If the mapping operation failed, return immediately. The caller 973 * is responsible for detecting the error status and failing the 974 * tracker manually. 975 */ 976 if (error != 0) { 977 nvme_printf(tr->qpair->ctrlr, 978 "nvme_payload_map err %d\n", error); 979 return; 980 } 981 982 /* 983 * Note that we specified PAGE_SIZE for alignment and max 984 * segment size when creating the bus dma tags. So here 985 * we can safely just transfer each segment to its 986 * associated PRP entry. 987 */ 988 tr->req->cmd.prp1 = htole64(seg[0].ds_addr); 989 990 if (nseg == 2) { 991 tr->req->cmd.prp2 = htole64(seg[1].ds_addr); 992 } else if (nseg > 2) { 993 cur_nseg = 1; 994 tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr); 995 while (cur_nseg < nseg) { 996 tr->prp[cur_nseg-1] = 997 htole64((uint64_t)seg[cur_nseg].ds_addr); 998 cur_nseg++; 999 } 1000 } else { 1001 /* 1002 * prp2 should not be used by the controller 1003 * since there is only one segment, but set 1004 * to 0 just to be safe. 1005 */ 1006 tr->req->cmd.prp2 = 0; 1007 } 1008 1009 bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map, 1010 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1011 nvme_qpair_submit_tracker(tr->qpair, tr); 1012 } 1013 1014 static void 1015 _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1016 { 1017 struct nvme_tracker *tr; 1018 int err = 0; 1019 1020 mtx_assert(&qpair->lock, MA_OWNED); 1021 1022 tr = TAILQ_FIRST(&qpair->free_tr); 1023 req->qpair = qpair; 1024 1025 if (tr == NULL || !qpair->is_enabled) { 1026 /* 1027 * No tracker is available, or the qpair is disabled due to 1028 * an in-progress controller-level reset or controller 1029 * failure. 1030 */ 1031 1032 if (qpair->ctrlr->is_failed) { 1033 /* 1034 * The controller has failed. Post the request to a 1035 * task where it will be aborted, so that we do not 1036 * invoke the request's callback in the context 1037 * of the submission. 1038 */ 1039 nvme_ctrlr_post_failed_request(qpair->ctrlr, req); 1040 } else { 1041 /* 1042 * Put the request on the qpair's request queue to be 1043 * processed when a tracker frees up via a command 1044 * completion or when the controller reset is 1045 * completed. 1046 */ 1047 STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq); 1048 } 1049 return; 1050 } 1051 1052 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 1053 TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq); 1054 tr->req = req; 1055 1056 switch (req->type) { 1057 case NVME_REQUEST_VADDR: 1058 KASSERT(req->payload_size <= qpair->ctrlr->max_xfer_size, 1059 ("payload_size (%d) exceeds max_xfer_size (%d)\n", 1060 req->payload_size, qpair->ctrlr->max_xfer_size)); 1061 err = bus_dmamap_load(tr->qpair->dma_tag_payload, 1062 tr->payload_dma_map, req->u.payload, req->payload_size, 1063 nvme_payload_map, tr, 0); 1064 if (err != 0) 1065 nvme_printf(qpair->ctrlr, 1066 "bus_dmamap_load returned 0x%x!\n", err); 1067 break; 1068 case NVME_REQUEST_NULL: 1069 nvme_qpair_submit_tracker(tr->qpair, tr); 1070 break; 1071 case NVME_REQUEST_BIO: 1072 KASSERT(req->u.bio->bio_bcount <= qpair->ctrlr->max_xfer_size, 1073 ("bio->bio_bcount (%jd) exceeds max_xfer_size (%d)\n", 1074 (intmax_t)req->u.bio->bio_bcount, 1075 qpair->ctrlr->max_xfer_size)); 1076 err = bus_dmamap_load_bio(tr->qpair->dma_tag_payload, 1077 tr->payload_dma_map, req->u.bio, nvme_payload_map, tr, 0); 1078 if (err != 0) 1079 nvme_printf(qpair->ctrlr, 1080 "bus_dmamap_load_bio returned 0x%x!\n", err); 1081 break; 1082 case NVME_REQUEST_CCB: 1083 err = bus_dmamap_load_ccb(tr->qpair->dma_tag_payload, 1084 tr->payload_dma_map, req->u.payload, 1085 nvme_payload_map, tr, 0); 1086 if (err != 0) 1087 nvme_printf(qpair->ctrlr, 1088 "bus_dmamap_load_ccb returned 0x%x!\n", err); 1089 break; 1090 default: 1091 panic("unknown nvme request type 0x%x\n", req->type); 1092 break; 1093 } 1094 1095 if (err != 0) { 1096 /* 1097 * The dmamap operation failed, so we manually fail the 1098 * tracker here with DATA_TRANSFER_ERROR status. 1099 * 1100 * nvme_qpair_manual_complete_tracker must not be called 1101 * with the qpair lock held. 1102 */ 1103 mtx_unlock(&qpair->lock); 1104 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1105 NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL); 1106 mtx_lock(&qpair->lock); 1107 } 1108 } 1109 1110 void 1111 nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1112 { 1113 1114 mtx_lock(&qpair->lock); 1115 _nvme_qpair_submit_request(qpair, req); 1116 mtx_unlock(&qpair->lock); 1117 } 1118 1119 static void 1120 nvme_qpair_enable(struct nvme_qpair *qpair) 1121 { 1122 1123 qpair->is_enabled = TRUE; 1124 } 1125 1126 void 1127 nvme_qpair_reset(struct nvme_qpair *qpair) 1128 { 1129 1130 qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0; 1131 1132 /* 1133 * First time through the completion queue, HW will set phase 1134 * bit on completions to 1. So set this to 1 here, indicating 1135 * we're looking for a 1 to know which entries have completed. 1136 * we'll toggle the bit each time when the completion queue 1137 * rolls over. 1138 */ 1139 qpair->phase = 1; 1140 1141 memset(qpair->cmd, 0, 1142 qpair->num_entries * sizeof(struct nvme_command)); 1143 memset(qpair->cpl, 0, 1144 qpair->num_entries * sizeof(struct nvme_completion)); 1145 } 1146 1147 void 1148 nvme_admin_qpair_enable(struct nvme_qpair *qpair) 1149 { 1150 struct nvme_tracker *tr; 1151 struct nvme_tracker *tr_temp; 1152 1153 /* 1154 * Manually abort each outstanding admin command. Do not retry 1155 * admin commands found here, since they will be left over from 1156 * a controller reset and its likely the context in which the 1157 * command was issued no longer applies. 1158 */ 1159 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1160 nvme_printf(qpair->ctrlr, 1161 "aborting outstanding admin command\n"); 1162 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1163 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1164 } 1165 1166 nvme_qpair_enable(qpair); 1167 } 1168 1169 void 1170 nvme_io_qpair_enable(struct nvme_qpair *qpair) 1171 { 1172 STAILQ_HEAD(, nvme_request) temp; 1173 struct nvme_tracker *tr; 1174 struct nvme_tracker *tr_temp; 1175 struct nvme_request *req; 1176 1177 /* 1178 * Manually abort each outstanding I/O. This normally results in a 1179 * retry, unless the retry count on the associated request has 1180 * reached its limit. 1181 */ 1182 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1183 nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n"); 1184 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1185 NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY); 1186 } 1187 1188 mtx_lock(&qpair->lock); 1189 1190 nvme_qpair_enable(qpair); 1191 1192 STAILQ_INIT(&temp); 1193 STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request); 1194 1195 while (!STAILQ_EMPTY(&temp)) { 1196 req = STAILQ_FIRST(&temp); 1197 STAILQ_REMOVE_HEAD(&temp, stailq); 1198 nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n"); 1199 nvme_qpair_print_command(qpair, &req->cmd); 1200 _nvme_qpair_submit_request(qpair, req); 1201 } 1202 1203 mtx_unlock(&qpair->lock); 1204 } 1205 1206 static void 1207 nvme_qpair_disable(struct nvme_qpair *qpair) 1208 { 1209 struct nvme_tracker *tr; 1210 1211 qpair->is_enabled = FALSE; 1212 mtx_lock(&qpair->lock); 1213 TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) 1214 callout_stop(&tr->timer); 1215 mtx_unlock(&qpair->lock); 1216 } 1217 1218 void 1219 nvme_admin_qpair_disable(struct nvme_qpair *qpair) 1220 { 1221 1222 nvme_qpair_disable(qpair); 1223 nvme_admin_qpair_abort_aers(qpair); 1224 } 1225 1226 void 1227 nvme_io_qpair_disable(struct nvme_qpair *qpair) 1228 { 1229 1230 nvme_qpair_disable(qpair); 1231 } 1232 1233 void 1234 nvme_qpair_fail(struct nvme_qpair *qpair) 1235 { 1236 struct nvme_tracker *tr; 1237 struct nvme_request *req; 1238 1239 if (!mtx_initialized(&qpair->lock)) 1240 return; 1241 1242 mtx_lock(&qpair->lock); 1243 1244 while (!STAILQ_EMPTY(&qpair->queued_req)) { 1245 req = STAILQ_FIRST(&qpair->queued_req); 1246 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 1247 nvme_printf(qpair->ctrlr, "failing queued i/o\n"); 1248 mtx_unlock(&qpair->lock); 1249 nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC, 1250 NVME_SC_ABORTED_BY_REQUEST); 1251 mtx_lock(&qpair->lock); 1252 } 1253 1254 /* Manually abort each outstanding I/O. */ 1255 while (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1256 tr = TAILQ_FIRST(&qpair->outstanding_tr); 1257 /* 1258 * Do not remove the tracker. The abort_tracker path will 1259 * do that for us. 1260 */ 1261 nvme_printf(qpair->ctrlr, "failing outstanding i/o\n"); 1262 mtx_unlock(&qpair->lock); 1263 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1264 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1265 mtx_lock(&qpair->lock); 1266 } 1267 1268 mtx_unlock(&qpair->lock); 1269 } 1270 1271