1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/proc.h> 36 37 #include <dev/pci/pcivar.h> 38 39 #include "nvme_private.h" 40 41 typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t; 42 #define DO_NOT_RETRY 1 43 44 static void _nvme_qpair_submit_request(struct nvme_qpair *qpair, 45 struct nvme_request *req); 46 static void nvme_qpair_destroy(struct nvme_qpair *qpair); 47 48 struct nvme_opcode_string { 49 50 uint16_t opc; 51 const char * str; 52 }; 53 54 static struct nvme_opcode_string admin_opcode[] = { 55 { NVME_OPC_DELETE_IO_SQ, "DELETE IO SQ" }, 56 { NVME_OPC_CREATE_IO_SQ, "CREATE IO SQ" }, 57 { NVME_OPC_GET_LOG_PAGE, "GET LOG PAGE" }, 58 { NVME_OPC_DELETE_IO_CQ, "DELETE IO CQ" }, 59 { NVME_OPC_CREATE_IO_CQ, "CREATE IO CQ" }, 60 { NVME_OPC_IDENTIFY, "IDENTIFY" }, 61 { NVME_OPC_ABORT, "ABORT" }, 62 { NVME_OPC_SET_FEATURES, "SET FEATURES" }, 63 { NVME_OPC_GET_FEATURES, "GET FEATURES" }, 64 { NVME_OPC_ASYNC_EVENT_REQUEST, "ASYNC EVENT REQUEST" }, 65 { NVME_OPC_FIRMWARE_ACTIVATE, "FIRMWARE ACTIVATE" }, 66 { NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD, "FIRMWARE IMAGE DOWNLOAD" }, 67 { NVME_OPC_DEVICE_SELF_TEST, "DEVICE SELF-TEST" }, 68 { NVME_OPC_NAMESPACE_ATTACHMENT, "NAMESPACE ATTACHMENT" }, 69 { NVME_OPC_KEEP_ALIVE, "KEEP ALIVE" }, 70 { NVME_OPC_DIRECTIVE_SEND, "DIRECTIVE SEND" }, 71 { NVME_OPC_DIRECTIVE_RECEIVE, "DIRECTIVE RECEIVE" }, 72 { NVME_OPC_VIRTUALIZATION_MANAGEMENT, "VIRTUALIZATION MANAGEMENT" }, 73 { NVME_OPC_NVME_MI_SEND, "NVME-MI SEND" }, 74 { NVME_OPC_NVME_MI_RECEIVE, "NVME-MI RECEIVE" }, 75 { NVME_OPC_DOORBELL_BUFFER_CONFIG, "DOORBELL BUFFER CONFIG" }, 76 { NVME_OPC_FORMAT_NVM, "FORMAT NVM" }, 77 { NVME_OPC_SECURITY_SEND, "SECURITY SEND" }, 78 { NVME_OPC_SECURITY_RECEIVE, "SECURITY RECEIVE" }, 79 { NVME_OPC_SANITIZE, "SANITIZE" }, 80 { 0xFFFF, "ADMIN COMMAND" } 81 }; 82 83 static struct nvme_opcode_string io_opcode[] = { 84 { NVME_OPC_FLUSH, "FLUSH" }, 85 { NVME_OPC_WRITE, "WRITE" }, 86 { NVME_OPC_READ, "READ" }, 87 { NVME_OPC_WRITE_UNCORRECTABLE, "WRITE UNCORRECTABLE" }, 88 { NVME_OPC_COMPARE, "COMPARE" }, 89 { NVME_OPC_WRITE_ZEROES, "WRITE ZEROES" }, 90 { NVME_OPC_DATASET_MANAGEMENT, "DATASET MANAGEMENT" }, 91 { NVME_OPC_RESERVATION_REGISTER, "RESERVATION REGISTER" }, 92 { NVME_OPC_RESERVATION_REPORT, "RESERVATION REPORT" }, 93 { NVME_OPC_RESERVATION_ACQUIRE, "RESERVATION ACQUIRE" }, 94 { NVME_OPC_RESERVATION_RELEASE, "RESERVATION RELEASE" }, 95 { 0xFFFF, "IO COMMAND" } 96 }; 97 98 static const char * 99 get_admin_opcode_string(uint16_t opc) 100 { 101 struct nvme_opcode_string *entry; 102 103 entry = admin_opcode; 104 105 while (entry->opc != 0xFFFF) { 106 if (entry->opc == opc) 107 return (entry->str); 108 entry++; 109 } 110 return (entry->str); 111 } 112 113 static const char * 114 get_io_opcode_string(uint16_t opc) 115 { 116 struct nvme_opcode_string *entry; 117 118 entry = io_opcode; 119 120 while (entry->opc != 0xFFFF) { 121 if (entry->opc == opc) 122 return (entry->str); 123 entry++; 124 } 125 return (entry->str); 126 } 127 128 129 static void 130 nvme_admin_qpair_print_command(struct nvme_qpair *qpair, 131 struct nvme_command *cmd) 132 { 133 134 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x " 135 "cdw10:%08x cdw11:%08x\n", 136 get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid, 137 le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11)); 138 } 139 140 static void 141 nvme_io_qpair_print_command(struct nvme_qpair *qpair, 142 struct nvme_command *cmd) 143 { 144 145 switch (cmd->opc) { 146 case NVME_OPC_WRITE: 147 case NVME_OPC_READ: 148 case NVME_OPC_WRITE_UNCORRECTABLE: 149 case NVME_OPC_COMPARE: 150 case NVME_OPC_WRITE_ZEROES: 151 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d " 152 "lba:%llu len:%d\n", 153 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid), 154 ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10), 155 (le32toh(cmd->cdw12) & 0xFFFF) + 1); 156 break; 157 case NVME_OPC_FLUSH: 158 case NVME_OPC_DATASET_MANAGEMENT: 159 case NVME_OPC_RESERVATION_REGISTER: 160 case NVME_OPC_RESERVATION_REPORT: 161 case NVME_OPC_RESERVATION_ACQUIRE: 162 case NVME_OPC_RESERVATION_RELEASE: 163 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n", 164 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid)); 165 break; 166 default: 167 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n", 168 get_io_opcode_string(cmd->opc), cmd->opc, qpair->id, 169 cmd->cid, le32toh(cmd->nsid)); 170 break; 171 } 172 } 173 174 static void 175 nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd) 176 { 177 if (qpair->id == 0) 178 nvme_admin_qpair_print_command(qpair, cmd); 179 else 180 nvme_io_qpair_print_command(qpair, cmd); 181 if (nvme_verbose_cmd_dump) { 182 nvme_printf(qpair->ctrlr, 183 "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n", 184 cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr, 185 (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2); 186 nvme_printf(qpair->ctrlr, 187 "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n", 188 cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14, 189 cmd->cdw15); 190 } 191 } 192 193 struct nvme_status_string { 194 195 uint16_t sc; 196 const char * str; 197 }; 198 199 static struct nvme_status_string generic_status[] = { 200 { NVME_SC_SUCCESS, "SUCCESS" }, 201 { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" }, 202 { NVME_SC_INVALID_FIELD, "INVALID_FIELD" }, 203 { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" }, 204 { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" }, 205 { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" }, 206 { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" }, 207 { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" }, 208 { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" }, 209 { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" }, 210 { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" }, 211 { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" }, 212 { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" }, 213 { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" }, 214 { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" }, 215 { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" }, 216 { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" }, 217 { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" }, 218 { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" }, 219 { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" }, 220 { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" }, 221 { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" }, 222 { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" }, 223 { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" }, 224 { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" }, 225 { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" }, 226 { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" }, 227 { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" }, 228 { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" }, 229 { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" }, 230 { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" }, 231 232 { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" }, 233 { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" }, 234 { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" }, 235 { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" }, 236 { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" }, 237 { 0xFFFF, "GENERIC" } 238 }; 239 240 static struct nvme_status_string command_specific_status[] = { 241 { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" }, 242 { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" }, 243 { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" }, 244 { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" }, 245 { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" }, 246 { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" }, 247 { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" }, 248 { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" }, 249 { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" }, 250 { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" }, 251 { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" }, 252 { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" }, 253 { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" }, 254 { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" }, 255 { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" }, 256 { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" }, 257 { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" }, 258 { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" }, 259 { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" }, 260 { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" }, 261 { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" }, 262 { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" }, 263 { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" }, 264 { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" }, 265 { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" }, 266 { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" }, 267 { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" }, 268 { NVME_SC_SELT_TEST_IN_PROGRESS, "DEVICE SELT-TEST IN PROGRESS" }, 269 { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" }, 270 { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" }, 271 { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" }, 272 { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" }, 273 { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" }, 274 275 { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" }, 276 { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" }, 277 { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" }, 278 { 0xFFFF, "COMMAND SPECIFIC" } 279 }; 280 281 static struct nvme_status_string media_error_status[] = { 282 { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" }, 283 { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" }, 284 { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" }, 285 { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" }, 286 { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" }, 287 { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" }, 288 { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" }, 289 { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" }, 290 { 0xFFFF, "MEDIA ERROR" } 291 }; 292 293 static const char * 294 get_status_string(uint16_t sct, uint16_t sc) 295 { 296 struct nvme_status_string *entry; 297 298 switch (sct) { 299 case NVME_SCT_GENERIC: 300 entry = generic_status; 301 break; 302 case NVME_SCT_COMMAND_SPECIFIC: 303 entry = command_specific_status; 304 break; 305 case NVME_SCT_MEDIA_ERROR: 306 entry = media_error_status; 307 break; 308 case NVME_SCT_VENDOR_SPECIFIC: 309 return ("VENDOR SPECIFIC"); 310 default: 311 return ("RESERVED"); 312 } 313 314 while (entry->sc != 0xFFFF) { 315 if (entry->sc == sc) 316 return (entry->str); 317 entry++; 318 } 319 return (entry->str); 320 } 321 322 static void 323 nvme_qpair_print_completion(struct nvme_qpair *qpair, 324 struct nvme_completion *cpl) 325 { 326 uint16_t sct, sc; 327 328 sct = NVME_STATUS_GET_SCT(cpl->status); 329 sc = NVME_STATUS_GET_SC(cpl->status); 330 331 nvme_printf(qpair->ctrlr, "%s (%02x/%02x) sqid:%d cid:%d cdw0:%x\n", 332 get_status_string(sct, sc), sct, sc, cpl->sqid, cpl->cid, 333 cpl->cdw0); 334 } 335 336 static boolean_t 337 nvme_completion_is_retry(const struct nvme_completion *cpl) 338 { 339 uint8_t sct, sc, dnr; 340 341 sct = NVME_STATUS_GET_SCT(cpl->status); 342 sc = NVME_STATUS_GET_SC(cpl->status); 343 dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */ 344 345 /* 346 * TODO: spec is not clear how commands that are aborted due 347 * to TLER will be marked. So for now, it seems 348 * NAMESPACE_NOT_READY is the only case where we should 349 * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST 350 * set the DNR bit correctly since the driver controls that. 351 */ 352 switch (sct) { 353 case NVME_SCT_GENERIC: 354 switch (sc) { 355 case NVME_SC_ABORTED_BY_REQUEST: 356 case NVME_SC_NAMESPACE_NOT_READY: 357 if (dnr) 358 return (0); 359 else 360 return (1); 361 case NVME_SC_INVALID_OPCODE: 362 case NVME_SC_INVALID_FIELD: 363 case NVME_SC_COMMAND_ID_CONFLICT: 364 case NVME_SC_DATA_TRANSFER_ERROR: 365 case NVME_SC_ABORTED_POWER_LOSS: 366 case NVME_SC_INTERNAL_DEVICE_ERROR: 367 case NVME_SC_ABORTED_SQ_DELETION: 368 case NVME_SC_ABORTED_FAILED_FUSED: 369 case NVME_SC_ABORTED_MISSING_FUSED: 370 case NVME_SC_INVALID_NAMESPACE_OR_FORMAT: 371 case NVME_SC_COMMAND_SEQUENCE_ERROR: 372 case NVME_SC_LBA_OUT_OF_RANGE: 373 case NVME_SC_CAPACITY_EXCEEDED: 374 default: 375 return (0); 376 } 377 case NVME_SCT_COMMAND_SPECIFIC: 378 case NVME_SCT_MEDIA_ERROR: 379 case NVME_SCT_VENDOR_SPECIFIC: 380 default: 381 return (0); 382 } 383 } 384 385 static void 386 nvme_qpair_complete_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr, 387 struct nvme_completion *cpl, error_print_t print_on_error) 388 { 389 struct nvme_request *req; 390 boolean_t retry, error, retriable; 391 392 req = tr->req; 393 error = nvme_completion_is_error(cpl); 394 retriable = nvme_completion_is_retry(cpl); 395 retry = error && retriable && req->retries < nvme_retry_count; 396 if (retry) 397 qpair->num_retries++; 398 if (error && req->retries >= nvme_retry_count && retriable) 399 qpair->num_failures++; 400 401 if (error && (print_on_error == ERROR_PRINT_ALL || 402 (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) { 403 nvme_qpair_print_command(qpair, &req->cmd); 404 nvme_qpair_print_completion(qpair, cpl); 405 } 406 407 qpair->act_tr[cpl->cid] = NULL; 408 409 KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n")); 410 411 if (req->cb_fn && !retry) 412 req->cb_fn(req->cb_arg, cpl); 413 414 mtx_lock(&qpair->lock); 415 callout_stop(&tr->timer); 416 417 if (retry) { 418 req->retries++; 419 nvme_qpair_submit_tracker(qpair, tr); 420 } else { 421 if (req->type != NVME_REQUEST_NULL) { 422 bus_dmamap_sync(qpair->dma_tag_payload, 423 tr->payload_dma_map, 424 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 425 bus_dmamap_unload(qpair->dma_tag_payload, 426 tr->payload_dma_map); 427 } 428 429 nvme_free_request(req); 430 tr->req = NULL; 431 432 TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq); 433 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 434 435 /* 436 * If the controller is in the middle of resetting, don't 437 * try to submit queued requests here - let the reset logic 438 * handle that instead. 439 */ 440 if (!STAILQ_EMPTY(&qpair->queued_req) && 441 !qpair->ctrlr->is_resetting) { 442 req = STAILQ_FIRST(&qpair->queued_req); 443 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 444 _nvme_qpair_submit_request(qpair, req); 445 } 446 } 447 448 mtx_unlock(&qpair->lock); 449 } 450 451 static void 452 nvme_qpair_manual_complete_tracker(struct nvme_qpair *qpair, 453 struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr, 454 error_print_t print_on_error) 455 { 456 struct nvme_completion cpl; 457 458 memset(&cpl, 0, sizeof(cpl)); 459 cpl.sqid = qpair->id; 460 cpl.cid = tr->cid; 461 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 462 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 463 cpl.status |= (dnr & NVME_STATUS_DNR_MASK) << NVME_STATUS_DNR_SHIFT; 464 nvme_qpair_complete_tracker(qpair, tr, &cpl, print_on_error); 465 } 466 467 void 468 nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 469 struct nvme_request *req, uint32_t sct, uint32_t sc) 470 { 471 struct nvme_completion cpl; 472 boolean_t error; 473 474 memset(&cpl, 0, sizeof(cpl)); 475 cpl.sqid = qpair->id; 476 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 477 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 478 479 error = nvme_completion_is_error(&cpl); 480 481 if (error) { 482 nvme_qpair_print_command(qpair, &req->cmd); 483 nvme_qpair_print_completion(qpair, &cpl); 484 } 485 486 if (req->cb_fn) 487 req->cb_fn(req->cb_arg, &cpl); 488 489 nvme_free_request(req); 490 } 491 492 bool 493 nvme_qpair_process_completions(struct nvme_qpair *qpair) 494 { 495 struct nvme_tracker *tr; 496 struct nvme_completion cpl; 497 int done = 0; 498 bool in_panic = dumping || SCHEDULER_STOPPED(); 499 500 qpair->num_intr_handler_calls++; 501 502 /* 503 * qpair is not enabled, likely because a controller reset is is in 504 * progress. Ignore the interrupt - any I/O that was associated with 505 * this interrupt will get retried when the reset is complete. 506 */ 507 if (!qpair->is_enabled) 508 return (false); 509 510 /* 511 * A panic can stop the CPU this routine is running on at any point. If 512 * we're called during a panic, complete the sq_head wrap protocol for 513 * the case where we are interrupted just after the increment at 1 514 * below, but before we can reset cq_head to zero at 2. Also cope with 515 * the case where we do the zero at 2, but may or may not have done the 516 * phase adjustment at step 3. The panic machinery flushes all pending 517 * memory writes, so we can make these strong ordering assumptions 518 * that would otherwise be unwise if we were racing in real time. 519 */ 520 if (__predict_false(in_panic)) { 521 if (qpair->cq_head == qpair->num_entries) { 522 /* 523 * Here we know that we need to zero cq_head and then negate 524 * the phase, which hasn't been assigned if cq_head isn't 525 * zero due to the atomic_store_rel. 526 */ 527 qpair->cq_head = 0; 528 qpair->phase = !qpair->phase; 529 } else if (qpair->cq_head == 0) { 530 /* 531 * In this case, we know that the assignment at 2 532 * happened below, but we don't know if it 3 happened or 533 * not. To do this, we look at the last completion 534 * entry and set the phase to the opposite phase 535 * that it has. This gets us back in sync 536 */ 537 cpl = qpair->cpl[qpair->num_entries - 1]; 538 nvme_completion_swapbytes(&cpl); 539 qpair->phase = !NVME_STATUS_GET_P(cpl.status); 540 } 541 } 542 543 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 544 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 545 while (1) { 546 cpl = qpair->cpl[qpair->cq_head]; 547 548 /* Convert to host endian */ 549 nvme_completion_swapbytes(&cpl); 550 551 if (NVME_STATUS_GET_P(cpl.status) != qpair->phase) 552 break; 553 554 tr = qpair->act_tr[cpl.cid]; 555 556 if (tr != NULL) { 557 nvme_qpair_complete_tracker(qpair, tr, &cpl, ERROR_PRINT_ALL); 558 qpair->sq_head = cpl.sqhd; 559 done++; 560 } else if (!in_panic) { 561 /* 562 * A missing tracker is normally an error. However, a 563 * panic can stop the CPU this routine is running on 564 * after completing an I/O but before updating 565 * qpair->cq_head at 1 below. Later, we re-enter this 566 * routine to poll I/O associated with the kernel 567 * dump. We find that the tr has been set to null before 568 * calling the completion routine. If it hasn't 569 * completed (or it triggers a panic), then '1' below 570 * won't have updated cq_head. Rather than panic again, 571 * ignore this condition because it's not unexpected. 572 */ 573 nvme_printf(qpair->ctrlr, 574 "cpl does not map to outstanding cmd\n"); 575 /* nvme_dump_completion expects device endianess */ 576 nvme_dump_completion(&qpair->cpl[qpair->cq_head]); 577 KASSERT(0, ("received completion for unknown cmd")); 578 } 579 580 /* 581 * There's a number of races with the following (see above) when 582 * the system panics. We compensate for each one of them by 583 * using the atomic store to force strong ordering (at least when 584 * viewed in the aftermath of a panic). 585 */ 586 if (++qpair->cq_head == qpair->num_entries) { /* 1 */ 587 atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */ 588 qpair->phase = !qpair->phase; /* 3 */ 589 } 590 591 nvme_mmio_write_4(qpair->ctrlr, doorbell[qpair->id].cq_hdbl, 592 qpair->cq_head); 593 } 594 return (done != 0); 595 } 596 597 static void 598 nvme_qpair_msix_handler(void *arg) 599 { 600 struct nvme_qpair *qpair = arg; 601 602 nvme_qpair_process_completions(qpair); 603 } 604 605 int 606 nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 607 uint16_t vector, uint32_t num_entries, uint32_t num_trackers, 608 struct nvme_controller *ctrlr) 609 { 610 struct nvme_tracker *tr; 611 size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz; 612 uint64_t queuemem_phys, prpmem_phys, list_phys; 613 uint8_t *queuemem, *prpmem, *prp_list; 614 int i, err; 615 616 qpair->id = id; 617 qpair->vector = vector; 618 qpair->num_entries = num_entries; 619 qpair->num_trackers = num_trackers; 620 qpair->ctrlr = ctrlr; 621 622 if (ctrlr->msix_enabled) { 623 624 /* 625 * MSI-X vector resource IDs start at 1, so we add one to 626 * the queue's vector to get the corresponding rid to use. 627 */ 628 qpair->rid = vector + 1; 629 630 qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 631 &qpair->rid, RF_ACTIVE); 632 bus_setup_intr(ctrlr->dev, qpair->res, 633 INTR_TYPE_MISC | INTR_MPSAFE, NULL, 634 nvme_qpair_msix_handler, qpair, &qpair->tag); 635 if (id == 0) { 636 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 637 "admin"); 638 } else { 639 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 640 "io%d", id - 1); 641 } 642 } 643 644 mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF); 645 646 /* Note: NVMe PRP format is restricted to 4-byte alignment. */ 647 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 648 4, PAGE_SIZE, BUS_SPACE_MAXADDR, 649 BUS_SPACE_MAXADDR, NULL, NULL, NVME_MAX_XFER_SIZE, 650 (NVME_MAX_XFER_SIZE/PAGE_SIZE)+1, PAGE_SIZE, 0, 651 NULL, NULL, &qpair->dma_tag_payload); 652 if (err != 0) { 653 nvme_printf(ctrlr, "payload tag create failed %d\n", err); 654 goto out; 655 } 656 657 /* 658 * Each component must be page aligned, and individual PRP lists 659 * cannot cross a page boundary. 660 */ 661 cmdsz = qpair->num_entries * sizeof(struct nvme_command); 662 cmdsz = roundup2(cmdsz, PAGE_SIZE); 663 cplsz = qpair->num_entries * sizeof(struct nvme_completion); 664 cplsz = roundup2(cplsz, PAGE_SIZE); 665 prpsz = sizeof(uint64_t) * NVME_MAX_PRP_LIST_ENTRIES;; 666 prpmemsz = qpair->num_trackers * prpsz; 667 allocsz = cmdsz + cplsz + prpmemsz; 668 669 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 670 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 671 allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag); 672 if (err != 0) { 673 nvme_printf(ctrlr, "tag create failed %d\n", err); 674 goto out; 675 } 676 677 if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem, 678 BUS_DMA_NOWAIT, &qpair->queuemem_map)) { 679 nvme_printf(ctrlr, "failed to alloc qpair memory\n"); 680 goto out; 681 } 682 683 if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map, 684 queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) { 685 nvme_printf(ctrlr, "failed to load qpair memory\n"); 686 goto out; 687 } 688 689 qpair->num_cmds = 0; 690 qpair->num_intr_handler_calls = 0; 691 qpair->num_retries = 0; 692 qpair->num_failures = 0; 693 qpair->cmd = (struct nvme_command *)queuemem; 694 qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz); 695 prpmem = (uint8_t *)(queuemem + cmdsz + cplsz); 696 qpair->cmd_bus_addr = queuemem_phys; 697 qpair->cpl_bus_addr = queuemem_phys + cmdsz; 698 prpmem_phys = queuemem_phys + cmdsz + cplsz; 699 700 qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[id].sq_tdbl); 701 qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[id].cq_hdbl); 702 703 TAILQ_INIT(&qpair->free_tr); 704 TAILQ_INIT(&qpair->outstanding_tr); 705 STAILQ_INIT(&qpair->queued_req); 706 707 list_phys = prpmem_phys; 708 prp_list = prpmem; 709 for (i = 0; i < qpair->num_trackers; i++) { 710 711 if (list_phys + prpsz > prpmem_phys + prpmemsz) { 712 qpair->num_trackers = i; 713 break; 714 } 715 716 /* 717 * Make sure that the PRP list for this tracker doesn't 718 * overflow to another page. 719 */ 720 if (trunc_page(list_phys) != 721 trunc_page(list_phys + prpsz - 1)) { 722 list_phys = roundup2(list_phys, PAGE_SIZE); 723 prp_list = 724 (uint8_t *)roundup2((uintptr_t)prp_list, PAGE_SIZE); 725 } 726 727 tr = malloc(sizeof(*tr), M_NVME, M_ZERO | M_WAITOK); 728 bus_dmamap_create(qpair->dma_tag_payload, 0, 729 &tr->payload_dma_map); 730 callout_init(&tr->timer, 1); 731 tr->cid = i; 732 tr->qpair = qpair; 733 tr->prp = (uint64_t *)prp_list; 734 tr->prp_bus_addr = list_phys; 735 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 736 list_phys += prpsz; 737 prp_list += prpsz; 738 } 739 740 if (qpair->num_trackers == 0) { 741 nvme_printf(ctrlr, "failed to allocate enough trackers\n"); 742 goto out; 743 } 744 745 qpair->act_tr = malloc(sizeof(struct nvme_tracker *) * 746 qpair->num_entries, M_NVME, M_ZERO | M_WAITOK); 747 return (0); 748 749 out: 750 nvme_qpair_destroy(qpair); 751 return (ENOMEM); 752 } 753 754 static void 755 nvme_qpair_destroy(struct nvme_qpair *qpair) 756 { 757 struct nvme_tracker *tr; 758 759 if (qpair->tag) 760 bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag); 761 762 if (mtx_initialized(&qpair->lock)) 763 mtx_destroy(&qpair->lock); 764 765 if (qpair->res) 766 bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ, 767 rman_get_rid(qpair->res), qpair->res); 768 769 if (qpair->cmd != NULL) { 770 bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map); 771 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 772 qpair->queuemem_map); 773 } 774 775 if (qpair->act_tr) 776 free(qpair->act_tr, M_NVME); 777 778 while (!TAILQ_EMPTY(&qpair->free_tr)) { 779 tr = TAILQ_FIRST(&qpair->free_tr); 780 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 781 bus_dmamap_destroy(qpair->dma_tag_payload, 782 tr->payload_dma_map); 783 free(tr, M_NVME); 784 } 785 786 if (qpair->dma_tag) 787 bus_dma_tag_destroy(qpair->dma_tag); 788 789 if (qpair->dma_tag_payload) 790 bus_dma_tag_destroy(qpair->dma_tag_payload); 791 } 792 793 static void 794 nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair) 795 { 796 struct nvme_tracker *tr; 797 798 tr = TAILQ_FIRST(&qpair->outstanding_tr); 799 while (tr != NULL) { 800 if (tr->req->cmd.opc == NVME_OPC_ASYNC_EVENT_REQUEST) { 801 nvme_qpair_manual_complete_tracker(qpair, tr, 802 NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0, 803 ERROR_PRINT_NONE); 804 tr = TAILQ_FIRST(&qpair->outstanding_tr); 805 } else { 806 tr = TAILQ_NEXT(tr, tailq); 807 } 808 } 809 } 810 811 void 812 nvme_admin_qpair_destroy(struct nvme_qpair *qpair) 813 { 814 815 nvme_admin_qpair_abort_aers(qpair); 816 nvme_qpair_destroy(qpair); 817 } 818 819 void 820 nvme_io_qpair_destroy(struct nvme_qpair *qpair) 821 { 822 823 nvme_qpair_destroy(qpair); 824 } 825 826 static void 827 nvme_abort_complete(void *arg, const struct nvme_completion *status) 828 { 829 struct nvme_tracker *tr = arg; 830 831 /* 832 * If cdw0 == 1, the controller was not able to abort the command 833 * we requested. We still need to check the active tracker array, 834 * to cover race where I/O timed out at same time controller was 835 * completing the I/O. 836 */ 837 if (status->cdw0 == 1 && tr->qpair->act_tr[tr->cid] != NULL) { 838 /* 839 * An I/O has timed out, and the controller was unable to 840 * abort it for some reason. Construct a fake completion 841 * status, and then complete the I/O's tracker manually. 842 */ 843 nvme_printf(tr->qpair->ctrlr, 844 "abort command failed, aborting command manually\n"); 845 nvme_qpair_manual_complete_tracker(tr->qpair, tr, 846 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_ALL); 847 } 848 } 849 850 static void 851 nvme_timeout(void *arg) 852 { 853 struct nvme_tracker *tr = arg; 854 struct nvme_qpair *qpair = tr->qpair; 855 struct nvme_controller *ctrlr = qpair->ctrlr; 856 uint32_t csts; 857 uint8_t cfs; 858 859 /* 860 * Read csts to get value of cfs - controller fatal status. 861 * If no fatal status, try to call the completion routine, and 862 * if completes transactions, report a missed interrupt and 863 * return (this may need to be rate limited). Otherwise, if 864 * aborts are enabled and the controller is not reporting 865 * fatal status, abort the command. Otherwise, just reset the 866 * controller and hope for the best. 867 */ 868 csts = nvme_mmio_read_4(ctrlr, csts); 869 cfs = (csts >> NVME_CSTS_REG_CFS_SHIFT) & NVME_CSTS_REG_CFS_MASK; 870 if (cfs == 0 && nvme_qpair_process_completions(qpair)) { 871 nvme_printf(ctrlr, "Missing interrupt\n"); 872 return; 873 } 874 if (ctrlr->enable_aborts && cfs == 0) { 875 nvme_printf(ctrlr, "Aborting command due to a timeout.\n"); 876 nvme_ctrlr_cmd_abort(ctrlr, tr->cid, qpair->id, 877 nvme_abort_complete, tr); 878 } else { 879 nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n", 880 cfs ? " and fatal error status" : ""); 881 nvme_ctrlr_reset(ctrlr); 882 } 883 } 884 885 void 886 nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr) 887 { 888 struct nvme_request *req; 889 struct nvme_controller *ctrlr; 890 891 mtx_assert(&qpair->lock, MA_OWNED); 892 893 req = tr->req; 894 req->cmd.cid = tr->cid; 895 qpair->act_tr[tr->cid] = tr; 896 ctrlr = qpair->ctrlr; 897 898 if (req->timeout) 899 callout_reset_curcpu(&tr->timer, ctrlr->timeout_period * hz, 900 nvme_timeout, tr); 901 902 /* Copy the command from the tracker to the submission queue. */ 903 memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd)); 904 905 if (++qpair->sq_tail == qpair->num_entries) 906 qpair->sq_tail = 0; 907 908 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 909 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 910 #ifndef __powerpc__ 911 /* 912 * powerpc's bus_dmamap_sync() already includes a heavyweight sync, but 913 * no other archs do. 914 */ 915 wmb(); 916 #endif 917 918 nvme_mmio_write_4(qpair->ctrlr, doorbell[qpair->id].sq_tdbl, 919 qpair->sq_tail); 920 921 qpair->num_cmds++; 922 } 923 924 static void 925 nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 926 { 927 struct nvme_tracker *tr = arg; 928 uint32_t cur_nseg; 929 930 /* 931 * If the mapping operation failed, return immediately. The caller 932 * is responsible for detecting the error status and failing the 933 * tracker manually. 934 */ 935 if (error != 0) { 936 nvme_printf(tr->qpair->ctrlr, 937 "nvme_payload_map err %d\n", error); 938 return; 939 } 940 941 /* 942 * Note that we specified PAGE_SIZE for alignment and max 943 * segment size when creating the bus dma tags. So here 944 * we can safely just transfer each segment to its 945 * associated PRP entry. 946 */ 947 tr->req->cmd.prp1 = htole64(seg[0].ds_addr); 948 949 if (nseg == 2) { 950 tr->req->cmd.prp2 = htole64(seg[1].ds_addr); 951 } else if (nseg > 2) { 952 cur_nseg = 1; 953 tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr); 954 while (cur_nseg < nseg) { 955 tr->prp[cur_nseg-1] = 956 htole64((uint64_t)seg[cur_nseg].ds_addr); 957 cur_nseg++; 958 } 959 } else { 960 /* 961 * prp2 should not be used by the controller 962 * since there is only one segment, but set 963 * to 0 just to be safe. 964 */ 965 tr->req->cmd.prp2 = 0; 966 } 967 968 bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map, 969 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 970 nvme_qpair_submit_tracker(tr->qpair, tr); 971 } 972 973 static void 974 _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 975 { 976 struct nvme_tracker *tr; 977 int err = 0; 978 979 mtx_assert(&qpair->lock, MA_OWNED); 980 981 tr = TAILQ_FIRST(&qpair->free_tr); 982 req->qpair = qpair; 983 984 if (tr == NULL || !qpair->is_enabled) { 985 /* 986 * No tracker is available, or the qpair is disabled due to 987 * an in-progress controller-level reset or controller 988 * failure. 989 */ 990 991 if (qpair->ctrlr->is_failed) { 992 /* 993 * The controller has failed. Post the request to a 994 * task where it will be aborted, so that we do not 995 * invoke the request's callback in the context 996 * of the submission. 997 */ 998 nvme_ctrlr_post_failed_request(qpair->ctrlr, req); 999 } else { 1000 /* 1001 * Put the request on the qpair's request queue to be 1002 * processed when a tracker frees up via a command 1003 * completion or when the controller reset is 1004 * completed. 1005 */ 1006 STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq); 1007 } 1008 return; 1009 } 1010 1011 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 1012 TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq); 1013 tr->req = req; 1014 1015 switch (req->type) { 1016 case NVME_REQUEST_VADDR: 1017 KASSERT(req->payload_size <= qpair->ctrlr->max_xfer_size, 1018 ("payload_size (%d) exceeds max_xfer_size (%d)\n", 1019 req->payload_size, qpair->ctrlr->max_xfer_size)); 1020 err = bus_dmamap_load(tr->qpair->dma_tag_payload, 1021 tr->payload_dma_map, req->u.payload, req->payload_size, 1022 nvme_payload_map, tr, 0); 1023 if (err != 0) 1024 nvme_printf(qpair->ctrlr, 1025 "bus_dmamap_load returned 0x%x!\n", err); 1026 break; 1027 case NVME_REQUEST_NULL: 1028 nvme_qpair_submit_tracker(tr->qpair, tr); 1029 break; 1030 case NVME_REQUEST_BIO: 1031 KASSERT(req->u.bio->bio_bcount <= qpair->ctrlr->max_xfer_size, 1032 ("bio->bio_bcount (%jd) exceeds max_xfer_size (%d)\n", 1033 (intmax_t)req->u.bio->bio_bcount, 1034 qpair->ctrlr->max_xfer_size)); 1035 err = bus_dmamap_load_bio(tr->qpair->dma_tag_payload, 1036 tr->payload_dma_map, req->u.bio, nvme_payload_map, tr, 0); 1037 if (err != 0) 1038 nvme_printf(qpair->ctrlr, 1039 "bus_dmamap_load_bio returned 0x%x!\n", err); 1040 break; 1041 case NVME_REQUEST_CCB: 1042 err = bus_dmamap_load_ccb(tr->qpair->dma_tag_payload, 1043 tr->payload_dma_map, req->u.payload, 1044 nvme_payload_map, tr, 0); 1045 if (err != 0) 1046 nvme_printf(qpair->ctrlr, 1047 "bus_dmamap_load_ccb returned 0x%x!\n", err); 1048 break; 1049 default: 1050 panic("unknown nvme request type 0x%x\n", req->type); 1051 break; 1052 } 1053 1054 if (err != 0) { 1055 /* 1056 * The dmamap operation failed, so we manually fail the 1057 * tracker here with DATA_TRANSFER_ERROR status. 1058 * 1059 * nvme_qpair_manual_complete_tracker must not be called 1060 * with the qpair lock held. 1061 */ 1062 mtx_unlock(&qpair->lock); 1063 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1064 NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL); 1065 mtx_lock(&qpair->lock); 1066 } 1067 } 1068 1069 void 1070 nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1071 { 1072 1073 mtx_lock(&qpair->lock); 1074 _nvme_qpair_submit_request(qpair, req); 1075 mtx_unlock(&qpair->lock); 1076 } 1077 1078 static void 1079 nvme_qpair_enable(struct nvme_qpair *qpair) 1080 { 1081 1082 qpair->is_enabled = TRUE; 1083 } 1084 1085 void 1086 nvme_qpair_reset(struct nvme_qpair *qpair) 1087 { 1088 1089 qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0; 1090 1091 /* 1092 * First time through the completion queue, HW will set phase 1093 * bit on completions to 1. So set this to 1 here, indicating 1094 * we're looking for a 1 to know which entries have completed. 1095 * we'll toggle the bit each time when the completion queue 1096 * rolls over. 1097 */ 1098 qpair->phase = 1; 1099 1100 memset(qpair->cmd, 0, 1101 qpair->num_entries * sizeof(struct nvme_command)); 1102 memset(qpair->cpl, 0, 1103 qpair->num_entries * sizeof(struct nvme_completion)); 1104 } 1105 1106 void 1107 nvme_admin_qpair_enable(struct nvme_qpair *qpair) 1108 { 1109 struct nvme_tracker *tr; 1110 struct nvme_tracker *tr_temp; 1111 1112 /* 1113 * Manually abort each outstanding admin command. Do not retry 1114 * admin commands found here, since they will be left over from 1115 * a controller reset and its likely the context in which the 1116 * command was issued no longer applies. 1117 */ 1118 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1119 nvme_printf(qpair->ctrlr, 1120 "aborting outstanding admin command\n"); 1121 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1122 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1123 } 1124 1125 nvme_qpair_enable(qpair); 1126 } 1127 1128 void 1129 nvme_io_qpair_enable(struct nvme_qpair *qpair) 1130 { 1131 STAILQ_HEAD(, nvme_request) temp; 1132 struct nvme_tracker *tr; 1133 struct nvme_tracker *tr_temp; 1134 struct nvme_request *req; 1135 1136 /* 1137 * Manually abort each outstanding I/O. This normally results in a 1138 * retry, unless the retry count on the associated request has 1139 * reached its limit. 1140 */ 1141 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1142 nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n"); 1143 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1144 NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY); 1145 } 1146 1147 mtx_lock(&qpair->lock); 1148 1149 nvme_qpair_enable(qpair); 1150 1151 STAILQ_INIT(&temp); 1152 STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request); 1153 1154 while (!STAILQ_EMPTY(&temp)) { 1155 req = STAILQ_FIRST(&temp); 1156 STAILQ_REMOVE_HEAD(&temp, stailq); 1157 nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n"); 1158 nvme_qpair_print_command(qpair, &req->cmd); 1159 _nvme_qpair_submit_request(qpair, req); 1160 } 1161 1162 mtx_unlock(&qpair->lock); 1163 } 1164 1165 static void 1166 nvme_qpair_disable(struct nvme_qpair *qpair) 1167 { 1168 struct nvme_tracker *tr; 1169 1170 qpair->is_enabled = FALSE; 1171 mtx_lock(&qpair->lock); 1172 TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) 1173 callout_stop(&tr->timer); 1174 mtx_unlock(&qpair->lock); 1175 } 1176 1177 void 1178 nvme_admin_qpair_disable(struct nvme_qpair *qpair) 1179 { 1180 1181 nvme_qpair_disable(qpair); 1182 nvme_admin_qpair_abort_aers(qpair); 1183 } 1184 1185 void 1186 nvme_io_qpair_disable(struct nvme_qpair *qpair) 1187 { 1188 1189 nvme_qpair_disable(qpair); 1190 } 1191 1192 void 1193 nvme_qpair_fail(struct nvme_qpair *qpair) 1194 { 1195 struct nvme_tracker *tr; 1196 struct nvme_request *req; 1197 1198 if (!mtx_initialized(&qpair->lock)) 1199 return; 1200 1201 mtx_lock(&qpair->lock); 1202 1203 while (!STAILQ_EMPTY(&qpair->queued_req)) { 1204 req = STAILQ_FIRST(&qpair->queued_req); 1205 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 1206 nvme_printf(qpair->ctrlr, "failing queued i/o\n"); 1207 mtx_unlock(&qpair->lock); 1208 nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC, 1209 NVME_SC_ABORTED_BY_REQUEST); 1210 mtx_lock(&qpair->lock); 1211 } 1212 1213 /* Manually abort each outstanding I/O. */ 1214 while (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1215 tr = TAILQ_FIRST(&qpair->outstanding_tr); 1216 /* 1217 * Do not remove the tracker. The abort_tracker path will 1218 * do that for us. 1219 */ 1220 nvme_printf(qpair->ctrlr, "failing outstanding i/o\n"); 1221 mtx_unlock(&qpair->lock); 1222 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1223 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1224 mtx_lock(&qpair->lock); 1225 } 1226 1227 mtx_unlock(&qpair->lock); 1228 } 1229 1230