1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/domainset.h> 36 #include <sys/proc.h> 37 38 #include <dev/pci/pcivar.h> 39 40 #include "nvme_private.h" 41 42 typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t; 43 #define DO_NOT_RETRY 1 44 45 static void _nvme_qpair_submit_request(struct nvme_qpair *qpair, 46 struct nvme_request *req); 47 static void nvme_qpair_destroy(struct nvme_qpair *qpair); 48 49 struct nvme_opcode_string { 50 uint16_t opc; 51 const char * str; 52 }; 53 54 static struct nvme_opcode_string admin_opcode[] = { 55 { NVME_OPC_DELETE_IO_SQ, "DELETE IO SQ" }, 56 { NVME_OPC_CREATE_IO_SQ, "CREATE IO SQ" }, 57 { NVME_OPC_GET_LOG_PAGE, "GET LOG PAGE" }, 58 { NVME_OPC_DELETE_IO_CQ, "DELETE IO CQ" }, 59 { NVME_OPC_CREATE_IO_CQ, "CREATE IO CQ" }, 60 { NVME_OPC_IDENTIFY, "IDENTIFY" }, 61 { NVME_OPC_ABORT, "ABORT" }, 62 { NVME_OPC_SET_FEATURES, "SET FEATURES" }, 63 { NVME_OPC_GET_FEATURES, "GET FEATURES" }, 64 { NVME_OPC_ASYNC_EVENT_REQUEST, "ASYNC EVENT REQUEST" }, 65 { NVME_OPC_FIRMWARE_ACTIVATE, "FIRMWARE ACTIVATE" }, 66 { NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD, "FIRMWARE IMAGE DOWNLOAD" }, 67 { NVME_OPC_DEVICE_SELF_TEST, "DEVICE SELF-TEST" }, 68 { NVME_OPC_NAMESPACE_ATTACHMENT, "NAMESPACE ATTACHMENT" }, 69 { NVME_OPC_KEEP_ALIVE, "KEEP ALIVE" }, 70 { NVME_OPC_DIRECTIVE_SEND, "DIRECTIVE SEND" }, 71 { NVME_OPC_DIRECTIVE_RECEIVE, "DIRECTIVE RECEIVE" }, 72 { NVME_OPC_VIRTUALIZATION_MANAGEMENT, "VIRTUALIZATION MANAGEMENT" }, 73 { NVME_OPC_NVME_MI_SEND, "NVME-MI SEND" }, 74 { NVME_OPC_NVME_MI_RECEIVE, "NVME-MI RECEIVE" }, 75 { NVME_OPC_DOORBELL_BUFFER_CONFIG, "DOORBELL BUFFER CONFIG" }, 76 { NVME_OPC_FORMAT_NVM, "FORMAT NVM" }, 77 { NVME_OPC_SECURITY_SEND, "SECURITY SEND" }, 78 { NVME_OPC_SECURITY_RECEIVE, "SECURITY RECEIVE" }, 79 { NVME_OPC_SANITIZE, "SANITIZE" }, 80 { NVME_OPC_GET_LBA_STATUS, "GET LBA STATUS" }, 81 { 0xFFFF, "ADMIN COMMAND" } 82 }; 83 84 static struct nvme_opcode_string io_opcode[] = { 85 { NVME_OPC_FLUSH, "FLUSH" }, 86 { NVME_OPC_WRITE, "WRITE" }, 87 { NVME_OPC_READ, "READ" }, 88 { NVME_OPC_WRITE_UNCORRECTABLE, "WRITE UNCORRECTABLE" }, 89 { NVME_OPC_COMPARE, "COMPARE" }, 90 { NVME_OPC_WRITE_ZEROES, "WRITE ZEROES" }, 91 { NVME_OPC_DATASET_MANAGEMENT, "DATASET MANAGEMENT" }, 92 { NVME_OPC_VERIFY, "VERIFY" }, 93 { NVME_OPC_RESERVATION_REGISTER, "RESERVATION REGISTER" }, 94 { NVME_OPC_RESERVATION_REPORT, "RESERVATION REPORT" }, 95 { NVME_OPC_RESERVATION_ACQUIRE, "RESERVATION ACQUIRE" }, 96 { NVME_OPC_RESERVATION_RELEASE, "RESERVATION RELEASE" }, 97 { 0xFFFF, "IO COMMAND" } 98 }; 99 100 static const char * 101 get_admin_opcode_string(uint16_t opc) 102 { 103 struct nvme_opcode_string *entry; 104 105 entry = admin_opcode; 106 107 while (entry->opc != 0xFFFF) { 108 if (entry->opc == opc) 109 return (entry->str); 110 entry++; 111 } 112 return (entry->str); 113 } 114 115 static const char * 116 get_io_opcode_string(uint16_t opc) 117 { 118 struct nvme_opcode_string *entry; 119 120 entry = io_opcode; 121 122 while (entry->opc != 0xFFFF) { 123 if (entry->opc == opc) 124 return (entry->str); 125 entry++; 126 } 127 return (entry->str); 128 } 129 130 static void 131 nvme_admin_qpair_print_command(struct nvme_qpair *qpair, 132 struct nvme_command *cmd) 133 { 134 135 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x " 136 "cdw10:%08x cdw11:%08x\n", 137 get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid, 138 le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11)); 139 } 140 141 static void 142 nvme_io_qpair_print_command(struct nvme_qpair *qpair, 143 struct nvme_command *cmd) 144 { 145 146 switch (cmd->opc) { 147 case NVME_OPC_WRITE: 148 case NVME_OPC_READ: 149 case NVME_OPC_WRITE_UNCORRECTABLE: 150 case NVME_OPC_COMPARE: 151 case NVME_OPC_WRITE_ZEROES: 152 case NVME_OPC_VERIFY: 153 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d " 154 "lba:%llu len:%d\n", 155 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid), 156 ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10), 157 (le32toh(cmd->cdw12) & 0xFFFF) + 1); 158 break; 159 case NVME_OPC_FLUSH: 160 case NVME_OPC_DATASET_MANAGEMENT: 161 case NVME_OPC_RESERVATION_REGISTER: 162 case NVME_OPC_RESERVATION_REPORT: 163 case NVME_OPC_RESERVATION_ACQUIRE: 164 case NVME_OPC_RESERVATION_RELEASE: 165 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n", 166 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid)); 167 break; 168 default: 169 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n", 170 get_io_opcode_string(cmd->opc), cmd->opc, qpair->id, 171 cmd->cid, le32toh(cmd->nsid)); 172 break; 173 } 174 } 175 176 static void 177 nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd) 178 { 179 if (qpair->id == 0) 180 nvme_admin_qpair_print_command(qpair, cmd); 181 else 182 nvme_io_qpair_print_command(qpair, cmd); 183 if (nvme_verbose_cmd_dump) { 184 nvme_printf(qpair->ctrlr, 185 "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n", 186 cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr, 187 (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2); 188 nvme_printf(qpair->ctrlr, 189 "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n", 190 cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14, 191 cmd->cdw15); 192 } 193 } 194 195 struct nvme_status_string { 196 uint16_t sc; 197 const char * str; 198 }; 199 200 static struct nvme_status_string generic_status[] = { 201 { NVME_SC_SUCCESS, "SUCCESS" }, 202 { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" }, 203 { NVME_SC_INVALID_FIELD, "INVALID_FIELD" }, 204 { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" }, 205 { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" }, 206 { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" }, 207 { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" }, 208 { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" }, 209 { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" }, 210 { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" }, 211 { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" }, 212 { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" }, 213 { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" }, 214 { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" }, 215 { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" }, 216 { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" }, 217 { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" }, 218 { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" }, 219 { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" }, 220 { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" }, 221 { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" }, 222 { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" }, 223 { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" }, 224 { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" }, 225 { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" }, 226 { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" }, 227 { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" }, 228 { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" }, 229 { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" }, 230 { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" }, 231 { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" }, 232 { NVME_SC_NAMESPACE_IS_WRITE_PROTECTED, "NAMESPACE IS WRITE PROTECTED" }, 233 { NVME_SC_COMMAND_INTERRUPTED, "COMMAND INTERRUPTED" }, 234 { NVME_SC_TRANSIENT_TRANSPORT_ERROR, "TRANSIENT TRANSPORT ERROR" }, 235 236 { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" }, 237 { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" }, 238 { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" }, 239 { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" }, 240 { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" }, 241 { 0xFFFF, "GENERIC" } 242 }; 243 244 static struct nvme_status_string command_specific_status[] = { 245 { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" }, 246 { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" }, 247 { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" }, 248 { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" }, 249 { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" }, 250 { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" }, 251 { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" }, 252 { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" }, 253 { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" }, 254 { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" }, 255 { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" }, 256 { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" }, 257 { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" }, 258 { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" }, 259 { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" }, 260 { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" }, 261 { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" }, 262 { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" }, 263 { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" }, 264 { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" }, 265 { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" }, 266 { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" }, 267 { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" }, 268 { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" }, 269 { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" }, 270 { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" }, 271 { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" }, 272 { NVME_SC_SELF_TEST_IN_PROGRESS, "DEVICE SELF-TEST IN PROGRESS" }, 273 { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" }, 274 { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" }, 275 { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" }, 276 { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" }, 277 { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" }, 278 { NVME_SC_SANITIZE_PROHIBITED_WPMRE, "SANITIZE PROHIBITED WRITE PERSISTENT MEMORY REGION ENABLED" }, 279 { NVME_SC_ANA_GROUP_ID_INVALID, "ANA GROUP IDENTIFIED INVALID" }, 280 { NVME_SC_ANA_ATTACH_FAILED, "ANA ATTACH FAILED" }, 281 282 { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" }, 283 { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" }, 284 { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" }, 285 { 0xFFFF, "COMMAND SPECIFIC" } 286 }; 287 288 static struct nvme_status_string media_error_status[] = { 289 { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" }, 290 { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" }, 291 { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" }, 292 { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" }, 293 { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" }, 294 { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" }, 295 { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" }, 296 { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" }, 297 { 0xFFFF, "MEDIA ERROR" } 298 }; 299 300 static struct nvme_status_string path_related_status[] = { 301 { NVME_SC_INTERNAL_PATH_ERROR, "INTERNAL PATH ERROR" }, 302 { NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS, "ASYMMETRIC ACCESS PERSISTENT LOSS" }, 303 { NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE, "ASYMMETRIC ACCESS INACCESSIBLE" }, 304 { NVME_SC_ASYMMETRIC_ACCESS_TRANSITION, "ASYMMETRIC ACCESS TRANSITION" }, 305 { NVME_SC_CONTROLLER_PATHING_ERROR, "CONTROLLER PATHING ERROR" }, 306 { NVME_SC_HOST_PATHING_ERROR, "HOST PATHING ERROR" }, 307 { NVME_SC_COMMAND_ABOTHED_BY_HOST, "COMMAND ABOTHED BY HOST" }, 308 { 0xFFFF, "PATH RELATED" }, 309 }; 310 311 static const char * 312 get_status_string(uint16_t sct, uint16_t sc) 313 { 314 struct nvme_status_string *entry; 315 316 switch (sct) { 317 case NVME_SCT_GENERIC: 318 entry = generic_status; 319 break; 320 case NVME_SCT_COMMAND_SPECIFIC: 321 entry = command_specific_status; 322 break; 323 case NVME_SCT_MEDIA_ERROR: 324 entry = media_error_status; 325 break; 326 case NVME_SCT_PATH_RELATED: 327 entry = path_related_status; 328 break; 329 case NVME_SCT_VENDOR_SPECIFIC: 330 return ("VENDOR SPECIFIC"); 331 default: 332 return ("RESERVED"); 333 } 334 335 while (entry->sc != 0xFFFF) { 336 if (entry->sc == sc) 337 return (entry->str); 338 entry++; 339 } 340 return (entry->str); 341 } 342 343 static void 344 nvme_qpair_print_completion(struct nvme_qpair *qpair, 345 struct nvme_completion *cpl) 346 { 347 uint16_t sct, sc; 348 349 sct = NVME_STATUS_GET_SCT(cpl->status); 350 sc = NVME_STATUS_GET_SC(cpl->status); 351 352 nvme_printf(qpair->ctrlr, "%s (%02x/%02x) sqid:%d cid:%d cdw0:%x\n", 353 get_status_string(sct, sc), sct, sc, cpl->sqid, cpl->cid, 354 cpl->cdw0); 355 } 356 357 static bool 358 nvme_completion_is_retry(const struct nvme_completion *cpl) 359 { 360 uint8_t sct, sc, dnr; 361 362 sct = NVME_STATUS_GET_SCT(cpl->status); 363 sc = NVME_STATUS_GET_SC(cpl->status); 364 dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */ 365 366 /* 367 * TODO: spec is not clear how commands that are aborted due 368 * to TLER will be marked. So for now, it seems 369 * NAMESPACE_NOT_READY is the only case where we should 370 * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST 371 * set the DNR bit correctly since the driver controls that. 372 */ 373 switch (sct) { 374 case NVME_SCT_GENERIC: 375 switch (sc) { 376 case NVME_SC_ABORTED_BY_REQUEST: 377 case NVME_SC_NAMESPACE_NOT_READY: 378 if (dnr) 379 return (0); 380 else 381 return (1); 382 case NVME_SC_INVALID_OPCODE: 383 case NVME_SC_INVALID_FIELD: 384 case NVME_SC_COMMAND_ID_CONFLICT: 385 case NVME_SC_DATA_TRANSFER_ERROR: 386 case NVME_SC_ABORTED_POWER_LOSS: 387 case NVME_SC_INTERNAL_DEVICE_ERROR: 388 case NVME_SC_ABORTED_SQ_DELETION: 389 case NVME_SC_ABORTED_FAILED_FUSED: 390 case NVME_SC_ABORTED_MISSING_FUSED: 391 case NVME_SC_INVALID_NAMESPACE_OR_FORMAT: 392 case NVME_SC_COMMAND_SEQUENCE_ERROR: 393 case NVME_SC_LBA_OUT_OF_RANGE: 394 case NVME_SC_CAPACITY_EXCEEDED: 395 default: 396 return (0); 397 } 398 case NVME_SCT_COMMAND_SPECIFIC: 399 case NVME_SCT_MEDIA_ERROR: 400 return (0); 401 case NVME_SCT_PATH_RELATED: 402 switch (sc) { 403 case NVME_SC_INTERNAL_PATH_ERROR: 404 if (dnr) 405 return (0); 406 else 407 return (1); 408 default: 409 return (0); 410 } 411 case NVME_SCT_VENDOR_SPECIFIC: 412 default: 413 return (0); 414 } 415 } 416 417 static void 418 nvme_qpair_complete_tracker(struct nvme_tracker *tr, 419 struct nvme_completion *cpl, error_print_t print_on_error) 420 { 421 struct nvme_qpair * qpair = tr->qpair; 422 struct nvme_request *req; 423 bool retry, error, retriable; 424 425 req = tr->req; 426 error = nvme_completion_is_error(cpl); 427 retriable = nvme_completion_is_retry(cpl); 428 retry = error && retriable && req->retries < nvme_retry_count; 429 if (retry) 430 qpair->num_retries++; 431 if (error && req->retries >= nvme_retry_count && retriable) 432 qpair->num_failures++; 433 434 if (error && (print_on_error == ERROR_PRINT_ALL || 435 (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) { 436 nvme_qpair_print_command(qpair, &req->cmd); 437 nvme_qpair_print_completion(qpair, cpl); 438 } 439 440 qpair->act_tr[cpl->cid] = NULL; 441 442 KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n")); 443 444 if (!retry) { 445 if (req->type != NVME_REQUEST_NULL) { 446 bus_dmamap_sync(qpair->dma_tag_payload, 447 tr->payload_dma_map, 448 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 449 } 450 if (req->cb_fn) 451 req->cb_fn(req->cb_arg, cpl); 452 } 453 454 mtx_lock(&qpair->lock); 455 456 if (retry) { 457 req->retries++; 458 nvme_qpair_submit_tracker(qpair, tr); 459 } else { 460 if (req->type != NVME_REQUEST_NULL) { 461 bus_dmamap_unload(qpair->dma_tag_payload, 462 tr->payload_dma_map); 463 } 464 465 nvme_free_request(req); 466 tr->req = NULL; 467 468 TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq); 469 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 470 471 /* 472 * If the controller is in the middle of resetting, don't 473 * try to submit queued requests here - let the reset logic 474 * handle that instead. 475 */ 476 if (!STAILQ_EMPTY(&qpair->queued_req) && 477 !qpair->ctrlr->is_resetting) { 478 req = STAILQ_FIRST(&qpair->queued_req); 479 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 480 _nvme_qpair_submit_request(qpair, req); 481 } 482 } 483 484 mtx_unlock(&qpair->lock); 485 } 486 487 static void 488 nvme_qpair_manual_complete_tracker( 489 struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr, 490 error_print_t print_on_error) 491 { 492 struct nvme_completion cpl; 493 494 memset(&cpl, 0, sizeof(cpl)); 495 496 struct nvme_qpair * qpair = tr->qpair; 497 498 cpl.sqid = qpair->id; 499 cpl.cid = tr->cid; 500 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 501 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 502 cpl.status |= (dnr & NVME_STATUS_DNR_MASK) << NVME_STATUS_DNR_SHIFT; 503 nvme_qpair_complete_tracker(tr, &cpl, print_on_error); 504 } 505 506 void 507 nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 508 struct nvme_request *req, uint32_t sct, uint32_t sc) 509 { 510 struct nvme_completion cpl; 511 bool error; 512 513 memset(&cpl, 0, sizeof(cpl)); 514 cpl.sqid = qpair->id; 515 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 516 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 517 518 error = nvme_completion_is_error(&cpl); 519 520 if (error) { 521 nvme_qpair_print_command(qpair, &req->cmd); 522 nvme_qpair_print_completion(qpair, &cpl); 523 } 524 525 if (req->cb_fn) 526 req->cb_fn(req->cb_arg, &cpl); 527 528 nvme_free_request(req); 529 } 530 531 bool 532 nvme_qpair_process_completions(struct nvme_qpair *qpair) 533 { 534 struct nvme_tracker *tr; 535 struct nvme_completion cpl; 536 int done = 0; 537 bool in_panic = dumping || SCHEDULER_STOPPED(); 538 539 /* 540 * qpair is not enabled, likely because a controller reset is in 541 * progress. Ignore the interrupt - any I/O that was associated with 542 * this interrupt will get retried when the reset is complete. Any 543 * pending completions for when we're in startup will be completed 544 * as soon as initialization is complete and we start sending commands 545 * to the device. 546 */ 547 if (qpair->recovery_state != RECOVERY_NONE) { 548 qpair->num_ignored++; 549 return (false); 550 } 551 552 /* 553 * Sanity check initialization. After we reset the hardware, the phase 554 * is defined to be 1. So if we get here with zero prior calls and the 555 * phase is 0, it means that we've lost a race between the 556 * initialization and the ISR running. With the phase wrong, we'll 557 * process a bunch of completions that aren't really completions leading 558 * to a KASSERT below. 559 */ 560 KASSERT(!(qpair->num_intr_handler_calls == 0 && qpair->phase == 0), 561 ("%s: Phase wrong for first interrupt call.", 562 device_get_nameunit(qpair->ctrlr->dev))); 563 564 qpair->num_intr_handler_calls++; 565 566 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 567 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 568 /* 569 * A panic can stop the CPU this routine is running on at any point. If 570 * we're called during a panic, complete the sq_head wrap protocol for 571 * the case where we are interrupted just after the increment at 1 572 * below, but before we can reset cq_head to zero at 2. Also cope with 573 * the case where we do the zero at 2, but may or may not have done the 574 * phase adjustment at step 3. The panic machinery flushes all pending 575 * memory writes, so we can make these strong ordering assumptions 576 * that would otherwise be unwise if we were racing in real time. 577 */ 578 if (__predict_false(in_panic)) { 579 if (qpair->cq_head == qpair->num_entries) { 580 /* 581 * Here we know that we need to zero cq_head and then negate 582 * the phase, which hasn't been assigned if cq_head isn't 583 * zero due to the atomic_store_rel. 584 */ 585 qpair->cq_head = 0; 586 qpair->phase = !qpair->phase; 587 } else if (qpair->cq_head == 0) { 588 /* 589 * In this case, we know that the assignment at 2 590 * happened below, but we don't know if it 3 happened or 591 * not. To do this, we look at the last completion 592 * entry and set the phase to the opposite phase 593 * that it has. This gets us back in sync 594 */ 595 cpl = qpair->cpl[qpair->num_entries - 1]; 596 nvme_completion_swapbytes(&cpl); 597 qpair->phase = !NVME_STATUS_GET_P(cpl.status); 598 } 599 } 600 601 while (1) { 602 uint16_t status; 603 604 /* 605 * We need to do this dance to avoid a race between the host and 606 * the device where the device overtakes the host while the host 607 * is reading this record, leaving the status field 'new' and 608 * the sqhd and cid fields potentially stale. If the phase 609 * doesn't match, that means status hasn't yet been updated and 610 * we'll get any pending changes next time. It also means that 611 * the phase must be the same the second time. We have to sync 612 * before reading to ensure any bouncing completes. 613 */ 614 status = le16toh(qpair->cpl[qpair->cq_head].status); 615 if (NVME_STATUS_GET_P(status) != qpair->phase) 616 break; 617 618 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 619 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 620 cpl = qpair->cpl[qpair->cq_head]; 621 nvme_completion_swapbytes(&cpl); 622 623 KASSERT( 624 NVME_STATUS_GET_P(status) == NVME_STATUS_GET_P(cpl.status), 625 ("Phase unexpectedly inconsistent")); 626 627 if (cpl.cid < qpair->num_trackers) 628 tr = qpair->act_tr[cpl.cid]; 629 else 630 tr = NULL; 631 632 done++; 633 if (tr != NULL) { 634 nvme_qpair_complete_tracker(tr, &cpl, ERROR_PRINT_ALL); 635 qpair->sq_head = cpl.sqhd; 636 } else if (!in_panic) { 637 /* 638 * A missing tracker is normally an error. However, a 639 * panic can stop the CPU this routine is running on 640 * after completing an I/O but before updating 641 * qpair->cq_head at 1 below. Later, we re-enter this 642 * routine to poll I/O associated with the kernel 643 * dump. We find that the tr has been set to null before 644 * calling the completion routine. If it hasn't 645 * completed (or it triggers a panic), then '1' below 646 * won't have updated cq_head. Rather than panic again, 647 * ignore this condition because it's not unexpected. 648 */ 649 nvme_printf(qpair->ctrlr, 650 "cpl (cid = %u) does not map to outstanding cmd\n", 651 cpl.cid); 652 /* nvme_dump_completion expects device endianess */ 653 nvme_dump_completion(&qpair->cpl[qpair->cq_head]); 654 KASSERT(0, ("received completion for unknown cmd")); 655 } 656 657 /* 658 * There's a number of races with the following (see above) when 659 * the system panics. We compensate for each one of them by 660 * using the atomic store to force strong ordering (at least when 661 * viewed in the aftermath of a panic). 662 */ 663 if (++qpair->cq_head == qpair->num_entries) { /* 1 */ 664 atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */ 665 qpair->phase = !qpair->phase; /* 3 */ 666 } 667 } 668 669 if (done != 0) { 670 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 671 qpair->cq_hdbl_off, qpair->cq_head); 672 } 673 674 return (done != 0); 675 } 676 677 static void 678 nvme_qpair_msi_handler(void *arg) 679 { 680 struct nvme_qpair *qpair = arg; 681 682 nvme_qpair_process_completions(qpair); 683 } 684 685 int 686 nvme_qpair_construct(struct nvme_qpair *qpair, 687 uint32_t num_entries, uint32_t num_trackers, 688 struct nvme_controller *ctrlr) 689 { 690 struct nvme_tracker *tr; 691 size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz; 692 uint64_t queuemem_phys, prpmem_phys, list_phys; 693 uint8_t *queuemem, *prpmem, *prp_list; 694 int i, err; 695 696 qpair->vector = ctrlr->msi_count > 1 ? qpair->id : 0; 697 qpair->num_entries = num_entries; 698 qpair->num_trackers = num_trackers; 699 qpair->ctrlr = ctrlr; 700 701 mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF); 702 703 /* Note: NVMe PRP format is restricted to 4-byte alignment. */ 704 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 705 4, ctrlr->page_size, BUS_SPACE_MAXADDR, 706 BUS_SPACE_MAXADDR, NULL, NULL, ctrlr->max_xfer_size, 707 howmany(ctrlr->max_xfer_size, ctrlr->page_size) + 1, 708 ctrlr->page_size, 0, 709 NULL, NULL, &qpair->dma_tag_payload); 710 if (err != 0) { 711 nvme_printf(ctrlr, "payload tag create failed %d\n", err); 712 goto out; 713 } 714 715 /* 716 * Each component must be page aligned, and individual PRP lists 717 * cannot cross a page boundary. 718 */ 719 cmdsz = qpair->num_entries * sizeof(struct nvme_command); 720 cmdsz = roundup2(cmdsz, ctrlr->page_size); 721 cplsz = qpair->num_entries * sizeof(struct nvme_completion); 722 cplsz = roundup2(cplsz, ctrlr->page_size); 723 /* 724 * For commands requiring more than 2 PRP entries, one PRP will be 725 * embedded in the command (prp1), and the rest of the PRP entries 726 * will be in a list pointed to by the command (prp2). 727 */ 728 prpsz = sizeof(uint64_t) * 729 howmany(ctrlr->max_xfer_size, ctrlr->page_size); 730 prpmemsz = qpair->num_trackers * prpsz; 731 allocsz = cmdsz + cplsz + prpmemsz; 732 733 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 734 ctrlr->page_size, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 735 allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag); 736 if (err != 0) { 737 nvme_printf(ctrlr, "tag create failed %d\n", err); 738 goto out; 739 } 740 bus_dma_tag_set_domain(qpair->dma_tag, qpair->domain); 741 742 if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem, 743 BUS_DMA_COHERENT | BUS_DMA_NOWAIT, &qpair->queuemem_map)) { 744 nvme_printf(ctrlr, "failed to alloc qpair memory\n"); 745 goto out; 746 } 747 748 if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map, 749 queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) { 750 nvme_printf(ctrlr, "failed to load qpair memory\n"); 751 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 752 qpair->queuemem_map); 753 goto out; 754 } 755 756 qpair->num_cmds = 0; 757 qpair->num_intr_handler_calls = 0; 758 qpair->num_retries = 0; 759 qpair->num_failures = 0; 760 qpair->num_ignored = 0; 761 qpair->cmd = (struct nvme_command *)queuemem; 762 qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz); 763 prpmem = (uint8_t *)(queuemem + cmdsz + cplsz); 764 qpair->cmd_bus_addr = queuemem_phys; 765 qpair->cpl_bus_addr = queuemem_phys + cmdsz; 766 prpmem_phys = queuemem_phys + cmdsz + cplsz; 767 768 callout_init(&qpair->timer, 1); 769 qpair->timer_armed = false; 770 qpair->recovery_state = RECOVERY_WAITING; 771 772 /* 773 * Calcuate the stride of the doorbell register. Many emulators set this 774 * value to correspond to a cache line. However, some hardware has set 775 * it to various small values. 776 */ 777 qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[0]) + 778 (qpair->id << (ctrlr->dstrd + 1)); 779 qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[0]) + 780 (qpair->id << (ctrlr->dstrd + 1)) + (1 << ctrlr->dstrd); 781 782 TAILQ_INIT(&qpair->free_tr); 783 TAILQ_INIT(&qpair->outstanding_tr); 784 STAILQ_INIT(&qpair->queued_req); 785 786 list_phys = prpmem_phys; 787 prp_list = prpmem; 788 for (i = 0; i < qpair->num_trackers; i++) { 789 if (list_phys + prpsz > prpmem_phys + prpmemsz) { 790 qpair->num_trackers = i; 791 break; 792 } 793 794 /* 795 * Make sure that the PRP list for this tracker doesn't 796 * overflow to another nvme page. 797 */ 798 if (trunc_page(list_phys) != 799 trunc_page(list_phys + prpsz - 1)) { 800 list_phys = roundup2(list_phys, ctrlr->page_size); 801 prp_list = 802 (uint8_t *)roundup2((uintptr_t)prp_list, ctrlr->page_size); 803 } 804 805 tr = malloc_domainset(sizeof(*tr), M_NVME, 806 DOMAINSET_PREF(qpair->domain), M_ZERO | M_WAITOK); 807 bus_dmamap_create(qpair->dma_tag_payload, 0, 808 &tr->payload_dma_map); 809 tr->cid = i; 810 tr->qpair = qpair; 811 tr->prp = (uint64_t *)prp_list; 812 tr->prp_bus_addr = list_phys; 813 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 814 list_phys += prpsz; 815 prp_list += prpsz; 816 } 817 818 if (qpair->num_trackers == 0) { 819 nvme_printf(ctrlr, "failed to allocate enough trackers\n"); 820 goto out; 821 } 822 823 qpair->act_tr = malloc_domainset(sizeof(struct nvme_tracker *) * 824 qpair->num_entries, M_NVME, DOMAINSET_PREF(qpair->domain), 825 M_ZERO | M_WAITOK); 826 827 if (ctrlr->msi_count > 1) { 828 /* 829 * MSI-X vector resource IDs start at 1, so we add one to 830 * the queue's vector to get the corresponding rid to use. 831 */ 832 qpair->rid = qpair->vector + 1; 833 834 qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 835 &qpair->rid, RF_ACTIVE); 836 if (qpair->res == NULL) { 837 nvme_printf(ctrlr, "unable to allocate MSI\n"); 838 goto out; 839 } 840 if (bus_setup_intr(ctrlr->dev, qpair->res, 841 INTR_TYPE_MISC | INTR_MPSAFE, NULL, 842 nvme_qpair_msi_handler, qpair, &qpair->tag) != 0) { 843 nvme_printf(ctrlr, "unable to setup MSI\n"); 844 goto out; 845 } 846 if (qpair->id == 0) { 847 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 848 "admin"); 849 } else { 850 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 851 "io%d", qpair->id - 1); 852 } 853 } 854 855 return (0); 856 857 out: 858 nvme_qpair_destroy(qpair); 859 return (ENOMEM); 860 } 861 862 static void 863 nvme_qpair_destroy(struct nvme_qpair *qpair) 864 { 865 struct nvme_tracker *tr; 866 867 callout_drain(&qpair->timer); 868 869 if (qpair->tag) { 870 bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag); 871 qpair->tag = NULL; 872 } 873 874 if (qpair->act_tr) { 875 free(qpair->act_tr, M_NVME); 876 qpair->act_tr = NULL; 877 } 878 879 while (!TAILQ_EMPTY(&qpair->free_tr)) { 880 tr = TAILQ_FIRST(&qpair->free_tr); 881 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 882 bus_dmamap_destroy(qpair->dma_tag_payload, 883 tr->payload_dma_map); 884 free(tr, M_NVME); 885 } 886 887 if (qpair->cmd != NULL) { 888 bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map); 889 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 890 qpair->queuemem_map); 891 qpair->cmd = NULL; 892 } 893 894 if (qpair->dma_tag) { 895 bus_dma_tag_destroy(qpair->dma_tag); 896 qpair->dma_tag = NULL; 897 } 898 899 if (qpair->dma_tag_payload) { 900 bus_dma_tag_destroy(qpair->dma_tag_payload); 901 qpair->dma_tag_payload = NULL; 902 } 903 904 if (mtx_initialized(&qpair->lock)) 905 mtx_destroy(&qpair->lock); 906 907 if (qpair->res) { 908 bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ, 909 rman_get_rid(qpair->res), qpair->res); 910 qpair->res = NULL; 911 } 912 } 913 914 static void 915 nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair) 916 { 917 struct nvme_tracker *tr; 918 919 tr = TAILQ_FIRST(&qpair->outstanding_tr); 920 while (tr != NULL) { 921 if (tr->req->cmd.opc == NVME_OPC_ASYNC_EVENT_REQUEST) { 922 nvme_qpair_manual_complete_tracker(tr, 923 NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0, 924 ERROR_PRINT_NONE); 925 tr = TAILQ_FIRST(&qpair->outstanding_tr); 926 } else { 927 tr = TAILQ_NEXT(tr, tailq); 928 } 929 } 930 } 931 932 void 933 nvme_admin_qpair_destroy(struct nvme_qpair *qpair) 934 { 935 936 nvme_admin_qpair_abort_aers(qpair); 937 nvme_qpair_destroy(qpair); 938 } 939 940 void 941 nvme_io_qpair_destroy(struct nvme_qpair *qpair) 942 { 943 944 nvme_qpair_destroy(qpair); 945 } 946 947 static void 948 nvme_qpair_timeout(void *arg) 949 { 950 struct nvme_qpair *qpair = arg; 951 struct nvme_controller *ctrlr = qpair->ctrlr; 952 struct nvme_tracker *tr; 953 sbintime_t now; 954 bool idle; 955 uint32_t csts; 956 uint8_t cfs; 957 958 mtx_lock(&qpair->lock); 959 idle = TAILQ_EMPTY(&qpair->outstanding_tr); 960 again: 961 switch (qpair->recovery_state) { 962 case RECOVERY_NONE: 963 if (idle) 964 break; 965 now = getsbinuptime(); 966 idle = true; 967 TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) { 968 if (tr->deadline == SBT_MAX) 969 continue; 970 idle = false; 971 if (now > tr->deadline) { 972 /* 973 * We're now passed our earliest deadline. We 974 * need to do expensive things to cope, but next 975 * time. Flag that and close the door to any 976 * further processing. 977 */ 978 qpair->recovery_state = RECOVERY_START; 979 nvme_printf(ctrlr, "RECOVERY_START %jd vs %jd\n", 980 (uintmax_t)now, (uintmax_t)tr->deadline); 981 break; 982 } 983 } 984 break; 985 case RECOVERY_START: 986 /* 987 * Read csts to get value of cfs - controller fatal status. 988 * If no fatal status, try to call the completion routine, and 989 * if completes transactions, report a missed interrupt and 990 * return (this may need to be rate limited). Otherwise, if 991 * aborts are enabled and the controller is not reporting 992 * fatal status, abort the command. Otherwise, just reset the 993 * controller and hope for the best. 994 */ 995 csts = nvme_mmio_read_4(ctrlr, csts); 996 cfs = (csts >> NVME_CSTS_REG_CFS_SHIFT) & NVME_CSTS_REG_CFS_MASK; 997 if (cfs) { 998 nvme_printf(ctrlr, "Controller in fatal status, resetting\n"); 999 qpair->recovery_state = RECOVERY_RESET; 1000 goto again; 1001 } 1002 mtx_unlock(&qpair->lock); 1003 if (nvme_qpair_process_completions(qpair)) { 1004 nvme_printf(ctrlr, "Completions present in output without an interrupt\n"); 1005 qpair->recovery_state = RECOVERY_NONE; 1006 } else { 1007 nvme_printf(ctrlr, "timeout with nothing complete, resetting\n"); 1008 qpair->recovery_state = RECOVERY_RESET; 1009 mtx_lock(&qpair->lock); 1010 goto again; 1011 } 1012 mtx_lock(&qpair->lock); 1013 break; 1014 case RECOVERY_RESET: 1015 /* 1016 * If we get here due to a possible surprise hot-unplug event, 1017 * then we let nvme_ctrlr_reset confirm and fail the 1018 * controller. 1019 */ 1020 nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n", 1021 (csts == 0xffffffff) ? " and possible hot unplug" : 1022 (cfs ? " and fatal error status" : "")); 1023 nvme_printf(ctrlr, "RECOVERY_WAITING\n"); 1024 qpair->recovery_state = RECOVERY_WAITING; 1025 nvme_ctrlr_reset(ctrlr); 1026 break; 1027 case RECOVERY_WAITING: 1028 nvme_printf(ctrlr, "waiting\n"); 1029 break; 1030 } 1031 1032 /* 1033 * Rearm the timeout. 1034 */ 1035 if (!idle) { 1036 callout_schedule_sbt(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 0); 1037 } else { 1038 qpair->timer_armed = false; 1039 } 1040 mtx_unlock(&qpair->lock); 1041 } 1042 1043 /* 1044 * Submit the tracker to the hardware. Must already be in the 1045 * outstanding queue when called. 1046 */ 1047 void 1048 nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr) 1049 { 1050 struct nvme_request *req; 1051 struct nvme_controller *ctrlr; 1052 int timeout; 1053 1054 mtx_assert(&qpair->lock, MA_OWNED); 1055 1056 req = tr->req; 1057 req->cmd.cid = tr->cid; 1058 qpair->act_tr[tr->cid] = tr; 1059 ctrlr = qpair->ctrlr; 1060 1061 if (req->timeout) { 1062 if (req->cb_fn == nvme_completion_poll_cb) 1063 timeout = 1; 1064 else 1065 timeout = ctrlr->timeout_period; 1066 tr->deadline = getsbinuptime() + timeout * SBT_1S; 1067 if (!qpair->timer_armed) { 1068 qpair->timer_armed = true; 1069 callout_reset_sbt_on(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 1070 nvme_qpair_timeout, qpair, qpair->cpu, 0); 1071 } 1072 } else 1073 tr->deadline = SBT_MAX; 1074 1075 /* Copy the command from the tracker to the submission queue. */ 1076 memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd)); 1077 1078 if (++qpair->sq_tail == qpair->num_entries) 1079 qpair->sq_tail = 0; 1080 1081 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 1082 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1083 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 1084 qpair->sq_tdbl_off, qpair->sq_tail); 1085 qpair->num_cmds++; 1086 } 1087 1088 static void 1089 nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 1090 { 1091 struct nvme_tracker *tr = arg; 1092 uint32_t cur_nseg; 1093 1094 /* 1095 * If the mapping operation failed, return immediately. The caller 1096 * is responsible for detecting the error status and failing the 1097 * tracker manually. 1098 */ 1099 if (error != 0) { 1100 nvme_printf(tr->qpair->ctrlr, 1101 "nvme_payload_map err %d\n", error); 1102 return; 1103 } 1104 1105 /* 1106 * Note that we specified ctrlr->page_size for alignment and max 1107 * segment size when creating the bus dma tags. So here we can safely 1108 * just transfer each segment to its associated PRP entry. 1109 */ 1110 tr->req->cmd.prp1 = htole64(seg[0].ds_addr); 1111 1112 if (nseg == 2) { 1113 tr->req->cmd.prp2 = htole64(seg[1].ds_addr); 1114 } else if (nseg > 2) { 1115 cur_nseg = 1; 1116 tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr); 1117 while (cur_nseg < nseg) { 1118 tr->prp[cur_nseg-1] = 1119 htole64((uint64_t)seg[cur_nseg].ds_addr); 1120 cur_nseg++; 1121 } 1122 } else { 1123 /* 1124 * prp2 should not be used by the controller 1125 * since there is only one segment, but set 1126 * to 0 just to be safe. 1127 */ 1128 tr->req->cmd.prp2 = 0; 1129 } 1130 1131 bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map, 1132 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1133 nvme_qpair_submit_tracker(tr->qpair, tr); 1134 } 1135 1136 static void 1137 _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1138 { 1139 struct nvme_tracker *tr; 1140 int err = 0; 1141 1142 mtx_assert(&qpair->lock, MA_OWNED); 1143 1144 tr = TAILQ_FIRST(&qpair->free_tr); 1145 req->qpair = qpair; 1146 1147 if (tr == NULL || qpair->recovery_state != RECOVERY_NONE) { 1148 /* 1149 * No tracker is available, or the qpair is disabled due to 1150 * an in-progress controller-level reset or controller 1151 * failure. 1152 */ 1153 1154 if (qpair->ctrlr->is_failed) { 1155 /* 1156 * The controller has failed, so fail the request. 1157 */ 1158 nvme_qpair_manual_complete_request(qpair, req, 1159 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST); 1160 } else { 1161 /* 1162 * Put the request on the qpair's request queue to be 1163 * processed when a tracker frees up via a command 1164 * completion or when the controller reset is 1165 * completed. 1166 */ 1167 STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq); 1168 } 1169 return; 1170 } 1171 1172 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 1173 TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq); 1174 if (!qpair->timer_armed) 1175 tr->deadline = SBT_MAX; 1176 tr->req = req; 1177 1178 switch (req->type) { 1179 case NVME_REQUEST_VADDR: 1180 KASSERT(req->payload_size <= qpair->ctrlr->max_xfer_size, 1181 ("payload_size (%d) exceeds max_xfer_size (%d)\n", 1182 req->payload_size, qpair->ctrlr->max_xfer_size)); 1183 err = bus_dmamap_load(tr->qpair->dma_tag_payload, 1184 tr->payload_dma_map, req->u.payload, req->payload_size, 1185 nvme_payload_map, tr, 0); 1186 if (err != 0) 1187 nvme_printf(qpair->ctrlr, 1188 "bus_dmamap_load returned 0x%x!\n", err); 1189 break; 1190 case NVME_REQUEST_NULL: 1191 nvme_qpair_submit_tracker(tr->qpair, tr); 1192 break; 1193 case NVME_REQUEST_BIO: 1194 KASSERT(req->u.bio->bio_bcount <= qpair->ctrlr->max_xfer_size, 1195 ("bio->bio_bcount (%jd) exceeds max_xfer_size (%d)\n", 1196 (intmax_t)req->u.bio->bio_bcount, 1197 qpair->ctrlr->max_xfer_size)); 1198 err = bus_dmamap_load_bio(tr->qpair->dma_tag_payload, 1199 tr->payload_dma_map, req->u.bio, nvme_payload_map, tr, 0); 1200 if (err != 0) 1201 nvme_printf(qpair->ctrlr, 1202 "bus_dmamap_load_bio returned 0x%x!\n", err); 1203 break; 1204 case NVME_REQUEST_CCB: 1205 err = bus_dmamap_load_ccb(tr->qpair->dma_tag_payload, 1206 tr->payload_dma_map, req->u.payload, 1207 nvme_payload_map, tr, 0); 1208 if (err != 0) 1209 nvme_printf(qpair->ctrlr, 1210 "bus_dmamap_load_ccb returned 0x%x!\n", err); 1211 break; 1212 default: 1213 panic("unknown nvme request type 0x%x\n", req->type); 1214 break; 1215 } 1216 1217 if (err != 0) { 1218 /* 1219 * The dmamap operation failed, so we manually fail the 1220 * tracker here with DATA_TRANSFER_ERROR status. 1221 * 1222 * nvme_qpair_manual_complete_tracker must not be called 1223 * with the qpair lock held. 1224 */ 1225 mtx_unlock(&qpair->lock); 1226 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1227 NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL); 1228 mtx_lock(&qpair->lock); 1229 } 1230 } 1231 1232 void 1233 nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1234 { 1235 1236 mtx_lock(&qpair->lock); 1237 _nvme_qpair_submit_request(qpair, req); 1238 mtx_unlock(&qpair->lock); 1239 } 1240 1241 static void 1242 nvme_qpair_enable(struct nvme_qpair *qpair) 1243 { 1244 mtx_assert(&qpair->lock, MA_OWNED); 1245 1246 qpair->recovery_state = RECOVERY_NONE; 1247 } 1248 1249 void 1250 nvme_qpair_reset(struct nvme_qpair *qpair) 1251 { 1252 1253 qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0; 1254 1255 /* 1256 * First time through the completion queue, HW will set phase 1257 * bit on completions to 1. So set this to 1 here, indicating 1258 * we're looking for a 1 to know which entries have completed. 1259 * we'll toggle the bit each time when the completion queue 1260 * rolls over. 1261 */ 1262 qpair->phase = 1; 1263 1264 memset(qpair->cmd, 0, 1265 qpair->num_entries * sizeof(struct nvme_command)); 1266 memset(qpair->cpl, 0, 1267 qpair->num_entries * sizeof(struct nvme_completion)); 1268 } 1269 1270 void 1271 nvme_admin_qpair_enable(struct nvme_qpair *qpair) 1272 { 1273 struct nvme_tracker *tr; 1274 struct nvme_tracker *tr_temp; 1275 1276 /* 1277 * Manually abort each outstanding admin command. Do not retry 1278 * admin commands found here, since they will be left over from 1279 * a controller reset and its likely the context in which the 1280 * command was issued no longer applies. 1281 */ 1282 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1283 nvme_printf(qpair->ctrlr, 1284 "aborting outstanding admin command\n"); 1285 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1286 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1287 } 1288 1289 mtx_lock(&qpair->lock); 1290 nvme_qpair_enable(qpair); 1291 mtx_unlock(&qpair->lock); 1292 } 1293 1294 void 1295 nvme_io_qpair_enable(struct nvme_qpair *qpair) 1296 { 1297 STAILQ_HEAD(, nvme_request) temp; 1298 struct nvme_tracker *tr; 1299 struct nvme_tracker *tr_temp; 1300 struct nvme_request *req; 1301 1302 /* 1303 * Manually abort each outstanding I/O. This normally results in a 1304 * retry, unless the retry count on the associated request has 1305 * reached its limit. 1306 */ 1307 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1308 nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n"); 1309 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1310 NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY); 1311 } 1312 1313 mtx_lock(&qpair->lock); 1314 1315 nvme_qpair_enable(qpair); 1316 1317 STAILQ_INIT(&temp); 1318 STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request); 1319 1320 while (!STAILQ_EMPTY(&temp)) { 1321 req = STAILQ_FIRST(&temp); 1322 STAILQ_REMOVE_HEAD(&temp, stailq); 1323 nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n"); 1324 nvme_qpair_print_command(qpair, &req->cmd); 1325 _nvme_qpair_submit_request(qpair, req); 1326 } 1327 1328 mtx_unlock(&qpair->lock); 1329 } 1330 1331 static void 1332 nvme_qpair_disable(struct nvme_qpair *qpair) 1333 { 1334 struct nvme_tracker *tr, *tr_temp; 1335 1336 mtx_lock(&qpair->lock); 1337 qpair->recovery_state = RECOVERY_WAITING; 1338 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1339 tr->deadline = SBT_MAX; 1340 } 1341 mtx_unlock(&qpair->lock); 1342 } 1343 1344 void 1345 nvme_admin_qpair_disable(struct nvme_qpair *qpair) 1346 { 1347 1348 nvme_qpair_disable(qpair); 1349 nvme_admin_qpair_abort_aers(qpair); 1350 } 1351 1352 void 1353 nvme_io_qpair_disable(struct nvme_qpair *qpair) 1354 { 1355 1356 nvme_qpair_disable(qpair); 1357 } 1358 1359 void 1360 nvme_qpair_fail(struct nvme_qpair *qpair) 1361 { 1362 struct nvme_tracker *tr; 1363 struct nvme_request *req; 1364 1365 if (!mtx_initialized(&qpair->lock)) 1366 return; 1367 1368 mtx_lock(&qpair->lock); 1369 1370 while (!STAILQ_EMPTY(&qpair->queued_req)) { 1371 req = STAILQ_FIRST(&qpair->queued_req); 1372 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 1373 nvme_printf(qpair->ctrlr, "failing queued i/o\n"); 1374 mtx_unlock(&qpair->lock); 1375 nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC, 1376 NVME_SC_ABORTED_BY_REQUEST); 1377 mtx_lock(&qpair->lock); 1378 } 1379 1380 /* Manually abort each outstanding I/O. */ 1381 while (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1382 tr = TAILQ_FIRST(&qpair->outstanding_tr); 1383 /* 1384 * Do not remove the tracker. The abort_tracker path will 1385 * do that for us. 1386 */ 1387 nvme_printf(qpair->ctrlr, "failing outstanding i/o\n"); 1388 mtx_unlock(&qpair->lock); 1389 nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 1390 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1391 mtx_lock(&qpair->lock); 1392 } 1393 1394 mtx_unlock(&qpair->lock); 1395 } 1396