1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/domainset.h> 36 #include <sys/proc.h> 37 38 #include <dev/pci/pcivar.h> 39 40 #include "nvme_private.h" 41 42 typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t; 43 #define DO_NOT_RETRY 1 44 45 static void _nvme_qpair_submit_request(struct nvme_qpair *qpair, 46 struct nvme_request *req); 47 static void nvme_qpair_destroy(struct nvme_qpair *qpair); 48 49 struct nvme_opcode_string { 50 51 uint16_t opc; 52 const char * str; 53 }; 54 55 static struct nvme_opcode_string admin_opcode[] = { 56 { NVME_OPC_DELETE_IO_SQ, "DELETE IO SQ" }, 57 { NVME_OPC_CREATE_IO_SQ, "CREATE IO SQ" }, 58 { NVME_OPC_GET_LOG_PAGE, "GET LOG PAGE" }, 59 { NVME_OPC_DELETE_IO_CQ, "DELETE IO CQ" }, 60 { NVME_OPC_CREATE_IO_CQ, "CREATE IO CQ" }, 61 { NVME_OPC_IDENTIFY, "IDENTIFY" }, 62 { NVME_OPC_ABORT, "ABORT" }, 63 { NVME_OPC_SET_FEATURES, "SET FEATURES" }, 64 { NVME_OPC_GET_FEATURES, "GET FEATURES" }, 65 { NVME_OPC_ASYNC_EVENT_REQUEST, "ASYNC EVENT REQUEST" }, 66 { NVME_OPC_FIRMWARE_ACTIVATE, "FIRMWARE ACTIVATE" }, 67 { NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD, "FIRMWARE IMAGE DOWNLOAD" }, 68 { NVME_OPC_DEVICE_SELF_TEST, "DEVICE SELF-TEST" }, 69 { NVME_OPC_NAMESPACE_ATTACHMENT, "NAMESPACE ATTACHMENT" }, 70 { NVME_OPC_KEEP_ALIVE, "KEEP ALIVE" }, 71 { NVME_OPC_DIRECTIVE_SEND, "DIRECTIVE SEND" }, 72 { NVME_OPC_DIRECTIVE_RECEIVE, "DIRECTIVE RECEIVE" }, 73 { NVME_OPC_VIRTUALIZATION_MANAGEMENT, "VIRTUALIZATION MANAGEMENT" }, 74 { NVME_OPC_NVME_MI_SEND, "NVME-MI SEND" }, 75 { NVME_OPC_NVME_MI_RECEIVE, "NVME-MI RECEIVE" }, 76 { NVME_OPC_DOORBELL_BUFFER_CONFIG, "DOORBELL BUFFER CONFIG" }, 77 { NVME_OPC_FORMAT_NVM, "FORMAT NVM" }, 78 { NVME_OPC_SECURITY_SEND, "SECURITY SEND" }, 79 { NVME_OPC_SECURITY_RECEIVE, "SECURITY RECEIVE" }, 80 { NVME_OPC_SANITIZE, "SANITIZE" }, 81 { NVME_OPC_GET_LBA_STATUS, "GET LBA STATUS" }, 82 { 0xFFFF, "ADMIN COMMAND" } 83 }; 84 85 static struct nvme_opcode_string io_opcode[] = { 86 { NVME_OPC_FLUSH, "FLUSH" }, 87 { NVME_OPC_WRITE, "WRITE" }, 88 { NVME_OPC_READ, "READ" }, 89 { NVME_OPC_WRITE_UNCORRECTABLE, "WRITE UNCORRECTABLE" }, 90 { NVME_OPC_COMPARE, "COMPARE" }, 91 { NVME_OPC_WRITE_ZEROES, "WRITE ZEROES" }, 92 { NVME_OPC_DATASET_MANAGEMENT, "DATASET MANAGEMENT" }, 93 { NVME_OPC_VERIFY, "VERIFY" }, 94 { NVME_OPC_RESERVATION_REGISTER, "RESERVATION REGISTER" }, 95 { NVME_OPC_RESERVATION_REPORT, "RESERVATION REPORT" }, 96 { NVME_OPC_RESERVATION_ACQUIRE, "RESERVATION ACQUIRE" }, 97 { NVME_OPC_RESERVATION_RELEASE, "RESERVATION RELEASE" }, 98 { 0xFFFF, "IO COMMAND" } 99 }; 100 101 static const char * 102 get_admin_opcode_string(uint16_t opc) 103 { 104 struct nvme_opcode_string *entry; 105 106 entry = admin_opcode; 107 108 while (entry->opc != 0xFFFF) { 109 if (entry->opc == opc) 110 return (entry->str); 111 entry++; 112 } 113 return (entry->str); 114 } 115 116 static const char * 117 get_io_opcode_string(uint16_t opc) 118 { 119 struct nvme_opcode_string *entry; 120 121 entry = io_opcode; 122 123 while (entry->opc != 0xFFFF) { 124 if (entry->opc == opc) 125 return (entry->str); 126 entry++; 127 } 128 return (entry->str); 129 } 130 131 132 static void 133 nvme_admin_qpair_print_command(struct nvme_qpair *qpair, 134 struct nvme_command *cmd) 135 { 136 137 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x " 138 "cdw10:%08x cdw11:%08x\n", 139 get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid, 140 le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11)); 141 } 142 143 static void 144 nvme_io_qpair_print_command(struct nvme_qpair *qpair, 145 struct nvme_command *cmd) 146 { 147 148 switch (cmd->opc) { 149 case NVME_OPC_WRITE: 150 case NVME_OPC_READ: 151 case NVME_OPC_WRITE_UNCORRECTABLE: 152 case NVME_OPC_COMPARE: 153 case NVME_OPC_WRITE_ZEROES: 154 case NVME_OPC_VERIFY: 155 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d " 156 "lba:%llu len:%d\n", 157 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid), 158 ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10), 159 (le32toh(cmd->cdw12) & 0xFFFF) + 1); 160 break; 161 case NVME_OPC_FLUSH: 162 case NVME_OPC_DATASET_MANAGEMENT: 163 case NVME_OPC_RESERVATION_REGISTER: 164 case NVME_OPC_RESERVATION_REPORT: 165 case NVME_OPC_RESERVATION_ACQUIRE: 166 case NVME_OPC_RESERVATION_RELEASE: 167 nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n", 168 get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid)); 169 break; 170 default: 171 nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n", 172 get_io_opcode_string(cmd->opc), cmd->opc, qpair->id, 173 cmd->cid, le32toh(cmd->nsid)); 174 break; 175 } 176 } 177 178 static void 179 nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd) 180 { 181 if (qpair->id == 0) 182 nvme_admin_qpair_print_command(qpair, cmd); 183 else 184 nvme_io_qpair_print_command(qpair, cmd); 185 if (nvme_verbose_cmd_dump) { 186 nvme_printf(qpair->ctrlr, 187 "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n", 188 cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr, 189 (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2); 190 nvme_printf(qpair->ctrlr, 191 "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n", 192 cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14, 193 cmd->cdw15); 194 } 195 } 196 197 struct nvme_status_string { 198 199 uint16_t sc; 200 const char * str; 201 }; 202 203 static struct nvme_status_string generic_status[] = { 204 { NVME_SC_SUCCESS, "SUCCESS" }, 205 { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" }, 206 { NVME_SC_INVALID_FIELD, "INVALID_FIELD" }, 207 { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" }, 208 { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" }, 209 { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" }, 210 { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" }, 211 { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" }, 212 { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" }, 213 { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" }, 214 { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" }, 215 { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" }, 216 { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" }, 217 { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" }, 218 { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" }, 219 { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" }, 220 { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" }, 221 { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" }, 222 { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" }, 223 { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" }, 224 { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" }, 225 { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" }, 226 { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" }, 227 { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" }, 228 { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" }, 229 { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" }, 230 { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" }, 231 { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" }, 232 { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" }, 233 { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" }, 234 { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" }, 235 { NVME_SC_NAMESPACE_IS_WRITE_PROTECTED, "NAMESPACE IS WRITE PROTECTED" }, 236 { NVME_SC_COMMAND_INTERRUPTED, "COMMAND INTERRUPTED" }, 237 { NVME_SC_TRANSIENT_TRANSPORT_ERROR, "TRANSIENT TRANSPORT ERROR" }, 238 239 { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" }, 240 { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" }, 241 { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" }, 242 { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" }, 243 { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" }, 244 { 0xFFFF, "GENERIC" } 245 }; 246 247 static struct nvme_status_string command_specific_status[] = { 248 { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" }, 249 { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" }, 250 { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" }, 251 { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" }, 252 { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" }, 253 { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" }, 254 { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" }, 255 { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" }, 256 { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" }, 257 { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" }, 258 { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" }, 259 { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" }, 260 { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" }, 261 { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" }, 262 { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" }, 263 { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" }, 264 { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" }, 265 { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" }, 266 { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" }, 267 { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" }, 268 { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" }, 269 { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" }, 270 { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" }, 271 { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" }, 272 { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" }, 273 { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" }, 274 { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" }, 275 { NVME_SC_SELT_TEST_IN_PROGRESS, "DEVICE SELT-TEST IN PROGRESS" }, 276 { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" }, 277 { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" }, 278 { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" }, 279 { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" }, 280 { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" }, 281 { NVME_SC_SANITIZE_PROHIBITED_WPMRE, "SANITIZE PROHIBITED WRITE PERSISTENT MEMORY REGION ENABLED" }, 282 { NVME_SC_ANA_GROUP_ID_INVALID, "ANA GROUP IDENTIFIED INVALID" }, 283 { NVME_SC_ANA_ATTACH_FAILED, "ANA ATTACH FAILED" }, 284 285 { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" }, 286 { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" }, 287 { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" }, 288 { 0xFFFF, "COMMAND SPECIFIC" } 289 }; 290 291 static struct nvme_status_string media_error_status[] = { 292 { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" }, 293 { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" }, 294 { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" }, 295 { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" }, 296 { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" }, 297 { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" }, 298 { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" }, 299 { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" }, 300 { 0xFFFF, "MEDIA ERROR" } 301 }; 302 303 static struct nvme_status_string path_related_status[] = { 304 { NVME_SC_INTERNAL_PATH_ERROR, "INTERNAL PATH ERROR" }, 305 { NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS, "ASYMMETRIC ACCESS PERSISTENT LOSS" }, 306 { NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE, "ASYMMETRIC ACCESS INACCESSIBLE" }, 307 { NVME_SC_ASYMMETRIC_ACCESS_TRANSITION, "ASYMMETRIC ACCESS TRANSITION" }, 308 { NVME_SC_CONTROLLER_PATHING_ERROR, "CONTROLLER PATHING ERROR" }, 309 { NVME_SC_HOST_PATHING_ERROR, "HOST PATHING ERROR" }, 310 { NVME_SC_COMMAND_ABOTHED_BY_HOST, "COMMAND ABOTHED BY HOST" }, 311 { 0xFFFF, "PATH RELATED" }, 312 }; 313 314 static const char * 315 get_status_string(uint16_t sct, uint16_t sc) 316 { 317 struct nvme_status_string *entry; 318 319 switch (sct) { 320 case NVME_SCT_GENERIC: 321 entry = generic_status; 322 break; 323 case NVME_SCT_COMMAND_SPECIFIC: 324 entry = command_specific_status; 325 break; 326 case NVME_SCT_MEDIA_ERROR: 327 entry = media_error_status; 328 break; 329 case NVME_SCT_PATH_RELATED: 330 entry = path_related_status; 331 break; 332 case NVME_SCT_VENDOR_SPECIFIC: 333 return ("VENDOR SPECIFIC"); 334 default: 335 return ("RESERVED"); 336 } 337 338 while (entry->sc != 0xFFFF) { 339 if (entry->sc == sc) 340 return (entry->str); 341 entry++; 342 } 343 return (entry->str); 344 } 345 346 static void 347 nvme_qpair_print_completion(struct nvme_qpair *qpair, 348 struct nvme_completion *cpl) 349 { 350 uint16_t sct, sc; 351 352 sct = NVME_STATUS_GET_SCT(cpl->status); 353 sc = NVME_STATUS_GET_SC(cpl->status); 354 355 nvme_printf(qpair->ctrlr, "%s (%02x/%02x) sqid:%d cid:%d cdw0:%x\n", 356 get_status_string(sct, sc), sct, sc, cpl->sqid, cpl->cid, 357 cpl->cdw0); 358 } 359 360 static boolean_t 361 nvme_completion_is_retry(const struct nvme_completion *cpl) 362 { 363 uint8_t sct, sc, dnr; 364 365 sct = NVME_STATUS_GET_SCT(cpl->status); 366 sc = NVME_STATUS_GET_SC(cpl->status); 367 dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */ 368 369 /* 370 * TODO: spec is not clear how commands that are aborted due 371 * to TLER will be marked. So for now, it seems 372 * NAMESPACE_NOT_READY is the only case where we should 373 * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST 374 * set the DNR bit correctly since the driver controls that. 375 */ 376 switch (sct) { 377 case NVME_SCT_GENERIC: 378 switch (sc) { 379 case NVME_SC_ABORTED_BY_REQUEST: 380 case NVME_SC_NAMESPACE_NOT_READY: 381 if (dnr) 382 return (0); 383 else 384 return (1); 385 case NVME_SC_INVALID_OPCODE: 386 case NVME_SC_INVALID_FIELD: 387 case NVME_SC_COMMAND_ID_CONFLICT: 388 case NVME_SC_DATA_TRANSFER_ERROR: 389 case NVME_SC_ABORTED_POWER_LOSS: 390 case NVME_SC_INTERNAL_DEVICE_ERROR: 391 case NVME_SC_ABORTED_SQ_DELETION: 392 case NVME_SC_ABORTED_FAILED_FUSED: 393 case NVME_SC_ABORTED_MISSING_FUSED: 394 case NVME_SC_INVALID_NAMESPACE_OR_FORMAT: 395 case NVME_SC_COMMAND_SEQUENCE_ERROR: 396 case NVME_SC_LBA_OUT_OF_RANGE: 397 case NVME_SC_CAPACITY_EXCEEDED: 398 default: 399 return (0); 400 } 401 case NVME_SCT_COMMAND_SPECIFIC: 402 case NVME_SCT_MEDIA_ERROR: 403 return (0); 404 case NVME_SCT_PATH_RELATED: 405 switch (sc) { 406 case NVME_SC_INTERNAL_PATH_ERROR: 407 if (dnr) 408 return (0); 409 else 410 return (1); 411 default: 412 return (0); 413 } 414 case NVME_SCT_VENDOR_SPECIFIC: 415 default: 416 return (0); 417 } 418 } 419 420 static void 421 nvme_qpair_complete_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr, 422 struct nvme_completion *cpl, error_print_t print_on_error) 423 { 424 struct nvme_request *req; 425 boolean_t retry, error, retriable; 426 427 req = tr->req; 428 error = nvme_completion_is_error(cpl); 429 retriable = nvme_completion_is_retry(cpl); 430 retry = error && retriable && req->retries < nvme_retry_count; 431 if (retry) 432 qpair->num_retries++; 433 if (error && req->retries >= nvme_retry_count && retriable) 434 qpair->num_failures++; 435 436 if (error && (print_on_error == ERROR_PRINT_ALL || 437 (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) { 438 nvme_qpair_print_command(qpair, &req->cmd); 439 nvme_qpair_print_completion(qpair, cpl); 440 } 441 442 qpair->act_tr[cpl->cid] = NULL; 443 444 KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n")); 445 446 if (req->cb_fn && !retry) 447 req->cb_fn(req->cb_arg, cpl); 448 449 mtx_lock(&qpair->lock); 450 callout_stop(&tr->timer); 451 452 if (retry) { 453 req->retries++; 454 nvme_qpair_submit_tracker(qpair, tr); 455 } else { 456 if (req->type != NVME_REQUEST_NULL) { 457 bus_dmamap_sync(qpair->dma_tag_payload, 458 tr->payload_dma_map, 459 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 460 bus_dmamap_unload(qpair->dma_tag_payload, 461 tr->payload_dma_map); 462 } 463 464 nvme_free_request(req); 465 tr->req = NULL; 466 467 TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq); 468 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 469 470 /* 471 * If the controller is in the middle of resetting, don't 472 * try to submit queued requests here - let the reset logic 473 * handle that instead. 474 */ 475 if (!STAILQ_EMPTY(&qpair->queued_req) && 476 !qpair->ctrlr->is_resetting) { 477 req = STAILQ_FIRST(&qpair->queued_req); 478 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 479 _nvme_qpair_submit_request(qpair, req); 480 } 481 } 482 483 mtx_unlock(&qpair->lock); 484 } 485 486 static void 487 nvme_qpair_manual_complete_tracker(struct nvme_qpair *qpair, 488 struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr, 489 error_print_t print_on_error) 490 { 491 struct nvme_completion cpl; 492 493 memset(&cpl, 0, sizeof(cpl)); 494 cpl.sqid = qpair->id; 495 cpl.cid = tr->cid; 496 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 497 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 498 cpl.status |= (dnr & NVME_STATUS_DNR_MASK) << NVME_STATUS_DNR_SHIFT; 499 nvme_qpair_complete_tracker(qpair, tr, &cpl, print_on_error); 500 } 501 502 void 503 nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 504 struct nvme_request *req, uint32_t sct, uint32_t sc) 505 { 506 struct nvme_completion cpl; 507 boolean_t error; 508 509 memset(&cpl, 0, sizeof(cpl)); 510 cpl.sqid = qpair->id; 511 cpl.status |= (sct & NVME_STATUS_SCT_MASK) << NVME_STATUS_SCT_SHIFT; 512 cpl.status |= (sc & NVME_STATUS_SC_MASK) << NVME_STATUS_SC_SHIFT; 513 514 error = nvme_completion_is_error(&cpl); 515 516 if (error) { 517 nvme_qpair_print_command(qpair, &req->cmd); 518 nvme_qpair_print_completion(qpair, &cpl); 519 } 520 521 if (req->cb_fn) 522 req->cb_fn(req->cb_arg, &cpl); 523 524 nvme_free_request(req); 525 } 526 527 bool 528 nvme_qpair_process_completions(struct nvme_qpair *qpair) 529 { 530 struct nvme_tracker *tr; 531 struct nvme_completion cpl; 532 int done = 0; 533 bool in_panic = dumping || SCHEDULER_STOPPED(); 534 535 qpair->num_intr_handler_calls++; 536 537 /* 538 * qpair is not enabled, likely because a controller reset is is in 539 * progress. Ignore the interrupt - any I/O that was associated with 540 * this interrupt will get retried when the reset is complete. 541 */ 542 if (!qpair->is_enabled) 543 return (false); 544 545 /* 546 * A panic can stop the CPU this routine is running on at any point. If 547 * we're called during a panic, complete the sq_head wrap protocol for 548 * the case where we are interrupted just after the increment at 1 549 * below, but before we can reset cq_head to zero at 2. Also cope with 550 * the case where we do the zero at 2, but may or may not have done the 551 * phase adjustment at step 3. The panic machinery flushes all pending 552 * memory writes, so we can make these strong ordering assumptions 553 * that would otherwise be unwise if we were racing in real time. 554 */ 555 if (__predict_false(in_panic)) { 556 if (qpair->cq_head == qpair->num_entries) { 557 /* 558 * Here we know that we need to zero cq_head and then negate 559 * the phase, which hasn't been assigned if cq_head isn't 560 * zero due to the atomic_store_rel. 561 */ 562 qpair->cq_head = 0; 563 qpair->phase = !qpair->phase; 564 } else if (qpair->cq_head == 0) { 565 /* 566 * In this case, we know that the assignment at 2 567 * happened below, but we don't know if it 3 happened or 568 * not. To do this, we look at the last completion 569 * entry and set the phase to the opposite phase 570 * that it has. This gets us back in sync 571 */ 572 cpl = qpair->cpl[qpair->num_entries - 1]; 573 nvme_completion_swapbytes(&cpl); 574 qpair->phase = !NVME_STATUS_GET_P(cpl.status); 575 } 576 } 577 578 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 579 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 580 while (1) { 581 cpl = qpair->cpl[qpair->cq_head]; 582 583 /* Convert to host endian */ 584 nvme_completion_swapbytes(&cpl); 585 586 if (NVME_STATUS_GET_P(cpl.status) != qpair->phase) 587 break; 588 589 tr = qpair->act_tr[cpl.cid]; 590 591 if (tr != NULL) { 592 nvme_qpair_complete_tracker(qpair, tr, &cpl, ERROR_PRINT_ALL); 593 qpair->sq_head = cpl.sqhd; 594 done++; 595 } else if (!in_panic) { 596 /* 597 * A missing tracker is normally an error. However, a 598 * panic can stop the CPU this routine is running on 599 * after completing an I/O but before updating 600 * qpair->cq_head at 1 below. Later, we re-enter this 601 * routine to poll I/O associated with the kernel 602 * dump. We find that the tr has been set to null before 603 * calling the completion routine. If it hasn't 604 * completed (or it triggers a panic), then '1' below 605 * won't have updated cq_head. Rather than panic again, 606 * ignore this condition because it's not unexpected. 607 */ 608 nvme_printf(qpair->ctrlr, 609 "cpl does not map to outstanding cmd\n"); 610 /* nvme_dump_completion expects device endianess */ 611 nvme_dump_completion(&qpair->cpl[qpair->cq_head]); 612 KASSERT(0, ("received completion for unknown cmd")); 613 } 614 615 /* 616 * There's a number of races with the following (see above) when 617 * the system panics. We compensate for each one of them by 618 * using the atomic store to force strong ordering (at least when 619 * viewed in the aftermath of a panic). 620 */ 621 if (++qpair->cq_head == qpair->num_entries) { /* 1 */ 622 atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */ 623 qpair->phase = !qpair->phase; /* 3 */ 624 } 625 626 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 627 qpair->cq_hdbl_off, qpair->cq_head); 628 } 629 return (done != 0); 630 } 631 632 static void 633 nvme_qpair_msix_handler(void *arg) 634 { 635 struct nvme_qpair *qpair = arg; 636 637 nvme_qpair_process_completions(qpair); 638 } 639 640 int 641 nvme_qpair_construct(struct nvme_qpair *qpair, 642 uint32_t num_entries, uint32_t num_trackers, 643 struct nvme_controller *ctrlr) 644 { 645 struct nvme_tracker *tr; 646 size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz; 647 uint64_t queuemem_phys, prpmem_phys, list_phys; 648 uint8_t *queuemem, *prpmem, *prp_list; 649 int i, err; 650 651 qpair->vector = ctrlr->msix_enabled ? qpair->id : 0; 652 qpair->num_entries = num_entries; 653 qpair->num_trackers = num_trackers; 654 qpair->ctrlr = ctrlr; 655 656 if (ctrlr->msix_enabled) { 657 658 /* 659 * MSI-X vector resource IDs start at 1, so we add one to 660 * the queue's vector to get the corresponding rid to use. 661 */ 662 qpair->rid = qpair->vector + 1; 663 664 qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 665 &qpair->rid, RF_ACTIVE); 666 bus_setup_intr(ctrlr->dev, qpair->res, 667 INTR_TYPE_MISC | INTR_MPSAFE, NULL, 668 nvme_qpair_msix_handler, qpair, &qpair->tag); 669 if (qpair->id == 0) { 670 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 671 "admin"); 672 } else { 673 bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 674 "io%d", qpair->id - 1); 675 } 676 } 677 678 mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF); 679 680 /* Note: NVMe PRP format is restricted to 4-byte alignment. */ 681 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 682 4, PAGE_SIZE, BUS_SPACE_MAXADDR, 683 BUS_SPACE_MAXADDR, NULL, NULL, NVME_MAX_XFER_SIZE, 684 (NVME_MAX_XFER_SIZE/PAGE_SIZE)+1, PAGE_SIZE, 0, 685 NULL, NULL, &qpair->dma_tag_payload); 686 if (err != 0) { 687 nvme_printf(ctrlr, "payload tag create failed %d\n", err); 688 goto out; 689 } 690 691 /* 692 * Each component must be page aligned, and individual PRP lists 693 * cannot cross a page boundary. 694 */ 695 cmdsz = qpair->num_entries * sizeof(struct nvme_command); 696 cmdsz = roundup2(cmdsz, PAGE_SIZE); 697 cplsz = qpair->num_entries * sizeof(struct nvme_completion); 698 cplsz = roundup2(cplsz, PAGE_SIZE); 699 prpsz = sizeof(uint64_t) * NVME_MAX_PRP_LIST_ENTRIES;; 700 prpmemsz = qpair->num_trackers * prpsz; 701 allocsz = cmdsz + cplsz + prpmemsz; 702 703 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 704 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 705 allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag); 706 if (err != 0) { 707 nvme_printf(ctrlr, "tag create failed %d\n", err); 708 goto out; 709 } 710 bus_dma_tag_set_domain(qpair->dma_tag, qpair->domain); 711 712 if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem, 713 BUS_DMA_NOWAIT, &qpair->queuemem_map)) { 714 nvme_printf(ctrlr, "failed to alloc qpair memory\n"); 715 goto out; 716 } 717 718 if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map, 719 queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) { 720 nvme_printf(ctrlr, "failed to load qpair memory\n"); 721 goto out; 722 } 723 724 qpair->num_cmds = 0; 725 qpair->num_intr_handler_calls = 0; 726 qpair->num_retries = 0; 727 qpair->num_failures = 0; 728 qpair->cmd = (struct nvme_command *)queuemem; 729 qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz); 730 prpmem = (uint8_t *)(queuemem + cmdsz + cplsz); 731 qpair->cmd_bus_addr = queuemem_phys; 732 qpair->cpl_bus_addr = queuemem_phys + cmdsz; 733 prpmem_phys = queuemem_phys + cmdsz + cplsz; 734 735 /* 736 * Calcuate the stride of the doorbell register. Many emulators set this 737 * value to correspond to a cache line. However, some hardware has set 738 * it to various small values. 739 */ 740 qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[0]) + 741 (qpair->id << (ctrlr->dstrd + 1)); 742 qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[0]) + 743 (qpair->id << (ctrlr->dstrd + 1)) + (1 << ctrlr->dstrd); 744 745 TAILQ_INIT(&qpair->free_tr); 746 TAILQ_INIT(&qpair->outstanding_tr); 747 STAILQ_INIT(&qpair->queued_req); 748 749 list_phys = prpmem_phys; 750 prp_list = prpmem; 751 for (i = 0; i < qpair->num_trackers; i++) { 752 753 if (list_phys + prpsz > prpmem_phys + prpmemsz) { 754 qpair->num_trackers = i; 755 break; 756 } 757 758 /* 759 * Make sure that the PRP list for this tracker doesn't 760 * overflow to another page. 761 */ 762 if (trunc_page(list_phys) != 763 trunc_page(list_phys + prpsz - 1)) { 764 list_phys = roundup2(list_phys, PAGE_SIZE); 765 prp_list = 766 (uint8_t *)roundup2((uintptr_t)prp_list, PAGE_SIZE); 767 } 768 769 tr = malloc_domainset(sizeof(*tr), M_NVME, 770 DOMAINSET_PREF(qpair->domain), M_ZERO | M_WAITOK); 771 bus_dmamap_create(qpair->dma_tag_payload, 0, 772 &tr->payload_dma_map); 773 callout_init(&tr->timer, 1); 774 tr->cid = i; 775 tr->qpair = qpair; 776 tr->prp = (uint64_t *)prp_list; 777 tr->prp_bus_addr = list_phys; 778 TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 779 list_phys += prpsz; 780 prp_list += prpsz; 781 } 782 783 if (qpair->num_trackers == 0) { 784 nvme_printf(ctrlr, "failed to allocate enough trackers\n"); 785 goto out; 786 } 787 788 qpair->act_tr = malloc_domainset(sizeof(struct nvme_tracker *) * 789 qpair->num_entries, M_NVME, DOMAINSET_PREF(qpair->domain), 790 M_ZERO | M_WAITOK); 791 return (0); 792 793 out: 794 nvme_qpair_destroy(qpair); 795 return (ENOMEM); 796 } 797 798 static void 799 nvme_qpair_destroy(struct nvme_qpair *qpair) 800 { 801 struct nvme_tracker *tr; 802 803 if (qpair->tag) 804 bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag); 805 806 if (mtx_initialized(&qpair->lock)) 807 mtx_destroy(&qpair->lock); 808 809 if (qpair->res) 810 bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ, 811 rman_get_rid(qpair->res), qpair->res); 812 813 if (qpair->cmd != NULL) { 814 bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map); 815 bus_dmamem_free(qpair->dma_tag, qpair->cmd, 816 qpair->queuemem_map); 817 } 818 819 if (qpair->act_tr) 820 free_domain(qpair->act_tr, M_NVME); 821 822 while (!TAILQ_EMPTY(&qpair->free_tr)) { 823 tr = TAILQ_FIRST(&qpair->free_tr); 824 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 825 bus_dmamap_destroy(qpair->dma_tag_payload, 826 tr->payload_dma_map); 827 free_domain(tr, M_NVME); 828 } 829 830 if (qpair->dma_tag) 831 bus_dma_tag_destroy(qpair->dma_tag); 832 833 if (qpair->dma_tag_payload) 834 bus_dma_tag_destroy(qpair->dma_tag_payload); 835 } 836 837 static void 838 nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair) 839 { 840 struct nvme_tracker *tr; 841 842 tr = TAILQ_FIRST(&qpair->outstanding_tr); 843 while (tr != NULL) { 844 if (tr->req->cmd.opc == NVME_OPC_ASYNC_EVENT_REQUEST) { 845 nvme_qpair_manual_complete_tracker(qpair, tr, 846 NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0, 847 ERROR_PRINT_NONE); 848 tr = TAILQ_FIRST(&qpair->outstanding_tr); 849 } else { 850 tr = TAILQ_NEXT(tr, tailq); 851 } 852 } 853 } 854 855 void 856 nvme_admin_qpair_destroy(struct nvme_qpair *qpair) 857 { 858 859 nvme_admin_qpair_abort_aers(qpair); 860 nvme_qpair_destroy(qpair); 861 } 862 863 void 864 nvme_io_qpair_destroy(struct nvme_qpair *qpair) 865 { 866 867 nvme_qpair_destroy(qpair); 868 } 869 870 static void 871 nvme_abort_complete(void *arg, const struct nvme_completion *status) 872 { 873 struct nvme_tracker *tr = arg; 874 875 /* 876 * If cdw0 == 1, the controller was not able to abort the command 877 * we requested. We still need to check the active tracker array, 878 * to cover race where I/O timed out at same time controller was 879 * completing the I/O. 880 */ 881 if (status->cdw0 == 1 && tr->qpair->act_tr[tr->cid] != NULL) { 882 /* 883 * An I/O has timed out, and the controller was unable to 884 * abort it for some reason. Construct a fake completion 885 * status, and then complete the I/O's tracker manually. 886 */ 887 nvme_printf(tr->qpair->ctrlr, 888 "abort command failed, aborting command manually\n"); 889 nvme_qpair_manual_complete_tracker(tr->qpair, tr, 890 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_ALL); 891 } 892 } 893 894 static void 895 nvme_timeout(void *arg) 896 { 897 struct nvme_tracker *tr = arg; 898 struct nvme_qpair *qpair = tr->qpair; 899 struct nvme_controller *ctrlr = qpair->ctrlr; 900 uint32_t csts; 901 uint8_t cfs; 902 903 /* 904 * Read csts to get value of cfs - controller fatal status. 905 * If no fatal status, try to call the completion routine, and 906 * if completes transactions, report a missed interrupt and 907 * return (this may need to be rate limited). Otherwise, if 908 * aborts are enabled and the controller is not reporting 909 * fatal status, abort the command. Otherwise, just reset the 910 * controller and hope for the best. 911 */ 912 csts = nvme_mmio_read_4(ctrlr, csts); 913 cfs = (csts >> NVME_CSTS_REG_CFS_SHIFT) & NVME_CSTS_REG_CFS_MASK; 914 if (cfs == 0 && nvme_qpair_process_completions(qpair)) { 915 nvme_printf(ctrlr, "Missing interrupt\n"); 916 return; 917 } 918 if (ctrlr->enable_aborts && cfs == 0) { 919 nvme_printf(ctrlr, "Aborting command due to a timeout.\n"); 920 nvme_ctrlr_cmd_abort(ctrlr, tr->cid, qpair->id, 921 nvme_abort_complete, tr); 922 } else { 923 nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n", 924 (csts == 0xffffffff) ? " and possible hot unplug" : 925 (cfs ? " and fatal error status" : "")); 926 nvme_ctrlr_reset(ctrlr); 927 } 928 } 929 930 void 931 nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr) 932 { 933 struct nvme_request *req; 934 struct nvme_controller *ctrlr; 935 936 mtx_assert(&qpair->lock, MA_OWNED); 937 938 req = tr->req; 939 req->cmd.cid = tr->cid; 940 qpair->act_tr[tr->cid] = tr; 941 ctrlr = qpair->ctrlr; 942 943 if (req->timeout) 944 callout_reset_on(&tr->timer, ctrlr->timeout_period * hz, 945 nvme_timeout, tr, qpair->cpu); 946 947 /* Copy the command from the tracker to the submission queue. */ 948 memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd)); 949 950 if (++qpair->sq_tail == qpair->num_entries) 951 qpair->sq_tail = 0; 952 953 bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 954 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 955 #ifndef __powerpc__ 956 /* 957 * powerpc's bus_dmamap_sync() already includes a heavyweight sync, but 958 * no other archs do. 959 */ 960 wmb(); 961 #endif 962 963 bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 964 qpair->sq_tdbl_off, qpair->sq_tail); 965 qpair->num_cmds++; 966 } 967 968 static void 969 nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 970 { 971 struct nvme_tracker *tr = arg; 972 uint32_t cur_nseg; 973 974 /* 975 * If the mapping operation failed, return immediately. The caller 976 * is responsible for detecting the error status and failing the 977 * tracker manually. 978 */ 979 if (error != 0) { 980 nvme_printf(tr->qpair->ctrlr, 981 "nvme_payload_map err %d\n", error); 982 return; 983 } 984 985 /* 986 * Note that we specified PAGE_SIZE for alignment and max 987 * segment size when creating the bus dma tags. So here 988 * we can safely just transfer each segment to its 989 * associated PRP entry. 990 */ 991 tr->req->cmd.prp1 = htole64(seg[0].ds_addr); 992 993 if (nseg == 2) { 994 tr->req->cmd.prp2 = htole64(seg[1].ds_addr); 995 } else if (nseg > 2) { 996 cur_nseg = 1; 997 tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr); 998 while (cur_nseg < nseg) { 999 tr->prp[cur_nseg-1] = 1000 htole64((uint64_t)seg[cur_nseg].ds_addr); 1001 cur_nseg++; 1002 } 1003 } else { 1004 /* 1005 * prp2 should not be used by the controller 1006 * since there is only one segment, but set 1007 * to 0 just to be safe. 1008 */ 1009 tr->req->cmd.prp2 = 0; 1010 } 1011 1012 bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map, 1013 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1014 nvme_qpair_submit_tracker(tr->qpair, tr); 1015 } 1016 1017 static void 1018 _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1019 { 1020 struct nvme_tracker *tr; 1021 int err = 0; 1022 1023 mtx_assert(&qpair->lock, MA_OWNED); 1024 1025 tr = TAILQ_FIRST(&qpair->free_tr); 1026 req->qpair = qpair; 1027 1028 if (tr == NULL || !qpair->is_enabled) { 1029 /* 1030 * No tracker is available, or the qpair is disabled due to 1031 * an in-progress controller-level reset or controller 1032 * failure. 1033 */ 1034 1035 if (qpair->ctrlr->is_failed) { 1036 /* 1037 * The controller has failed. Post the request to a 1038 * task where it will be aborted, so that we do not 1039 * invoke the request's callback in the context 1040 * of the submission. 1041 */ 1042 nvme_ctrlr_post_failed_request(qpair->ctrlr, req); 1043 } else { 1044 /* 1045 * Put the request on the qpair's request queue to be 1046 * processed when a tracker frees up via a command 1047 * completion or when the controller reset is 1048 * completed. 1049 */ 1050 STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq); 1051 } 1052 return; 1053 } 1054 1055 TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 1056 TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq); 1057 tr->req = req; 1058 1059 switch (req->type) { 1060 case NVME_REQUEST_VADDR: 1061 KASSERT(req->payload_size <= qpair->ctrlr->max_xfer_size, 1062 ("payload_size (%d) exceeds max_xfer_size (%d)\n", 1063 req->payload_size, qpair->ctrlr->max_xfer_size)); 1064 err = bus_dmamap_load(tr->qpair->dma_tag_payload, 1065 tr->payload_dma_map, req->u.payload, req->payload_size, 1066 nvme_payload_map, tr, 0); 1067 if (err != 0) 1068 nvme_printf(qpair->ctrlr, 1069 "bus_dmamap_load returned 0x%x!\n", err); 1070 break; 1071 case NVME_REQUEST_NULL: 1072 nvme_qpair_submit_tracker(tr->qpair, tr); 1073 break; 1074 case NVME_REQUEST_BIO: 1075 KASSERT(req->u.bio->bio_bcount <= qpair->ctrlr->max_xfer_size, 1076 ("bio->bio_bcount (%jd) exceeds max_xfer_size (%d)\n", 1077 (intmax_t)req->u.bio->bio_bcount, 1078 qpair->ctrlr->max_xfer_size)); 1079 err = bus_dmamap_load_bio(tr->qpair->dma_tag_payload, 1080 tr->payload_dma_map, req->u.bio, nvme_payload_map, tr, 0); 1081 if (err != 0) 1082 nvme_printf(qpair->ctrlr, 1083 "bus_dmamap_load_bio returned 0x%x!\n", err); 1084 break; 1085 case NVME_REQUEST_CCB: 1086 err = bus_dmamap_load_ccb(tr->qpair->dma_tag_payload, 1087 tr->payload_dma_map, req->u.payload, 1088 nvme_payload_map, tr, 0); 1089 if (err != 0) 1090 nvme_printf(qpair->ctrlr, 1091 "bus_dmamap_load_ccb returned 0x%x!\n", err); 1092 break; 1093 default: 1094 panic("unknown nvme request type 0x%x\n", req->type); 1095 break; 1096 } 1097 1098 if (err != 0) { 1099 /* 1100 * The dmamap operation failed, so we manually fail the 1101 * tracker here with DATA_TRANSFER_ERROR status. 1102 * 1103 * nvme_qpair_manual_complete_tracker must not be called 1104 * with the qpair lock held. 1105 */ 1106 mtx_unlock(&qpair->lock); 1107 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1108 NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL); 1109 mtx_lock(&qpair->lock); 1110 } 1111 } 1112 1113 void 1114 nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1115 { 1116 1117 mtx_lock(&qpair->lock); 1118 _nvme_qpair_submit_request(qpair, req); 1119 mtx_unlock(&qpair->lock); 1120 } 1121 1122 static void 1123 nvme_qpair_enable(struct nvme_qpair *qpair) 1124 { 1125 1126 qpair->is_enabled = TRUE; 1127 } 1128 1129 void 1130 nvme_qpair_reset(struct nvme_qpair *qpair) 1131 { 1132 1133 qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0; 1134 1135 /* 1136 * First time through the completion queue, HW will set phase 1137 * bit on completions to 1. So set this to 1 here, indicating 1138 * we're looking for a 1 to know which entries have completed. 1139 * we'll toggle the bit each time when the completion queue 1140 * rolls over. 1141 */ 1142 qpair->phase = 1; 1143 1144 memset(qpair->cmd, 0, 1145 qpair->num_entries * sizeof(struct nvme_command)); 1146 memset(qpair->cpl, 0, 1147 qpair->num_entries * sizeof(struct nvme_completion)); 1148 } 1149 1150 void 1151 nvme_admin_qpair_enable(struct nvme_qpair *qpair) 1152 { 1153 struct nvme_tracker *tr; 1154 struct nvme_tracker *tr_temp; 1155 1156 /* 1157 * Manually abort each outstanding admin command. Do not retry 1158 * admin commands found here, since they will be left over from 1159 * a controller reset and its likely the context in which the 1160 * command was issued no longer applies. 1161 */ 1162 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1163 nvme_printf(qpair->ctrlr, 1164 "aborting outstanding admin command\n"); 1165 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1166 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1167 } 1168 1169 nvme_qpair_enable(qpair); 1170 } 1171 1172 void 1173 nvme_io_qpair_enable(struct nvme_qpair *qpair) 1174 { 1175 STAILQ_HEAD(, nvme_request) temp; 1176 struct nvme_tracker *tr; 1177 struct nvme_tracker *tr_temp; 1178 struct nvme_request *req; 1179 1180 /* 1181 * Manually abort each outstanding I/O. This normally results in a 1182 * retry, unless the retry count on the associated request has 1183 * reached its limit. 1184 */ 1185 TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1186 nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n"); 1187 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1188 NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY); 1189 } 1190 1191 mtx_lock(&qpair->lock); 1192 1193 nvme_qpair_enable(qpair); 1194 1195 STAILQ_INIT(&temp); 1196 STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request); 1197 1198 while (!STAILQ_EMPTY(&temp)) { 1199 req = STAILQ_FIRST(&temp); 1200 STAILQ_REMOVE_HEAD(&temp, stailq); 1201 nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n"); 1202 nvme_qpair_print_command(qpair, &req->cmd); 1203 _nvme_qpair_submit_request(qpair, req); 1204 } 1205 1206 mtx_unlock(&qpair->lock); 1207 } 1208 1209 static void 1210 nvme_qpair_disable(struct nvme_qpair *qpair) 1211 { 1212 struct nvme_tracker *tr; 1213 1214 qpair->is_enabled = FALSE; 1215 mtx_lock(&qpair->lock); 1216 TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) 1217 callout_stop(&tr->timer); 1218 mtx_unlock(&qpair->lock); 1219 } 1220 1221 void 1222 nvme_admin_qpair_disable(struct nvme_qpair *qpair) 1223 { 1224 1225 nvme_qpair_disable(qpair); 1226 nvme_admin_qpair_abort_aers(qpair); 1227 } 1228 1229 void 1230 nvme_io_qpair_disable(struct nvme_qpair *qpair) 1231 { 1232 1233 nvme_qpair_disable(qpair); 1234 } 1235 1236 void 1237 nvme_qpair_fail(struct nvme_qpair *qpair) 1238 { 1239 struct nvme_tracker *tr; 1240 struct nvme_request *req; 1241 1242 if (!mtx_initialized(&qpair->lock)) 1243 return; 1244 1245 mtx_lock(&qpair->lock); 1246 1247 while (!STAILQ_EMPTY(&qpair->queued_req)) { 1248 req = STAILQ_FIRST(&qpair->queued_req); 1249 STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 1250 nvme_printf(qpair->ctrlr, "failing queued i/o\n"); 1251 mtx_unlock(&qpair->lock); 1252 nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC, 1253 NVME_SC_ABORTED_BY_REQUEST); 1254 mtx_lock(&qpair->lock); 1255 } 1256 1257 /* Manually abort each outstanding I/O. */ 1258 while (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1259 tr = TAILQ_FIRST(&qpair->outstanding_tr); 1260 /* 1261 * Do not remove the tracker. The abort_tracker path will 1262 * do that for us. 1263 */ 1264 nvme_printf(qpair->ctrlr, "failing outstanding i/o\n"); 1265 mtx_unlock(&qpair->lock); 1266 nvme_qpair_manual_complete_tracker(qpair, tr, NVME_SCT_GENERIC, 1267 NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1268 mtx_lock(&qpair->lock); 1269 } 1270 1271 mtx_unlock(&qpair->lock); 1272 } 1273 1274