1bb0ec6b3SJim Harris /*- 24d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 3718cf2ccSPedro F. Giffuni * 4f42ca756SJim Harris * Copyright (C) 2012-2014 Intel Corporation 5bb0ec6b3SJim Harris * All rights reserved. 6bb0ec6b3SJim Harris * 7bb0ec6b3SJim Harris * Redistribution and use in source and binary forms, with or without 8bb0ec6b3SJim Harris * modification, are permitted provided that the following conditions 9bb0ec6b3SJim Harris * are met: 10bb0ec6b3SJim Harris * 1. Redistributions of source code must retain the above copyright 11bb0ec6b3SJim Harris * notice, this list of conditions and the following disclaimer. 12bb0ec6b3SJim Harris * 2. Redistributions in binary form must reproduce the above copyright 13bb0ec6b3SJim Harris * notice, this list of conditions and the following disclaimer in the 14bb0ec6b3SJim Harris * documentation and/or other materials provided with the distribution. 15bb0ec6b3SJim Harris * 16bb0ec6b3SJim Harris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17bb0ec6b3SJim Harris * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18bb0ec6b3SJim Harris * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19bb0ec6b3SJim Harris * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20bb0ec6b3SJim Harris * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21bb0ec6b3SJim Harris * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22bb0ec6b3SJim Harris * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23bb0ec6b3SJim Harris * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24bb0ec6b3SJim Harris * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25bb0ec6b3SJim Harris * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26bb0ec6b3SJim Harris * SUCH DAMAGE. 27bb0ec6b3SJim Harris */ 28bb0ec6b3SJim Harris 29bb0ec6b3SJim Harris #include <sys/param.h> 30bb0ec6b3SJim Harris #include <sys/bus.h> 31d0aaeffdSWarner Losh #include <sys/conf.h> 321eab19cbSAlexander Motin #include <sys/domainset.h> 33d0aaeffdSWarner Losh #include <sys/proc.h> 34bb0ec6b3SJim Harris 350f71ecf7SJim Harris #include <dev/pci/pcivar.h> 360f71ecf7SJim Harris 37bb0ec6b3SJim Harris #include "nvme_private.h" 38bb0ec6b3SJim Harris 392ffd6fceSWarner Losh typedef enum error_print { ERROR_PRINT_NONE, ERROR_PRINT_NO_RETRY, ERROR_PRINT_ALL } error_print_t; 402ffd6fceSWarner Losh #define DO_NOT_RETRY 1 412ffd6fceSWarner Losh 42d6f54866SJim Harris static void _nvme_qpair_submit_request(struct nvme_qpair *qpair, 43d6f54866SJim Harris struct nvme_request *req); 44a965389bSScott Long static void nvme_qpair_destroy(struct nvme_qpair *qpair); 45d6f54866SJim Harris 462ad9a815SWarner Losh #define DEFAULT_INDEX 256 472ad9a815SWarner Losh #define DEFAULT_ENTRY(x) [DEFAULT_INDEX] = x 482ad9a815SWarner Losh #define OPC_ENTRY(x) [NVME_OPC_ ## x] = #x 492ad9a815SWarner Losh 502ad9a815SWarner Losh static const char *admin_opcode[DEFAULT_INDEX + 1] = { 512ad9a815SWarner Losh OPC_ENTRY(DELETE_IO_SQ), 522ad9a815SWarner Losh OPC_ENTRY(CREATE_IO_SQ), 532ad9a815SWarner Losh OPC_ENTRY(GET_LOG_PAGE), 542ad9a815SWarner Losh OPC_ENTRY(DELETE_IO_CQ), 552ad9a815SWarner Losh OPC_ENTRY(CREATE_IO_CQ), 562ad9a815SWarner Losh OPC_ENTRY(IDENTIFY), 572ad9a815SWarner Losh OPC_ENTRY(ABORT), 582ad9a815SWarner Losh OPC_ENTRY(SET_FEATURES), 592ad9a815SWarner Losh OPC_ENTRY(GET_FEATURES), 602ad9a815SWarner Losh OPC_ENTRY(ASYNC_EVENT_REQUEST), 612ad9a815SWarner Losh OPC_ENTRY(NAMESPACE_MANAGEMENT), 622ad9a815SWarner Losh OPC_ENTRY(FIRMWARE_ACTIVATE), 632ad9a815SWarner Losh OPC_ENTRY(FIRMWARE_IMAGE_DOWNLOAD), 642ad9a815SWarner Losh OPC_ENTRY(DEVICE_SELF_TEST), 652ad9a815SWarner Losh OPC_ENTRY(NAMESPACE_ATTACHMENT), 662ad9a815SWarner Losh OPC_ENTRY(KEEP_ALIVE), 672ad9a815SWarner Losh OPC_ENTRY(DIRECTIVE_SEND), 682ad9a815SWarner Losh OPC_ENTRY(DIRECTIVE_RECEIVE), 692ad9a815SWarner Losh OPC_ENTRY(VIRTUALIZATION_MANAGEMENT), 702ad9a815SWarner Losh OPC_ENTRY(NVME_MI_SEND), 712ad9a815SWarner Losh OPC_ENTRY(NVME_MI_RECEIVE), 722ad9a815SWarner Losh OPC_ENTRY(CAPACITY_MANAGEMENT), 732ad9a815SWarner Losh OPC_ENTRY(LOCKDOWN), 742ad9a815SWarner Losh OPC_ENTRY(DOORBELL_BUFFER_CONFIG), 752ad9a815SWarner Losh OPC_ENTRY(FABRICS_COMMANDS), 762ad9a815SWarner Losh OPC_ENTRY(FORMAT_NVM), 772ad9a815SWarner Losh OPC_ENTRY(SECURITY_SEND), 782ad9a815SWarner Losh OPC_ENTRY(SECURITY_RECEIVE), 792ad9a815SWarner Losh OPC_ENTRY(SANITIZE), 802ad9a815SWarner Losh OPC_ENTRY(GET_LBA_STATUS), 812ad9a815SWarner Losh DEFAULT_ENTRY("ADMIN COMMAND"), 82547d523eSJim Harris }; 83547d523eSJim Harris 842ad9a815SWarner Losh static const char *io_opcode[DEFAULT_INDEX + 1] = { 852ad9a815SWarner Losh OPC_ENTRY(FLUSH), 862ad9a815SWarner Losh OPC_ENTRY(WRITE), 872ad9a815SWarner Losh OPC_ENTRY(READ), 882ad9a815SWarner Losh OPC_ENTRY(WRITE_UNCORRECTABLE), 892ad9a815SWarner Losh OPC_ENTRY(COMPARE), 902ad9a815SWarner Losh OPC_ENTRY(WRITE_ZEROES), 912ad9a815SWarner Losh OPC_ENTRY(DATASET_MANAGEMENT), 922ad9a815SWarner Losh OPC_ENTRY(VERIFY), 932ad9a815SWarner Losh OPC_ENTRY(RESERVATION_REGISTER), 942ad9a815SWarner Losh OPC_ENTRY(RESERVATION_REPORT), 952ad9a815SWarner Losh OPC_ENTRY(RESERVATION_ACQUIRE), 962ad9a815SWarner Losh OPC_ENTRY(RESERVATION_RELEASE), 972ad9a815SWarner Losh OPC_ENTRY(COPY), 982ad9a815SWarner Losh DEFAULT_ENTRY("IO COMMAND"), 99547d523eSJim Harris }; 100547d523eSJim Harris 101547d523eSJim Harris static const char * 1022ad9a815SWarner Losh get_opcode_string(const char *op[DEFAULT_INDEX + 1], uint16_t opc) 103547d523eSJim Harris { 1042ad9a815SWarner Losh const char *nm = opc < DEFAULT_INDEX ? op[opc] : op[DEFAULT_INDEX]; 1052ad9a815SWarner Losh 1062ad9a815SWarner Losh return (nm != NULL ? nm : op[DEFAULT_INDEX]); 107547d523eSJim Harris } 108547d523eSJim Harris 109547d523eSJim Harris static const char * 110edd23e4dSWarner Losh get_admin_opcode_string(uint16_t opc) 111edd23e4dSWarner Losh { 112edd23e4dSWarner Losh return (get_opcode_string(admin_opcode, opc)); 113edd23e4dSWarner Losh } 114edd23e4dSWarner Losh 115edd23e4dSWarner Losh static const char * 116547d523eSJim Harris get_io_opcode_string(uint16_t opc) 117547d523eSJim Harris { 118edd23e4dSWarner Losh return (get_opcode_string(io_opcode, opc)); 119547d523eSJim Harris } 120547d523eSJim Harris 121547d523eSJim Harris static void 122547d523eSJim Harris nvme_admin_qpair_print_command(struct nvme_qpair *qpair, 123547d523eSJim Harris struct nvme_command *cmd) 124547d523eSJim Harris { 125547d523eSJim Harris 126547d523eSJim Harris nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%x " 127547d523eSJim Harris "cdw10:%08x cdw11:%08x\n", 1289544e6dcSChuck Tuffli get_admin_opcode_string(cmd->opc), cmd->opc, qpair->id, cmd->cid, 1290d787e9bSWojciech Macek le32toh(cmd->nsid), le32toh(cmd->cdw10), le32toh(cmd->cdw11)); 130547d523eSJim Harris } 131547d523eSJim Harris 132547d523eSJim Harris static void 133547d523eSJim Harris nvme_io_qpair_print_command(struct nvme_qpair *qpair, 134547d523eSJim Harris struct nvme_command *cmd) 135547d523eSJim Harris { 136547d523eSJim Harris 1379544e6dcSChuck Tuffli switch (cmd->opc) { 138547d523eSJim Harris case NVME_OPC_WRITE: 139547d523eSJim Harris case NVME_OPC_READ: 140547d523eSJim Harris case NVME_OPC_WRITE_UNCORRECTABLE: 141547d523eSJim Harris case NVME_OPC_COMPARE: 1426b1a96b1SAlexander Motin case NVME_OPC_WRITE_ZEROES: 14390dfa8f0SAlexander Motin case NVME_OPC_VERIFY: 144547d523eSJim Harris nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d " 145bdd1fd40SJim Harris "lba:%llu len:%d\n", 1469544e6dcSChuck Tuffli get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid), 1470d787e9bSWojciech Macek ((unsigned long long)le32toh(cmd->cdw11) << 32) + le32toh(cmd->cdw10), 1480d787e9bSWojciech Macek (le32toh(cmd->cdw12) & 0xFFFF) + 1); 149547d523eSJim Harris break; 150547d523eSJim Harris case NVME_OPC_FLUSH: 151547d523eSJim Harris case NVME_OPC_DATASET_MANAGEMENT: 1526b1a96b1SAlexander Motin case NVME_OPC_RESERVATION_REGISTER: 1536b1a96b1SAlexander Motin case NVME_OPC_RESERVATION_REPORT: 1546b1a96b1SAlexander Motin case NVME_OPC_RESERVATION_ACQUIRE: 1556b1a96b1SAlexander Motin case NVME_OPC_RESERVATION_RELEASE: 156547d523eSJim Harris nvme_printf(qpair->ctrlr, "%s sqid:%d cid:%d nsid:%d\n", 1579544e6dcSChuck Tuffli get_io_opcode_string(cmd->opc), qpair->id, cmd->cid, le32toh(cmd->nsid)); 158547d523eSJim Harris break; 159547d523eSJim Harris default: 160547d523eSJim Harris nvme_printf(qpair->ctrlr, "%s (%02x) sqid:%d cid:%d nsid:%d\n", 1619544e6dcSChuck Tuffli get_io_opcode_string(cmd->opc), cmd->opc, qpair->id, 1620d787e9bSWojciech Macek cmd->cid, le32toh(cmd->nsid)); 163547d523eSJim Harris break; 164547d523eSJim Harris } 165547d523eSJim Harris } 166547d523eSJim Harris 1677be0b068SWarner Losh void 168547d523eSJim Harris nvme_qpair_print_command(struct nvme_qpair *qpair, struct nvme_command *cmd) 169547d523eSJim Harris { 170547d523eSJim Harris if (qpair->id == 0) 171547d523eSJim Harris nvme_admin_qpair_print_command(qpair, cmd); 172547d523eSJim Harris else 173547d523eSJim Harris nvme_io_qpair_print_command(qpair, cmd); 174c75bdc04SWarner Losh if (nvme_verbose_cmd_dump) { 175c75bdc04SWarner Losh nvme_printf(qpair->ctrlr, 176c75bdc04SWarner Losh "nsid:%#x rsvd2:%#x rsvd3:%#x mptr:%#jx prp1:%#jx prp2:%#jx\n", 177c75bdc04SWarner Losh cmd->nsid, cmd->rsvd2, cmd->rsvd3, (uintmax_t)cmd->mptr, 178c75bdc04SWarner Losh (uintmax_t)cmd->prp1, (uintmax_t)cmd->prp2); 179c75bdc04SWarner Losh nvme_printf(qpair->ctrlr, 180c75bdc04SWarner Losh "cdw10: %#x cdw11:%#x cdw12:%#x cdw13:%#x cdw14:%#x cdw15:%#x\n", 181c75bdc04SWarner Losh cmd->cdw10, cmd->cdw11, cmd->cdw12, cmd->cdw13, cmd->cdw14, 182c75bdc04SWarner Losh cmd->cdw15); 183c75bdc04SWarner Losh } 184547d523eSJim Harris } 185547d523eSJim Harris 186547d523eSJim Harris struct nvme_status_string { 187547d523eSJim Harris uint16_t sc; 188547d523eSJim Harris const char * str; 189547d523eSJim Harris }; 190547d523eSJim Harris 191547d523eSJim Harris static struct nvme_status_string generic_status[] = { 192547d523eSJim Harris { NVME_SC_SUCCESS, "SUCCESS" }, 193547d523eSJim Harris { NVME_SC_INVALID_OPCODE, "INVALID OPCODE" }, 194547d523eSJim Harris { NVME_SC_INVALID_FIELD, "INVALID_FIELD" }, 195547d523eSJim Harris { NVME_SC_COMMAND_ID_CONFLICT, "COMMAND ID CONFLICT" }, 196547d523eSJim Harris { NVME_SC_DATA_TRANSFER_ERROR, "DATA TRANSFER ERROR" }, 197547d523eSJim Harris { NVME_SC_ABORTED_POWER_LOSS, "ABORTED - POWER LOSS" }, 198547d523eSJim Harris { NVME_SC_INTERNAL_DEVICE_ERROR, "INTERNAL DEVICE ERROR" }, 199547d523eSJim Harris { NVME_SC_ABORTED_BY_REQUEST, "ABORTED - BY REQUEST" }, 200547d523eSJim Harris { NVME_SC_ABORTED_SQ_DELETION, "ABORTED - SQ DELETION" }, 201547d523eSJim Harris { NVME_SC_ABORTED_FAILED_FUSED, "ABORTED - FAILED FUSED" }, 202547d523eSJim Harris { NVME_SC_ABORTED_MISSING_FUSED, "ABORTED - MISSING FUSED" }, 203547d523eSJim Harris { NVME_SC_INVALID_NAMESPACE_OR_FORMAT, "INVALID NAMESPACE OR FORMAT" }, 204547d523eSJim Harris { NVME_SC_COMMAND_SEQUENCE_ERROR, "COMMAND SEQUENCE ERROR" }, 2056b1a96b1SAlexander Motin { NVME_SC_INVALID_SGL_SEGMENT_DESCR, "INVALID SGL SEGMENT DESCRIPTOR" }, 2066b1a96b1SAlexander Motin { NVME_SC_INVALID_NUMBER_OF_SGL_DESCR, "INVALID NUMBER OF SGL DESCRIPTORS" }, 2076b1a96b1SAlexander Motin { NVME_SC_DATA_SGL_LENGTH_INVALID, "DATA SGL LENGTH INVALID" }, 2086b1a96b1SAlexander Motin { NVME_SC_METADATA_SGL_LENGTH_INVALID, "METADATA SGL LENGTH INVALID" }, 2096b1a96b1SAlexander Motin { NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID, "SGL DESCRIPTOR TYPE INVALID" }, 2106b1a96b1SAlexander Motin { NVME_SC_INVALID_USE_OF_CMB, "INVALID USE OF CONTROLLER MEMORY BUFFER" }, 2116b1a96b1SAlexander Motin { NVME_SC_PRP_OFFET_INVALID, "PRP OFFET INVALID" }, 2126b1a96b1SAlexander Motin { NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED, "ATOMIC WRITE UNIT EXCEEDED" }, 2136b1a96b1SAlexander Motin { NVME_SC_OPERATION_DENIED, "OPERATION DENIED" }, 2146b1a96b1SAlexander Motin { NVME_SC_SGL_OFFSET_INVALID, "SGL OFFSET INVALID" }, 2156b1a96b1SAlexander Motin { NVME_SC_HOST_ID_INCONSISTENT_FORMAT, "HOST IDENTIFIER INCONSISTENT FORMAT" }, 2166b1a96b1SAlexander Motin { NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED, "KEEP ALIVE TIMEOUT EXPIRED" }, 2176b1a96b1SAlexander Motin { NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID, "KEEP ALIVE TIMEOUT INVALID" }, 2186b1a96b1SAlexander Motin { NVME_SC_ABORTED_DUE_TO_PREEMPT, "COMMAND ABORTED DUE TO PREEMPT AND ABORT" }, 2196b1a96b1SAlexander Motin { NVME_SC_SANITIZE_FAILED, "SANITIZE FAILED" }, 2206b1a96b1SAlexander Motin { NVME_SC_SANITIZE_IN_PROGRESS, "SANITIZE IN PROGRESS" }, 2216b1a96b1SAlexander Motin { NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID, "SGL_DATA_BLOCK_GRANULARITY_INVALID" }, 2226b1a96b1SAlexander Motin { NVME_SC_NOT_SUPPORTED_IN_CMB, "COMMAND NOT SUPPORTED FOR QUEUE IN CMB" }, 22390dfa8f0SAlexander Motin { NVME_SC_NAMESPACE_IS_WRITE_PROTECTED, "NAMESPACE IS WRITE PROTECTED" }, 22490dfa8f0SAlexander Motin { NVME_SC_COMMAND_INTERRUPTED, "COMMAND INTERRUPTED" }, 22590dfa8f0SAlexander Motin { NVME_SC_TRANSIENT_TRANSPORT_ERROR, "TRANSIENT TRANSPORT ERROR" }, 2266b1a96b1SAlexander Motin 227547d523eSJim Harris { NVME_SC_LBA_OUT_OF_RANGE, "LBA OUT OF RANGE" }, 228547d523eSJim Harris { NVME_SC_CAPACITY_EXCEEDED, "CAPACITY EXCEEDED" }, 229547d523eSJim Harris { NVME_SC_NAMESPACE_NOT_READY, "NAMESPACE NOT READY" }, 2306b1a96b1SAlexander Motin { NVME_SC_RESERVATION_CONFLICT, "RESERVATION CONFLICT" }, 2316b1a96b1SAlexander Motin { NVME_SC_FORMAT_IN_PROGRESS, "FORMAT IN PROGRESS" }, 232547d523eSJim Harris { 0xFFFF, "GENERIC" } 233547d523eSJim Harris }; 234547d523eSJim Harris 235547d523eSJim Harris static struct nvme_status_string command_specific_status[] = { 236547d523eSJim Harris { NVME_SC_COMPLETION_QUEUE_INVALID, "INVALID COMPLETION QUEUE" }, 237547d523eSJim Harris { NVME_SC_INVALID_QUEUE_IDENTIFIER, "INVALID QUEUE IDENTIFIER" }, 238547d523eSJim Harris { NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED, "MAX QUEUE SIZE EXCEEDED" }, 239547d523eSJim Harris { NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED, "ABORT CMD LIMIT EXCEEDED" }, 240547d523eSJim Harris { NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED, "ASYNC LIMIT EXCEEDED" }, 241547d523eSJim Harris { NVME_SC_INVALID_FIRMWARE_SLOT, "INVALID FIRMWARE SLOT" }, 242547d523eSJim Harris { NVME_SC_INVALID_FIRMWARE_IMAGE, "INVALID FIRMWARE IMAGE" }, 243547d523eSJim Harris { NVME_SC_INVALID_INTERRUPT_VECTOR, "INVALID INTERRUPT VECTOR" }, 244547d523eSJim Harris { NVME_SC_INVALID_LOG_PAGE, "INVALID LOG PAGE" }, 245547d523eSJim Harris { NVME_SC_INVALID_FORMAT, "INVALID FORMAT" }, 246547d523eSJim Harris { NVME_SC_FIRMWARE_REQUIRES_RESET, "FIRMWARE REQUIRES RESET" }, 2476b1a96b1SAlexander Motin { NVME_SC_INVALID_QUEUE_DELETION, "INVALID QUEUE DELETION" }, 2486b1a96b1SAlexander Motin { NVME_SC_FEATURE_NOT_SAVEABLE, "FEATURE IDENTIFIER NOT SAVEABLE" }, 2496b1a96b1SAlexander Motin { NVME_SC_FEATURE_NOT_CHANGEABLE, "FEATURE NOT CHANGEABLE" }, 2506b1a96b1SAlexander Motin { NVME_SC_FEATURE_NOT_NS_SPECIFIC, "FEATURE NOT NAMESPACE SPECIFIC" }, 2516b1a96b1SAlexander Motin { NVME_SC_FW_ACT_REQUIRES_NVMS_RESET, "FIRMWARE ACTIVATION REQUIRES NVM SUBSYSTEM RESET" }, 2526b1a96b1SAlexander Motin { NVME_SC_FW_ACT_REQUIRES_RESET, "FIRMWARE ACTIVATION REQUIRES RESET" }, 2536b1a96b1SAlexander Motin { NVME_SC_FW_ACT_REQUIRES_TIME, "FIRMWARE ACTIVATION REQUIRES MAXIMUM TIME VIOLATION" }, 2546b1a96b1SAlexander Motin { NVME_SC_FW_ACT_PROHIBITED, "FIRMWARE ACTIVATION PROHIBITED" }, 2556b1a96b1SAlexander Motin { NVME_SC_OVERLAPPING_RANGE, "OVERLAPPING RANGE" }, 2566b1a96b1SAlexander Motin { NVME_SC_NS_INSUFFICIENT_CAPACITY, "NAMESPACE INSUFFICIENT CAPACITY" }, 2576b1a96b1SAlexander Motin { NVME_SC_NS_ID_UNAVAILABLE, "NAMESPACE IDENTIFIER UNAVAILABLE" }, 2586b1a96b1SAlexander Motin { NVME_SC_NS_ALREADY_ATTACHED, "NAMESPACE ALREADY ATTACHED" }, 2596b1a96b1SAlexander Motin { NVME_SC_NS_IS_PRIVATE, "NAMESPACE IS PRIVATE" }, 2606b1a96b1SAlexander Motin { NVME_SC_NS_NOT_ATTACHED, "NS NOT ATTACHED" }, 2616b1a96b1SAlexander Motin { NVME_SC_THIN_PROV_NOT_SUPPORTED, "THIN PROVISIONING NOT SUPPORTED" }, 2626b1a96b1SAlexander Motin { NVME_SC_CTRLR_LIST_INVALID, "CONTROLLER LIST INVALID" }, 2638d08cdc7SChuck Tuffli { NVME_SC_SELF_TEST_IN_PROGRESS, "DEVICE SELF-TEST IN PROGRESS" }, 2646b1a96b1SAlexander Motin { NVME_SC_BOOT_PART_WRITE_PROHIB, "BOOT PARTITION WRITE PROHIBITED" }, 2656b1a96b1SAlexander Motin { NVME_SC_INVALID_CTRLR_ID, "INVALID CONTROLLER IDENTIFIER" }, 2666b1a96b1SAlexander Motin { NVME_SC_INVALID_SEC_CTRLR_STATE, "INVALID SECONDARY CONTROLLER STATE" }, 2676b1a96b1SAlexander Motin { NVME_SC_INVALID_NUM_OF_CTRLR_RESRC, "INVALID NUMBER OF CONTROLLER RESOURCES" }, 2686b1a96b1SAlexander Motin { NVME_SC_INVALID_RESOURCE_ID, "INVALID RESOURCE IDENTIFIER" }, 26990dfa8f0SAlexander Motin { NVME_SC_SANITIZE_PROHIBITED_WPMRE, "SANITIZE PROHIBITED WRITE PERSISTENT MEMORY REGION ENABLED" }, 27090dfa8f0SAlexander Motin { NVME_SC_ANA_GROUP_ID_INVALID, "ANA GROUP IDENTIFIED INVALID" }, 27190dfa8f0SAlexander Motin { NVME_SC_ANA_ATTACH_FAILED, "ANA ATTACH FAILED" }, 2726b1a96b1SAlexander Motin 273547d523eSJim Harris { NVME_SC_CONFLICTING_ATTRIBUTES, "CONFLICTING ATTRIBUTES" }, 274547d523eSJim Harris { NVME_SC_INVALID_PROTECTION_INFO, "INVALID PROTECTION INFO" }, 275547d523eSJim Harris { NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE, "WRITE TO RO PAGE" }, 276547d523eSJim Harris { 0xFFFF, "COMMAND SPECIFIC" } 277547d523eSJim Harris }; 278547d523eSJim Harris 279547d523eSJim Harris static struct nvme_status_string media_error_status[] = { 280547d523eSJim Harris { NVME_SC_WRITE_FAULTS, "WRITE FAULTS" }, 281547d523eSJim Harris { NVME_SC_UNRECOVERED_READ_ERROR, "UNRECOVERED READ ERROR" }, 282547d523eSJim Harris { NVME_SC_GUARD_CHECK_ERROR, "GUARD CHECK ERROR" }, 283547d523eSJim Harris { NVME_SC_APPLICATION_TAG_CHECK_ERROR, "APPLICATION TAG CHECK ERROR" }, 284547d523eSJim Harris { NVME_SC_REFERENCE_TAG_CHECK_ERROR, "REFERENCE TAG CHECK ERROR" }, 285547d523eSJim Harris { NVME_SC_COMPARE_FAILURE, "COMPARE FAILURE" }, 286547d523eSJim Harris { NVME_SC_ACCESS_DENIED, "ACCESS DENIED" }, 2876b1a96b1SAlexander Motin { NVME_SC_DEALLOCATED_OR_UNWRITTEN, "DEALLOCATED OR UNWRITTEN LOGICAL BLOCK" }, 288547d523eSJim Harris { 0xFFFF, "MEDIA ERROR" } 289547d523eSJim Harris }; 290547d523eSJim Harris 291a6d222ebSAlexander Motin static struct nvme_status_string path_related_status[] = { 292a6d222ebSAlexander Motin { NVME_SC_INTERNAL_PATH_ERROR, "INTERNAL PATH ERROR" }, 293a6d222ebSAlexander Motin { NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS, "ASYMMETRIC ACCESS PERSISTENT LOSS" }, 294a6d222ebSAlexander Motin { NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE, "ASYMMETRIC ACCESS INACCESSIBLE" }, 295a6d222ebSAlexander Motin { NVME_SC_ASYMMETRIC_ACCESS_TRANSITION, "ASYMMETRIC ACCESS TRANSITION" }, 296a6d222ebSAlexander Motin { NVME_SC_CONTROLLER_PATHING_ERROR, "CONTROLLER PATHING ERROR" }, 297a6d222ebSAlexander Motin { NVME_SC_HOST_PATHING_ERROR, "HOST PATHING ERROR" }, 2985ae44634SJohn Baldwin { NVME_SC_COMMAND_ABORTED_BY_HOST, "COMMAND ABORTED BY HOST" }, 299a6d222ebSAlexander Motin { 0xFFFF, "PATH RELATED" }, 300a6d222ebSAlexander Motin }; 301a6d222ebSAlexander Motin 302547d523eSJim Harris static const char * 303547d523eSJim Harris get_status_string(uint16_t sct, uint16_t sc) 304547d523eSJim Harris { 305547d523eSJim Harris struct nvme_status_string *entry; 306547d523eSJim Harris 307547d523eSJim Harris switch (sct) { 308547d523eSJim Harris case NVME_SCT_GENERIC: 309547d523eSJim Harris entry = generic_status; 310547d523eSJim Harris break; 311547d523eSJim Harris case NVME_SCT_COMMAND_SPECIFIC: 312547d523eSJim Harris entry = command_specific_status; 313547d523eSJim Harris break; 314547d523eSJim Harris case NVME_SCT_MEDIA_ERROR: 315547d523eSJim Harris entry = media_error_status; 316547d523eSJim Harris break; 317a6d222ebSAlexander Motin case NVME_SCT_PATH_RELATED: 318a6d222ebSAlexander Motin entry = path_related_status; 319a6d222ebSAlexander Motin break; 320547d523eSJim Harris case NVME_SCT_VENDOR_SPECIFIC: 321547d523eSJim Harris return ("VENDOR SPECIFIC"); 322547d523eSJim Harris default: 323547d523eSJim Harris return ("RESERVED"); 324547d523eSJim Harris } 325547d523eSJim Harris 326547d523eSJim Harris while (entry->sc != 0xFFFF) { 327547d523eSJim Harris if (entry->sc == sc) 328547d523eSJim Harris return (entry->str); 329547d523eSJim Harris entry++; 330547d523eSJim Harris } 331547d523eSJim Harris return (entry->str); 332547d523eSJim Harris } 333547d523eSJim Harris 3346f76d493SWarner Losh void 335547d523eSJim Harris nvme_qpair_print_completion(struct nvme_qpair *qpair, 336547d523eSJim Harris struct nvme_completion *cpl) 337547d523eSJim Harris { 3386f76d493SWarner Losh uint8_t sct, sc, crd, m, dnr, p; 3390d787e9bSWojciech Macek 3400d787e9bSWojciech Macek sct = NVME_STATUS_GET_SCT(cpl->status); 3410d787e9bSWojciech Macek sc = NVME_STATUS_GET_SC(cpl->status); 342a69c0964SAlexander Motin crd = NVME_STATUS_GET_CRD(cpl->status); 343a69c0964SAlexander Motin m = NVME_STATUS_GET_M(cpl->status); 344a69c0964SAlexander Motin dnr = NVME_STATUS_GET_DNR(cpl->status); 3456f76d493SWarner Losh p = NVME_STATUS_GET_P(cpl->status); 3460d787e9bSWojciech Macek 3476f76d493SWarner Losh nvme_printf(qpair->ctrlr, "%s (%02x/%02x) crd:%x m:%x dnr:%x p:%d " 348a69c0964SAlexander Motin "sqid:%d cid:%d cdw0:%x\n", 3496f76d493SWarner Losh get_status_string(sct, sc), sct, sc, crd, m, dnr, p, 350a69c0964SAlexander Motin cpl->sqid, cpl->cid, cpl->cdw0); 351547d523eSJim Harris } 352547d523eSJim Harris 3537588c6ccSWarner Losh static bool 3546cb06070SJim Harris nvme_completion_is_retry(const struct nvme_completion *cpl) 355bb0ec6b3SJim Harris { 3560d787e9bSWojciech Macek uint8_t sct, sc, dnr; 3570d787e9bSWojciech Macek 3580d787e9bSWojciech Macek sct = NVME_STATUS_GET_SCT(cpl->status); 3590d787e9bSWojciech Macek sc = NVME_STATUS_GET_SC(cpl->status); 3602ffd6fceSWarner Losh dnr = NVME_STATUS_GET_DNR(cpl->status); /* Do Not Retry Bit */ 3610d787e9bSWojciech Macek 362bb0ec6b3SJim Harris /* 363bb0ec6b3SJim Harris * TODO: spec is not clear how commands that are aborted due 364bb0ec6b3SJim Harris * to TLER will be marked. So for now, it seems 365bb0ec6b3SJim Harris * NAMESPACE_NOT_READY is the only case where we should 36695108cadSWarner Losh * look at the DNR bit. Requests failed with ABORTED_BY_REQUEST 36795108cadSWarner Losh * set the DNR bit correctly since the driver controls that. 368bb0ec6b3SJim Harris */ 3690d787e9bSWojciech Macek switch (sct) { 370bb0ec6b3SJim Harris case NVME_SCT_GENERIC: 3710d787e9bSWojciech Macek switch (sc) { 372448195e7SJim Harris case NVME_SC_ABORTED_BY_REQUEST: 373bb0ec6b3SJim Harris case NVME_SC_NAMESPACE_NOT_READY: 3740d787e9bSWojciech Macek if (dnr) 375bb0ec6b3SJim Harris return (0); 376bb0ec6b3SJim Harris else 377bb0ec6b3SJim Harris return (1); 378bb0ec6b3SJim Harris case NVME_SC_INVALID_OPCODE: 379bb0ec6b3SJim Harris case NVME_SC_INVALID_FIELD: 380bb0ec6b3SJim Harris case NVME_SC_COMMAND_ID_CONFLICT: 381bb0ec6b3SJim Harris case NVME_SC_DATA_TRANSFER_ERROR: 382bb0ec6b3SJim Harris case NVME_SC_ABORTED_POWER_LOSS: 383bb0ec6b3SJim Harris case NVME_SC_INTERNAL_DEVICE_ERROR: 384bb0ec6b3SJim Harris case NVME_SC_ABORTED_SQ_DELETION: 385bb0ec6b3SJim Harris case NVME_SC_ABORTED_FAILED_FUSED: 386bb0ec6b3SJim Harris case NVME_SC_ABORTED_MISSING_FUSED: 387bb0ec6b3SJim Harris case NVME_SC_INVALID_NAMESPACE_OR_FORMAT: 388bb0ec6b3SJim Harris case NVME_SC_COMMAND_SEQUENCE_ERROR: 389bb0ec6b3SJim Harris case NVME_SC_LBA_OUT_OF_RANGE: 390bb0ec6b3SJim Harris case NVME_SC_CAPACITY_EXCEEDED: 391bb0ec6b3SJim Harris default: 392bb0ec6b3SJim Harris return (0); 393bb0ec6b3SJim Harris } 394bb0ec6b3SJim Harris case NVME_SCT_COMMAND_SPECIFIC: 395bb0ec6b3SJim Harris case NVME_SCT_MEDIA_ERROR: 396a6d222ebSAlexander Motin return (0); 397a6d222ebSAlexander Motin case NVME_SCT_PATH_RELATED: 398a6d222ebSAlexander Motin switch (sc) { 399a6d222ebSAlexander Motin case NVME_SC_INTERNAL_PATH_ERROR: 400a6d222ebSAlexander Motin if (dnr) 401a6d222ebSAlexander Motin return (0); 402a6d222ebSAlexander Motin else 403a6d222ebSAlexander Motin return (1); 404a6d222ebSAlexander Motin default: 405a6d222ebSAlexander Motin return (0); 406a6d222ebSAlexander Motin } 407bb0ec6b3SJim Harris case NVME_SCT_VENDOR_SPECIFIC: 408bb0ec6b3SJim Harris default: 409bb0ec6b3SJim Harris return (0); 410bb0ec6b3SJim Harris } 411bb0ec6b3SJim Harris } 412bb0ec6b3SJim Harris 41321b6da58SJim Harris static void 41443393e8bSWarner Losh nvme_qpair_complete_tracker(struct nvme_tracker *tr, 4152ffd6fceSWarner Losh struct nvme_completion *cpl, error_print_t print_on_error) 416bb0ec6b3SJim Harris { 41743393e8bSWarner Losh struct nvme_qpair *qpair = tr->qpair; 418ad697276SJim Harris struct nvme_request *req; 4197588c6ccSWarner Losh bool retry, error, retriable; 420bb0ec6b3SJim Harris 4215a178b83SWarner Losh mtx_assert(&qpair->lock, MA_NOTOWNED); 4225a178b83SWarner Losh 423ad697276SJim Harris req = tr->req; 4246cb06070SJim Harris error = nvme_completion_is_error(cpl); 4255e83c2ffSWarner Losh retriable = nvme_completion_is_retry(cpl); 4265e83c2ffSWarner Losh retry = error && retriable && req->retries < nvme_retry_count; 427c37fc318SWarner Losh if (retry) 428c37fc318SWarner Losh qpair->num_retries++; 4295e83c2ffSWarner Losh if (error && req->retries >= nvme_retry_count && retriable) 4305e83c2ffSWarner Losh qpair->num_failures++; 431ad697276SJim Harris 4322ffd6fceSWarner Losh if (error && (print_on_error == ERROR_PRINT_ALL || 4332ffd6fceSWarner Losh (!retry && print_on_error == ERROR_PRINT_NO_RETRY))) { 434547d523eSJim Harris nvme_qpair_print_command(qpair, &req->cmd); 435547d523eSJim Harris nvme_qpair_print_completion(qpair, cpl); 436bb0ec6b3SJim Harris } 437bb0ec6b3SJim Harris 438bb0ec6b3SJim Harris qpair->act_tr[cpl->cid] = NULL; 439bb0ec6b3SJim Harris 4406cb06070SJim Harris KASSERT(cpl->cid == req->cmd.cid, ("cpl cid does not match cmd cid\n")); 441bb0ec6b3SJim Harris 4420a4b14e8SMichal Meloun if (!retry) { 44392103adbSJohn Baldwin if (req->payload_valid) { 4440a4b14e8SMichal Meloun bus_dmamap_sync(qpair->dma_tag_payload, 4450a4b14e8SMichal Meloun tr->payload_dma_map, 4460a4b14e8SMichal Meloun BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4470a4b14e8SMichal Meloun } 4480a4b14e8SMichal Meloun if (req->cb_fn) 449ad697276SJim Harris req->cb_fn(req->cb_arg, cpl); 4500a4b14e8SMichal Meloun } 451bb0ec6b3SJim Harris 452bb0ec6b3SJim Harris mtx_lock(&qpair->lock); 453bb0ec6b3SJim Harris 454cb5b7c13SJim Harris if (retry) { 455cb5b7c13SJim Harris req->retries++; 456b846efd7SJim Harris nvme_qpair_submit_tracker(qpair, tr); 457cb5b7c13SJim Harris } else { 45892103adbSJohn Baldwin if (req->payload_valid) { 459a6e30963SJim Harris bus_dmamap_unload(qpair->dma_tag_payload, 460f2b19f67SJim Harris tr->payload_dma_map); 4612e0090afSJustin Hibbits } 462bb0ec6b3SJim Harris 463ad697276SJim Harris nvme_free_request(req); 4640a0b08ccSJim Harris tr->req = NULL; 46521b6da58SJim Harris 46665c2474eSJim Harris TAILQ_REMOVE(&qpair->outstanding_tr, tr, tailq); 46765c2474eSJim Harris TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 4680f71ecf7SJim Harris 469f37c22a3SJim Harris /* 470f37c22a3SJim Harris * If the controller is in the middle of resetting, don't 471f37c22a3SJim Harris * try to submit queued requests here - let the reset logic 472f37c22a3SJim Harris * handle that instead. 473f37c22a3SJim Harris */ 474f37c22a3SJim Harris if (!STAILQ_EMPTY(&qpair->queued_req) && 475f37c22a3SJim Harris !qpair->ctrlr->is_resetting) { 4760f71ecf7SJim Harris req = STAILQ_FIRST(&qpair->queued_req); 4770f71ecf7SJim Harris STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 478d6f54866SJim Harris _nvme_qpair_submit_request(qpair, req); 4790f71ecf7SJim Harris } 480c2e83b40SJim Harris } 481bb0ec6b3SJim Harris 482bb0ec6b3SJim Harris mtx_unlock(&qpair->lock); 4836cb06070SJim Harris } 4846cb06070SJim Harris 485123e2906SWarner Losh static uint32_t 486123e2906SWarner Losh nvme_qpair_make_status(uint32_t sct, uint32_t sc, uint32_t dnr) 487123e2906SWarner Losh { 488123e2906SWarner Losh uint32_t status = 0; 489123e2906SWarner Losh 490123e2906SWarner Losh status |= NVMEF(NVME_STATUS_SCT, sct); 491123e2906SWarner Losh status |= NVMEF(NVME_STATUS_SC, sc); 492123e2906SWarner Losh status |= NVMEF(NVME_STATUS_DNR, dnr); 493123e2906SWarner Losh /* M=0 : this is artificial so no data in error log page */ 494123e2906SWarner Losh /* CRD=0 : this is artificial and no delayed retry support anyway */ 495123e2906SWarner Losh /* P=0 : phase not checked */ 496123e2906SWarner Losh return (status); 497123e2906SWarner Losh } 498123e2906SWarner Losh 499b846efd7SJim Harris static void 50043393e8bSWarner Losh nvme_qpair_manual_complete_tracker( 501232e2edbSJim Harris struct nvme_tracker *tr, uint32_t sct, uint32_t sc, uint32_t dnr, 5022ffd6fceSWarner Losh error_print_t print_on_error) 503b846efd7SJim Harris { 504b846efd7SJim Harris struct nvme_completion cpl; 5055a178b83SWarner Losh struct nvme_qpair * qpair = tr->qpair; 5065a178b83SWarner Losh 5075a178b83SWarner Losh mtx_assert(&qpair->lock, MA_NOTOWNED); 508b846efd7SJim Harris 509b846efd7SJim Harris memset(&cpl, 0, sizeof(cpl)); 51043393e8bSWarner Losh 511b846efd7SJim Harris cpl.sqid = qpair->id; 512b846efd7SJim Harris cpl.cid = tr->cid; 513123e2906SWarner Losh cpl.status = nvme_qpair_make_status(sct, sc, dnr); 51443393e8bSWarner Losh nvme_qpair_complete_tracker(tr, &cpl, print_on_error); 515b846efd7SJim Harris } 516b846efd7SJim Harris 517123e2906SWarner Losh static void 518232e2edbSJim Harris nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 519123e2906SWarner Losh struct nvme_request *req, uint32_t sct, uint32_t sc, uint32_t dnr, 520123e2906SWarner Losh error_print_t print_on_error) 521232e2edbSJim Harris { 522232e2edbSJim Harris struct nvme_completion cpl; 5237588c6ccSWarner Losh bool error; 524232e2edbSJim Harris 525232e2edbSJim Harris memset(&cpl, 0, sizeof(cpl)); 526232e2edbSJim Harris cpl.sqid = qpair->id; 527123e2906SWarner Losh cpl.status = nvme_qpair_make_status(sct, sc, dnr); 528232e2edbSJim Harris error = nvme_completion_is_error(&cpl); 529232e2edbSJim Harris 530123e2906SWarner Losh if (error && print_on_error == ERROR_PRINT_ALL) { 531547d523eSJim Harris nvme_qpair_print_command(qpair, &req->cmd); 532547d523eSJim Harris nvme_qpair_print_completion(qpair, &cpl); 533232e2edbSJim Harris } 534232e2edbSJim Harris 535232e2edbSJim Harris if (req->cb_fn) 536232e2edbSJim Harris req->cb_fn(req->cb_arg, &cpl); 537232e2edbSJim Harris 538232e2edbSJim Harris nvme_free_request(req); 539232e2edbSJim Harris } 540232e2edbSJim Harris 5418052b01eSWarner Losh /* Locked version of completion processor */ 5428052b01eSWarner Losh static bool 5438052b01eSWarner Losh _nvme_qpair_process_completions(struct nvme_qpair *qpair) 5446cb06070SJim Harris { 5456cb06070SJim Harris struct nvme_tracker *tr; 5460d787e9bSWojciech Macek struct nvme_completion cpl; 5478052b01eSWarner Losh bool done = false; 548d0aaeffdSWarner Losh bool in_panic = dumping || SCHEDULER_STOPPED(); 5496cb06070SJim Harris 5508052b01eSWarner Losh mtx_assert(&qpair->recovery, MA_OWNED); 5518052b01eSWarner Losh 552b846efd7SJim Harris /* 553dfa01f4fSGordon Bergling * qpair is not enabled, likely because a controller reset is in 554d0aaeffdSWarner Losh * progress. Ignore the interrupt - any I/O that was associated with 5557d5eebe0SWarner Losh * this interrupt will get retried when the reset is complete. Any 5567d5eebe0SWarner Losh * pending completions for when we're in startup will be completed 5577d5eebe0SWarner Losh * as soon as initialization is complete and we start sending commands 5587d5eebe0SWarner Losh * to the device. 559b846efd7SJim Harris */ 560587aa255SWarner Losh if (qpair->recovery_state != RECOVERY_NONE) { 561587aa255SWarner Losh qpair->num_ignored++; 562d85d9648SWarner Losh return (false); 563587aa255SWarner Losh } 564b846efd7SJim Harris 5657d5eebe0SWarner Losh /* 5667d5eebe0SWarner Losh * Sanity check initialization. After we reset the hardware, the phase 5677d5eebe0SWarner Losh * is defined to be 1. So if we get here with zero prior calls and the 5687d5eebe0SWarner Losh * phase is 0, it means that we've lost a race between the 5697d5eebe0SWarner Losh * initialization and the ISR running. With the phase wrong, we'll 5707d5eebe0SWarner Losh * process a bunch of completions that aren't really completions leading 5717d5eebe0SWarner Losh * to a KASSERT below. 5727d5eebe0SWarner Losh */ 5737d5eebe0SWarner Losh KASSERT(!(qpair->num_intr_handler_calls == 0 && qpair->phase == 0), 5747d5eebe0SWarner Losh ("%s: Phase wrong for first interrupt call.", 5757d5eebe0SWarner Losh device_get_nameunit(qpair->ctrlr->dev))); 5767d5eebe0SWarner Losh 5777d5eebe0SWarner Losh qpair->num_intr_handler_calls++; 5787d5eebe0SWarner Losh 5798f9d5a8dSMichal Meloun bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 5808f9d5a8dSMichal Meloun BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 581d0aaeffdSWarner Losh /* 582d0aaeffdSWarner Losh * A panic can stop the CPU this routine is running on at any point. If 583d0aaeffdSWarner Losh * we're called during a panic, complete the sq_head wrap protocol for 584d0aaeffdSWarner Losh * the case where we are interrupted just after the increment at 1 585d0aaeffdSWarner Losh * below, but before we can reset cq_head to zero at 2. Also cope with 586d0aaeffdSWarner Losh * the case where we do the zero at 2, but may or may not have done the 587d0aaeffdSWarner Losh * phase adjustment at step 3. The panic machinery flushes all pending 588d0aaeffdSWarner Losh * memory writes, so we can make these strong ordering assumptions 589d0aaeffdSWarner Losh * that would otherwise be unwise if we were racing in real time. 590d0aaeffdSWarner Losh */ 591d0aaeffdSWarner Losh if (__predict_false(in_panic)) { 592d0aaeffdSWarner Losh if (qpair->cq_head == qpair->num_entries) { 593d0aaeffdSWarner Losh /* 594d0aaeffdSWarner Losh * Here we know that we need to zero cq_head and then negate 595d0aaeffdSWarner Losh * the phase, which hasn't been assigned if cq_head isn't 596d0aaeffdSWarner Losh * zero due to the atomic_store_rel. 597d0aaeffdSWarner Losh */ 598d0aaeffdSWarner Losh qpair->cq_head = 0; 599d0aaeffdSWarner Losh qpair->phase = !qpair->phase; 600d0aaeffdSWarner Losh } else if (qpair->cq_head == 0) { 601d0aaeffdSWarner Losh /* 602d0aaeffdSWarner Losh * In this case, we know that the assignment at 2 603d0aaeffdSWarner Losh * happened below, but we don't know if it 3 happened or 604d0aaeffdSWarner Losh * not. To do this, we look at the last completion 605d0aaeffdSWarner Losh * entry and set the phase to the opposite phase 606d0aaeffdSWarner Losh * that it has. This gets us back in sync 607d0aaeffdSWarner Losh */ 608d0aaeffdSWarner Losh cpl = qpair->cpl[qpair->num_entries - 1]; 609d0aaeffdSWarner Losh nvme_completion_swapbytes(&cpl); 610d0aaeffdSWarner Losh qpair->phase = !NVME_STATUS_GET_P(cpl.status); 611d0aaeffdSWarner Losh } 612d0aaeffdSWarner Losh } 613d0aaeffdSWarner Losh 6146cb06070SJim Harris while (1) { 615aa0ab681SWarner Losh uint16_t status; 6166cb06070SJim Harris 617aa0ab681SWarner Losh /* 618aa0ab681SWarner Losh * We need to do this dance to avoid a race between the host and 619aa0ab681SWarner Losh * the device where the device overtakes the host while the host 620aa0ab681SWarner Losh * is reading this record, leaving the status field 'new' and 621aa0ab681SWarner Losh * the sqhd and cid fields potentially stale. If the phase 622aa0ab681SWarner Losh * doesn't match, that means status hasn't yet been updated and 623aa0ab681SWarner Losh * we'll get any pending changes next time. It also means that 624aa0ab681SWarner Losh * the phase must be the same the second time. We have to sync 625aa0ab681SWarner Losh * before reading to ensure any bouncing completes. 626aa0ab681SWarner Losh */ 627aa0ab681SWarner Losh status = le16toh(qpair->cpl[qpair->cq_head].status); 628aa0ab681SWarner Losh if (NVME_STATUS_GET_P(status) != qpair->phase) 629aa0ab681SWarner Losh break; 630aa0ab681SWarner Losh 631aa0ab681SWarner Losh bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 632aa0ab681SWarner Losh BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 633aa0ab681SWarner Losh cpl = qpair->cpl[qpair->cq_head]; 6340d787e9bSWojciech Macek nvme_completion_swapbytes(&cpl); 6350d787e9bSWojciech Macek 636aa0ab681SWarner Losh KASSERT( 637aa0ab681SWarner Losh NVME_STATUS_GET_P(status) == NVME_STATUS_GET_P(cpl.status), 638aa0ab681SWarner Losh ("Phase unexpectedly inconsistent")); 6396cb06070SJim Harris 64036a87d0cSWarner Losh if (cpl.cid < qpair->num_trackers) 6410d787e9bSWojciech Macek tr = qpair->act_tr[cpl.cid]; 64236a87d0cSWarner Losh else 64336a87d0cSWarner Losh tr = NULL; 6446cb06070SJim Harris 6458052b01eSWarner Losh done = true; 6466cb06070SJim Harris if (tr != NULL) { 64743393e8bSWarner Losh nvme_qpair_complete_tracker(tr, &cpl, ERROR_PRINT_ALL); 6480d787e9bSWojciech Macek qpair->sq_head = cpl.sqhd; 649d0aaeffdSWarner Losh } else if (!in_panic) { 650d0aaeffdSWarner Losh /* 651d0aaeffdSWarner Losh * A missing tracker is normally an error. However, a 652d0aaeffdSWarner Losh * panic can stop the CPU this routine is running on 653d0aaeffdSWarner Losh * after completing an I/O but before updating 654d0aaeffdSWarner Losh * qpair->cq_head at 1 below. Later, we re-enter this 655d0aaeffdSWarner Losh * routine to poll I/O associated with the kernel 656d0aaeffdSWarner Losh * dump. We find that the tr has been set to null before 657d0aaeffdSWarner Losh * calling the completion routine. If it hasn't 658d0aaeffdSWarner Losh * completed (or it triggers a panic), then '1' below 659d0aaeffdSWarner Losh * won't have updated cq_head. Rather than panic again, 660d0aaeffdSWarner Losh * ignore this condition because it's not unexpected. 661d0aaeffdSWarner Losh */ 662547d523eSJim Harris nvme_printf(qpair->ctrlr, 66336a87d0cSWarner Losh "cpl (cid = %u) does not map to outstanding cmd\n", 66436a87d0cSWarner Losh cpl.cid); 6656f76d493SWarner Losh nvme_qpair_print_completion(qpair, 6666f76d493SWarner Losh &qpair->cpl[qpair->cq_head]); 667d0aaeffdSWarner Losh KASSERT(0, ("received completion for unknown cmd")); 6686cb06070SJim Harris } 669bb0ec6b3SJim Harris 670d0aaeffdSWarner Losh /* 671d0aaeffdSWarner Losh * There's a number of races with the following (see above) when 672d0aaeffdSWarner Losh * the system panics. We compensate for each one of them by 673d0aaeffdSWarner Losh * using the atomic store to force strong ordering (at least when 674d0aaeffdSWarner Losh * viewed in the aftermath of a panic). 675d0aaeffdSWarner Losh */ 676d0aaeffdSWarner Losh if (++qpair->cq_head == qpair->num_entries) { /* 1 */ 677d0aaeffdSWarner Losh atomic_store_rel_int(&qpair->cq_head, 0); /* 2 */ 678d0aaeffdSWarner Losh qpair->phase = !qpair->phase; /* 3 */ 679bb0ec6b3SJim Harris } 6802ec165e3SWarner Losh } 681bb0ec6b3SJim Harris 6828052b01eSWarner Losh if (done) { 683f93b7f95SWarner Losh bus_space_write_4(qpair->ctrlr->bus_tag, qpair->ctrlr->bus_handle, 684f93b7f95SWarner Losh qpair->cq_hdbl_off, qpair->cq_head); 685bb0ec6b3SJim Harris } 6862ec165e3SWarner Losh 6878052b01eSWarner Losh return (done); 6888052b01eSWarner Losh } 6898052b01eSWarner Losh 6908052b01eSWarner Losh bool 6918052b01eSWarner Losh nvme_qpair_process_completions(struct nvme_qpair *qpair) 6928052b01eSWarner Losh { 69386909f7aSWarner Losh bool done = false; 6948052b01eSWarner Losh 6958052b01eSWarner Losh /* 6968052b01eSWarner Losh * Interlock with reset / recovery code. This is an usually uncontended 6978052b01eSWarner Losh * to make sure that we drain out of the ISRs before we reset the card 6988052b01eSWarner Losh * and to prevent races with the recovery process called from a timeout 6998052b01eSWarner Losh * context. 7008052b01eSWarner Losh */ 70186909f7aSWarner Losh mtx_lock(&qpair->recovery); 7028052b01eSWarner Losh 70386909f7aSWarner Losh if (__predict_true(qpair->recovery_state == RECOVERY_NONE)) 7048052b01eSWarner Losh done = _nvme_qpair_process_completions(qpair); 70586909f7aSWarner Losh else 70686909f7aSWarner Losh qpair->num_recovery_nolock++; // XXX likely need to rename 7078052b01eSWarner Losh 7088052b01eSWarner Losh mtx_unlock(&qpair->recovery); 7098052b01eSWarner Losh 7108052b01eSWarner Losh return (done); 711bb0ec6b3SJim Harris } 712bb0ec6b3SJim Harris 713bb0ec6b3SJim Harris static void 714e3bdf3daSAlexander Motin nvme_qpair_msi_handler(void *arg) 715bb0ec6b3SJim Harris { 716bb0ec6b3SJim Harris struct nvme_qpair *qpair = arg; 717bb0ec6b3SJim Harris 718bb0ec6b3SJim Harris nvme_qpair_process_completions(qpair); 719bb0ec6b3SJim Harris } 720bb0ec6b3SJim Harris 721a965389bSScott Long int 7221eab19cbSAlexander Motin nvme_qpair_construct(struct nvme_qpair *qpair, 7231eab19cbSAlexander Motin uint32_t num_entries, uint32_t num_trackers, 7248d09e3c4SJim Harris struct nvme_controller *ctrlr) 725bb0ec6b3SJim Harris { 72621b6da58SJim Harris struct nvme_tracker *tr; 727a965389bSScott Long size_t cmdsz, cplsz, prpsz, allocsz, prpmemsz; 728a965389bSScott Long uint64_t queuemem_phys, prpmem_phys, list_phys; 729a965389bSScott Long uint8_t *queuemem, *prpmem, *prp_list; 730a965389bSScott Long int i, err; 731bb0ec6b3SJim Harris 732e3bdf3daSAlexander Motin qpair->vector = ctrlr->msi_count > 1 ? qpair->id : 0; 733bb0ec6b3SJim Harris qpair->num_entries = num_entries; 7340f71ecf7SJim Harris qpair->num_trackers = num_trackers; 735bb0ec6b3SJim Harris qpair->ctrlr = ctrlr; 736bb0ec6b3SJim Harris 737bb0ec6b3SJim Harris mtx_init(&qpair->lock, "nvme qpair lock", NULL, MTX_DEF); 7388052b01eSWarner Losh mtx_init(&qpair->recovery, "nvme qpair recovery", NULL, MTX_DEF); 739bb0ec6b3SJim Harris 740afc3d49bSWarner Losh callout_init_mtx(&qpair->timer, &qpair->recovery, 0); 741afc3d49bSWarner Losh qpair->timer_armed = false; 742afc3d49bSWarner Losh qpair->recovery_state = RECOVERY_WAITING; 743afc3d49bSWarner Losh 7441416ef36SJim Harris /* Note: NVMe PRP format is restricted to 4-byte alignment. */ 745a6e30963SJim Harris err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 7460fd4cd40SWarner Losh 4, ctrlr->page_size, BUS_SPACE_MAXADDR, 747ac90f70dSAlexander Motin BUS_SPACE_MAXADDR, NULL, NULL, ctrlr->max_xfer_size, 7480fd4cd40SWarner Losh howmany(ctrlr->max_xfer_size, ctrlr->page_size) + 1, 7490fd4cd40SWarner Losh ctrlr->page_size, 0, 750a6e30963SJim Harris NULL, NULL, &qpair->dma_tag_payload); 751a965389bSScott Long if (err != 0) { 752a6e30963SJim Harris nvme_printf(ctrlr, "payload tag create failed %d\n", err); 753a965389bSScott Long goto out; 754a965389bSScott Long } 755a965389bSScott Long 756a965389bSScott Long /* 757a965389bSScott Long * Each component must be page aligned, and individual PRP lists 758a965389bSScott Long * cannot cross a page boundary. 759a965389bSScott Long */ 760a965389bSScott Long cmdsz = qpair->num_entries * sizeof(struct nvme_command); 7610fd4cd40SWarner Losh cmdsz = roundup2(cmdsz, ctrlr->page_size); 762a965389bSScott Long cplsz = qpair->num_entries * sizeof(struct nvme_completion); 7630fd4cd40SWarner Losh cplsz = roundup2(cplsz, ctrlr->page_size); 764ac90f70dSAlexander Motin /* 765ac90f70dSAlexander Motin * For commands requiring more than 2 PRP entries, one PRP will be 766ac90f70dSAlexander Motin * embedded in the command (prp1), and the rest of the PRP entries 767ac90f70dSAlexander Motin * will be in a list pointed to by the command (prp2). 768ac90f70dSAlexander Motin */ 7690fd4cd40SWarner Losh prpsz = sizeof(uint64_t) * 7700fd4cd40SWarner Losh howmany(ctrlr->max_xfer_size, ctrlr->page_size); 771a965389bSScott Long prpmemsz = qpair->num_trackers * prpsz; 772a965389bSScott Long allocsz = cmdsz + cplsz + prpmemsz; 773a6e30963SJim Harris 774a6e30963SJim Harris err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 7750fd4cd40SWarner Losh ctrlr->page_size, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 776a965389bSScott Long allocsz, 1, allocsz, 0, NULL, NULL, &qpair->dma_tag); 777a965389bSScott Long if (err != 0) { 778a6e30963SJim Harris nvme_printf(ctrlr, "tag create failed %d\n", err); 779a965389bSScott Long goto out; 780a965389bSScott Long } 7811eab19cbSAlexander Motin bus_dma_tag_set_domain(qpair->dma_tag, qpair->domain); 782a965389bSScott Long 783a965389bSScott Long if (bus_dmamem_alloc(qpair->dma_tag, (void **)&queuemem, 7848f9d5a8dSMichal Meloun BUS_DMA_COHERENT | BUS_DMA_NOWAIT, &qpair->queuemem_map)) { 785a965389bSScott Long nvme_printf(ctrlr, "failed to alloc qpair memory\n"); 786a965389bSScott Long goto out; 787a965389bSScott Long } 788a965389bSScott Long 789a965389bSScott Long if (bus_dmamap_load(qpair->dma_tag, qpair->queuemem_map, 790a965389bSScott Long queuemem, allocsz, nvme_single_map, &queuemem_phys, 0) != 0) { 791a965389bSScott Long nvme_printf(ctrlr, "failed to load qpair memory\n"); 792550d5d64SAlexander Motin bus_dmamem_free(qpair->dma_tag, qpair->cmd, 793550d5d64SAlexander Motin qpair->queuemem_map); 794a965389bSScott Long goto out; 795a965389bSScott Long } 796bb0ec6b3SJim Harris 797bb0ec6b3SJim Harris qpair->num_cmds = 0; 7986568ebfcSJim Harris qpair->num_intr_handler_calls = 0; 799c37fc318SWarner Losh qpair->num_retries = 0; 8005e83c2ffSWarner Losh qpair->num_failures = 0; 801587aa255SWarner Losh qpair->num_ignored = 0; 802a965389bSScott Long qpair->cmd = (struct nvme_command *)queuemem; 803a965389bSScott Long qpair->cpl = (struct nvme_completion *)(queuemem + cmdsz); 804a965389bSScott Long prpmem = (uint8_t *)(queuemem + cmdsz + cplsz); 805a965389bSScott Long qpair->cmd_bus_addr = queuemem_phys; 806a965389bSScott Long qpair->cpl_bus_addr = queuemem_phys + cmdsz; 807a965389bSScott Long prpmem_phys = queuemem_phys + cmdsz + cplsz; 808bb0ec6b3SJim Harris 809f93b7f95SWarner Losh /* 810f93b7f95SWarner Losh * Calcuate the stride of the doorbell register. Many emulators set this 811f93b7f95SWarner Losh * value to correspond to a cache line. However, some hardware has set 812f93b7f95SWarner Losh * it to various small values. 813f93b7f95SWarner Losh */ 814f93b7f95SWarner Losh qpair->sq_tdbl_off = nvme_mmio_offsetof(doorbell[0]) + 8151eab19cbSAlexander Motin (qpair->id << (ctrlr->dstrd + 1)); 816f93b7f95SWarner Losh qpair->cq_hdbl_off = nvme_mmio_offsetof(doorbell[0]) + 8171eab19cbSAlexander Motin (qpair->id << (ctrlr->dstrd + 1)) + (1 << ctrlr->dstrd); 818bb0ec6b3SJim Harris 81965c2474eSJim Harris TAILQ_INIT(&qpair->free_tr); 82065c2474eSJim Harris TAILQ_INIT(&qpair->outstanding_tr); 8210f71ecf7SJim Harris STAILQ_INIT(&qpair->queued_req); 822bb0ec6b3SJim Harris 823a965389bSScott Long list_phys = prpmem_phys; 824a965389bSScott Long prp_list = prpmem; 8250f71ecf7SJim Harris for (i = 0; i < qpair->num_trackers; i++) { 826a965389bSScott Long if (list_phys + prpsz > prpmem_phys + prpmemsz) { 827a965389bSScott Long qpair->num_trackers = i; 828a965389bSScott Long break; 82921b6da58SJim Harris } 83021b6da58SJim Harris 831a965389bSScott Long /* 832a965389bSScott Long * Make sure that the PRP list for this tracker doesn't 8330fd4cd40SWarner Losh * overflow to another nvme page. 834a965389bSScott Long */ 835a965389bSScott Long if (trunc_page(list_phys) != 836a965389bSScott Long trunc_page(list_phys + prpsz - 1)) { 8370fd4cd40SWarner Losh list_phys = roundup2(list_phys, ctrlr->page_size); 838a965389bSScott Long prp_list = 8390fd4cd40SWarner Losh (uint8_t *)roundup2((uintptr_t)prp_list, ctrlr->page_size); 840a965389bSScott Long } 841a965389bSScott Long 8421eab19cbSAlexander Motin tr = malloc_domainset(sizeof(*tr), M_NVME, 8431eab19cbSAlexander Motin DOMAINSET_PREF(qpair->domain), M_ZERO | M_WAITOK); 844a965389bSScott Long bus_dmamap_create(qpair->dma_tag_payload, 0, 845a965389bSScott Long &tr->payload_dma_map); 846a965389bSScott Long tr->cid = i; 847a965389bSScott Long tr->qpair = qpair; 848a965389bSScott Long tr->prp = (uint64_t *)prp_list; 849a965389bSScott Long tr->prp_bus_addr = list_phys; 850a965389bSScott Long TAILQ_INSERT_HEAD(&qpair->free_tr, tr, tailq); 851a965389bSScott Long list_phys += prpsz; 852a965389bSScott Long prp_list += prpsz; 853a965389bSScott Long } 854a965389bSScott Long 855a965389bSScott Long if (qpair->num_trackers == 0) { 856a965389bSScott Long nvme_printf(ctrlr, "failed to allocate enough trackers\n"); 857a965389bSScott Long goto out; 858a965389bSScott Long } 859a965389bSScott Long 8601eab19cbSAlexander Motin qpair->act_tr = malloc_domainset(sizeof(struct nvme_tracker *) * 8611eab19cbSAlexander Motin qpair->num_entries, M_NVME, DOMAINSET_PREF(qpair->domain), 8621eab19cbSAlexander Motin M_ZERO | M_WAITOK); 863fc9a0840SWarner Losh 864e3bdf3daSAlexander Motin if (ctrlr->msi_count > 1) { 865fc9a0840SWarner Losh /* 866fc9a0840SWarner Losh * MSI-X vector resource IDs start at 1, so we add one to 867fc9a0840SWarner Losh * the queue's vector to get the corresponding rid to use. 868fc9a0840SWarner Losh */ 869fc9a0840SWarner Losh qpair->rid = qpair->vector + 1; 870fc9a0840SWarner Losh 871fc9a0840SWarner Losh qpair->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 872fc9a0840SWarner Losh &qpair->rid, RF_ACTIVE); 873e3bdf3daSAlexander Motin if (qpair->res == NULL) { 874e3bdf3daSAlexander Motin nvme_printf(ctrlr, "unable to allocate MSI\n"); 875e3bdf3daSAlexander Motin goto out; 876e3bdf3daSAlexander Motin } 877fc9a0840SWarner Losh if (bus_setup_intr(ctrlr->dev, qpair->res, 878fc9a0840SWarner Losh INTR_TYPE_MISC | INTR_MPSAFE, NULL, 879e3bdf3daSAlexander Motin nvme_qpair_msi_handler, qpair, &qpair->tag) != 0) { 880e3bdf3daSAlexander Motin nvme_printf(ctrlr, "unable to setup MSI\n"); 881fc9a0840SWarner Losh goto out; 882fc9a0840SWarner Losh } 883fc9a0840SWarner Losh if (qpair->id == 0) { 884fc9a0840SWarner Losh bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 885fc9a0840SWarner Losh "admin"); 886fc9a0840SWarner Losh } else { 887fc9a0840SWarner Losh bus_describe_intr(ctrlr->dev, qpair->res, qpair->tag, 888fc9a0840SWarner Losh "io%d", qpair->id - 1); 889fc9a0840SWarner Losh } 890fc9a0840SWarner Losh } 891fc9a0840SWarner Losh 892a965389bSScott Long return (0); 893a965389bSScott Long 894a965389bSScott Long out: 895a965389bSScott Long nvme_qpair_destroy(qpair); 896a965389bSScott Long return (ENOMEM); 897bb0ec6b3SJim Harris } 898bb0ec6b3SJim Harris 899bb0ec6b3SJim Harris static void 900bb0ec6b3SJim Harris nvme_qpair_destroy(struct nvme_qpair *qpair) 901bb0ec6b3SJim Harris { 902bb0ec6b3SJim Harris struct nvme_tracker *tr; 903bb0ec6b3SJim Harris 904afc3d49bSWarner Losh mtx_lock(&qpair->recovery); 905afc3d49bSWarner Losh qpair->timer_armed = false; 906afc3d49bSWarner Losh mtx_unlock(&qpair->recovery); 907502dc84aSWarner Losh callout_drain(&qpair->timer); 908502dc84aSWarner Losh 909550d5d64SAlexander Motin if (qpair->tag) { 910bb0ec6b3SJim Harris bus_teardown_intr(qpair->ctrlr->dev, qpair->res, qpair->tag); 911550d5d64SAlexander Motin qpair->tag = NULL; 9123d7eb41cSJim Harris } 9133d7eb41cSJim Harris 914550d5d64SAlexander Motin if (qpair->act_tr) { 91596ad26eeSMark Johnston free(qpair->act_tr, M_NVME); 916550d5d64SAlexander Motin qpair->act_tr = NULL; 917550d5d64SAlexander Motin } 918bb0ec6b3SJim Harris 91965c2474eSJim Harris while (!TAILQ_EMPTY(&qpair->free_tr)) { 92065c2474eSJim Harris tr = TAILQ_FIRST(&qpair->free_tr); 92165c2474eSJim Harris TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 922c6c70c07SAlexander Motin bus_dmamap_destroy(qpair->dma_tag_payload, 923c6c70c07SAlexander Motin tr->payload_dma_map); 92496ad26eeSMark Johnston free(tr, M_NVME); 925bb0ec6b3SJim Harris } 926c6c70c07SAlexander Motin 927550d5d64SAlexander Motin if (qpair->cmd != NULL) { 928550d5d64SAlexander Motin bus_dmamap_unload(qpair->dma_tag, qpair->queuemem_map); 929550d5d64SAlexander Motin bus_dmamem_free(qpair->dma_tag, qpair->cmd, 930550d5d64SAlexander Motin qpair->queuemem_map); 931550d5d64SAlexander Motin qpair->cmd = NULL; 932550d5d64SAlexander Motin } 933c6c70c07SAlexander Motin 934550d5d64SAlexander Motin if (qpair->dma_tag) { 935550d5d64SAlexander Motin bus_dma_tag_destroy(qpair->dma_tag); 936550d5d64SAlexander Motin qpair->dma_tag = NULL; 937550d5d64SAlexander Motin } 938550d5d64SAlexander Motin 939550d5d64SAlexander Motin if (qpair->dma_tag_payload) { 940c6c70c07SAlexander Motin bus_dma_tag_destroy(qpair->dma_tag_payload); 941550d5d64SAlexander Motin qpair->dma_tag_payload = NULL; 942550d5d64SAlexander Motin } 943550d5d64SAlexander Motin 944550d5d64SAlexander Motin if (mtx_initialized(&qpair->lock)) 945550d5d64SAlexander Motin mtx_destroy(&qpair->lock); 9468052b01eSWarner Losh if (mtx_initialized(&qpair->recovery)) 9478052b01eSWarner Losh mtx_destroy(&qpair->recovery); 948550d5d64SAlexander Motin 949550d5d64SAlexander Motin if (qpair->res) { 950550d5d64SAlexander Motin bus_release_resource(qpair->ctrlr->dev, SYS_RES_IRQ, 951550d5d64SAlexander Motin rman_get_rid(qpair->res), qpair->res); 952550d5d64SAlexander Motin qpair->res = NULL; 953550d5d64SAlexander Motin } 954bb0ec6b3SJim Harris } 955bb0ec6b3SJim Harris 956b846efd7SJim Harris static void 957b846efd7SJim Harris nvme_admin_qpair_abort_aers(struct nvme_qpair *qpair) 958b846efd7SJim Harris { 959b846efd7SJim Harris struct nvme_tracker *tr; 960b846efd7SJim Harris 961da8324a9SWarner Losh /* 962da8324a9SWarner Losh * nvme_complete_tracker must be called without the qpair lock held. It 963da8324a9SWarner Losh * takes the lock to adjust outstanding_tr list, so make sure we don't 9649db8ca92SWarner Losh * have it yet. We need the lock to make the list traverse safe, but 9659db8ca92SWarner Losh * have to drop the lock to complete any AER. We restart the list scan 9669db8ca92SWarner Losh * when we do this to make this safe. There's interlock with the ISR so 9679db8ca92SWarner Losh * we know this tracker won't be completed twice. 968da8324a9SWarner Losh */ 969da8324a9SWarner Losh mtx_assert(&qpair->lock, MA_NOTOWNED); 970da8324a9SWarner Losh 971da8324a9SWarner Losh mtx_lock(&qpair->lock); 972b846efd7SJim Harris tr = TAILQ_FIRST(&qpair->outstanding_tr); 973b846efd7SJim Harris while (tr != NULL) { 9749db8ca92SWarner Losh if (tr->req->cmd.opc != NVME_OPC_ASYNC_EVENT_REQUEST) { 9759db8ca92SWarner Losh tr = TAILQ_NEXT(tr, tailq); 9769db8ca92SWarner Losh continue; 9779db8ca92SWarner Losh } 978da8324a9SWarner Losh mtx_unlock(&qpair->lock); 97943393e8bSWarner Losh nvme_qpair_manual_complete_tracker(tr, 980232e2edbSJim Harris NVME_SCT_GENERIC, NVME_SC_ABORTED_SQ_DELETION, 0, 9812ffd6fceSWarner Losh ERROR_PRINT_NONE); 982da8324a9SWarner Losh mtx_lock(&qpair->lock); 983b846efd7SJim Harris tr = TAILQ_FIRST(&qpair->outstanding_tr); 984b846efd7SJim Harris } 985da8324a9SWarner Losh mtx_unlock(&qpair->lock); 986b846efd7SJim Harris } 987b846efd7SJim Harris 988bb0ec6b3SJim Harris void 989bb0ec6b3SJim Harris nvme_admin_qpair_destroy(struct nvme_qpair *qpair) 990bb0ec6b3SJim Harris { 991da8324a9SWarner Losh mtx_assert(&qpair->lock, MA_NOTOWNED); 992bb0ec6b3SJim Harris 993b846efd7SJim Harris nvme_admin_qpair_abort_aers(qpair); 994bb0ec6b3SJim Harris nvme_qpair_destroy(qpair); 995bb0ec6b3SJim Harris } 996bb0ec6b3SJim Harris 997bb0ec6b3SJim Harris void 998bb0ec6b3SJim Harris nvme_io_qpair_destroy(struct nvme_qpair *qpair) 999bb0ec6b3SJim Harris { 1000bb0ec6b3SJim Harris 1001bb0ec6b3SJim Harris nvme_qpair_destroy(qpair); 1002bb0ec6b3SJim Harris } 1003bb0ec6b3SJim Harris 1004bb0ec6b3SJim Harris static void 10052a6b7055SWarner Losh nvme_abort_complete(void *arg, const struct nvme_completion *status) 10062a6b7055SWarner Losh { 10072a6b7055SWarner Losh struct nvme_tracker *tr = arg; 10082a6b7055SWarner Losh 10092a6b7055SWarner Losh /* 1010e6d3ba4bSWarner Losh * If cdw0 bit 0 == 1, the controller was not able to abort the command 1011e6d3ba4bSWarner Losh * we requested. We still need to check the active tracker array, to 1012e6d3ba4bSWarner Losh * cover race where I/O timed out at same time controller was completing 1013e6d3ba4bSWarner Losh * the I/O. An abort command always is on the admin queue, but affects 1014e6d3ba4bSWarner Losh * either an admin or an I/O queue, so take the appropriate qpair lock 1015e6d3ba4bSWarner Losh * for the original command's queue, since we'll need it to avoid races 1016e6d3ba4bSWarner Losh * with the completion code and to complete the command manually. 10172a6b7055SWarner Losh */ 1018e6d3ba4bSWarner Losh mtx_lock(&tr->qpair->lock); 1019e6d3ba4bSWarner Losh if ((status->cdw0 & 1) == 1 && tr->qpair->act_tr[tr->cid] != NULL) { 10202a6b7055SWarner Losh /* 1021e6d3ba4bSWarner Losh * An I/O has timed out, and the controller was unable to abort 1022e6d3ba4bSWarner Losh * it for some reason. And we've not processed a completion for 1023e6d3ba4bSWarner Losh * it yet. Construct a fake completion status, and then complete 1024e6d3ba4bSWarner Losh * the I/O's tracker manually. 10252a6b7055SWarner Losh */ 10262a6b7055SWarner Losh nvme_printf(tr->qpair->ctrlr, 10272a6b7055SWarner Losh "abort command failed, aborting command manually\n"); 10282a6b7055SWarner Losh nvme_qpair_manual_complete_tracker(tr, 10292a6b7055SWarner Losh NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_ALL); 10302a6b7055SWarner Losh } 1031e6d3ba4bSWarner Losh /* 1032e6d3ba4bSWarner Losh * XXX We don't check status for the possible 'Could not abort because 1033e6d3ba4bSWarner Losh * excess aborts were submitted to the controller'. We don't prevent 1034e6d3ba4bSWarner Losh * that, either. Document for the future here, since the standard is 1035e6d3ba4bSWarner Losh * squishy and only says 'may generate' but implies anything is possible 1036e6d3ba4bSWarner Losh * including hangs if you exceed the ACL. 1037e6d3ba4bSWarner Losh */ 1038e6d3ba4bSWarner Losh mtx_unlock(&tr->qpair->lock); 10392a6b7055SWarner Losh } 10402a6b7055SWarner Losh 10412a6b7055SWarner Losh static void 1042502dc84aSWarner Losh nvme_qpair_timeout(void *arg) 10430a0b08ccSJim Harris { 1044502dc84aSWarner Losh struct nvme_qpair *qpair = arg; 104512d191ecSJim Harris struct nvme_controller *ctrlr = qpair->ctrlr; 1046502dc84aSWarner Losh struct nvme_tracker *tr; 1047502dc84aSWarner Losh sbintime_t now; 1048*aa413543SWarner Losh bool idle = true; 1049*aa413543SWarner Losh bool fast; 10500d787e9bSWojciech Macek uint32_t csts; 10510d787e9bSWojciech Macek uint8_t cfs; 1052448195e7SJim Harris 10538052b01eSWarner Losh mtx_assert(&qpair->recovery, MA_OWNED); 10542a6b7055SWarner Losh 10559cd7b624SWarner Losh /* 10569cd7b624SWarner Losh * If the controller is failed, then stop polling. This ensures that any 10579cd7b624SWarner Losh * failure processing that races with the qpair timeout will fail 10589cd7b624SWarner Losh * safely. 10599cd7b624SWarner Losh */ 10609cd7b624SWarner Losh if (qpair->ctrlr->is_failed) { 10619cd7b624SWarner Losh nvme_printf(qpair->ctrlr, 10629cd7b624SWarner Losh "Failed controller, stopping watchdog timeout.\n"); 10639cd7b624SWarner Losh qpair->timer_armed = false; 10649cd7b624SWarner Losh return; 10659cd7b624SWarner Losh } 10669cd7b624SWarner Losh 1067afc3d49bSWarner Losh /* 1068afc3d49bSWarner Losh * Shutdown condition: We set qpair->timer_armed to false in 1069afc3d49bSWarner Losh * nvme_qpair_destroy before calling callout_drain. When we call that, 1070afc3d49bSWarner Losh * this routine might get called one last time. Exit w/o setting a 1071afc3d49bSWarner Losh * timeout. None of the watchdog stuff needs to be done since we're 1072afc3d49bSWarner Losh * destroying the qpair. 1073afc3d49bSWarner Losh */ 1074afc3d49bSWarner Losh if (!qpair->timer_armed) { 1075afc3d49bSWarner Losh nvme_printf(qpair->ctrlr, 1076afc3d49bSWarner Losh "Timeout fired during nvme_qpair_destroy\n"); 1077afc3d49bSWarner Losh return; 1078afc3d49bSWarner Losh } 1079afc3d49bSWarner Losh 1080502dc84aSWarner Losh switch (qpair->recovery_state) { 1081502dc84aSWarner Losh case RECOVERY_NONE: 10822a6b7055SWarner Losh /* 1083d4959bfcSWarner Losh * Read csts to get value of cfs - controller fatal status. If 1084d4959bfcSWarner Losh * we are in the hot-plug or controller failed status proceed 1085d4959bfcSWarner Losh * directly to reset. We also bail early if the status reads all 1086d4959bfcSWarner Losh * 1's or the control fatal status bit is now 1. The latter is 1087d4959bfcSWarner Losh * always true when the former is true, but not vice versa. The 1088d4959bfcSWarner Losh * intent of the code is that if the card is gone (all 1's) or 1089d4959bfcSWarner Losh * we've failed, then try to do a reset (which someitmes 1090d4959bfcSWarner Losh * unwedges a card reading all 1's that's not gone away, but 1091d4959bfcSWarner Losh * usually doesn't). 1092d4959bfcSWarner Losh */ 1093d4959bfcSWarner Losh csts = nvme_mmio_read_4(ctrlr, csts); 1094479680f2SJohn Baldwin cfs = NVMEV(NVME_CSTS_REG_CFS, csts); 1095*aa413543SWarner Losh if (csts == NVME_GONE || cfs == 1) { 1096d4959bfcSWarner Losh /* 1097*aa413543SWarner Losh * We've had a command timeout that we weren't able to 1098*aa413543SWarner Losh * abort or we have aborts disabled and any command 1099*aa413543SWarner Losh * timed out. 1100d4959bfcSWarner Losh * 1101*aa413543SWarner Losh * If we get here due to a possible surprise hot-unplug 1102*aa413543SWarner Losh * event, then we let nvme_ctrlr_reset confirm and fail 1103*aa413543SWarner Losh * the controller. 1104502dc84aSWarner Losh */ 1105d4959bfcSWarner Losh do_reset: 1106502dc84aSWarner Losh nvme_printf(ctrlr, "Resetting controller due to a timeout%s.\n", 110718dc12bfSWarner Losh (csts == 0xffffffff) ? " and possible hot unplug" : 110818dc12bfSWarner Losh (cfs ? " and fatal error status" : "")); 1109502dc84aSWarner Losh qpair->recovery_state = RECOVERY_WAITING; 1110502dc84aSWarner Losh nvme_ctrlr_reset(ctrlr); 1111*aa413543SWarner Losh idle = false; 1112502dc84aSWarner Losh break; 1113*aa413543SWarner Losh } 1114*aa413543SWarner Losh 1115*aa413543SWarner Losh 1116*aa413543SWarner Losh /* 1117*aa413543SWarner Losh * See if there's any recovery needed. First, do a fast check to 1118*aa413543SWarner Losh * see if anything could have timed out. If not, then skip 1119*aa413543SWarner Losh * everything else. 1120*aa413543SWarner Losh */ 1121*aa413543SWarner Losh fast = false; 1122*aa413543SWarner Losh mtx_lock(&qpair->lock); 1123*aa413543SWarner Losh now = getsbinuptime(); 1124*aa413543SWarner Losh TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) { 1125*aa413543SWarner Losh /* 1126*aa413543SWarner Losh * Skip async commands, they are posted to the card for 1127*aa413543SWarner Losh * an indefinite amount of time and have no deadline. 1128*aa413543SWarner Losh */ 1129*aa413543SWarner Losh if (tr->deadline == SBT_MAX) 1130*aa413543SWarner Losh continue; 1131*aa413543SWarner Losh 1132*aa413543SWarner Losh /* 1133*aa413543SWarner Losh * If the first real transaction is not in timeout, then 1134*aa413543SWarner Losh * we're done. Otherwise, we try recovery. 1135*aa413543SWarner Losh */ 1136*aa413543SWarner Losh idle = false; 1137*aa413543SWarner Losh if (now <= tr->deadline) 1138*aa413543SWarner Losh fast = true; 1139*aa413543SWarner Losh break; 1140*aa413543SWarner Losh } 1141*aa413543SWarner Losh mtx_unlock(&qpair->lock); 1142*aa413543SWarner Losh if (idle || fast) 1143*aa413543SWarner Losh break; 1144*aa413543SWarner Losh 1145*aa413543SWarner Losh /* 1146*aa413543SWarner Losh * There's a stale transaction at the start of the queue whose 1147*aa413543SWarner Losh * deadline has passed. Poll the competions as a last-ditch 1148*aa413543SWarner Losh * effort in case an interrupt has been missed. 1149*aa413543SWarner Losh */ 1150*aa413543SWarner Losh _nvme_qpair_process_completions(qpair); 1151*aa413543SWarner Losh 1152*aa413543SWarner Losh /* 1153*aa413543SWarner Losh * Now that we've run the ISR, re-rheck to see if there's any 1154*aa413543SWarner Losh * timed out commands and abort them or reset the card if so. 1155*aa413543SWarner Losh */ 1156*aa413543SWarner Losh mtx_lock(&qpair->lock); 1157*aa413543SWarner Losh idle = true; 1158*aa413543SWarner Losh TAILQ_FOREACH(tr, &qpair->outstanding_tr, tailq) { 1159*aa413543SWarner Losh /* 1160*aa413543SWarner Losh * Skip async commands, they are posted to the card for 1161*aa413543SWarner Losh * an indefinite amount of time and have no deadline. 1162*aa413543SWarner Losh */ 1163*aa413543SWarner Losh if (tr->deadline == SBT_MAX) 1164*aa413543SWarner Losh continue; 1165*aa413543SWarner Losh 1166*aa413543SWarner Losh /* 1167*aa413543SWarner Losh * If we know this tracker hasn't timed out, we also 1168*aa413543SWarner Losh * know all subsequent ones haven't timed out. The tr 1169*aa413543SWarner Losh * queue is in submission order and all normal commands 1170*aa413543SWarner Losh * in a queue have the same timeout (or the timeout was 1171*aa413543SWarner Losh * changed by the user, but we eventually timeout then). 1172*aa413543SWarner Losh */ 1173*aa413543SWarner Losh idle = false; 1174*aa413543SWarner Losh if (now <= tr->deadline) 1175*aa413543SWarner Losh break; 1176*aa413543SWarner Losh 1177*aa413543SWarner Losh /* 1178*aa413543SWarner Losh * Timeout expired, abort it or reset controller. 1179*aa413543SWarner Losh */ 1180*aa413543SWarner Losh if (ctrlr->enable_aborts && 1181*aa413543SWarner Losh tr->req->cb_fn != nvme_abort_complete) { 1182*aa413543SWarner Losh /* 1183*aa413543SWarner Losh * This isn't an abort command, ask for a 1184*aa413543SWarner Losh * hardware abort. This goes to the admin 1185*aa413543SWarner Losh * queue which will reset the card if it 1186*aa413543SWarner Losh * times out. 1187*aa413543SWarner Losh */ 1188*aa413543SWarner Losh nvme_ctrlr_cmd_abort(ctrlr, tr->cid, qpair->id, 1189*aa413543SWarner Losh nvme_abort_complete, tr); 1190*aa413543SWarner Losh } else { 1191*aa413543SWarner Losh /* 1192*aa413543SWarner Losh * We have a live command in the card (either 1193*aa413543SWarner Losh * one we couldn't abort, or aborts weren't 1194*aa413543SWarner Losh * enabled). We can only reset. 1195*aa413543SWarner Losh */ 1196*aa413543SWarner Losh mtx_unlock(&qpair->lock); 1197*aa413543SWarner Losh goto do_reset; 1198*aa413543SWarner Losh } 1199*aa413543SWarner Losh } 1200*aa413543SWarner Losh mtx_unlock(&qpair->lock); 1201*aa413543SWarner Losh break; 1202*aa413543SWarner Losh 1203502dc84aSWarner Losh case RECOVERY_WAITING: 12041d6021cdSWarner Losh /* 12051d6021cdSWarner Losh * These messages aren't interesting while we're suspended. We 12061d6021cdSWarner Losh * put the queues into waiting state while 12071d6021cdSWarner Losh * suspending. Suspending takes a while, so we'll see these 12081d6021cdSWarner Losh * during that time and they aren't diagnostic. At other times, 12091d6021cdSWarner Losh * they indicate a problem that's worth complaining about. 12101d6021cdSWarner Losh */ 12111d6021cdSWarner Losh if (!device_is_suspended(ctrlr->dev)) 1212d9543162SWarner Losh nvme_printf(ctrlr, "Waiting for reset to complete\n"); 12138052b01eSWarner Losh idle = false; /* We want to keep polling */ 1214502dc84aSWarner Losh break; 1215d85d9648SWarner Losh } 1216bb0ec6b3SJim Harris 1217502dc84aSWarner Losh /* 1218502dc84aSWarner Losh * Rearm the timeout. 1219502dc84aSWarner Losh */ 1220502dc84aSWarner Losh if (!idle) { 1221b3c9b606SAlexander Motin callout_schedule_sbt(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 0); 1222502dc84aSWarner Losh } else { 1223502dc84aSWarner Losh qpair->timer_armed = false; 1224502dc84aSWarner Losh } 1225502dc84aSWarner Losh } 1226502dc84aSWarner Losh 1227502dc84aSWarner Losh /* 1228502dc84aSWarner Losh * Submit the tracker to the hardware. Must already be in the 1229502dc84aSWarner Losh * outstanding queue when called. 1230502dc84aSWarner Losh */ 1231bb0ec6b3SJim Harris void 1232b846efd7SJim Harris nvme_qpair_submit_tracker(struct nvme_qpair *qpair, struct nvme_tracker *tr) 1233bb0ec6b3SJim Harris { 1234ad697276SJim Harris struct nvme_request *req; 123594143332SJim Harris struct nvme_controller *ctrlr; 1236ead7e103SAlexander Motin int timeout; 1237bb0ec6b3SJim Harris 1238b846efd7SJim Harris mtx_assert(&qpair->lock, MA_OWNED); 1239b846efd7SJim Harris 1240ad697276SJim Harris req = tr->req; 1241ad697276SJim Harris req->cmd.cid = tr->cid; 1242bb0ec6b3SJim Harris qpair->act_tr[tr->cid] = tr; 124394143332SJim Harris ctrlr = qpair->ctrlr; 1244bb0ec6b3SJim Harris 1245ead7e103SAlexander Motin if (req->timeout) { 1246ead7e103SAlexander Motin if (req->cb_fn == nvme_completion_poll_cb) 1247502dc84aSWarner Losh timeout = 1; 12488d6c0743SAlexander Motin else if (qpair->id == 0) 12498d6c0743SAlexander Motin timeout = ctrlr->admin_timeout_period; 1250ead7e103SAlexander Motin else 1251502dc84aSWarner Losh timeout = ctrlr->timeout_period; 1252502dc84aSWarner Losh tr->deadline = getsbinuptime() + timeout * SBT_1S; 1253502dc84aSWarner Losh if (!qpair->timer_armed) { 1254502dc84aSWarner Losh qpair->timer_armed = true; 1255b3c9b606SAlexander Motin callout_reset_sbt_on(&qpair->timer, SBT_1S / 2, SBT_1S / 2, 1256b3c9b606SAlexander Motin nvme_qpair_timeout, qpair, qpair->cpu, 0); 1257ead7e103SAlexander Motin } 1258502dc84aSWarner Losh } else 1259502dc84aSWarner Losh tr->deadline = SBT_MAX; 1260bb0ec6b3SJim Harris 1261bb0ec6b3SJim Harris /* Copy the command from the tracker to the submission queue. */ 1262ad697276SJim Harris memcpy(&qpair->cmd[qpair->sq_tail], &req->cmd, sizeof(req->cmd)); 1263bb0ec6b3SJim Harris 1264bb0ec6b3SJim Harris if (++qpair->sq_tail == qpair->num_entries) 1265bb0ec6b3SJim Harris qpair->sq_tail = 0; 1266bb0ec6b3SJim Harris 12672e0090afSJustin Hibbits bus_dmamap_sync(qpair->dma_tag, qpair->queuemem_map, 12682e0090afSJustin Hibbits BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1269c931cf6aSWarner Losh bus_space_write_4(ctrlr->bus_tag, ctrlr->bus_handle, 1270f93b7f95SWarner Losh qpair->sq_tdbl_off, qpair->sq_tail); 1271bb0ec6b3SJim Harris qpair->num_cmds++; 1272bb0ec6b3SJim Harris } 12735ae9ed68SJim Harris 1274d6f54866SJim Harris static void 1275ca269f32SJim Harris nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 1276ca269f32SJim Harris { 1277ca269f32SJim Harris struct nvme_tracker *tr = arg; 1278ca269f32SJim Harris uint32_t cur_nseg; 1279ca269f32SJim Harris 1280ca269f32SJim Harris /* 1281ca269f32SJim Harris * If the mapping operation failed, return immediately. The caller 1282ca269f32SJim Harris * is responsible for detecting the error status and failing the 1283ca269f32SJim Harris * tracker manually. 1284ca269f32SJim Harris */ 1285a6e30963SJim Harris if (error != 0) { 1286a6e30963SJim Harris nvme_printf(tr->qpair->ctrlr, 1287a6e30963SJim Harris "nvme_payload_map err %d\n", error); 1288ca269f32SJim Harris return; 1289a6e30963SJim Harris } 1290ca269f32SJim Harris 1291ca269f32SJim Harris /* 12920fd4cd40SWarner Losh * Note that we specified ctrlr->page_size for alignment and max 12930fd4cd40SWarner Losh * segment size when creating the bus dma tags. So here we can safely 12940fd4cd40SWarner Losh * just transfer each segment to its associated PRP entry. 1295ca269f32SJim Harris */ 12960d787e9bSWojciech Macek tr->req->cmd.prp1 = htole64(seg[0].ds_addr); 1297ca269f32SJim Harris 1298ca269f32SJim Harris if (nseg == 2) { 12990d787e9bSWojciech Macek tr->req->cmd.prp2 = htole64(seg[1].ds_addr); 1300ca269f32SJim Harris } else if (nseg > 2) { 1301ca269f32SJim Harris cur_nseg = 1; 13020d787e9bSWojciech Macek tr->req->cmd.prp2 = htole64((uint64_t)tr->prp_bus_addr); 1303ca269f32SJim Harris while (cur_nseg < nseg) { 1304ca269f32SJim Harris tr->prp[cur_nseg-1] = 13050d787e9bSWojciech Macek htole64((uint64_t)seg[cur_nseg].ds_addr); 1306ca269f32SJim Harris cur_nseg++; 1307ca269f32SJim Harris } 1308a6e30963SJim Harris } else { 1309a6e30963SJim Harris /* 1310a6e30963SJim Harris * prp2 should not be used by the controller 1311a6e30963SJim Harris * since there is only one segment, but set 1312a6e30963SJim Harris * to 0 just to be safe. 1313a6e30963SJim Harris */ 1314a6e30963SJim Harris tr->req->cmd.prp2 = 0; 1315ca269f32SJim Harris } 1316ca269f32SJim Harris 13172e0090afSJustin Hibbits bus_dmamap_sync(tr->qpair->dma_tag_payload, tr->payload_dma_map, 13182e0090afSJustin Hibbits BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1319ca269f32SJim Harris nvme_qpair_submit_tracker(tr->qpair, tr); 1320ca269f32SJim Harris } 1321ca269f32SJim Harris 1322ca269f32SJim Harris static void 1323d6f54866SJim Harris _nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 13245ae9ed68SJim Harris { 13255ae9ed68SJim Harris struct nvme_tracker *tr; 1326e2b99004SJim Harris int err = 0; 13275ae9ed68SJim Harris 1328d6f54866SJim Harris mtx_assert(&qpair->lock, MA_OWNED); 13295ae9ed68SJim Harris 133065c2474eSJim Harris tr = TAILQ_FIRST(&qpair->free_tr); 1331232e2edbSJim Harris req->qpair = qpair; 133221b6da58SJim Harris 13339229b310SWarner Losh /* 13349229b310SWarner Losh * The controller has failed, so fail the request. Note, that this races 13359229b310SWarner Losh * the recovery / timeout code. Since we hold the qpair lock, we know 13369229b310SWarner Losh * it's safe to fail directly. is_failed is set when we fail the controller. 13379229b310SWarner Losh * It is only ever reset in the ioctl reset controller path, which is safe 13389229b310SWarner Losh * to race (for failed controllers, we make no guarantees about bringing 13399229b310SWarner Losh * it out of failed state relative to other commands). 13409229b310SWarner Losh */ 13419229b310SWarner Losh if (qpair->ctrlr->is_failed) { 13429229b310SWarner Losh nvme_qpair_manual_complete_request(qpair, req, 1343123e2906SWarner Losh NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, 1, 1344123e2906SWarner Losh ERROR_PRINT_NONE); 13459229b310SWarner Losh return; 13469229b310SWarner Losh } 13479229b310SWarner Losh 13480f71ecf7SJim Harris /* 13498052b01eSWarner Losh * No tracker is available, or the qpair is disabled due to an 13509cd7b624SWarner Losh * in-progress controller-level reset. If we lose the race with 13519229b310SWarner Losh * recovery_state, then we may add an extra request to the queue which 13529229b310SWarner Losh * will be resubmitted later. We only set recovery_state to NONE with 13539229b310SWarner Losh * qpair->lock also held, so if we observe that the state is not NONE, 13549229b310SWarner Losh * we know it won't transition back to NONE without retrying queued 13559229b310SWarner Losh * request. 1356232e2edbSJim Harris */ 13579229b310SWarner Losh if (tr == NULL || qpair->recovery_state != RECOVERY_NONE) { 13580f71ecf7SJim Harris STAILQ_INSERT_TAIL(&qpair->queued_req, req, stailq); 1359d6f54866SJim Harris return; 136021b6da58SJim Harris } 136121b6da58SJim Harris 136265c2474eSJim Harris TAILQ_REMOVE(&qpair->free_tr, tr, tailq); 136365c2474eSJim Harris TAILQ_INSERT_TAIL(&qpair->outstanding_tr, tr, tailq); 1364502dc84aSWarner Losh tr->deadline = SBT_MAX; 13655ae9ed68SJim Harris tr->req = req; 13665ae9ed68SJim Harris 136792103adbSJohn Baldwin if (!req->payload_valid) { 1368b846efd7SJim Harris nvme_qpair_submit_tracker(tr->qpair, tr); 136992103adbSJohn Baldwin return; 13705ae9ed68SJim Harris } 1371e2b99004SJim Harris 13720dd84c3bSWarner Losh /* 13730dd84c3bSWarner Losh * tr->deadline updating when nvme_payload_map calls 13740dd84c3bSWarner Losh * nvme_qpair_submit_tracker (we call it above directly 13750dd84c3bSWarner Losh * when there's no map to load). 13760dd84c3bSWarner Losh */ 137792103adbSJohn Baldwin err = bus_dmamap_load_mem(tr->qpair->dma_tag_payload, 137892103adbSJohn Baldwin tr->payload_dma_map, &req->payload, nvme_payload_map, tr, 0); 1379e2b99004SJim Harris if (err != 0) { 1380e2b99004SJim Harris /* 1381e2b99004SJim Harris * The dmamap operation failed, so we manually fail the 1382e2b99004SJim Harris * tracker here with DATA_TRANSFER_ERROR status. 1383e2b99004SJim Harris * 1384e2b99004SJim Harris * nvme_qpair_manual_complete_tracker must not be called 1385e2b99004SJim Harris * with the qpair lock held. 1386e2b99004SJim Harris */ 138792103adbSJohn Baldwin nvme_printf(qpair->ctrlr, 138892103adbSJohn Baldwin "bus_dmamap_load_mem returned 0x%x!\n", err); 1389e2b99004SJim Harris mtx_unlock(&qpair->lock); 139043393e8bSWarner Losh nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 13912ffd6fceSWarner Losh NVME_SC_DATA_TRANSFER_ERROR, DO_NOT_RETRY, ERROR_PRINT_ALL); 1392e2b99004SJim Harris mtx_lock(&qpair->lock); 1393e2b99004SJim Harris } 1394d6f54866SJim Harris } 13955ae9ed68SJim Harris 1396d6f54866SJim Harris void 1397d6f54866SJim Harris nvme_qpair_submit_request(struct nvme_qpair *qpair, struct nvme_request *req) 1398d6f54866SJim Harris { 1399d6f54866SJim Harris 1400d6f54866SJim Harris mtx_lock(&qpair->lock); 1401d6f54866SJim Harris _nvme_qpair_submit_request(qpair, req); 14025ae9ed68SJim Harris mtx_unlock(&qpair->lock); 14035ae9ed68SJim Harris } 1404b846efd7SJim Harris 1405b846efd7SJim Harris static void 1406b846efd7SJim Harris nvme_qpair_enable(struct nvme_qpair *qpair) 1407b846efd7SJim Harris { 14088052b01eSWarner Losh if (mtx_initialized(&qpair->recovery)) 14098052b01eSWarner Losh mtx_assert(&qpair->recovery, MA_OWNED); 14108052b01eSWarner Losh if (mtx_initialized(&qpair->lock)) 1411502dc84aSWarner Losh mtx_assert(&qpair->lock, MA_OWNED); 14129cd7b624SWarner Losh KASSERT(!qpair->ctrlr->is_failed, 1413da8324a9SWarner Losh ("Enabling a failed qpair\n")); 1414b846efd7SJim Harris 1415502dc84aSWarner Losh qpair->recovery_state = RECOVERY_NONE; 1416cb5b7c13SJim Harris } 1417cb5b7c13SJim Harris 1418cb5b7c13SJim Harris void 1419cb5b7c13SJim Harris nvme_qpair_reset(struct nvme_qpair *qpair) 1420cb5b7c13SJim Harris { 1421cb5b7c13SJim Harris 1422b846efd7SJim Harris qpair->sq_head = qpair->sq_tail = qpair->cq_head = 0; 1423b846efd7SJim Harris 1424b846efd7SJim Harris /* 1425b846efd7SJim Harris * First time through the completion queue, HW will set phase 1426b846efd7SJim Harris * bit on completions to 1. So set this to 1 here, indicating 1427b846efd7SJim Harris * we're looking for a 1 to know which entries have completed. 1428b846efd7SJim Harris * we'll toggle the bit each time when the completion queue 1429b846efd7SJim Harris * rolls over. 1430b846efd7SJim Harris */ 1431b846efd7SJim Harris qpair->phase = 1; 1432b846efd7SJim Harris 1433b846efd7SJim Harris memset(qpair->cmd, 0, 1434b846efd7SJim Harris qpair->num_entries * sizeof(struct nvme_command)); 1435b846efd7SJim Harris memset(qpair->cpl, 0, 1436b846efd7SJim Harris qpair->num_entries * sizeof(struct nvme_completion)); 1437b846efd7SJim Harris } 1438b846efd7SJim Harris 1439b846efd7SJim Harris void 1440b846efd7SJim Harris nvme_admin_qpair_enable(struct nvme_qpair *qpair) 1441b846efd7SJim Harris { 144243a37256SJim Harris struct nvme_tracker *tr; 144343a37256SJim Harris struct nvme_tracker *tr_temp; 1444a510dbc8SWarner Losh bool rpt; 144543a37256SJim Harris 144643a37256SJim Harris /* 144743a37256SJim Harris * Manually abort each outstanding admin command. Do not retry 144843a37256SJim Harris * admin commands found here, since they will be left over from 144943a37256SJim Harris * a controller reset and its likely the context in which the 145043a37256SJim Harris * command was issued no longer applies. 145143a37256SJim Harris */ 1452a510dbc8SWarner Losh rpt = !TAILQ_EMPTY(&qpair->outstanding_tr); 1453a510dbc8SWarner Losh if (rpt) 1454547d523eSJim Harris nvme_printf(qpair->ctrlr, 145543a37256SJim Harris "aborting outstanding admin command\n"); 1456a510dbc8SWarner Losh TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 145743393e8bSWarner Losh nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 14582ffd6fceSWarner Losh NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 145943a37256SJim Harris } 1460a510dbc8SWarner Losh if (rpt) 1461a510dbc8SWarner Losh nvme_printf(qpair->ctrlr, 1462a510dbc8SWarner Losh "done aborting outstanding admin\n"); 1463b846efd7SJim Harris 14648052b01eSWarner Losh mtx_lock(&qpair->recovery); 1465502dc84aSWarner Losh mtx_lock(&qpair->lock); 1466b846efd7SJim Harris nvme_qpair_enable(qpair); 1467502dc84aSWarner Losh mtx_unlock(&qpair->lock); 14688052b01eSWarner Losh mtx_unlock(&qpair->recovery); 1469b846efd7SJim Harris } 1470b846efd7SJim Harris 1471b846efd7SJim Harris void 1472b846efd7SJim Harris nvme_io_qpair_enable(struct nvme_qpair *qpair) 1473b846efd7SJim Harris { 1474b846efd7SJim Harris STAILQ_HEAD(, nvme_request) temp; 1475b846efd7SJim Harris struct nvme_tracker *tr; 1476cb5b7c13SJim Harris struct nvme_tracker *tr_temp; 1477b846efd7SJim Harris struct nvme_request *req; 1478a510dbc8SWarner Losh bool report; 1479b846efd7SJim Harris 1480cb5b7c13SJim Harris /* 1481cb5b7c13SJim Harris * Manually abort each outstanding I/O. This normally results in a 1482cb5b7c13SJim Harris * retry, unless the retry count on the associated request has 1483cb5b7c13SJim Harris * reached its limit. 1484cb5b7c13SJim Harris */ 1485a510dbc8SWarner Losh report = !TAILQ_EMPTY(&qpair->outstanding_tr); 1486a510dbc8SWarner Losh if (report) 1487547d523eSJim Harris nvme_printf(qpair->ctrlr, "aborting outstanding i/o\n"); 1488a510dbc8SWarner Losh TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 148943393e8bSWarner Losh nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 14902ffd6fceSWarner Losh NVME_SC_ABORTED_BY_REQUEST, 0, ERROR_PRINT_NO_RETRY); 1491cb5b7c13SJim Harris } 1492a510dbc8SWarner Losh if (report) 1493a510dbc8SWarner Losh nvme_printf(qpair->ctrlr, "done aborting outstanding i/o\n"); 1494cb5b7c13SJim Harris 14958052b01eSWarner Losh mtx_lock(&qpair->recovery); 1496b846efd7SJim Harris mtx_lock(&qpair->lock); 1497b846efd7SJim Harris nvme_qpair_enable(qpair); 1498b846efd7SJim Harris 1499b846efd7SJim Harris STAILQ_INIT(&temp); 1500b846efd7SJim Harris STAILQ_SWAP(&qpair->queued_req, &temp, nvme_request); 1501b846efd7SJim Harris 1502a510dbc8SWarner Losh report = !STAILQ_EMPTY(&temp); 1503a510dbc8SWarner Losh if (report) 1504a510dbc8SWarner Losh nvme_printf(qpair->ctrlr, "resubmitting queued i/o\n"); 1505b846efd7SJim Harris while (!STAILQ_EMPTY(&temp)) { 1506b846efd7SJim Harris req = STAILQ_FIRST(&temp); 1507b846efd7SJim Harris STAILQ_REMOVE_HEAD(&temp, stailq); 1508547d523eSJim Harris nvme_qpair_print_command(qpair, &req->cmd); 1509b846efd7SJim Harris _nvme_qpair_submit_request(qpair, req); 1510b846efd7SJim Harris } 1511a510dbc8SWarner Losh if (report) 1512a510dbc8SWarner Losh nvme_printf(qpair->ctrlr, "done resubmitting i/o\n"); 1513b846efd7SJim Harris 1514b846efd7SJim Harris mtx_unlock(&qpair->lock); 15158052b01eSWarner Losh mtx_unlock(&qpair->recovery); 1516b846efd7SJim Harris } 1517b846efd7SJim Harris 1518b846efd7SJim Harris static void 1519b846efd7SJim Harris nvme_qpair_disable(struct nvme_qpair *qpair) 1520b846efd7SJim Harris { 1521502dc84aSWarner Losh struct nvme_tracker *tr, *tr_temp; 1522b846efd7SJim Harris 15238052b01eSWarner Losh if (mtx_initialized(&qpair->recovery)) 15248052b01eSWarner Losh mtx_assert(&qpair->recovery, MA_OWNED); 15258052b01eSWarner Losh if (mtx_initialized(&qpair->lock)) 15268052b01eSWarner Losh mtx_assert(&qpair->lock, MA_OWNED); 15278052b01eSWarner Losh 1528502dc84aSWarner Losh qpair->recovery_state = RECOVERY_WAITING; 1529502dc84aSWarner Losh TAILQ_FOREACH_SAFE(tr, &qpair->outstanding_tr, tailq, tr_temp) { 1530502dc84aSWarner Losh tr->deadline = SBT_MAX; 1531502dc84aSWarner Losh } 1532b846efd7SJim Harris } 1533b846efd7SJim Harris 1534b846efd7SJim Harris void 1535b846efd7SJim Harris nvme_admin_qpair_disable(struct nvme_qpair *qpair) 1536b846efd7SJim Harris { 15378052b01eSWarner Losh mtx_lock(&qpair->recovery); 1538b846efd7SJim Harris 1539da8324a9SWarner Losh mtx_lock(&qpair->lock); 1540b846efd7SJim Harris nvme_qpair_disable(qpair); 1541da8324a9SWarner Losh mtx_unlock(&qpair->lock); 1542da8324a9SWarner Losh 1543b846efd7SJim Harris nvme_admin_qpair_abort_aers(qpair); 15448052b01eSWarner Losh 15458052b01eSWarner Losh mtx_unlock(&qpair->recovery); 1546b846efd7SJim Harris } 1547b846efd7SJim Harris 1548b846efd7SJim Harris void 1549b846efd7SJim Harris nvme_io_qpair_disable(struct nvme_qpair *qpair) 1550b846efd7SJim Harris { 15518052b01eSWarner Losh mtx_lock(&qpair->recovery); 15528052b01eSWarner Losh mtx_lock(&qpair->lock); 1553b846efd7SJim Harris 1554b846efd7SJim Harris nvme_qpair_disable(qpair); 15558052b01eSWarner Losh 15568052b01eSWarner Losh mtx_unlock(&qpair->lock); 15578052b01eSWarner Losh mtx_unlock(&qpair->recovery); 1558b846efd7SJim Harris } 1559232e2edbSJim Harris 1560232e2edbSJim Harris void 1561232e2edbSJim Harris nvme_qpair_fail(struct nvme_qpair *qpair) 1562232e2edbSJim Harris { 1563232e2edbSJim Harris struct nvme_tracker *tr; 1564232e2edbSJim Harris struct nvme_request *req; 1565232e2edbSJim Harris 1566824073fbSWarner Losh if (!mtx_initialized(&qpair->lock)) 1567824073fbSWarner Losh return; 1568824073fbSWarner Losh 1569232e2edbSJim Harris mtx_lock(&qpair->lock); 1570232e2edbSJim Harris 1571da8324a9SWarner Losh if (!STAILQ_EMPTY(&qpair->queued_req)) { 1572da8324a9SWarner Losh nvme_printf(qpair->ctrlr, "failing queued i/o\n"); 1573da8324a9SWarner Losh } 1574232e2edbSJim Harris while (!STAILQ_EMPTY(&qpair->queued_req)) { 1575232e2edbSJim Harris req = STAILQ_FIRST(&qpair->queued_req); 1576232e2edbSJim Harris STAILQ_REMOVE_HEAD(&qpair->queued_req, stailq); 1577232e2edbSJim Harris mtx_unlock(&qpair->lock); 1578232e2edbSJim Harris nvme_qpair_manual_complete_request(qpair, req, NVME_SCT_GENERIC, 1579123e2906SWarner Losh NVME_SC_ABORTED_BY_REQUEST, 1, ERROR_PRINT_ALL); 1580232e2edbSJim Harris mtx_lock(&qpair->lock); 1581232e2edbSJim Harris } 1582232e2edbSJim Harris 1583da8324a9SWarner Losh if (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1584da8324a9SWarner Losh nvme_printf(qpair->ctrlr, "failing outstanding i/o\n"); 1585da8324a9SWarner Losh } 1586232e2edbSJim Harris /* Manually abort each outstanding I/O. */ 1587232e2edbSJim Harris while (!TAILQ_EMPTY(&qpair->outstanding_tr)) { 1588232e2edbSJim Harris tr = TAILQ_FIRST(&qpair->outstanding_tr); 1589232e2edbSJim Harris /* 1590232e2edbSJim Harris * Do not remove the tracker. The abort_tracker path will 1591232e2edbSJim Harris * do that for us. 1592232e2edbSJim Harris */ 1593232e2edbSJim Harris mtx_unlock(&qpair->lock); 159443393e8bSWarner Losh nvme_qpair_manual_complete_tracker(tr, NVME_SCT_GENERIC, 15952ffd6fceSWarner Losh NVME_SC_ABORTED_BY_REQUEST, DO_NOT_RETRY, ERROR_PRINT_ALL); 1596232e2edbSJim Harris mtx_lock(&qpair->lock); 1597232e2edbSJim Harris } 1598232e2edbSJim Harris 1599232e2edbSJim Harris mtx_unlock(&qpair->lock); 1600232e2edbSJim Harris } 1601