1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __NVME_PRIVATE_H__ 30 #define __NVME_PRIVATE_H__ 31 32 #include <sys/param.h> 33 #include <sys/bio.h> 34 #include <sys/bus.h> 35 #include <sys/counter.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/memdesc.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/systm.h> 44 #include <sys/taskqueue.h> 45 46 #include <vm/uma.h> 47 48 #include <machine/bus.h> 49 50 #include "nvme.h" 51 52 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 53 54 MALLOC_DECLARE(M_NVME); 55 56 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 57 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 58 59 #define NVME_ADMIN_TRACKERS (16) 60 #define NVME_ADMIN_ENTRIES (128) 61 62 /* 63 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 64 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 65 * will allow outstanding on an I/O qpair at any time. The only advantage in 66 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 67 * the contents of the submission and completion queues, it will show a longer 68 * history of data. 69 */ 70 #define NVME_IO_ENTRIES (256) 71 #define NVME_IO_TRACKERS (128) 72 #define NVME_MIN_IO_TRACKERS (4) 73 #define NVME_MAX_IO_TRACKERS (1024) 74 75 #define NVME_INT_COAL_TIME (0) /* disabled */ 76 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 77 78 #define NVME_MAX_NAMESPACES (16) 79 #define NVME_MAX_CONSUMERS (2) 80 #define NVME_MAX_ASYNC_EVENTS (8) 81 82 #define NVME_ADMIN_TIMEOUT_PERIOD (60) /* in seconds */ 83 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 84 #define NVME_MIN_TIMEOUT_PERIOD (5) 85 #define NVME_MAX_TIMEOUT_PERIOD (120) 86 87 #define NVME_DEFAULT_RETRY_COUNT (4) 88 89 /* Maximum log page size to fetch for AERs. */ 90 #define NVME_MAX_AER_LOG_SIZE (4096) 91 92 /* 93 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 94 * it. 95 */ 96 #ifndef CACHE_LINE_SIZE 97 #define CACHE_LINE_SIZE (64) 98 #endif 99 100 #define NVME_GONE 0xfffffffful 101 102 extern int32_t nvme_retry_count; 103 extern bool nvme_verbose_cmd_dump; 104 105 struct nvme_completion_poll_status { 106 struct nvme_completion cpl; 107 int done; 108 }; 109 110 struct nvme_request { 111 struct nvme_command cmd; 112 struct nvme_qpair *qpair; 113 struct memdesc payload; 114 nvme_cb_fn_t cb_fn; 115 void *cb_arg; 116 int32_t retries; 117 bool payload_valid; 118 bool timeout; 119 bool spare[2]; /* Future use */ 120 STAILQ_ENTRY(nvme_request) stailq; 121 }; 122 123 struct nvme_async_event_request { 124 struct nvme_controller *ctrlr; 125 struct nvme_request *req; 126 struct task task; 127 struct mtx mtx; 128 struct nvme_completion cpl; 129 uint32_t log_page_id; 130 uint32_t log_page_size; 131 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 132 }; 133 134 struct nvme_tracker { 135 TAILQ_ENTRY(nvme_tracker) tailq; 136 struct nvme_request *req; 137 struct nvme_qpair *qpair; 138 sbintime_t deadline; 139 bus_dmamap_t payload_dma_map; 140 uint16_t cid; 141 142 uint64_t *prp; 143 bus_addr_t prp_bus_addr; 144 }; 145 146 enum nvme_recovery { 147 RECOVERY_NONE = 0, /* Normal operations */ 148 RECOVERY_WAITING, /* waiting for the reset to complete */ 149 }; 150 struct nvme_qpair { 151 struct nvme_controller *ctrlr; 152 uint32_t id; 153 int domain; 154 int cpu; 155 156 uint16_t vector; 157 int rid; 158 struct resource *res; 159 void *tag; 160 161 struct callout timer; /* recovery lock */ 162 bool timer_armed; /* recovery lock */ 163 enum nvme_recovery recovery_state; /* recovery lock */ 164 165 uint32_t num_entries; 166 uint32_t num_trackers; 167 uint32_t sq_tdbl_off; 168 uint32_t cq_hdbl_off; 169 170 uint32_t phase; 171 uint32_t sq_head; 172 uint32_t sq_tail; 173 uint32_t cq_head; 174 175 int64_t num_cmds; 176 int64_t num_intr_handler_calls; 177 int64_t num_retries; 178 int64_t num_failures; 179 int64_t num_ignored; 180 int64_t num_recovery_nolock; 181 182 struct nvme_command *cmd; 183 struct nvme_completion *cpl; 184 185 bus_dma_tag_t dma_tag; 186 bus_dma_tag_t dma_tag_payload; 187 188 bus_dmamap_t queuemem_map; 189 uint64_t cmd_bus_addr; 190 uint64_t cpl_bus_addr; 191 192 TAILQ_HEAD(, nvme_tracker) free_tr; 193 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 194 STAILQ_HEAD(, nvme_request) queued_req; 195 196 struct nvme_tracker **act_tr; 197 198 struct mtx_padalign lock; 199 struct mtx_padalign recovery; 200 } __aligned(CACHE_LINE_SIZE); 201 202 struct nvme_namespace { 203 struct nvme_controller *ctrlr; 204 struct nvme_namespace_data data; 205 uint32_t id; 206 uint32_t flags; 207 struct cdev *cdev; 208 void *cons_cookie[NVME_MAX_CONSUMERS]; 209 uint32_t boundary; 210 struct mtx lock; 211 }; 212 213 /* 214 * One of these per allocated PCI device. 215 */ 216 struct nvme_controller { 217 device_t dev; 218 219 struct mtx lock; 220 int domain; 221 uint32_t ready_timeout_in_ms; 222 uint32_t quirks; 223 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 224 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 225 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */ 226 #define QUIRK_AHCI 8 /* Attached via AHCI redirect */ 227 228 bus_space_tag_t bus_tag; 229 bus_space_handle_t bus_handle; 230 int resource_id; 231 struct resource *resource; 232 233 /* 234 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 235 * separate from the control registers which are in BAR 0/1. These 236 * members track the mapping of BAR 4/5 for that reason. 237 */ 238 int msix_table_resource_id; 239 struct resource *msix_table_resource; 240 int msix_pba_resource_id; 241 struct resource *msix_pba_resource; 242 243 int msi_count; 244 uint32_t enable_aborts; 245 246 uint32_t num_io_queues; 247 uint32_t max_hw_pend_io; 248 249 /* Fields for tracking progress during controller initialization. */ 250 struct intr_config_hook config_hook; 251 uint32_t ns_identified; 252 uint32_t queues_created; 253 254 struct task reset_task; 255 struct taskqueue *taskqueue; 256 257 /* For shared legacy interrupt. */ 258 int rid; 259 struct resource *res; 260 void *tag; 261 262 /** maximum i/o size in bytes */ 263 uint32_t max_xfer_size; 264 265 /** LO and HI capacity mask */ 266 uint32_t cap_lo; 267 uint32_t cap_hi; 268 269 /** Page size and log2(page_size) - 12 that we're currently using */ 270 uint32_t page_size; 271 uint32_t mps; 272 273 /** interrupt coalescing time period (in microseconds) */ 274 uint32_t int_coal_time; 275 276 /** interrupt coalescing threshold */ 277 uint32_t int_coal_threshold; 278 279 /** timeout period in seconds */ 280 uint32_t admin_timeout_period; 281 uint32_t timeout_period; 282 283 /** doorbell stride */ 284 uint32_t dstrd; 285 286 struct nvme_qpair adminq; 287 struct nvme_qpair *ioq; 288 289 struct nvme_registers *regs; 290 291 struct nvme_controller_data cdata; 292 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 293 294 struct cdev *cdev; 295 296 /** bit mask of event types currently enabled for async events */ 297 uint32_t async_event_config; 298 299 uint32_t num_aers; 300 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 301 302 void *cons_cookie[NVME_MAX_CONSUMERS]; 303 304 uint32_t is_resetting; 305 uint32_t notification_sent; 306 u_int fail_on_reset; 307 308 bool is_failed; 309 bool is_failed_admin; 310 bool is_dying; 311 bool isr_warned; 312 bool is_initialized; 313 314 /* Host Memory Buffer */ 315 int hmb_nchunks; 316 size_t hmb_chunk; 317 bus_dma_tag_t hmb_tag; 318 struct nvme_hmb_chunk { 319 bus_dmamap_t hmbc_map; 320 void *hmbc_vaddr; 321 uint64_t hmbc_paddr; 322 } *hmb_chunks; 323 bus_dma_tag_t hmb_desc_tag; 324 bus_dmamap_t hmb_desc_map; 325 struct nvme_hmb_desc *hmb_desc_vaddr; 326 uint64_t hmb_desc_paddr; 327 328 /* Statistics */ 329 counter_u64_t alignment_splits; 330 }; 331 332 #define nvme_mmio_offsetof(reg) \ 333 offsetof(struct nvme_registers, reg) 334 335 #define nvme_mmio_read_4(sc, reg) \ 336 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 337 nvme_mmio_offsetof(reg)) 338 339 #define nvme_mmio_write_4(sc, reg, val) \ 340 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 341 nvme_mmio_offsetof(reg), val) 342 343 #define nvme_mmio_write_8(sc, reg, val) \ 344 do { \ 345 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 346 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 347 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 348 nvme_mmio_offsetof(reg)+4, \ 349 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 350 } while (0); 351 352 #define nvme_printf(ctrlr, fmt, args...) \ 353 device_printf(ctrlr->dev, fmt, ##args) 354 355 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 356 357 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 358 void *payload, 359 nvme_cb_fn_t cb_fn, void *cb_arg); 360 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 361 uint32_t nsid, void *payload, 362 nvme_cb_fn_t cb_fn, void *cb_arg); 363 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 364 uint32_t microseconds, 365 uint32_t threshold, 366 nvme_cb_fn_t cb_fn, 367 void *cb_arg); 368 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 369 struct nvme_error_information_entry *payload, 370 uint32_t num_entries, /* 0 = max */ 371 nvme_cb_fn_t cb_fn, 372 void *cb_arg); 373 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 374 uint32_t nsid, 375 struct nvme_health_information_page *payload, 376 nvme_cb_fn_t cb_fn, 377 void *cb_arg); 378 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 379 struct nvme_firmware_page *payload, 380 nvme_cb_fn_t cb_fn, 381 void *cb_arg); 382 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 383 struct nvme_qpair *io_que, 384 nvme_cb_fn_t cb_fn, void *cb_arg); 385 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 386 struct nvme_qpair *io_que, 387 nvme_cb_fn_t cb_fn, void *cb_arg); 388 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 389 struct nvme_qpair *io_que, 390 nvme_cb_fn_t cb_fn, void *cb_arg); 391 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 392 struct nvme_qpair *io_que, 393 nvme_cb_fn_t cb_fn, void *cb_arg); 394 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 395 uint32_t num_queues, nvme_cb_fn_t cb_fn, 396 void *cb_arg); 397 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 398 uint32_t state, 399 nvme_cb_fn_t cb_fn, void *cb_arg); 400 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 401 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 402 403 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 404 405 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 406 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 407 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 408 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 409 /* ctrlr defined as void * to allow use with config_intrhook. */ 410 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 411 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 412 struct nvme_request *req); 413 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 414 struct nvme_request *req); 415 416 int nvme_qpair_construct(struct nvme_qpair *qpair, 417 uint32_t num_entries, uint32_t num_trackers, 418 struct nvme_controller *ctrlr); 419 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 420 struct nvme_tracker *tr); 421 bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 422 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 423 struct nvme_request *req); 424 void nvme_qpair_reset(struct nvme_qpair *qpair); 425 void nvme_qpair_fail(struct nvme_qpair *qpair); 426 427 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 428 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 429 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 430 431 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 432 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 433 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 434 435 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 436 struct nvme_controller *ctrlr); 437 void nvme_ns_destruct(struct nvme_namespace *ns); 438 439 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 440 441 void nvme_qpair_print_command(struct nvme_qpair *qpair, 442 struct nvme_command *cmd); 443 void nvme_qpair_print_completion(struct nvme_qpair *qpair, 444 struct nvme_completion *cpl); 445 446 int nvme_attach(device_t dev); 447 int nvme_shutdown(device_t dev); 448 int nvme_detach(device_t dev); 449 450 /* 451 * Wait for a command to complete using the nvme_completion_poll_cb. Used in 452 * limited contexts where the caller knows it's OK to block briefly while the 453 * command runs. The ISR will run the callback which will set status->done to 454 * true, usually within microseconds. If not, then after one second timeout 455 * handler should reset the controller and abort all outstanding requests 456 * including this polled one. If still not after ten seconds, then something is 457 * wrong with the driver, and panic is the only way to recover. 458 * 459 * Most commands using this interface aren't actual I/O to the drive's media so 460 * complete within a few microseconds. Adaptively spin for one tick to catch the 461 * vast majority of these without waiting for a tick plus scheduling delays. Since 462 * these are on startup, this drastically reduces startup time. 463 */ 464 static __inline void 465 nvme_completion_poll(struct nvme_completion_poll_status *status) 466 { 467 int timeout = ticks + 10 * hz; 468 sbintime_t delta = SBT_1US; 469 470 while (!atomic_load_acq_int(&status->done)) { 471 if (timeout - ticks < 0) 472 panic("NVME polled command failed to complete within 10s."); 473 pause_sbt("nvme", delta, 0, C_PREL(1)); 474 delta = min(SBT_1MS, delta + delta / 2); 475 } 476 } 477 478 static __inline void 479 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 480 { 481 uint64_t *bus_addr = (uint64_t *)arg; 482 483 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg)); 484 if (error != 0) 485 printf("nvme_single_map err %d\n", error); 486 *bus_addr = seg[0].ds_addr; 487 } 488 489 static __inline struct nvme_request * 490 _nvme_allocate_request(const int how, nvme_cb_fn_t cb_fn, void *cb_arg) 491 { 492 struct nvme_request *req; 493 494 KASSERT(how == M_WAITOK || how == M_NOWAIT, 495 ("nvme_allocate_request: invalid how %d", how)); 496 497 req = malloc(sizeof(*req), M_NVME, how | M_ZERO); 498 if (req != NULL) { 499 req->cb_fn = cb_fn; 500 req->cb_arg = cb_arg; 501 req->timeout = true; 502 } 503 return (req); 504 } 505 506 static __inline struct nvme_request * 507 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 508 const int how, nvme_cb_fn_t cb_fn, void *cb_arg) 509 { 510 struct nvme_request *req; 511 512 req = _nvme_allocate_request(how, cb_fn, cb_arg); 513 if (req != NULL) { 514 req->payload = memdesc_vaddr(payload, payload_size); 515 req->payload_valid = true; 516 } 517 return (req); 518 } 519 520 static __inline struct nvme_request * 521 nvme_allocate_request_null(const int how, nvme_cb_fn_t cb_fn, void *cb_arg) 522 { 523 struct nvme_request *req; 524 525 req = _nvme_allocate_request(how, cb_fn, cb_arg); 526 return (req); 527 } 528 529 static __inline struct nvme_request * 530 nvme_allocate_request_bio(struct bio *bio, const int how, nvme_cb_fn_t cb_fn, 531 void *cb_arg) 532 { 533 struct nvme_request *req; 534 535 req = _nvme_allocate_request(how, cb_fn, cb_arg); 536 if (req != NULL) { 537 req->payload = memdesc_bio(bio); 538 req->payload_valid = true; 539 } 540 return (req); 541 } 542 543 static __inline struct nvme_request * 544 nvme_allocate_request_ccb(union ccb *ccb, const int how, nvme_cb_fn_t cb_fn, 545 void *cb_arg) 546 { 547 struct nvme_request *req; 548 549 req = _nvme_allocate_request(how, cb_fn, cb_arg); 550 if (req != NULL) { 551 req->payload = memdesc_ccb(ccb); 552 req->payload_valid = true; 553 } 554 return (req); 555 } 556 557 #define nvme_free_request(req) free(req, M_NVME) 558 559 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 560 const struct nvme_completion *async_cpl, 561 uint32_t log_page_id, void *log_page_buffer, 562 uint32_t log_page_size); 563 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 564 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 565 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 566 567 void nvme_ctrlr_shared_handler(void *arg); 568 void nvme_ctrlr_get_ident(const struct nvme_controller *ctrlr, uint8_t *sn); 569 void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 570 571 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr); 572 int nvme_ctrlr_resume(struct nvme_controller *ctrlr); 573 574 #endif /* __NVME_PRIVATE_H__ */ 575