1 /*- 2 * Copyright (C) 2012 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __NVME_PRIVATE_H__ 30 #define __NVME_PRIVATE_H__ 31 32 #include <sys/param.h> 33 #include <sys/bio.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 #include <sys/systm.h> 41 #include <sys/taskqueue.h> 42 43 #include <vm/uma.h> 44 45 #include <machine/bus.h> 46 47 #include "nvme.h" 48 49 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 50 51 MALLOC_DECLARE(M_NVME); 52 53 #define CHATHAM2 54 55 #ifdef CHATHAM2 56 #define CHATHAM_PCI_ID 0x20118086 57 #define CHATHAM_CONTROL_BAR 0 58 #endif 59 60 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 61 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 62 63 #define NVME_MAX_PRP_LIST_ENTRIES (32) 64 65 /* 66 * For commands requiring more than 2 PRP entries, one PRP will be 67 * embedded in the command (prp1), and the rest of the PRP entries 68 * will be in a list pointed to by the command (prp2). This means 69 * that real max number of PRP entries we support is 32+1, which 70 * results in a max xfer size of 32*PAGE_SIZE. 71 */ 72 #define NVME_MAX_XFER_SIZE NVME_MAX_PRP_LIST_ENTRIES * PAGE_SIZE 73 74 #define NVME_ADMIN_TRACKERS (16) 75 #define NVME_ADMIN_ENTRIES (128) 76 /* min and max are defined in admin queue attributes section of spec */ 77 #define NVME_MIN_ADMIN_ENTRIES (2) 78 #define NVME_MAX_ADMIN_ENTRIES (4096) 79 80 /* 81 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 82 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 83 * will allow outstanding on an I/O qpair at any time. The only advantage in 84 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 85 * the contents of the submission and completion queues, it will show a longer 86 * history of data. 87 */ 88 #define NVME_IO_ENTRIES (256) 89 #define NVME_IO_TRACKERS (128) 90 #define NVME_MIN_IO_TRACKERS (4) 91 #define NVME_MAX_IO_TRACKERS (1024) 92 93 /* 94 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 95 * for each controller. 96 */ 97 98 #define NVME_INT_COAL_TIME (0) /* disabled */ 99 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 100 101 #define NVME_MAX_NAMESPACES (16) 102 #define NVME_MAX_CONSUMERS (2) 103 #define NVME_MAX_ASYNC_EVENTS (8) 104 105 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 106 #define NVME_MIN_TIMEOUT_PERIOD (5) 107 #define NVME_MAX_TIMEOUT_PERIOD (120) 108 109 #define NVME_DEFAULT_RETRY_COUNT (4) 110 111 /* Maximum log page size to fetch for AERs. */ 112 #define NVME_MAX_AER_LOG_SIZE (4096) 113 114 #ifndef CACHE_LINE_SIZE 115 #define CACHE_LINE_SIZE (64) 116 #endif 117 118 /* 119 * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O 120 * support and the bus_dmamap_load_bio API are available on the target 121 * kernel. This will ease porting back to earlier stable branches at a 122 * later point. 123 */ 124 #ifdef BIO_UNMAPPED 125 #define NVME_UNMAPPED_BIO_SUPPORT 126 #endif 127 128 extern uma_zone_t nvme_request_zone; 129 extern int32_t nvme_retry_count; 130 131 struct nvme_completion_poll_status { 132 133 struct nvme_completion cpl; 134 boolean_t done; 135 }; 136 137 #define NVME_REQUEST_VADDR 1 138 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 139 #define NVME_REQUEST_UIO 3 140 #ifdef NVME_UNMAPPED_BIO_SUPPORT 141 #define NVME_REQUEST_BIO 4 142 #endif 143 144 struct nvme_request { 145 146 struct nvme_command cmd; 147 struct nvme_qpair *qpair; 148 union { 149 void *payload; 150 struct uio *uio; 151 struct bio *bio; 152 } u; 153 uint32_t type; 154 uint32_t payload_size; 155 boolean_t timeout; 156 nvme_cb_fn_t cb_fn; 157 void *cb_arg; 158 int32_t retries; 159 STAILQ_ENTRY(nvme_request) stailq; 160 }; 161 162 struct nvme_async_event_request { 163 164 struct nvme_controller *ctrlr; 165 struct nvme_request *req; 166 struct nvme_completion cpl; 167 uint32_t log_page_id; 168 uint32_t log_page_size; 169 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 170 }; 171 172 struct nvme_tracker { 173 174 TAILQ_ENTRY(nvme_tracker) tailq; 175 struct nvme_request *req; 176 struct nvme_qpair *qpair; 177 struct callout timer; 178 bus_dmamap_t payload_dma_map; 179 uint16_t cid; 180 181 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 182 bus_addr_t prp_bus_addr; 183 bus_dmamap_t prp_dma_map; 184 }; 185 186 struct nvme_qpair { 187 188 struct nvme_controller *ctrlr; 189 uint32_t id; 190 uint32_t phase; 191 192 uint16_t vector; 193 int rid; 194 struct resource *res; 195 void *tag; 196 197 uint32_t max_xfer_size; 198 uint32_t num_entries; 199 uint32_t num_trackers; 200 uint32_t sq_tdbl_off; 201 uint32_t cq_hdbl_off; 202 203 uint32_t sq_head; 204 uint32_t sq_tail; 205 uint32_t cq_head; 206 207 int64_t num_cmds; 208 int64_t num_intr_handler_calls; 209 210 struct nvme_command *cmd; 211 struct nvme_completion *cpl; 212 213 bus_dma_tag_t dma_tag; 214 215 bus_dmamap_t cmd_dma_map; 216 uint64_t cmd_bus_addr; 217 218 bus_dmamap_t cpl_dma_map; 219 uint64_t cpl_bus_addr; 220 221 TAILQ_HEAD(, nvme_tracker) free_tr; 222 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 223 STAILQ_HEAD(, nvme_request) queued_req; 224 225 struct nvme_tracker **act_tr; 226 227 boolean_t is_enabled; 228 229 struct mtx lock __aligned(CACHE_LINE_SIZE); 230 231 } __aligned(CACHE_LINE_SIZE); 232 233 struct nvme_namespace { 234 235 struct nvme_controller *ctrlr; 236 struct nvme_namespace_data data; 237 uint16_t id; 238 uint16_t flags; 239 struct cdev *cdev; 240 void *cons_cookie[NVME_MAX_CONSUMERS]; 241 }; 242 243 /* 244 * One of these per allocated PCI device. 245 */ 246 struct nvme_controller { 247 248 device_t dev; 249 250 uint32_t ready_timeout_in_ms; 251 252 bus_space_tag_t bus_tag; 253 bus_space_handle_t bus_handle; 254 int resource_id; 255 struct resource *resource; 256 257 /* 258 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 259 * separate from the control registers which are in BAR 0/1. These 260 * members track the mapping of BAR 4/5 for that reason. 261 */ 262 int bar4_resource_id; 263 struct resource *bar4_resource; 264 265 #ifdef CHATHAM2 266 bus_space_tag_t chatham_bus_tag; 267 bus_space_handle_t chatham_bus_handle; 268 int chatham_resource_id; 269 struct resource *chatham_resource; 270 #endif 271 272 uint32_t msix_enabled; 273 uint32_t force_intx; 274 uint32_t enable_aborts; 275 276 uint32_t num_io_queues; 277 boolean_t per_cpu_io_queues; 278 279 /* Fields for tracking progress during controller initialization. */ 280 struct intr_config_hook config_hook; 281 uint32_t ns_identified; 282 uint32_t queues_created; 283 284 struct task reset_task; 285 struct task fail_req_task; 286 struct taskqueue *taskqueue; 287 288 /* For shared legacy interrupt. */ 289 int rid; 290 struct resource *res; 291 void *tag; 292 293 bus_dma_tag_t hw_desc_tag; 294 bus_dmamap_t hw_desc_map; 295 296 /** maximum i/o size in bytes */ 297 uint32_t max_xfer_size; 298 299 /** minimum page size supported by this controller in bytes */ 300 uint32_t min_page_size; 301 302 /** interrupt coalescing time period (in microseconds) */ 303 uint32_t int_coal_time; 304 305 /** interrupt coalescing threshold */ 306 uint32_t int_coal_threshold; 307 308 /** timeout period in seconds */ 309 uint32_t timeout_period; 310 311 struct nvme_qpair adminq; 312 struct nvme_qpair *ioq; 313 314 struct nvme_registers *regs; 315 316 struct nvme_controller_data cdata; 317 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 318 319 struct cdev *cdev; 320 321 uint32_t num_aers; 322 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 323 324 void *cons_cookie[NVME_MAX_CONSUMERS]; 325 326 uint32_t is_resetting; 327 328 struct mtx fail_req_lock; 329 boolean_t is_failed; 330 STAILQ_HEAD(, nvme_request) fail_req; 331 332 #ifdef CHATHAM2 333 uint64_t chatham_size; 334 uint64_t chatham_lbas; 335 #endif 336 }; 337 338 #define nvme_mmio_offsetof(reg) \ 339 offsetof(struct nvme_registers, reg) 340 341 #define nvme_mmio_read_4(sc, reg) \ 342 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 343 nvme_mmio_offsetof(reg)) 344 345 #define nvme_mmio_write_4(sc, reg, val) \ 346 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 347 nvme_mmio_offsetof(reg), val) 348 349 #define nvme_mmio_write_8(sc, reg, val) \ 350 do { \ 351 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 352 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 353 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 354 nvme_mmio_offsetof(reg)+4, \ 355 (val & 0xFFFFFFFF00000000UL) >> 32); \ 356 } while (0); 357 358 #ifdef CHATHAM2 359 #define chatham_read_4(softc, reg) \ 360 bus_space_read_4((softc)->chatham_bus_tag, \ 361 (softc)->chatham_bus_handle, reg) 362 363 #define chatham_write_8(sc, reg, val) \ 364 do { \ 365 bus_space_write_4((sc)->chatham_bus_tag, \ 366 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 367 bus_space_write_4((sc)->chatham_bus_tag, \ 368 (sc)->chatham_bus_handle, reg+4, \ 369 (val & 0xFFFFFFFF00000000UL) >> 32); \ 370 } while (0); 371 372 #endif /* CHATHAM2 */ 373 374 #if __FreeBSD_version < 800054 375 #define wmb() __asm volatile("sfence" ::: "memory") 376 #define mb() __asm volatile("mfence" ::: "memory") 377 #endif 378 379 #define nvme_printf(ctrlr, fmt, args...) \ 380 device_printf(ctrlr->dev, fmt, ##args) 381 382 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 383 384 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 385 void *payload, 386 nvme_cb_fn_t cb_fn, void *cb_arg); 387 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 388 uint16_t nsid, void *payload, 389 nvme_cb_fn_t cb_fn, void *cb_arg); 390 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 391 uint32_t microseconds, 392 uint32_t threshold, 393 nvme_cb_fn_t cb_fn, 394 void *cb_arg); 395 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 396 struct nvme_error_information_entry *payload, 397 uint32_t num_entries, /* 0 = max */ 398 nvme_cb_fn_t cb_fn, 399 void *cb_arg); 400 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 401 uint32_t nsid, 402 struct nvme_health_information_page *payload, 403 nvme_cb_fn_t cb_fn, 404 void *cb_arg); 405 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 406 struct nvme_firmware_page *payload, 407 nvme_cb_fn_t cb_fn, 408 void *cb_arg); 409 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 410 struct nvme_qpair *io_que, uint16_t vector, 411 nvme_cb_fn_t cb_fn, void *cb_arg); 412 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 413 struct nvme_qpair *io_que, 414 nvme_cb_fn_t cb_fn, void *cb_arg); 415 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 416 struct nvme_qpair *io_que, 417 nvme_cb_fn_t cb_fn, void *cb_arg); 418 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 419 struct nvme_qpair *io_que, 420 nvme_cb_fn_t cb_fn, void *cb_arg); 421 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 422 uint32_t num_queues, nvme_cb_fn_t cb_fn, 423 void *cb_arg); 424 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 425 union nvme_critical_warning_state state, 426 nvme_cb_fn_t cb_fn, void *cb_arg); 427 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 428 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 429 430 void nvme_payload_map(void *arg, bus_dma_segment_t *seg, int nseg, 431 int error); 432 void nvme_payload_map_uio(void *arg, bus_dma_segment_t *seg, int nseg, 433 bus_size_t mapsize, int error); 434 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 435 436 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 437 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 438 int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 439 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 440 /* ctrlr defined as void * to allow use with config_intrhook. */ 441 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 442 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 443 struct nvme_request *req); 444 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 445 struct nvme_request *req); 446 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 447 struct nvme_request *req); 448 449 void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 450 uint16_t vector, uint32_t num_entries, 451 uint32_t num_trackers, uint32_t max_xfer_size, 452 struct nvme_controller *ctrlr); 453 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 454 struct nvme_tracker *tr); 455 void nvme_qpair_process_completions(struct nvme_qpair *qpair); 456 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 457 struct nvme_request *req); 458 void nvme_qpair_reset(struct nvme_qpair *qpair); 459 void nvme_qpair_fail(struct nvme_qpair *qpair); 460 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 461 struct nvme_request *req, 462 uint32_t sct, uint32_t sc, 463 boolean_t print_on_error); 464 465 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 466 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 467 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 468 469 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 470 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 471 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 472 473 int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 474 struct nvme_controller *ctrlr); 475 void nvme_ns_destruct(struct nvme_namespace *ns); 476 477 int nvme_ns_physio(struct cdev *dev, struct uio *uio, int ioflag); 478 479 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 480 481 void nvme_dump_command(struct nvme_command *cmd); 482 void nvme_dump_completion(struct nvme_completion *cpl); 483 484 static __inline void 485 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 486 { 487 uint64_t *bus_addr = (uint64_t *)arg; 488 489 *bus_addr = seg[0].ds_addr; 490 } 491 492 static __inline struct nvme_request * 493 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 494 { 495 struct nvme_request *req; 496 497 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 498 if (req != NULL) { 499 req->cb_fn = cb_fn; 500 req->cb_arg = cb_arg; 501 req->timeout = TRUE; 502 } 503 return (req); 504 } 505 506 static __inline struct nvme_request * 507 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 508 nvme_cb_fn_t cb_fn, void *cb_arg) 509 { 510 struct nvme_request *req; 511 512 req = _nvme_allocate_request(cb_fn, cb_arg); 513 if (req != NULL) { 514 req->type = NVME_REQUEST_VADDR; 515 req->u.payload = payload; 516 req->payload_size = payload_size; 517 } 518 return (req); 519 } 520 521 static __inline struct nvme_request * 522 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 523 { 524 struct nvme_request *req; 525 526 req = _nvme_allocate_request(cb_fn, cb_arg); 527 if (req != NULL) 528 req->type = NVME_REQUEST_NULL; 529 return (req); 530 } 531 532 static __inline struct nvme_request * 533 nvme_allocate_request_uio(struct uio *uio, nvme_cb_fn_t cb_fn, void *cb_arg) 534 { 535 struct nvme_request *req; 536 537 req = _nvme_allocate_request(cb_fn, cb_arg); 538 if (req != NULL) { 539 req->type = NVME_REQUEST_UIO; 540 req->u.uio = uio; 541 } 542 return (req); 543 } 544 545 static __inline struct nvme_request * 546 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 547 { 548 struct nvme_request *req; 549 550 req = _nvme_allocate_request(cb_fn, cb_arg); 551 if (req != NULL) { 552 #ifdef NVME_UNMAPPED_BIO_SUPPORT 553 req->type = NVME_REQUEST_BIO; 554 req->u.bio = bio; 555 #else 556 req->type = NVME_REQUEST_VADDR; 557 req->u.payload = bio->bio_data; 558 req->payload_size = bio->bio_bcount; 559 #endif 560 } 561 return (req); 562 } 563 564 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 565 566 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 567 const struct nvme_completion *async_cpl, 568 uint32_t log_page_id, void *log_page_buffer, 569 uint32_t log_page_size); 570 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 571 572 #endif /* __NVME_PRIVATE_H__ */ 573