1 /*- 2 * Copyright (C) 2012-2013 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __NVME_PRIVATE_H__ 30 #define __NVME_PRIVATE_H__ 31 32 #include <sys/param.h> 33 #include <sys/bio.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 #include <sys/systm.h> 41 #include <sys/taskqueue.h> 42 43 #include <vm/uma.h> 44 45 #include <machine/bus.h> 46 47 #include "nvme.h" 48 49 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 50 51 MALLOC_DECLARE(M_NVME); 52 53 #define CHATHAM2 54 55 #ifdef CHATHAM2 56 #define CHATHAM_PCI_ID 0x20118086 57 #define CHATHAM_CONTROL_BAR 0 58 #endif 59 60 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 61 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 62 63 /* 64 * For commands requiring more than 2 PRP entries, one PRP will be 65 * embedded in the command (prp1), and the rest of the PRP entries 66 * will be in a list pointed to by the command (prp2). This means 67 * that real max number of PRP entries we support is 32+1, which 68 * results in a max xfer size of 32*PAGE_SIZE. 69 */ 70 #define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE) 71 72 #define NVME_ADMIN_TRACKERS (16) 73 #define NVME_ADMIN_ENTRIES (128) 74 /* min and max are defined in admin queue attributes section of spec */ 75 #define NVME_MIN_ADMIN_ENTRIES (2) 76 #define NVME_MAX_ADMIN_ENTRIES (4096) 77 78 /* 79 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 80 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 81 * will allow outstanding on an I/O qpair at any time. The only advantage in 82 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 83 * the contents of the submission and completion queues, it will show a longer 84 * history of data. 85 */ 86 #define NVME_IO_ENTRIES (256) 87 #define NVME_IO_TRACKERS (128) 88 #define NVME_MIN_IO_TRACKERS (4) 89 #define NVME_MAX_IO_TRACKERS (1024) 90 91 /* 92 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 93 * for each controller. 94 */ 95 96 #define NVME_INT_COAL_TIME (0) /* disabled */ 97 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 98 99 #define NVME_MAX_NAMESPACES (16) 100 #define NVME_MAX_CONSUMERS (2) 101 #define NVME_MAX_ASYNC_EVENTS (8) 102 103 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 104 #define NVME_MIN_TIMEOUT_PERIOD (5) 105 #define NVME_MAX_TIMEOUT_PERIOD (120) 106 107 #define NVME_DEFAULT_RETRY_COUNT (4) 108 109 /* Maximum log page size to fetch for AERs. */ 110 #define NVME_MAX_AER_LOG_SIZE (4096) 111 112 /* 113 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 114 * it. 115 */ 116 #ifndef CACHE_LINE_SIZE 117 #define CACHE_LINE_SIZE (64) 118 #endif 119 120 /* 121 * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O 122 * support and the bus_dmamap_load_bio API are available on the target 123 * kernel. This will ease porting back to earlier stable branches at a 124 * later point. 125 */ 126 #ifdef BIO_UNMAPPED 127 #define NVME_UNMAPPED_BIO_SUPPORT 128 #endif 129 130 extern uma_zone_t nvme_request_zone; 131 extern int32_t nvme_retry_count; 132 133 struct nvme_completion_poll_status { 134 135 struct nvme_completion cpl; 136 boolean_t done; 137 }; 138 139 #define NVME_REQUEST_VADDR 1 140 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 141 #define NVME_REQUEST_UIO 3 142 #ifdef NVME_UNMAPPED_BIO_SUPPORT 143 #define NVME_REQUEST_BIO 4 144 #endif 145 146 struct nvme_request { 147 148 struct nvme_command cmd; 149 struct nvme_qpair *qpair; 150 union { 151 void *payload; 152 struct bio *bio; 153 } u; 154 uint32_t type; 155 uint32_t payload_size; 156 boolean_t timeout; 157 nvme_cb_fn_t cb_fn; 158 void *cb_arg; 159 int32_t retries; 160 STAILQ_ENTRY(nvme_request) stailq; 161 }; 162 163 struct nvme_async_event_request { 164 165 struct nvme_controller *ctrlr; 166 struct nvme_request *req; 167 struct nvme_completion cpl; 168 uint32_t log_page_id; 169 uint32_t log_page_size; 170 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 171 }; 172 173 struct nvme_tracker { 174 175 TAILQ_ENTRY(nvme_tracker) tailq; 176 struct nvme_request *req; 177 struct nvme_qpair *qpair; 178 struct callout timer; 179 bus_dmamap_t payload_dma_map; 180 uint16_t cid; 181 182 uint64_t prp[NVME_MAX_PRP_LIST_ENTRIES]; 183 bus_addr_t prp_bus_addr; 184 bus_dmamap_t prp_dma_map; 185 }; 186 187 struct nvme_qpair { 188 189 struct nvme_controller *ctrlr; 190 uint32_t id; 191 uint32_t phase; 192 193 uint16_t vector; 194 int rid; 195 struct resource *res; 196 void *tag; 197 198 uint32_t num_entries; 199 uint32_t num_trackers; 200 uint32_t sq_tdbl_off; 201 uint32_t cq_hdbl_off; 202 203 uint32_t sq_head; 204 uint32_t sq_tail; 205 uint32_t cq_head; 206 207 int64_t num_cmds; 208 int64_t num_intr_handler_calls; 209 210 struct nvme_command *cmd; 211 struct nvme_completion *cpl; 212 213 bus_dma_tag_t dma_tag; 214 215 bus_dmamap_t cmd_dma_map; 216 uint64_t cmd_bus_addr; 217 218 bus_dmamap_t cpl_dma_map; 219 uint64_t cpl_bus_addr; 220 221 TAILQ_HEAD(, nvme_tracker) free_tr; 222 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 223 STAILQ_HEAD(, nvme_request) queued_req; 224 225 struct nvme_tracker **act_tr; 226 227 boolean_t is_enabled; 228 229 struct mtx lock __aligned(CACHE_LINE_SIZE); 230 231 } __aligned(CACHE_LINE_SIZE); 232 233 struct nvme_namespace { 234 235 struct nvme_controller *ctrlr; 236 struct nvme_namespace_data data; 237 uint16_t id; 238 uint16_t flags; 239 struct cdev *cdev; 240 void *cons_cookie[NVME_MAX_CONSUMERS]; 241 struct mtx lock; 242 }; 243 244 /* 245 * One of these per allocated PCI device. 246 */ 247 struct nvme_controller { 248 249 device_t dev; 250 251 struct mtx lock; 252 253 uint32_t ready_timeout_in_ms; 254 255 bus_space_tag_t bus_tag; 256 bus_space_handle_t bus_handle; 257 int resource_id; 258 struct resource *resource; 259 260 /* 261 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 262 * separate from the control registers which are in BAR 0/1. These 263 * members track the mapping of BAR 4/5 for that reason. 264 */ 265 int bar4_resource_id; 266 struct resource *bar4_resource; 267 268 #ifdef CHATHAM2 269 bus_space_tag_t chatham_bus_tag; 270 bus_space_handle_t chatham_bus_handle; 271 int chatham_resource_id; 272 struct resource *chatham_resource; 273 #endif 274 275 uint32_t msix_enabled; 276 uint32_t force_intx; 277 uint32_t enable_aborts; 278 279 uint32_t num_io_queues; 280 boolean_t per_cpu_io_queues; 281 282 /* Fields for tracking progress during controller initialization. */ 283 struct intr_config_hook config_hook; 284 uint32_t ns_identified; 285 uint32_t queues_created; 286 287 struct task reset_task; 288 struct task fail_req_task; 289 struct taskqueue *taskqueue; 290 291 /* For shared legacy interrupt. */ 292 int rid; 293 struct resource *res; 294 void *tag; 295 296 bus_dma_tag_t hw_desc_tag; 297 bus_dmamap_t hw_desc_map; 298 299 /** maximum i/o size in bytes */ 300 uint32_t max_xfer_size; 301 302 /** minimum page size supported by this controller in bytes */ 303 uint32_t min_page_size; 304 305 /** interrupt coalescing time period (in microseconds) */ 306 uint32_t int_coal_time; 307 308 /** interrupt coalescing threshold */ 309 uint32_t int_coal_threshold; 310 311 /** timeout period in seconds */ 312 uint32_t timeout_period; 313 314 struct nvme_qpair adminq; 315 struct nvme_qpair *ioq; 316 317 struct nvme_registers *regs; 318 319 struct nvme_controller_data cdata; 320 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 321 322 struct cdev *cdev; 323 324 uint32_t num_aers; 325 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 326 327 void *cons_cookie[NVME_MAX_CONSUMERS]; 328 329 uint32_t is_resetting; 330 331 boolean_t is_failed; 332 STAILQ_HEAD(, nvme_request) fail_req; 333 334 #ifdef CHATHAM2 335 uint64_t chatham_size; 336 uint64_t chatham_lbas; 337 #endif 338 }; 339 340 #define nvme_mmio_offsetof(reg) \ 341 offsetof(struct nvme_registers, reg) 342 343 #define nvme_mmio_read_4(sc, reg) \ 344 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 345 nvme_mmio_offsetof(reg)) 346 347 #define nvme_mmio_write_4(sc, reg, val) \ 348 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 349 nvme_mmio_offsetof(reg), val) 350 351 #define nvme_mmio_write_8(sc, reg, val) \ 352 do { \ 353 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 354 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 355 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 356 nvme_mmio_offsetof(reg)+4, \ 357 (val & 0xFFFFFFFF00000000UL) >> 32); \ 358 } while (0); 359 360 #ifdef CHATHAM2 361 #define chatham_read_4(softc, reg) \ 362 bus_space_read_4((softc)->chatham_bus_tag, \ 363 (softc)->chatham_bus_handle, reg) 364 365 #define chatham_write_8(sc, reg, val) \ 366 do { \ 367 bus_space_write_4((sc)->chatham_bus_tag, \ 368 (sc)->chatham_bus_handle, reg, val & 0xffffffff); \ 369 bus_space_write_4((sc)->chatham_bus_tag, \ 370 (sc)->chatham_bus_handle, reg+4, \ 371 (val & 0xFFFFFFFF00000000UL) >> 32); \ 372 } while (0); 373 374 #endif /* CHATHAM2 */ 375 376 #if __FreeBSD_version < 800054 377 #define wmb() __asm volatile("sfence" ::: "memory") 378 #define mb() __asm volatile("mfence" ::: "memory") 379 #endif 380 381 #define nvme_printf(ctrlr, fmt, args...) \ 382 device_printf(ctrlr->dev, fmt, ##args) 383 384 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 385 386 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 387 void *payload, 388 nvme_cb_fn_t cb_fn, void *cb_arg); 389 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 390 uint16_t nsid, void *payload, 391 nvme_cb_fn_t cb_fn, void *cb_arg); 392 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 393 uint32_t microseconds, 394 uint32_t threshold, 395 nvme_cb_fn_t cb_fn, 396 void *cb_arg); 397 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 398 struct nvme_error_information_entry *payload, 399 uint32_t num_entries, /* 0 = max */ 400 nvme_cb_fn_t cb_fn, 401 void *cb_arg); 402 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 403 uint32_t nsid, 404 struct nvme_health_information_page *payload, 405 nvme_cb_fn_t cb_fn, 406 void *cb_arg); 407 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 408 struct nvme_firmware_page *payload, 409 nvme_cb_fn_t cb_fn, 410 void *cb_arg); 411 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 412 struct nvme_qpair *io_que, uint16_t vector, 413 nvme_cb_fn_t cb_fn, void *cb_arg); 414 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 415 struct nvme_qpair *io_que, 416 nvme_cb_fn_t cb_fn, void *cb_arg); 417 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 418 struct nvme_qpair *io_que, 419 nvme_cb_fn_t cb_fn, void *cb_arg); 420 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 421 struct nvme_qpair *io_que, 422 nvme_cb_fn_t cb_fn, void *cb_arg); 423 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 424 uint32_t num_queues, nvme_cb_fn_t cb_fn, 425 void *cb_arg); 426 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 427 union nvme_critical_warning_state state, 428 nvme_cb_fn_t cb_fn, void *cb_arg); 429 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 430 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 431 432 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 433 434 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 435 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 436 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 437 int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 438 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 439 /* ctrlr defined as void * to allow use with config_intrhook. */ 440 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 441 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 442 struct nvme_request *req); 443 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 444 struct nvme_request *req); 445 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 446 struct nvme_request *req); 447 448 void nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 449 uint16_t vector, uint32_t num_entries, 450 uint32_t num_trackers, 451 struct nvme_controller *ctrlr); 452 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 453 struct nvme_tracker *tr); 454 void nvme_qpair_process_completions(struct nvme_qpair *qpair); 455 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 456 struct nvme_request *req); 457 void nvme_qpair_reset(struct nvme_qpair *qpair); 458 void nvme_qpair_fail(struct nvme_qpair *qpair); 459 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 460 struct nvme_request *req, 461 uint32_t sct, uint32_t sc, 462 boolean_t print_on_error); 463 464 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 465 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 466 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 467 468 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 469 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 470 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 471 472 int nvme_ns_construct(struct nvme_namespace *ns, uint16_t id, 473 struct nvme_controller *ctrlr); 474 void nvme_ns_destruct(struct nvme_namespace *ns); 475 476 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 477 478 void nvme_dump_command(struct nvme_command *cmd); 479 void nvme_dump_completion(struct nvme_completion *cpl); 480 481 static __inline void 482 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 483 { 484 uint64_t *bus_addr = (uint64_t *)arg; 485 486 *bus_addr = seg[0].ds_addr; 487 } 488 489 static __inline struct nvme_request * 490 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 491 { 492 struct nvme_request *req; 493 494 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 495 if (req != NULL) { 496 req->cb_fn = cb_fn; 497 req->cb_arg = cb_arg; 498 req->timeout = TRUE; 499 } 500 return (req); 501 } 502 503 static __inline struct nvme_request * 504 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 505 nvme_cb_fn_t cb_fn, void *cb_arg) 506 { 507 struct nvme_request *req; 508 509 req = _nvme_allocate_request(cb_fn, cb_arg); 510 if (req != NULL) { 511 req->type = NVME_REQUEST_VADDR; 512 req->u.payload = payload; 513 req->payload_size = payload_size; 514 } 515 return (req); 516 } 517 518 static __inline struct nvme_request * 519 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 520 { 521 struct nvme_request *req; 522 523 req = _nvme_allocate_request(cb_fn, cb_arg); 524 if (req != NULL) 525 req->type = NVME_REQUEST_NULL; 526 return (req); 527 } 528 529 static __inline struct nvme_request * 530 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 531 { 532 struct nvme_request *req; 533 534 req = _nvme_allocate_request(cb_fn, cb_arg); 535 if (req != NULL) { 536 #ifdef NVME_UNMAPPED_BIO_SUPPORT 537 req->type = NVME_REQUEST_BIO; 538 req->u.bio = bio; 539 #else 540 req->type = NVME_REQUEST_VADDR; 541 req->u.payload = bio->bio_data; 542 req->payload_size = bio->bio_bcount; 543 #endif 544 } 545 return (req); 546 } 547 548 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 549 550 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 551 const struct nvme_completion *async_cpl, 552 uint32_t log_page_id, void *log_page_buffer, 553 uint32_t log_page_size); 554 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 555 556 #endif /* __NVME_PRIVATE_H__ */ 557