1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __NVME_PRIVATE_H__ 30 #define __NVME_PRIVATE_H__ 31 32 #include <sys/param.h> 33 #include <sys/bio.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/memdesc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/systm.h> 43 #include <sys/taskqueue.h> 44 45 #include <vm/uma.h> 46 47 #include <machine/bus.h> 48 49 #include "nvme.h" 50 51 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 52 53 MALLOC_DECLARE(M_NVME); 54 55 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 56 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 57 58 #define NVME_ADMIN_TRACKERS (16) 59 #define NVME_ADMIN_ENTRIES (128) 60 /* min and max are defined in admin queue attributes section of spec */ 61 #define NVME_MIN_ADMIN_ENTRIES (2) 62 #define NVME_MAX_ADMIN_ENTRIES (4096) 63 64 /* 65 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 66 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 67 * will allow outstanding on an I/O qpair at any time. The only advantage in 68 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 69 * the contents of the submission and completion queues, it will show a longer 70 * history of data. 71 */ 72 #define NVME_IO_ENTRIES (256) 73 #define NVME_IO_TRACKERS (128) 74 #define NVME_MIN_IO_TRACKERS (4) 75 #define NVME_MAX_IO_TRACKERS (1024) 76 77 /* 78 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 79 * for each controller. 80 */ 81 82 #define NVME_INT_COAL_TIME (0) /* disabled */ 83 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 84 85 #define NVME_MAX_NAMESPACES (16) 86 #define NVME_MAX_CONSUMERS (2) 87 #define NVME_MAX_ASYNC_EVENTS (8) 88 89 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 90 #define NVME_MIN_TIMEOUT_PERIOD (5) 91 #define NVME_MAX_TIMEOUT_PERIOD (120) 92 93 #define NVME_DEFAULT_RETRY_COUNT (4) 94 95 /* Maximum log page size to fetch for AERs. */ 96 #define NVME_MAX_AER_LOG_SIZE (4096) 97 98 /* 99 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 100 * it. 101 */ 102 #ifndef CACHE_LINE_SIZE 103 #define CACHE_LINE_SIZE (64) 104 #endif 105 106 #define NVME_GONE 0xfffffffful 107 108 extern int32_t nvme_retry_count; 109 extern bool nvme_verbose_cmd_dump; 110 111 struct nvme_completion_poll_status { 112 struct nvme_completion cpl; 113 int done; 114 }; 115 116 struct nvme_request { 117 struct nvme_command cmd; 118 struct nvme_qpair *qpair; 119 struct memdesc payload; 120 nvme_cb_fn_t cb_fn; 121 void *cb_arg; 122 int32_t retries; 123 bool payload_valid; 124 bool timeout; 125 bool spare[2]; /* Future use */ 126 STAILQ_ENTRY(nvme_request) stailq; 127 }; 128 129 struct nvme_async_event_request { 130 struct nvme_controller *ctrlr; 131 struct nvme_request *req; 132 struct nvme_completion cpl; 133 uint32_t log_page_id; 134 uint32_t log_page_size; 135 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 136 }; 137 138 struct nvme_tracker { 139 TAILQ_ENTRY(nvme_tracker) tailq; 140 struct nvme_request *req; 141 struct nvme_qpair *qpair; 142 sbintime_t deadline; 143 bus_dmamap_t payload_dma_map; 144 uint16_t cid; 145 146 uint64_t *prp; 147 bus_addr_t prp_bus_addr; 148 }; 149 150 enum nvme_recovery { 151 RECOVERY_NONE = 0, /* Normal operations */ 152 RECOVERY_START, /* Deadline has passed, start recovering */ 153 RECOVERY_RESET, /* This pass, initiate reset of controller */ 154 RECOVERY_WAITING, /* waiting for the reset to complete */ 155 }; 156 struct nvme_qpair { 157 struct nvme_controller *ctrlr; 158 uint32_t id; 159 int domain; 160 int cpu; 161 162 uint16_t vector; 163 int rid; 164 struct resource *res; 165 void *tag; 166 167 struct callout timer; 168 sbintime_t deadline; 169 bool timer_armed; 170 enum nvme_recovery recovery_state; 171 172 uint32_t num_entries; 173 uint32_t num_trackers; 174 uint32_t sq_tdbl_off; 175 uint32_t cq_hdbl_off; 176 177 uint32_t phase; 178 uint32_t sq_head; 179 uint32_t sq_tail; 180 uint32_t cq_head; 181 182 int64_t num_cmds; 183 int64_t num_intr_handler_calls; 184 int64_t num_retries; 185 int64_t num_failures; 186 int64_t num_ignored; 187 188 struct nvme_command *cmd; 189 struct nvme_completion *cpl; 190 191 bus_dma_tag_t dma_tag; 192 bus_dma_tag_t dma_tag_payload; 193 194 bus_dmamap_t queuemem_map; 195 uint64_t cmd_bus_addr; 196 uint64_t cpl_bus_addr; 197 198 TAILQ_HEAD(, nvme_tracker) free_tr; 199 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 200 STAILQ_HEAD(, nvme_request) queued_req; 201 202 struct nvme_tracker **act_tr; 203 204 struct mtx_padalign lock; 205 206 } __aligned(CACHE_LINE_SIZE); 207 208 struct nvme_namespace { 209 struct nvme_controller *ctrlr; 210 struct nvme_namespace_data data; 211 uint32_t id; 212 uint32_t flags; 213 struct cdev *cdev; 214 void *cons_cookie[NVME_MAX_CONSUMERS]; 215 uint32_t boundary; 216 struct mtx lock; 217 }; 218 219 /* 220 * One of these per allocated PCI device. 221 */ 222 struct nvme_controller { 223 device_t dev; 224 225 struct mtx lock; 226 int domain; 227 uint32_t ready_timeout_in_ms; 228 uint32_t quirks; 229 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 230 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 231 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */ 232 #define QUIRK_AHCI 8 /* Attached via AHCI redirect */ 233 234 bus_space_tag_t bus_tag; 235 bus_space_handle_t bus_handle; 236 int resource_id; 237 struct resource *resource; 238 239 /* 240 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 241 * separate from the control registers which are in BAR 0/1. These 242 * members track the mapping of BAR 4/5 for that reason. 243 */ 244 int bar4_resource_id; 245 struct resource *bar4_resource; 246 247 int msi_count; 248 uint32_t enable_aborts; 249 250 uint32_t num_io_queues; 251 uint32_t max_hw_pend_io; 252 253 /* Fields for tracking progress during controller initialization. */ 254 struct intr_config_hook config_hook; 255 uint32_t ns_identified; 256 uint32_t queues_created; 257 258 struct task reset_task; 259 struct task fail_req_task; 260 struct taskqueue *taskqueue; 261 262 /* For shared legacy interrupt. */ 263 int rid; 264 struct resource *res; 265 void *tag; 266 267 /** maximum i/o size in bytes */ 268 uint32_t max_xfer_size; 269 270 /** LO and HI capacity mask */ 271 uint32_t cap_lo; 272 uint32_t cap_hi; 273 274 /** Page size and log2(page_size) - 12 that we're currently using */ 275 uint32_t page_size; 276 uint32_t mps; 277 278 /** interrupt coalescing time period (in microseconds) */ 279 uint32_t int_coal_time; 280 281 /** interrupt coalescing threshold */ 282 uint32_t int_coal_threshold; 283 284 /** timeout period in seconds */ 285 uint32_t timeout_period; 286 287 /** doorbell stride */ 288 uint32_t dstrd; 289 290 struct nvme_qpair adminq; 291 struct nvme_qpair *ioq; 292 293 struct nvme_registers *regs; 294 295 struct nvme_controller_data cdata; 296 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 297 298 struct cdev *cdev; 299 300 /** bit mask of event types currently enabled for async events */ 301 uint32_t async_event_config; 302 303 uint32_t num_aers; 304 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 305 306 void *cons_cookie[NVME_MAX_CONSUMERS]; 307 308 uint32_t is_resetting; 309 uint32_t is_initialized; 310 uint32_t notification_sent; 311 312 bool is_failed; 313 bool is_dying; 314 STAILQ_HEAD(, nvme_request) fail_req; 315 316 /* Host Memory Buffer */ 317 int hmb_nchunks; 318 size_t hmb_chunk; 319 bus_dma_tag_t hmb_tag; 320 struct nvme_hmb_chunk { 321 bus_dmamap_t hmbc_map; 322 void *hmbc_vaddr; 323 uint64_t hmbc_paddr; 324 } *hmb_chunks; 325 bus_dma_tag_t hmb_desc_tag; 326 bus_dmamap_t hmb_desc_map; 327 struct nvme_hmb_desc *hmb_desc_vaddr; 328 uint64_t hmb_desc_paddr; 329 }; 330 331 #define nvme_mmio_offsetof(reg) \ 332 offsetof(struct nvme_registers, reg) 333 334 #define nvme_mmio_read_4(sc, reg) \ 335 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 336 nvme_mmio_offsetof(reg)) 337 338 #define nvme_mmio_write_4(sc, reg, val) \ 339 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 340 nvme_mmio_offsetof(reg), val) 341 342 #define nvme_mmio_write_8(sc, reg, val) \ 343 do { \ 344 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 345 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 346 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 347 nvme_mmio_offsetof(reg)+4, \ 348 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 349 } while (0); 350 351 #define nvme_printf(ctrlr, fmt, args...) \ 352 device_printf(ctrlr->dev, fmt, ##args) 353 354 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 355 356 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 357 void *payload, 358 nvme_cb_fn_t cb_fn, void *cb_arg); 359 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 360 uint32_t nsid, void *payload, 361 nvme_cb_fn_t cb_fn, void *cb_arg); 362 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 363 uint32_t microseconds, 364 uint32_t threshold, 365 nvme_cb_fn_t cb_fn, 366 void *cb_arg); 367 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 368 struct nvme_error_information_entry *payload, 369 uint32_t num_entries, /* 0 = max */ 370 nvme_cb_fn_t cb_fn, 371 void *cb_arg); 372 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 373 uint32_t nsid, 374 struct nvme_health_information_page *payload, 375 nvme_cb_fn_t cb_fn, 376 void *cb_arg); 377 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 378 struct nvme_firmware_page *payload, 379 nvme_cb_fn_t cb_fn, 380 void *cb_arg); 381 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 382 struct nvme_qpair *io_que, 383 nvme_cb_fn_t cb_fn, void *cb_arg); 384 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 385 struct nvme_qpair *io_que, 386 nvme_cb_fn_t cb_fn, void *cb_arg); 387 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 388 struct nvme_qpair *io_que, 389 nvme_cb_fn_t cb_fn, void *cb_arg); 390 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 391 struct nvme_qpair *io_que, 392 nvme_cb_fn_t cb_fn, void *cb_arg); 393 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 394 uint32_t num_queues, nvme_cb_fn_t cb_fn, 395 void *cb_arg); 396 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 397 uint32_t state, 398 nvme_cb_fn_t cb_fn, void *cb_arg); 399 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 400 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 401 402 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 403 404 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 405 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 406 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 407 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 408 /* ctrlr defined as void * to allow use with config_intrhook. */ 409 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 410 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 411 struct nvme_request *req); 412 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 413 struct nvme_request *req); 414 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 415 struct nvme_request *req); 416 417 int nvme_qpair_construct(struct nvme_qpair *qpair, 418 uint32_t num_entries, uint32_t num_trackers, 419 struct nvme_controller *ctrlr); 420 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 421 struct nvme_tracker *tr); 422 bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 423 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 424 struct nvme_request *req); 425 void nvme_qpair_reset(struct nvme_qpair *qpair); 426 void nvme_qpair_fail(struct nvme_qpair *qpair); 427 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 428 struct nvme_request *req, 429 uint32_t sct, uint32_t sc); 430 431 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 432 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 433 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 434 435 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 436 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 437 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 438 439 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 440 struct nvme_controller *ctrlr); 441 void nvme_ns_destruct(struct nvme_namespace *ns); 442 443 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 444 445 void nvme_qpair_print_command(struct nvme_qpair *qpair, 446 struct nvme_command *cmd); 447 void nvme_qpair_print_completion(struct nvme_qpair *qpair, 448 struct nvme_completion *cpl); 449 450 int nvme_attach(device_t dev); 451 int nvme_shutdown(device_t dev); 452 int nvme_detach(device_t dev); 453 454 /* 455 * Wait for a command to complete using the nvme_completion_poll_cb. Used in 456 * limited contexts where the caller knows it's OK to block briefly while the 457 * command runs. The ISR will run the callback which will set status->done to 458 * true, usually within microseconds. If not, then after one second timeout 459 * handler should reset the controller and abort all outstanding requests 460 * including this polled one. If still not after ten seconds, then something is 461 * wrong with the driver, and panic is the only way to recover. 462 * 463 * Most commands using this interface aren't actual I/O to the drive's media so 464 * complete within a few microseconds. Adaptively spin for one tick to catch the 465 * vast majority of these without waiting for a tick plus scheduling delays. Since 466 * these are on startup, this drastically reduces startup time. 467 */ 468 static __inline 469 void 470 nvme_completion_poll(struct nvme_completion_poll_status *status) 471 { 472 int timeout = ticks + 10 * hz; 473 sbintime_t delta_t = SBT_1US; 474 475 while (!atomic_load_acq_int(&status->done)) { 476 if (timeout - ticks < 0) 477 panic("NVME polled command failed to complete within 10s."); 478 pause_sbt("nvme", delta_t, 0, C_PREL(1)); 479 delta_t = min(SBT_1MS, delta_t * 3 / 2); 480 } 481 } 482 483 static __inline void 484 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 485 { 486 uint64_t *bus_addr = (uint64_t *)arg; 487 488 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg)); 489 if (error != 0) 490 printf("nvme_single_map err %d\n", error); 491 *bus_addr = seg[0].ds_addr; 492 } 493 494 static __inline struct nvme_request * 495 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 496 { 497 struct nvme_request *req; 498 499 req = malloc(sizeof(*req), M_NVME, M_NOWAIT | M_ZERO); 500 if (req != NULL) { 501 req->cb_fn = cb_fn; 502 req->cb_arg = cb_arg; 503 req->timeout = true; 504 } 505 return (req); 506 } 507 508 static __inline struct nvme_request * 509 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 510 nvme_cb_fn_t cb_fn, void *cb_arg) 511 { 512 struct nvme_request *req; 513 514 req = _nvme_allocate_request(cb_fn, cb_arg); 515 if (req != NULL) { 516 req->payload = memdesc_vaddr(payload, payload_size); 517 req->payload_valid = true; 518 } 519 return (req); 520 } 521 522 static __inline struct nvme_request * 523 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 524 { 525 struct nvme_request *req; 526 527 req = _nvme_allocate_request(cb_fn, cb_arg); 528 return (req); 529 } 530 531 static __inline struct nvme_request * 532 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 533 { 534 struct nvme_request *req; 535 536 req = _nvme_allocate_request(cb_fn, cb_arg); 537 if (req != NULL) { 538 req->payload = memdesc_bio(bio); 539 req->payload_valid = true; 540 } 541 return (req); 542 } 543 544 static __inline struct nvme_request * 545 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 546 { 547 struct nvme_request *req; 548 549 req = _nvme_allocate_request(cb_fn, cb_arg); 550 if (req != NULL) { 551 req->payload = memdesc_ccb(ccb); 552 req->payload_valid = true; 553 } 554 555 return (req); 556 } 557 558 #define nvme_free_request(req) free(req, M_NVME) 559 560 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 561 const struct nvme_completion *async_cpl, 562 uint32_t log_page_id, void *log_page_buffer, 563 uint32_t log_page_size); 564 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 565 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 566 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 567 568 void nvme_ctrlr_shared_handler(void *arg); 569 void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 570 571 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr); 572 int nvme_ctrlr_resume(struct nvme_controller *ctrlr); 573 574 #endif /* __NVME_PRIVATE_H__ */ 575