1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_PRIVATE_H__ 32 #define __NVME_PRIVATE_H__ 33 34 #include <sys/param.h> 35 #include <sys/bio.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/memdesc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/rman.h> 44 #include <sys/systm.h> 45 #include <sys/taskqueue.h> 46 47 #include <vm/uma.h> 48 49 #include <machine/bus.h> 50 51 #include "nvme.h" 52 53 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 54 55 MALLOC_DECLARE(M_NVME); 56 57 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 58 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 59 60 #define NVME_ADMIN_TRACKERS (16) 61 #define NVME_ADMIN_ENTRIES (128) 62 /* min and max are defined in admin queue attributes section of spec */ 63 #define NVME_MIN_ADMIN_ENTRIES (2) 64 #define NVME_MAX_ADMIN_ENTRIES (4096) 65 66 /* 67 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 68 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 69 * will allow outstanding on an I/O qpair at any time. The only advantage in 70 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 71 * the contents of the submission and completion queues, it will show a longer 72 * history of data. 73 */ 74 #define NVME_IO_ENTRIES (256) 75 #define NVME_IO_TRACKERS (128) 76 #define NVME_MIN_IO_TRACKERS (4) 77 #define NVME_MAX_IO_TRACKERS (1024) 78 79 /* 80 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 81 * for each controller. 82 */ 83 84 #define NVME_INT_COAL_TIME (0) /* disabled */ 85 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 86 87 #define NVME_MAX_NAMESPACES (16) 88 #define NVME_MAX_CONSUMERS (2) 89 #define NVME_MAX_ASYNC_EVENTS (8) 90 91 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 92 #define NVME_MIN_TIMEOUT_PERIOD (5) 93 #define NVME_MAX_TIMEOUT_PERIOD (120) 94 95 #define NVME_DEFAULT_RETRY_COUNT (4) 96 97 /* Maximum log page size to fetch for AERs. */ 98 #define NVME_MAX_AER_LOG_SIZE (4096) 99 100 /* 101 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 102 * it. 103 */ 104 #ifndef CACHE_LINE_SIZE 105 #define CACHE_LINE_SIZE (64) 106 #endif 107 108 #define NVME_GONE 0xfffffffful 109 110 extern int32_t nvme_retry_count; 111 extern bool nvme_verbose_cmd_dump; 112 113 struct nvme_completion_poll_status { 114 struct nvme_completion cpl; 115 int done; 116 }; 117 118 struct nvme_request { 119 struct nvme_command cmd; 120 struct nvme_qpair *qpair; 121 struct memdesc payload; 122 bool payload_valid; 123 bool timeout; 124 nvme_cb_fn_t cb_fn; 125 void *cb_arg; 126 int32_t retries; 127 STAILQ_ENTRY(nvme_request) stailq; 128 }; 129 130 struct nvme_async_event_request { 131 struct nvme_controller *ctrlr; 132 struct nvme_request *req; 133 struct nvme_completion cpl; 134 uint32_t log_page_id; 135 uint32_t log_page_size; 136 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 137 }; 138 139 struct nvme_tracker { 140 TAILQ_ENTRY(nvme_tracker) tailq; 141 struct nvme_request *req; 142 struct nvme_qpair *qpair; 143 sbintime_t deadline; 144 bus_dmamap_t payload_dma_map; 145 uint16_t cid; 146 147 uint64_t *prp; 148 bus_addr_t prp_bus_addr; 149 }; 150 151 enum nvme_recovery { 152 RECOVERY_NONE = 0, /* Normal operations */ 153 RECOVERY_START, /* Deadline has passed, start recovering */ 154 RECOVERY_RESET, /* This pass, initiate reset of controller */ 155 RECOVERY_WAITING, /* waiting for the reset to complete */ 156 }; 157 struct nvme_qpair { 158 struct nvme_controller *ctrlr; 159 uint32_t id; 160 int domain; 161 int cpu; 162 163 uint16_t vector; 164 int rid; 165 struct resource *res; 166 void *tag; 167 168 struct callout timer; 169 sbintime_t deadline; 170 bool timer_armed; 171 enum nvme_recovery recovery_state; 172 173 uint32_t num_entries; 174 uint32_t num_trackers; 175 uint32_t sq_tdbl_off; 176 uint32_t cq_hdbl_off; 177 178 uint32_t phase; 179 uint32_t sq_head; 180 uint32_t sq_tail; 181 uint32_t cq_head; 182 183 int64_t num_cmds; 184 int64_t num_intr_handler_calls; 185 int64_t num_retries; 186 int64_t num_failures; 187 int64_t num_ignored; 188 189 struct nvme_command *cmd; 190 struct nvme_completion *cpl; 191 192 bus_dma_tag_t dma_tag; 193 bus_dma_tag_t dma_tag_payload; 194 195 bus_dmamap_t queuemem_map; 196 uint64_t cmd_bus_addr; 197 uint64_t cpl_bus_addr; 198 199 TAILQ_HEAD(, nvme_tracker) free_tr; 200 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 201 STAILQ_HEAD(, nvme_request) queued_req; 202 203 struct nvme_tracker **act_tr; 204 205 struct mtx lock __aligned(CACHE_LINE_SIZE); 206 207 } __aligned(CACHE_LINE_SIZE); 208 209 struct nvme_namespace { 210 struct nvme_controller *ctrlr; 211 struct nvme_namespace_data data; 212 uint32_t id; 213 uint32_t flags; 214 struct cdev *cdev; 215 void *cons_cookie[NVME_MAX_CONSUMERS]; 216 uint32_t boundary; 217 struct mtx lock; 218 }; 219 220 /* 221 * One of these per allocated PCI device. 222 */ 223 struct nvme_controller { 224 device_t dev; 225 226 struct mtx lock; 227 int domain; 228 uint32_t ready_timeout_in_ms; 229 uint32_t quirks; 230 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 231 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 232 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */ 233 #define QUIRK_AHCI 8 /* Attached via AHCI redirect */ 234 235 bus_space_tag_t bus_tag; 236 bus_space_handle_t bus_handle; 237 int resource_id; 238 struct resource *resource; 239 240 /* 241 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 242 * separate from the control registers which are in BAR 0/1. These 243 * members track the mapping of BAR 4/5 for that reason. 244 */ 245 int bar4_resource_id; 246 struct resource *bar4_resource; 247 248 int msi_count; 249 uint32_t enable_aborts; 250 251 uint32_t num_io_queues; 252 uint32_t max_hw_pend_io; 253 254 /* Fields for tracking progress during controller initialization. */ 255 struct intr_config_hook config_hook; 256 uint32_t ns_identified; 257 uint32_t queues_created; 258 259 struct task reset_task; 260 struct task fail_req_task; 261 struct taskqueue *taskqueue; 262 263 /* For shared legacy interrupt. */ 264 int rid; 265 struct resource *res; 266 void *tag; 267 268 /** maximum i/o size in bytes */ 269 uint32_t max_xfer_size; 270 271 /** LO and HI capacity mask */ 272 uint32_t cap_lo; 273 uint32_t cap_hi; 274 275 /** Page size and log2(page_size) - 12 that we're currently using */ 276 uint32_t page_size; 277 uint32_t mps; 278 279 /** interrupt coalescing time period (in microseconds) */ 280 uint32_t int_coal_time; 281 282 /** interrupt coalescing threshold */ 283 uint32_t int_coal_threshold; 284 285 /** timeout period in seconds */ 286 uint32_t timeout_period; 287 288 /** doorbell stride */ 289 uint32_t dstrd; 290 291 struct nvme_qpair adminq; 292 struct nvme_qpair *ioq; 293 294 struct nvme_registers *regs; 295 296 struct nvme_controller_data cdata; 297 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 298 299 struct cdev *cdev; 300 301 /** bit mask of event types currently enabled for async events */ 302 uint32_t async_event_config; 303 304 uint32_t num_aers; 305 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 306 307 void *cons_cookie[NVME_MAX_CONSUMERS]; 308 309 uint32_t is_resetting; 310 uint32_t is_initialized; 311 uint32_t notification_sent; 312 313 bool is_failed; 314 bool is_dying; 315 STAILQ_HEAD(, nvme_request) fail_req; 316 317 /* Host Memory Buffer */ 318 int hmb_nchunks; 319 size_t hmb_chunk; 320 bus_dma_tag_t hmb_tag; 321 struct nvme_hmb_chunk { 322 bus_dmamap_t hmbc_map; 323 void *hmbc_vaddr; 324 uint64_t hmbc_paddr; 325 } *hmb_chunks; 326 bus_dma_tag_t hmb_desc_tag; 327 bus_dmamap_t hmb_desc_map; 328 struct nvme_hmb_desc *hmb_desc_vaddr; 329 uint64_t hmb_desc_paddr; 330 }; 331 332 #define nvme_mmio_offsetof(reg) \ 333 offsetof(struct nvme_registers, reg) 334 335 #define nvme_mmio_read_4(sc, reg) \ 336 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 337 nvme_mmio_offsetof(reg)) 338 339 #define nvme_mmio_write_4(sc, reg, val) \ 340 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 341 nvme_mmio_offsetof(reg), val) 342 343 #define nvme_mmio_write_8(sc, reg, val) \ 344 do { \ 345 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 346 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 347 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 348 nvme_mmio_offsetof(reg)+4, \ 349 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 350 } while (0); 351 352 #define nvme_printf(ctrlr, fmt, args...) \ 353 device_printf(ctrlr->dev, fmt, ##args) 354 355 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 356 357 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 358 void *payload, 359 nvme_cb_fn_t cb_fn, void *cb_arg); 360 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 361 uint32_t nsid, void *payload, 362 nvme_cb_fn_t cb_fn, void *cb_arg); 363 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 364 uint32_t microseconds, 365 uint32_t threshold, 366 nvme_cb_fn_t cb_fn, 367 void *cb_arg); 368 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 369 struct nvme_error_information_entry *payload, 370 uint32_t num_entries, /* 0 = max */ 371 nvme_cb_fn_t cb_fn, 372 void *cb_arg); 373 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 374 uint32_t nsid, 375 struct nvme_health_information_page *payload, 376 nvme_cb_fn_t cb_fn, 377 void *cb_arg); 378 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 379 struct nvme_firmware_page *payload, 380 nvme_cb_fn_t cb_fn, 381 void *cb_arg); 382 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 383 struct nvme_qpair *io_que, 384 nvme_cb_fn_t cb_fn, void *cb_arg); 385 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 386 struct nvme_qpair *io_que, 387 nvme_cb_fn_t cb_fn, void *cb_arg); 388 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 389 struct nvme_qpair *io_que, 390 nvme_cb_fn_t cb_fn, void *cb_arg); 391 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 392 struct nvme_qpair *io_que, 393 nvme_cb_fn_t cb_fn, void *cb_arg); 394 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 395 uint32_t num_queues, nvme_cb_fn_t cb_fn, 396 void *cb_arg); 397 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 398 uint32_t state, 399 nvme_cb_fn_t cb_fn, void *cb_arg); 400 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 401 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 402 403 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 404 405 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 406 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 407 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 408 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 409 /* ctrlr defined as void * to allow use with config_intrhook. */ 410 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 411 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 412 struct nvme_request *req); 413 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 414 struct nvme_request *req); 415 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 416 struct nvme_request *req); 417 418 int nvme_qpair_construct(struct nvme_qpair *qpair, 419 uint32_t num_entries, uint32_t num_trackers, 420 struct nvme_controller *ctrlr); 421 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 422 struct nvme_tracker *tr); 423 bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 424 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 425 struct nvme_request *req); 426 void nvme_qpair_reset(struct nvme_qpair *qpair); 427 void nvme_qpair_fail(struct nvme_qpair *qpair); 428 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 429 struct nvme_request *req, 430 uint32_t sct, uint32_t sc); 431 432 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 433 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 434 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 435 436 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 437 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 438 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 439 440 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 441 struct nvme_controller *ctrlr); 442 void nvme_ns_destruct(struct nvme_namespace *ns); 443 444 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 445 446 void nvme_dump_command(struct nvme_command *cmd); 447 void nvme_dump_completion(struct nvme_completion *cpl); 448 449 int nvme_attach(device_t dev); 450 int nvme_shutdown(device_t dev); 451 int nvme_detach(device_t dev); 452 453 /* 454 * Wait for a command to complete using the nvme_completion_poll_cb. Used in 455 * limited contexts where the caller knows it's OK to block briefly while the 456 * command runs. The ISR will run the callback which will set status->done to 457 * true, usually within microseconds. If not, then after one second timeout 458 * handler should reset the controller and abort all outstanding requests 459 * including this polled one. If still not after ten seconds, then something is 460 * wrong with the driver, and panic is the only way to recover. 461 * 462 * Most commands using this interface aren't actual I/O to the drive's media so 463 * complete within a few microseconds. Adaptively spin for one tick to catch the 464 * vast majority of these without waiting for a tick plus scheduling delays. Since 465 * these are on startup, this drastically reduces startup time. 466 */ 467 static __inline 468 void 469 nvme_completion_poll(struct nvme_completion_poll_status *status) 470 { 471 int timeout = ticks + 10 * hz; 472 sbintime_t delta_t = SBT_1US; 473 474 while (!atomic_load_acq_int(&status->done)) { 475 if (timeout - ticks < 0) 476 panic("NVME polled command failed to complete within 10s."); 477 pause_sbt("nvme", delta_t, 0, C_PREL(1)); 478 delta_t = min(SBT_1MS, delta_t * 3 / 2); 479 } 480 } 481 482 static __inline void 483 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 484 { 485 uint64_t *bus_addr = (uint64_t *)arg; 486 487 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg)); 488 if (error != 0) 489 printf("nvme_single_map err %d\n", error); 490 *bus_addr = seg[0].ds_addr; 491 } 492 493 static __inline struct nvme_request * 494 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 495 { 496 struct nvme_request *req; 497 498 req = malloc(sizeof(*req), M_NVME, M_NOWAIT | M_ZERO); 499 if (req != NULL) { 500 req->cb_fn = cb_fn; 501 req->cb_arg = cb_arg; 502 req->timeout = true; 503 } 504 return (req); 505 } 506 507 static __inline struct nvme_request * 508 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 509 nvme_cb_fn_t cb_fn, void *cb_arg) 510 { 511 struct nvme_request *req; 512 513 req = _nvme_allocate_request(cb_fn, cb_arg); 514 if (req != NULL) { 515 req->payload = memdesc_vaddr(payload, payload_size); 516 req->payload_valid = true; 517 } 518 return (req); 519 } 520 521 static __inline struct nvme_request * 522 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 523 { 524 struct nvme_request *req; 525 526 req = _nvme_allocate_request(cb_fn, cb_arg); 527 return (req); 528 } 529 530 static __inline struct nvme_request * 531 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 532 { 533 struct nvme_request *req; 534 535 req = _nvme_allocate_request(cb_fn, cb_arg); 536 if (req != NULL) { 537 req->payload = memdesc_bio(bio); 538 req->payload_valid = true; 539 } 540 return (req); 541 } 542 543 static __inline struct nvme_request * 544 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 545 { 546 struct nvme_request *req; 547 548 req = _nvme_allocate_request(cb_fn, cb_arg); 549 if (req != NULL) { 550 req->payload = memdesc_ccb(ccb); 551 req->payload_valid = true; 552 } 553 554 return (req); 555 } 556 557 #define nvme_free_request(req) free(req, M_NVME) 558 559 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 560 const struct nvme_completion *async_cpl, 561 uint32_t log_page_id, void *log_page_buffer, 562 uint32_t log_page_size); 563 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 564 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 565 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 566 567 void nvme_ctrlr_shared_handler(void *arg); 568 void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 569 570 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr); 571 int nvme_ctrlr_resume(struct nvme_controller *ctrlr); 572 573 #endif /* __NVME_PRIVATE_H__ */ 574