1 /*- 2 * Copyright (C) 2012-2014 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __NVME_PRIVATE_H__ 30 #define __NVME_PRIVATE_H__ 31 32 #include <sys/param.h> 33 #include <sys/bio.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/mutex.h> 39 #include <sys/rman.h> 40 #include <sys/systm.h> 41 #include <sys/taskqueue.h> 42 43 #include <vm/uma.h> 44 45 #include <machine/bus.h> 46 47 #include "nvme.h" 48 49 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 50 51 MALLOC_DECLARE(M_NVME); 52 53 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 54 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 55 56 /* 57 * For commands requiring more than 2 PRP entries, one PRP will be 58 * embedded in the command (prp1), and the rest of the PRP entries 59 * will be in a list pointed to by the command (prp2). This means 60 * that real max number of PRP entries we support is 32+1, which 61 * results in a max xfer size of 32*PAGE_SIZE. 62 */ 63 #define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE) 64 65 #define NVME_ADMIN_TRACKERS (16) 66 #define NVME_ADMIN_ENTRIES (128) 67 /* min and max are defined in admin queue attributes section of spec */ 68 #define NVME_MIN_ADMIN_ENTRIES (2) 69 #define NVME_MAX_ADMIN_ENTRIES (4096) 70 71 /* 72 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 73 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 74 * will allow outstanding on an I/O qpair at any time. The only advantage in 75 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 76 * the contents of the submission and completion queues, it will show a longer 77 * history of data. 78 */ 79 #define NVME_IO_ENTRIES (256) 80 #define NVME_IO_TRACKERS (128) 81 #define NVME_MIN_IO_TRACKERS (4) 82 #define NVME_MAX_IO_TRACKERS (1024) 83 84 /* 85 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 86 * for each controller. 87 */ 88 89 #define NVME_INT_COAL_TIME (0) /* disabled */ 90 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 91 92 #define NVME_MAX_NAMESPACES (16) 93 #define NVME_MAX_CONSUMERS (2) 94 #define NVME_MAX_ASYNC_EVENTS (8) 95 96 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 97 #define NVME_MIN_TIMEOUT_PERIOD (5) 98 #define NVME_MAX_TIMEOUT_PERIOD (120) 99 100 #define NVME_DEFAULT_RETRY_COUNT (4) 101 102 /* Maximum log page size to fetch for AERs. */ 103 #define NVME_MAX_AER_LOG_SIZE (4096) 104 105 /* 106 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 107 * it. 108 */ 109 #ifndef CACHE_LINE_SIZE 110 #define CACHE_LINE_SIZE (64) 111 #endif 112 113 /* 114 * Use presence of the BIO_UNMAPPED flag to determine whether unmapped I/O 115 * support and the bus_dmamap_load_bio API are available on the target 116 * kernel. This will ease porting back to earlier stable branches at a 117 * later point. 118 */ 119 #ifdef BIO_UNMAPPED 120 #define NVME_UNMAPPED_BIO_SUPPORT 121 #endif 122 123 extern uma_zone_t nvme_request_zone; 124 extern int32_t nvme_retry_count; 125 126 struct nvme_completion_poll_status { 127 128 struct nvme_completion cpl; 129 boolean_t done; 130 }; 131 132 #define NVME_REQUEST_VADDR 1 133 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 134 #define NVME_REQUEST_UIO 3 135 #ifdef NVME_UNMAPPED_BIO_SUPPORT 136 #define NVME_REQUEST_BIO 4 137 #endif 138 #define NVME_REQUEST_CCB 5 139 140 struct nvme_request { 141 142 struct nvme_command cmd; 143 struct nvme_qpair *qpair; 144 union { 145 void *payload; 146 struct bio *bio; 147 } u; 148 uint32_t type; 149 uint32_t payload_size; 150 boolean_t timeout; 151 nvme_cb_fn_t cb_fn; 152 void *cb_arg; 153 int32_t retries; 154 STAILQ_ENTRY(nvme_request) stailq; 155 }; 156 157 struct nvme_async_event_request { 158 159 struct nvme_controller *ctrlr; 160 struct nvme_request *req; 161 struct nvme_completion cpl; 162 uint32_t log_page_id; 163 uint32_t log_page_size; 164 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 165 }; 166 167 struct nvme_tracker { 168 169 TAILQ_ENTRY(nvme_tracker) tailq; 170 struct nvme_request *req; 171 struct nvme_qpair *qpair; 172 struct callout timer; 173 bus_dmamap_t payload_dma_map; 174 uint16_t cid; 175 176 uint64_t *prp; 177 bus_addr_t prp_bus_addr; 178 }; 179 180 struct nvme_qpair { 181 182 struct nvme_controller *ctrlr; 183 uint32_t id; 184 uint32_t phase; 185 186 uint16_t vector; 187 int rid; 188 struct resource *res; 189 void *tag; 190 191 uint32_t num_entries; 192 uint32_t num_trackers; 193 uint32_t sq_tdbl_off; 194 uint32_t cq_hdbl_off; 195 196 uint32_t sq_head; 197 uint32_t sq_tail; 198 uint32_t cq_head; 199 200 int64_t num_cmds; 201 int64_t num_intr_handler_calls; 202 203 struct nvme_command *cmd; 204 struct nvme_completion *cpl; 205 206 bus_dma_tag_t dma_tag; 207 bus_dma_tag_t dma_tag_payload; 208 209 bus_dmamap_t queuemem_map; 210 uint64_t cmd_bus_addr; 211 uint64_t cpl_bus_addr; 212 213 TAILQ_HEAD(, nvme_tracker) free_tr; 214 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 215 STAILQ_HEAD(, nvme_request) queued_req; 216 217 struct nvme_tracker **act_tr; 218 219 boolean_t is_enabled; 220 221 struct mtx lock __aligned(CACHE_LINE_SIZE); 222 223 } __aligned(CACHE_LINE_SIZE); 224 225 struct nvme_namespace { 226 227 struct nvme_controller *ctrlr; 228 struct nvme_namespace_data data; 229 uint32_t id; 230 uint32_t flags; 231 struct cdev *cdev; 232 void *cons_cookie[NVME_MAX_CONSUMERS]; 233 uint32_t stripesize; 234 struct mtx lock; 235 }; 236 237 /* 238 * One of these per allocated PCI device. 239 */ 240 struct nvme_controller { 241 242 device_t dev; 243 244 struct mtx lock; 245 246 uint32_t ready_timeout_in_ms; 247 248 bus_space_tag_t bus_tag; 249 bus_space_handle_t bus_handle; 250 int resource_id; 251 struct resource *resource; 252 253 /* 254 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 255 * separate from the control registers which are in BAR 0/1. These 256 * members track the mapping of BAR 4/5 for that reason. 257 */ 258 int bar4_resource_id; 259 struct resource *bar4_resource; 260 261 uint32_t msix_enabled; 262 uint32_t force_intx; 263 uint32_t enable_aborts; 264 265 uint32_t num_io_queues; 266 uint32_t num_cpus_per_ioq; 267 uint32_t max_hw_pend_io; 268 269 /* Fields for tracking progress during controller initialization. */ 270 struct intr_config_hook config_hook; 271 uint32_t ns_identified; 272 uint32_t queues_created; 273 274 struct task reset_task; 275 struct task fail_req_task; 276 struct taskqueue *taskqueue; 277 278 /* For shared legacy interrupt. */ 279 int rid; 280 struct resource *res; 281 void *tag; 282 283 bus_dma_tag_t hw_desc_tag; 284 bus_dmamap_t hw_desc_map; 285 286 /** maximum i/o size in bytes */ 287 uint32_t max_xfer_size; 288 289 /** minimum page size supported by this controller in bytes */ 290 uint32_t min_page_size; 291 292 /** interrupt coalescing time period (in microseconds) */ 293 uint32_t int_coal_time; 294 295 /** interrupt coalescing threshold */ 296 uint32_t int_coal_threshold; 297 298 /** timeout period in seconds */ 299 uint32_t timeout_period; 300 301 struct nvme_qpair adminq; 302 struct nvme_qpair *ioq; 303 304 struct nvme_registers *regs; 305 306 struct nvme_controller_data cdata; 307 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 308 309 struct cdev *cdev; 310 311 /** bit mask of warning types currently enabled for async events */ 312 union nvme_critical_warning_state async_event_config; 313 314 uint32_t num_aers; 315 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 316 317 void *cons_cookie[NVME_MAX_CONSUMERS]; 318 319 uint32_t is_resetting; 320 uint32_t is_initialized; 321 uint32_t notification_sent; 322 323 boolean_t is_failed; 324 STAILQ_HEAD(, nvme_request) fail_req; 325 }; 326 327 #define nvme_mmio_offsetof(reg) \ 328 offsetof(struct nvme_registers, reg) 329 330 #define nvme_mmio_read_4(sc, reg) \ 331 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 332 nvme_mmio_offsetof(reg)) 333 334 #define nvme_mmio_write_4(sc, reg, val) \ 335 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 336 nvme_mmio_offsetof(reg), val) 337 338 #define nvme_mmio_write_8(sc, reg, val) \ 339 do { \ 340 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 341 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 342 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 343 nvme_mmio_offsetof(reg)+4, \ 344 (val & 0xFFFFFFFF00000000UL) >> 32); \ 345 } while (0); 346 347 #if __FreeBSD_version < 800054 348 #define wmb() __asm volatile("sfence" ::: "memory") 349 #define mb() __asm volatile("mfence" ::: "memory") 350 #endif 351 352 #define nvme_printf(ctrlr, fmt, args...) \ 353 device_printf(ctrlr->dev, fmt, ##args) 354 355 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 356 357 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 358 void *payload, 359 nvme_cb_fn_t cb_fn, void *cb_arg); 360 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 361 uint32_t nsid, void *payload, 362 nvme_cb_fn_t cb_fn, void *cb_arg); 363 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 364 uint32_t microseconds, 365 uint32_t threshold, 366 nvme_cb_fn_t cb_fn, 367 void *cb_arg); 368 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 369 struct nvme_error_information_entry *payload, 370 uint32_t num_entries, /* 0 = max */ 371 nvme_cb_fn_t cb_fn, 372 void *cb_arg); 373 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 374 uint32_t nsid, 375 struct nvme_health_information_page *payload, 376 nvme_cb_fn_t cb_fn, 377 void *cb_arg); 378 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 379 struct nvme_firmware_page *payload, 380 nvme_cb_fn_t cb_fn, 381 void *cb_arg); 382 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 383 struct nvme_qpair *io_que, uint16_t vector, 384 nvme_cb_fn_t cb_fn, void *cb_arg); 385 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 386 struct nvme_qpair *io_que, 387 nvme_cb_fn_t cb_fn, void *cb_arg); 388 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 389 struct nvme_qpair *io_que, 390 nvme_cb_fn_t cb_fn, void *cb_arg); 391 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 392 struct nvme_qpair *io_que, 393 nvme_cb_fn_t cb_fn, void *cb_arg); 394 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 395 uint32_t num_queues, nvme_cb_fn_t cb_fn, 396 void *cb_arg); 397 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 398 union nvme_critical_warning_state state, 399 nvme_cb_fn_t cb_fn, void *cb_arg); 400 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 401 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 402 403 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 404 405 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 406 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 407 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 408 int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 409 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 410 /* ctrlr defined as void * to allow use with config_intrhook. */ 411 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 412 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 413 struct nvme_request *req); 414 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 415 struct nvme_request *req); 416 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 417 struct nvme_request *req); 418 419 int nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 420 uint16_t vector, uint32_t num_entries, 421 uint32_t num_trackers, 422 struct nvme_controller *ctrlr); 423 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 424 struct nvme_tracker *tr); 425 void nvme_qpair_process_completions(struct nvme_qpair *qpair); 426 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 427 struct nvme_request *req); 428 void nvme_qpair_reset(struct nvme_qpair *qpair); 429 void nvme_qpair_fail(struct nvme_qpair *qpair); 430 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 431 struct nvme_request *req, 432 uint32_t sct, uint32_t sc, 433 boolean_t print_on_error); 434 435 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 436 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 437 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 438 439 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 440 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 441 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 442 443 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 444 struct nvme_controller *ctrlr); 445 void nvme_ns_destruct(struct nvme_namespace *ns); 446 447 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 448 449 void nvme_dump_command(struct nvme_command *cmd); 450 void nvme_dump_completion(struct nvme_completion *cpl); 451 452 static __inline void 453 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 454 { 455 uint64_t *bus_addr = (uint64_t *)arg; 456 457 if (error != 0) 458 printf("nvme_single_map err %d\n", error); 459 *bus_addr = seg[0].ds_addr; 460 } 461 462 static __inline struct nvme_request * 463 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 464 { 465 struct nvme_request *req; 466 467 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 468 if (req != NULL) { 469 req->cb_fn = cb_fn; 470 req->cb_arg = cb_arg; 471 req->timeout = TRUE; 472 } 473 return (req); 474 } 475 476 static __inline struct nvme_request * 477 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 478 nvme_cb_fn_t cb_fn, void *cb_arg) 479 { 480 struct nvme_request *req; 481 482 req = _nvme_allocate_request(cb_fn, cb_arg); 483 if (req != NULL) { 484 req->type = NVME_REQUEST_VADDR; 485 req->u.payload = payload; 486 req->payload_size = payload_size; 487 } 488 return (req); 489 } 490 491 static __inline struct nvme_request * 492 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 493 { 494 struct nvme_request *req; 495 496 req = _nvme_allocate_request(cb_fn, cb_arg); 497 if (req != NULL) 498 req->type = NVME_REQUEST_NULL; 499 return (req); 500 } 501 502 static __inline struct nvme_request * 503 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 504 { 505 struct nvme_request *req; 506 507 req = _nvme_allocate_request(cb_fn, cb_arg); 508 if (req != NULL) { 509 #ifdef NVME_UNMAPPED_BIO_SUPPORT 510 req->type = NVME_REQUEST_BIO; 511 req->u.bio = bio; 512 #else 513 req->type = NVME_REQUEST_VADDR; 514 req->u.payload = bio->bio_data; 515 req->payload_size = bio->bio_bcount; 516 #endif 517 } 518 return (req); 519 } 520 521 static __inline struct nvme_request * 522 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 523 { 524 struct nvme_request *req; 525 526 req = _nvme_allocate_request(cb_fn, cb_arg); 527 if (req != NULL) { 528 req->type = NVME_REQUEST_CCB; 529 req->u.payload = ccb; 530 } 531 532 return (req); 533 } 534 535 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 536 537 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 538 const struct nvme_completion *async_cpl, 539 uint32_t log_page_id, void *log_page_buffer, 540 uint32_t log_page_size); 541 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 542 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 543 544 void nvme_ctrlr_intx_handler(void *arg); 545 546 #endif /* __NVME_PRIVATE_H__ */ 547