1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __NVME_PRIVATE_H__ 30 #define __NVME_PRIVATE_H__ 31 32 #include <sys/param.h> 33 #include <sys/bio.h> 34 #include <sys/bus.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/malloc.h> 38 #include <sys/memdesc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/systm.h> 43 #include <sys/taskqueue.h> 44 45 #include <vm/uma.h> 46 47 #include <machine/bus.h> 48 49 #include "nvme.h" 50 51 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 52 53 MALLOC_DECLARE(M_NVME); 54 55 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 56 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 57 58 #define NVME_ADMIN_TRACKERS (16) 59 #define NVME_ADMIN_ENTRIES (128) 60 /* min and max are defined in admin queue attributes section of spec */ 61 #define NVME_MIN_ADMIN_ENTRIES (2) 62 #define NVME_MAX_ADMIN_ENTRIES (4096) 63 64 /* 65 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 66 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 67 * will allow outstanding on an I/O qpair at any time. The only advantage in 68 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 69 * the contents of the submission and completion queues, it will show a longer 70 * history of data. 71 */ 72 #define NVME_IO_ENTRIES (256) 73 #define NVME_IO_TRACKERS (128) 74 #define NVME_MIN_IO_TRACKERS (4) 75 #define NVME_MAX_IO_TRACKERS (1024) 76 77 /* 78 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 79 * for each controller. 80 */ 81 82 #define NVME_INT_COAL_TIME (0) /* disabled */ 83 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 84 85 #define NVME_MAX_NAMESPACES (16) 86 #define NVME_MAX_CONSUMERS (2) 87 #define NVME_MAX_ASYNC_EVENTS (8) 88 89 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 90 #define NVME_MIN_TIMEOUT_PERIOD (5) 91 #define NVME_MAX_TIMEOUT_PERIOD (120) 92 93 #define NVME_DEFAULT_RETRY_COUNT (4) 94 95 /* Maximum log page size to fetch for AERs. */ 96 #define NVME_MAX_AER_LOG_SIZE (4096) 97 98 /* 99 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 100 * it. 101 */ 102 #ifndef CACHE_LINE_SIZE 103 #define CACHE_LINE_SIZE (64) 104 #endif 105 106 #define NVME_GONE 0xfffffffful 107 108 extern int32_t nvme_retry_count; 109 extern bool nvme_verbose_cmd_dump; 110 111 struct nvme_completion_poll_status { 112 struct nvme_completion cpl; 113 int done; 114 }; 115 116 struct nvme_request { 117 struct nvme_command cmd; 118 struct nvme_qpair *qpair; 119 struct memdesc payload; 120 nvme_cb_fn_t cb_fn; 121 void *cb_arg; 122 int32_t retries; 123 bool payload_valid; 124 bool timeout; 125 bool spare[2]; /* Future use */ 126 STAILQ_ENTRY(nvme_request) stailq; 127 }; 128 129 struct nvme_async_event_request { 130 struct nvme_controller *ctrlr; 131 struct nvme_request *req; 132 struct nvme_completion cpl; 133 uint32_t log_page_id; 134 uint32_t log_page_size; 135 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 136 }; 137 138 struct nvme_tracker { 139 TAILQ_ENTRY(nvme_tracker) tailq; 140 struct nvme_request *req; 141 struct nvme_qpair *qpair; 142 sbintime_t deadline; 143 bus_dmamap_t payload_dma_map; 144 uint16_t cid; 145 146 uint64_t *prp; 147 bus_addr_t prp_bus_addr; 148 }; 149 150 enum nvme_recovery { 151 RECOVERY_NONE = 0, /* Normal operations */ 152 RECOVERY_WAITING, /* waiting for the reset to complete */ 153 }; 154 struct nvme_qpair { 155 struct nvme_controller *ctrlr; 156 uint32_t id; 157 int domain; 158 int cpu; 159 160 uint16_t vector; 161 int rid; 162 struct resource *res; 163 void *tag; 164 165 struct callout timer; /* recovery lock */ 166 bool timer_armed; /* recovery lock */ 167 enum nvme_recovery recovery_state; /* recovery lock */ 168 169 uint32_t num_entries; 170 uint32_t num_trackers; 171 uint32_t sq_tdbl_off; 172 uint32_t cq_hdbl_off; 173 174 uint32_t phase; 175 uint32_t sq_head; 176 uint32_t sq_tail; 177 uint32_t cq_head; 178 179 int64_t num_cmds; 180 int64_t num_intr_handler_calls; 181 int64_t num_retries; 182 int64_t num_failures; 183 int64_t num_ignored; 184 int64_t num_recovery_nolock; 185 186 struct nvme_command *cmd; 187 struct nvme_completion *cpl; 188 189 bus_dma_tag_t dma_tag; 190 bus_dma_tag_t dma_tag_payload; 191 192 bus_dmamap_t queuemem_map; 193 uint64_t cmd_bus_addr; 194 uint64_t cpl_bus_addr; 195 196 TAILQ_HEAD(, nvme_tracker) free_tr; 197 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 198 STAILQ_HEAD(, nvme_request) queued_req; 199 200 struct nvme_tracker **act_tr; 201 202 struct mtx_padalign lock; 203 struct mtx_padalign recovery; 204 } __aligned(CACHE_LINE_SIZE); 205 206 struct nvme_namespace { 207 struct nvme_controller *ctrlr; 208 struct nvme_namespace_data data; 209 uint32_t id; 210 uint32_t flags; 211 struct cdev *cdev; 212 void *cons_cookie[NVME_MAX_CONSUMERS]; 213 uint32_t boundary; 214 struct mtx lock; 215 }; 216 217 /* 218 * One of these per allocated PCI device. 219 */ 220 struct nvme_controller { 221 device_t dev; 222 223 struct mtx lock; 224 int domain; 225 uint32_t ready_timeout_in_ms; 226 uint32_t quirks; 227 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 228 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 229 #define QUIRK_INTEL_ALIGNMENT 4 /* Pre NVMe 1.3 performance alignment */ 230 #define QUIRK_AHCI 8 /* Attached via AHCI redirect */ 231 232 bus_space_tag_t bus_tag; 233 bus_space_handle_t bus_handle; 234 int resource_id; 235 struct resource *resource; 236 237 /* 238 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 239 * separate from the control registers which are in BAR 0/1. These 240 * members track the mapping of BAR 4/5 for that reason. 241 */ 242 int bar4_resource_id; 243 struct resource *bar4_resource; 244 245 int msi_count; 246 uint32_t enable_aborts; 247 248 uint32_t num_io_queues; 249 uint32_t max_hw_pend_io; 250 251 /* Fields for tracking progress during controller initialization. */ 252 struct intr_config_hook config_hook; 253 uint32_t ns_identified; 254 uint32_t queues_created; 255 256 struct task reset_task; 257 struct task fail_req_task; 258 struct taskqueue *taskqueue; 259 260 /* For shared legacy interrupt. */ 261 int rid; 262 struct resource *res; 263 void *tag; 264 265 /** maximum i/o size in bytes */ 266 uint32_t max_xfer_size; 267 268 /** LO and HI capacity mask */ 269 uint32_t cap_lo; 270 uint32_t cap_hi; 271 272 /** Page size and log2(page_size) - 12 that we're currently using */ 273 uint32_t page_size; 274 uint32_t mps; 275 276 /** interrupt coalescing time period (in microseconds) */ 277 uint32_t int_coal_time; 278 279 /** interrupt coalescing threshold */ 280 uint32_t int_coal_threshold; 281 282 /** timeout period in seconds */ 283 uint32_t timeout_period; 284 285 /** doorbell stride */ 286 uint32_t dstrd; 287 288 struct nvme_qpair adminq; 289 struct nvme_qpair *ioq; 290 291 struct nvme_registers *regs; 292 293 struct nvme_controller_data cdata; 294 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 295 296 struct cdev *cdev; 297 298 /** bit mask of event types currently enabled for async events */ 299 uint32_t async_event_config; 300 301 uint32_t num_aers; 302 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 303 304 void *cons_cookie[NVME_MAX_CONSUMERS]; 305 306 uint32_t is_resetting; 307 uint32_t is_initialized; 308 uint32_t notification_sent; 309 310 bool is_failed; 311 bool is_dying; 312 STAILQ_HEAD(, nvme_request) fail_req; 313 314 /* Host Memory Buffer */ 315 int hmb_nchunks; 316 size_t hmb_chunk; 317 bus_dma_tag_t hmb_tag; 318 struct nvme_hmb_chunk { 319 bus_dmamap_t hmbc_map; 320 void *hmbc_vaddr; 321 uint64_t hmbc_paddr; 322 } *hmb_chunks; 323 bus_dma_tag_t hmb_desc_tag; 324 bus_dmamap_t hmb_desc_map; 325 struct nvme_hmb_desc *hmb_desc_vaddr; 326 uint64_t hmb_desc_paddr; 327 }; 328 329 #define nvme_mmio_offsetof(reg) \ 330 offsetof(struct nvme_registers, reg) 331 332 #define nvme_mmio_read_4(sc, reg) \ 333 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 334 nvme_mmio_offsetof(reg)) 335 336 #define nvme_mmio_write_4(sc, reg, val) \ 337 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 338 nvme_mmio_offsetof(reg), val) 339 340 #define nvme_mmio_write_8(sc, reg, val) \ 341 do { \ 342 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 343 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 344 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 345 nvme_mmio_offsetof(reg)+4, \ 346 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 347 } while (0); 348 349 #define nvme_printf(ctrlr, fmt, args...) \ 350 device_printf(ctrlr->dev, fmt, ##args) 351 352 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 353 354 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 355 void *payload, 356 nvme_cb_fn_t cb_fn, void *cb_arg); 357 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 358 uint32_t nsid, void *payload, 359 nvme_cb_fn_t cb_fn, void *cb_arg); 360 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 361 uint32_t microseconds, 362 uint32_t threshold, 363 nvme_cb_fn_t cb_fn, 364 void *cb_arg); 365 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 366 struct nvme_error_information_entry *payload, 367 uint32_t num_entries, /* 0 = max */ 368 nvme_cb_fn_t cb_fn, 369 void *cb_arg); 370 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 371 uint32_t nsid, 372 struct nvme_health_information_page *payload, 373 nvme_cb_fn_t cb_fn, 374 void *cb_arg); 375 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 376 struct nvme_firmware_page *payload, 377 nvme_cb_fn_t cb_fn, 378 void *cb_arg); 379 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 380 struct nvme_qpair *io_que, 381 nvme_cb_fn_t cb_fn, void *cb_arg); 382 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 383 struct nvme_qpair *io_que, 384 nvme_cb_fn_t cb_fn, void *cb_arg); 385 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 386 struct nvme_qpair *io_que, 387 nvme_cb_fn_t cb_fn, void *cb_arg); 388 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 389 struct nvme_qpair *io_que, 390 nvme_cb_fn_t cb_fn, void *cb_arg); 391 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 392 uint32_t num_queues, nvme_cb_fn_t cb_fn, 393 void *cb_arg); 394 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 395 uint32_t state, 396 nvme_cb_fn_t cb_fn, void *cb_arg); 397 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 398 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 399 400 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 401 402 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 403 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 404 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 405 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 406 /* ctrlr defined as void * to allow use with config_intrhook. */ 407 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 408 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 409 struct nvme_request *req); 410 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 411 struct nvme_request *req); 412 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 413 struct nvme_request *req); 414 415 int nvme_qpair_construct(struct nvme_qpair *qpair, 416 uint32_t num_entries, uint32_t num_trackers, 417 struct nvme_controller *ctrlr); 418 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 419 struct nvme_tracker *tr); 420 bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 421 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 422 struct nvme_request *req); 423 void nvme_qpair_reset(struct nvme_qpair *qpair); 424 void nvme_qpair_fail(struct nvme_qpair *qpair); 425 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 426 struct nvme_request *req, 427 uint32_t sct, uint32_t sc); 428 429 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 430 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 431 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 432 433 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 434 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 435 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 436 437 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 438 struct nvme_controller *ctrlr); 439 void nvme_ns_destruct(struct nvme_namespace *ns); 440 441 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 442 443 void nvme_qpair_print_command(struct nvme_qpair *qpair, 444 struct nvme_command *cmd); 445 void nvme_qpair_print_completion(struct nvme_qpair *qpair, 446 struct nvme_completion *cpl); 447 448 int nvme_attach(device_t dev); 449 int nvme_shutdown(device_t dev); 450 int nvme_detach(device_t dev); 451 452 /* 453 * Wait for a command to complete using the nvme_completion_poll_cb. Used in 454 * limited contexts where the caller knows it's OK to block briefly while the 455 * command runs. The ISR will run the callback which will set status->done to 456 * true, usually within microseconds. If not, then after one second timeout 457 * handler should reset the controller and abort all outstanding requests 458 * including this polled one. If still not after ten seconds, then something is 459 * wrong with the driver, and panic is the only way to recover. 460 * 461 * Most commands using this interface aren't actual I/O to the drive's media so 462 * complete within a few microseconds. Adaptively spin for one tick to catch the 463 * vast majority of these without waiting for a tick plus scheduling delays. Since 464 * these are on startup, this drastically reduces startup time. 465 */ 466 static __inline 467 void 468 nvme_completion_poll(struct nvme_completion_poll_status *status) 469 { 470 int timeout = ticks + 10 * hz; 471 sbintime_t delta_t = SBT_1US; 472 473 while (!atomic_load_acq_int(&status->done)) { 474 if (timeout - ticks < 0) 475 panic("NVME polled command failed to complete within 10s."); 476 pause_sbt("nvme", delta_t, 0, C_PREL(1)); 477 delta_t = min(SBT_1MS, delta_t * 3 / 2); 478 } 479 } 480 481 static __inline void 482 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 483 { 484 uint64_t *bus_addr = (uint64_t *)arg; 485 486 KASSERT(nseg == 1, ("number of segments (%d) is not 1", nseg)); 487 if (error != 0) 488 printf("nvme_single_map err %d\n", error); 489 *bus_addr = seg[0].ds_addr; 490 } 491 492 static __inline struct nvme_request * 493 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 494 { 495 struct nvme_request *req; 496 497 req = malloc(sizeof(*req), M_NVME, M_NOWAIT | M_ZERO); 498 if (req != NULL) { 499 req->cb_fn = cb_fn; 500 req->cb_arg = cb_arg; 501 req->timeout = true; 502 } 503 return (req); 504 } 505 506 static __inline struct nvme_request * 507 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 508 nvme_cb_fn_t cb_fn, void *cb_arg) 509 { 510 struct nvme_request *req; 511 512 req = _nvme_allocate_request(cb_fn, cb_arg); 513 if (req != NULL) { 514 req->payload = memdesc_vaddr(payload, payload_size); 515 req->payload_valid = true; 516 } 517 return (req); 518 } 519 520 static __inline struct nvme_request * 521 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 522 { 523 struct nvme_request *req; 524 525 req = _nvme_allocate_request(cb_fn, cb_arg); 526 return (req); 527 } 528 529 static __inline struct nvme_request * 530 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 531 { 532 struct nvme_request *req; 533 534 req = _nvme_allocate_request(cb_fn, cb_arg); 535 if (req != NULL) { 536 req->payload = memdesc_bio(bio); 537 req->payload_valid = true; 538 } 539 return (req); 540 } 541 542 static __inline struct nvme_request * 543 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 544 { 545 struct nvme_request *req; 546 547 req = _nvme_allocate_request(cb_fn, cb_arg); 548 if (req != NULL) { 549 req->payload = memdesc_ccb(ccb); 550 req->payload_valid = true; 551 } 552 553 return (req); 554 } 555 556 #define nvme_free_request(req) free(req, M_NVME) 557 558 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 559 const struct nvme_completion *async_cpl, 560 uint32_t log_page_id, void *log_page_buffer, 561 uint32_t log_page_size); 562 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 563 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 564 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 565 566 void nvme_ctrlr_shared_handler(void *arg); 567 void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 568 569 int nvme_ctrlr_suspend(struct nvme_controller *ctrlr); 570 int nvme_ctrlr_resume(struct nvme_controller *ctrlr); 571 572 #endif /* __NVME_PRIVATE_H__ */ 573