1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2014 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_PRIVATE_H__ 32 #define __NVME_PRIVATE_H__ 33 34 #include <sys/param.h> 35 #include <sys/bio.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/mutex.h> 41 #include <sys/rman.h> 42 #include <sys/systm.h> 43 #include <sys/taskqueue.h> 44 45 #include <vm/uma.h> 46 47 #include <machine/bus.h> 48 49 #include "nvme.h" 50 51 #define DEVICE2SOFTC(dev) ((struct nvme_controller *) device_get_softc(dev)) 52 53 MALLOC_DECLARE(M_NVME); 54 55 #define IDT32_PCI_ID 0x80d0111d /* 32 channel board */ 56 #define IDT8_PCI_ID 0x80d2111d /* 8 channel board */ 57 58 /* 59 * For commands requiring more than 2 PRP entries, one PRP will be 60 * embedded in the command (prp1), and the rest of the PRP entries 61 * will be in a list pointed to by the command (prp2). This means 62 * that real max number of PRP entries we support is 32+1, which 63 * results in a max xfer size of 32*PAGE_SIZE. 64 */ 65 #define NVME_MAX_PRP_LIST_ENTRIES (NVME_MAX_XFER_SIZE / PAGE_SIZE) 66 67 #define NVME_ADMIN_TRACKERS (16) 68 #define NVME_ADMIN_ENTRIES (128) 69 /* min and max are defined in admin queue attributes section of spec */ 70 #define NVME_MIN_ADMIN_ENTRIES (2) 71 #define NVME_MAX_ADMIN_ENTRIES (4096) 72 73 /* 74 * NVME_IO_ENTRIES defines the size of an I/O qpair's submission and completion 75 * queues, while NVME_IO_TRACKERS defines the maximum number of I/O that we 76 * will allow outstanding on an I/O qpair at any time. The only advantage in 77 * having IO_ENTRIES > IO_TRACKERS is for debugging purposes - when dumping 78 * the contents of the submission and completion queues, it will show a longer 79 * history of data. 80 */ 81 #define NVME_IO_ENTRIES (256) 82 #define NVME_IO_TRACKERS (128) 83 #define NVME_MIN_IO_TRACKERS (4) 84 #define NVME_MAX_IO_TRACKERS (1024) 85 86 /* 87 * NVME_MAX_IO_ENTRIES is not defined, since it is specified in CC.MQES 88 * for each controller. 89 */ 90 91 #define NVME_INT_COAL_TIME (0) /* disabled */ 92 #define NVME_INT_COAL_THRESHOLD (0) /* 0-based */ 93 94 #define NVME_MAX_NAMESPACES (16) 95 #define NVME_MAX_CONSUMERS (2) 96 #define NVME_MAX_ASYNC_EVENTS (8) 97 98 #define NVME_DEFAULT_TIMEOUT_PERIOD (30) /* in seconds */ 99 #define NVME_MIN_TIMEOUT_PERIOD (5) 100 #define NVME_MAX_TIMEOUT_PERIOD (120) 101 102 #define NVME_DEFAULT_RETRY_COUNT (4) 103 104 /* Maximum log page size to fetch for AERs. */ 105 #define NVME_MAX_AER_LOG_SIZE (4096) 106 107 /* 108 * Define CACHE_LINE_SIZE here for older FreeBSD versions that do not define 109 * it. 110 */ 111 #ifndef CACHE_LINE_SIZE 112 #define CACHE_LINE_SIZE (64) 113 #endif 114 115 extern uma_zone_t nvme_request_zone; 116 extern int32_t nvme_retry_count; 117 extern bool nvme_verbose_cmd_dump; 118 119 struct nvme_completion_poll_status { 120 121 struct nvme_completion cpl; 122 int done; 123 }; 124 125 #define NVME_REQUEST_VADDR 1 126 #define NVME_REQUEST_NULL 2 /* For requests with no payload. */ 127 #define NVME_REQUEST_UIO 3 128 #define NVME_REQUEST_BIO 4 129 #define NVME_REQUEST_CCB 5 130 131 struct nvme_request { 132 133 struct nvme_command cmd; 134 struct nvme_qpair *qpair; 135 union { 136 void *payload; 137 struct bio *bio; 138 } u; 139 uint32_t type; 140 uint32_t payload_size; 141 boolean_t timeout; 142 nvme_cb_fn_t cb_fn; 143 void *cb_arg; 144 int32_t retries; 145 STAILQ_ENTRY(nvme_request) stailq; 146 }; 147 148 struct nvme_async_event_request { 149 150 struct nvme_controller *ctrlr; 151 struct nvme_request *req; 152 struct nvme_completion cpl; 153 uint32_t log_page_id; 154 uint32_t log_page_size; 155 uint8_t log_page_buffer[NVME_MAX_AER_LOG_SIZE]; 156 }; 157 158 struct nvme_tracker { 159 160 TAILQ_ENTRY(nvme_tracker) tailq; 161 struct nvme_request *req; 162 struct nvme_qpair *qpair; 163 struct callout timer; 164 bus_dmamap_t payload_dma_map; 165 uint16_t cid; 166 167 uint64_t *prp; 168 bus_addr_t prp_bus_addr; 169 }; 170 171 struct nvme_qpair { 172 173 struct nvme_controller *ctrlr; 174 uint32_t id; 175 uint32_t phase; 176 177 uint16_t vector; 178 int rid; 179 struct resource *res; 180 void *tag; 181 182 uint32_t num_entries; 183 uint32_t num_trackers; 184 uint32_t sq_tdbl_off; 185 uint32_t cq_hdbl_off; 186 187 uint32_t sq_head; 188 uint32_t sq_tail; 189 uint32_t cq_head; 190 191 int64_t num_cmds; 192 int64_t num_intr_handler_calls; 193 int64_t num_retries; 194 int64_t num_failures; 195 196 struct nvme_command *cmd; 197 struct nvme_completion *cpl; 198 199 bus_dma_tag_t dma_tag; 200 bus_dma_tag_t dma_tag_payload; 201 202 bus_dmamap_t queuemem_map; 203 uint64_t cmd_bus_addr; 204 uint64_t cpl_bus_addr; 205 206 TAILQ_HEAD(, nvme_tracker) free_tr; 207 TAILQ_HEAD(, nvme_tracker) outstanding_tr; 208 STAILQ_HEAD(, nvme_request) queued_req; 209 210 struct nvme_tracker **act_tr; 211 212 boolean_t is_enabled; 213 214 struct mtx lock __aligned(CACHE_LINE_SIZE); 215 216 } __aligned(CACHE_LINE_SIZE); 217 218 struct nvme_namespace { 219 220 struct nvme_controller *ctrlr; 221 struct nvme_namespace_data data; 222 uint32_t id; 223 uint32_t flags; 224 struct cdev *cdev; 225 void *cons_cookie[NVME_MAX_CONSUMERS]; 226 uint32_t stripesize; 227 struct mtx lock; 228 }; 229 230 /* 231 * One of these per allocated PCI device. 232 */ 233 struct nvme_controller { 234 235 device_t dev; 236 237 struct mtx lock; 238 239 uint32_t ready_timeout_in_ms; 240 uint32_t quirks; 241 #define QUIRK_DELAY_B4_CHK_RDY 1 /* Can't touch MMIO on disable */ 242 #define QUIRK_DISABLE_TIMEOUT 2 /* Disable broken completion timeout feature */ 243 244 bus_space_tag_t bus_tag; 245 bus_space_handle_t bus_handle; 246 int resource_id; 247 struct resource *resource; 248 249 /* 250 * The NVMe spec allows for the MSI-X table to be placed in BAR 4/5, 251 * separate from the control registers which are in BAR 0/1. These 252 * members track the mapping of BAR 4/5 for that reason. 253 */ 254 int bar4_resource_id; 255 struct resource *bar4_resource; 256 257 uint32_t msix_enabled; 258 uint32_t force_intx; 259 uint32_t enable_aborts; 260 261 uint32_t num_io_queues; 262 uint32_t num_cpus_per_ioq; 263 uint32_t max_hw_pend_io; 264 265 /* Fields for tracking progress during controller initialization. */ 266 struct intr_config_hook config_hook; 267 uint32_t ns_identified; 268 uint32_t queues_created; 269 270 struct task reset_task; 271 struct task fail_req_task; 272 struct taskqueue *taskqueue; 273 274 /* For shared legacy interrupt. */ 275 int rid; 276 struct resource *res; 277 void *tag; 278 279 bus_dma_tag_t hw_desc_tag; 280 bus_dmamap_t hw_desc_map; 281 282 /** maximum i/o size in bytes */ 283 uint32_t max_xfer_size; 284 285 /** minimum page size supported by this controller in bytes */ 286 uint32_t min_page_size; 287 288 /** interrupt coalescing time period (in microseconds) */ 289 uint32_t int_coal_time; 290 291 /** interrupt coalescing threshold */ 292 uint32_t int_coal_threshold; 293 294 /** timeout period in seconds */ 295 uint32_t timeout_period; 296 297 struct nvme_qpair adminq; 298 struct nvme_qpair *ioq; 299 300 struct nvme_registers *regs; 301 302 struct nvme_controller_data cdata; 303 struct nvme_namespace ns[NVME_MAX_NAMESPACES]; 304 305 struct cdev *cdev; 306 307 /** bit mask of event types currently enabled for async events */ 308 uint32_t async_event_config; 309 310 uint32_t num_aers; 311 struct nvme_async_event_request aer[NVME_MAX_ASYNC_EVENTS]; 312 313 void *cons_cookie[NVME_MAX_CONSUMERS]; 314 315 uint32_t is_resetting; 316 uint32_t is_initialized; 317 uint32_t notification_sent; 318 319 boolean_t is_failed; 320 STAILQ_HEAD(, nvme_request) fail_req; 321 }; 322 323 #define nvme_mmio_offsetof(reg) \ 324 offsetof(struct nvme_registers, reg) 325 326 #define nvme_mmio_read_4(sc, reg) \ 327 bus_space_read_4((sc)->bus_tag, (sc)->bus_handle, \ 328 nvme_mmio_offsetof(reg)) 329 330 #define nvme_mmio_write_4(sc, reg, val) \ 331 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 332 nvme_mmio_offsetof(reg), val) 333 334 #define nvme_mmio_write_8(sc, reg, val) \ 335 do { \ 336 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 337 nvme_mmio_offsetof(reg), val & 0xFFFFFFFF); \ 338 bus_space_write_4((sc)->bus_tag, (sc)->bus_handle, \ 339 nvme_mmio_offsetof(reg)+4, \ 340 (val & 0xFFFFFFFF00000000ULL) >> 32); \ 341 } while (0); 342 343 #define nvme_printf(ctrlr, fmt, args...) \ 344 device_printf(ctrlr->dev, fmt, ##args) 345 346 void nvme_ns_test(struct nvme_namespace *ns, u_long cmd, caddr_t arg); 347 348 void nvme_ctrlr_cmd_identify_controller(struct nvme_controller *ctrlr, 349 void *payload, 350 nvme_cb_fn_t cb_fn, void *cb_arg); 351 void nvme_ctrlr_cmd_identify_namespace(struct nvme_controller *ctrlr, 352 uint32_t nsid, void *payload, 353 nvme_cb_fn_t cb_fn, void *cb_arg); 354 void nvme_ctrlr_cmd_set_interrupt_coalescing(struct nvme_controller *ctrlr, 355 uint32_t microseconds, 356 uint32_t threshold, 357 nvme_cb_fn_t cb_fn, 358 void *cb_arg); 359 void nvme_ctrlr_cmd_get_error_page(struct nvme_controller *ctrlr, 360 struct nvme_error_information_entry *payload, 361 uint32_t num_entries, /* 0 = max */ 362 nvme_cb_fn_t cb_fn, 363 void *cb_arg); 364 void nvme_ctrlr_cmd_get_health_information_page(struct nvme_controller *ctrlr, 365 uint32_t nsid, 366 struct nvme_health_information_page *payload, 367 nvme_cb_fn_t cb_fn, 368 void *cb_arg); 369 void nvme_ctrlr_cmd_get_firmware_page(struct nvme_controller *ctrlr, 370 struct nvme_firmware_page *payload, 371 nvme_cb_fn_t cb_fn, 372 void *cb_arg); 373 void nvme_ctrlr_cmd_create_io_cq(struct nvme_controller *ctrlr, 374 struct nvme_qpair *io_que, uint16_t vector, 375 nvme_cb_fn_t cb_fn, void *cb_arg); 376 void nvme_ctrlr_cmd_create_io_sq(struct nvme_controller *ctrlr, 377 struct nvme_qpair *io_que, 378 nvme_cb_fn_t cb_fn, void *cb_arg); 379 void nvme_ctrlr_cmd_delete_io_cq(struct nvme_controller *ctrlr, 380 struct nvme_qpair *io_que, 381 nvme_cb_fn_t cb_fn, void *cb_arg); 382 void nvme_ctrlr_cmd_delete_io_sq(struct nvme_controller *ctrlr, 383 struct nvme_qpair *io_que, 384 nvme_cb_fn_t cb_fn, void *cb_arg); 385 void nvme_ctrlr_cmd_set_num_queues(struct nvme_controller *ctrlr, 386 uint32_t num_queues, nvme_cb_fn_t cb_fn, 387 void *cb_arg); 388 void nvme_ctrlr_cmd_set_async_event_config(struct nvme_controller *ctrlr, 389 uint32_t state, 390 nvme_cb_fn_t cb_fn, void *cb_arg); 391 void nvme_ctrlr_cmd_abort(struct nvme_controller *ctrlr, uint16_t cid, 392 uint16_t sqid, nvme_cb_fn_t cb_fn, void *cb_arg); 393 394 void nvme_completion_poll_cb(void *arg, const struct nvme_completion *cpl); 395 396 int nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev); 397 void nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev); 398 void nvme_ctrlr_shutdown(struct nvme_controller *ctrlr); 399 int nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr); 400 void nvme_ctrlr_reset(struct nvme_controller *ctrlr); 401 /* ctrlr defined as void * to allow use with config_intrhook. */ 402 void nvme_ctrlr_start_config_hook(void *ctrlr_arg); 403 void nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 404 struct nvme_request *req); 405 void nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 406 struct nvme_request *req); 407 void nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 408 struct nvme_request *req); 409 410 int nvme_qpair_construct(struct nvme_qpair *qpair, uint32_t id, 411 uint16_t vector, uint32_t num_entries, 412 uint32_t num_trackers, 413 struct nvme_controller *ctrlr); 414 void nvme_qpair_submit_tracker(struct nvme_qpair *qpair, 415 struct nvme_tracker *tr); 416 bool nvme_qpair_process_completions(struct nvme_qpair *qpair); 417 void nvme_qpair_submit_request(struct nvme_qpair *qpair, 418 struct nvme_request *req); 419 void nvme_qpair_reset(struct nvme_qpair *qpair); 420 void nvme_qpair_fail(struct nvme_qpair *qpair); 421 void nvme_qpair_manual_complete_request(struct nvme_qpair *qpair, 422 struct nvme_request *req, 423 uint32_t sct, uint32_t sc); 424 425 void nvme_admin_qpair_enable(struct nvme_qpair *qpair); 426 void nvme_admin_qpair_disable(struct nvme_qpair *qpair); 427 void nvme_admin_qpair_destroy(struct nvme_qpair *qpair); 428 429 void nvme_io_qpair_enable(struct nvme_qpair *qpair); 430 void nvme_io_qpair_disable(struct nvme_qpair *qpair); 431 void nvme_io_qpair_destroy(struct nvme_qpair *qpair); 432 433 int nvme_ns_construct(struct nvme_namespace *ns, uint32_t id, 434 struct nvme_controller *ctrlr); 435 void nvme_ns_destruct(struct nvme_namespace *ns); 436 437 void nvme_sysctl_initialize_ctrlr(struct nvme_controller *ctrlr); 438 439 void nvme_dump_command(struct nvme_command *cmd); 440 void nvme_dump_completion(struct nvme_completion *cpl); 441 442 static __inline void 443 nvme_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) 444 { 445 uint64_t *bus_addr = (uint64_t *)arg; 446 447 if (error != 0) 448 printf("nvme_single_map err %d\n", error); 449 *bus_addr = seg[0].ds_addr; 450 } 451 452 static __inline struct nvme_request * 453 _nvme_allocate_request(nvme_cb_fn_t cb_fn, void *cb_arg) 454 { 455 struct nvme_request *req; 456 457 req = uma_zalloc(nvme_request_zone, M_NOWAIT | M_ZERO); 458 if (req != NULL) { 459 req->cb_fn = cb_fn; 460 req->cb_arg = cb_arg; 461 req->timeout = TRUE; 462 } 463 return (req); 464 } 465 466 static __inline struct nvme_request * 467 nvme_allocate_request_vaddr(void *payload, uint32_t payload_size, 468 nvme_cb_fn_t cb_fn, void *cb_arg) 469 { 470 struct nvme_request *req; 471 472 req = _nvme_allocate_request(cb_fn, cb_arg); 473 if (req != NULL) { 474 req->type = NVME_REQUEST_VADDR; 475 req->u.payload = payload; 476 req->payload_size = payload_size; 477 } 478 return (req); 479 } 480 481 static __inline struct nvme_request * 482 nvme_allocate_request_null(nvme_cb_fn_t cb_fn, void *cb_arg) 483 { 484 struct nvme_request *req; 485 486 req = _nvme_allocate_request(cb_fn, cb_arg); 487 if (req != NULL) 488 req->type = NVME_REQUEST_NULL; 489 return (req); 490 } 491 492 static __inline struct nvme_request * 493 nvme_allocate_request_bio(struct bio *bio, nvme_cb_fn_t cb_fn, void *cb_arg) 494 { 495 struct nvme_request *req; 496 497 req = _nvme_allocate_request(cb_fn, cb_arg); 498 if (req != NULL) { 499 req->type = NVME_REQUEST_BIO; 500 req->u.bio = bio; 501 } 502 return (req); 503 } 504 505 static __inline struct nvme_request * 506 nvme_allocate_request_ccb(union ccb *ccb, nvme_cb_fn_t cb_fn, void *cb_arg) 507 { 508 struct nvme_request *req; 509 510 req = _nvme_allocate_request(cb_fn, cb_arg); 511 if (req != NULL) { 512 req->type = NVME_REQUEST_CCB; 513 req->u.payload = ccb; 514 } 515 516 return (req); 517 } 518 519 #define nvme_free_request(req) uma_zfree(nvme_request_zone, req) 520 521 void nvme_notify_async_consumers(struct nvme_controller *ctrlr, 522 const struct nvme_completion *async_cpl, 523 uint32_t log_page_id, void *log_page_buffer, 524 uint32_t log_page_size); 525 void nvme_notify_fail_consumers(struct nvme_controller *ctrlr); 526 void nvme_notify_new_controller(struct nvme_controller *ctrlr); 527 void nvme_notify_ns(struct nvme_controller *ctrlr, int nsid); 528 529 void nvme_ctrlr_intx_handler(void *arg); 530 void nvme_ctrlr_poll(struct nvme_controller *ctrlr); 531 532 #endif /* __NVME_PRIVATE_H__ */ 533