1 /*- 2 * Copyright (C) 2012-2016 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/buf.h> 31 #include <sys/bus.h> 32 #include <sys/conf.h> 33 #include <sys/proc.h> 34 #include <sys/smp.h> 35 #include <vm/vm.h> 36 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include "nvme_private.h" 41 42 static int nvme_pci_probe(device_t); 43 static int nvme_pci_attach(device_t); 44 static int nvme_pci_detach(device_t); 45 static int nvme_pci_suspend(device_t); 46 static int nvme_pci_resume(device_t); 47 48 static int nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); 49 50 static device_method_t nvme_pci_methods[] = { 51 /* Device interface */ 52 DEVMETHOD(device_probe, nvme_pci_probe), 53 DEVMETHOD(device_attach, nvme_pci_attach), 54 DEVMETHOD(device_detach, nvme_pci_detach), 55 DEVMETHOD(device_suspend, nvme_pci_suspend), 56 DEVMETHOD(device_resume, nvme_pci_resume), 57 DEVMETHOD(device_shutdown, nvme_shutdown), 58 { 0, 0 } 59 }; 60 61 static driver_t nvme_pci_driver = { 62 "nvme", 63 nvme_pci_methods, 64 sizeof(struct nvme_controller), 65 }; 66 67 DRIVER_MODULE(nvme, pci, nvme_pci_driver, NULL, NULL); 68 69 static struct _pcsid 70 { 71 uint32_t devid; 72 int match_subdevice; 73 uint16_t subdevice; 74 const char *desc; 75 uint32_t quirks; 76 } pci_ids[] = { 77 { 0x01118086, 0, 0, "NVMe Controller" }, 78 { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, 79 { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, 80 { 0x09538086, 1, 0x3702, "DC P3700 SSD" }, 81 { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, 82 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, 83 { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, 84 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, 85 { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, 86 { 0x09538086, 0, 0, "Intel DC PC3500", QUIRK_INTEL_ALIGNMENT }, 87 { 0x0a538086, 0, 0, "Intel DC PC3520", QUIRK_INTEL_ALIGNMENT }, 88 { 0x0a548086, 0, 0, "Intel DC PC4500", QUIRK_INTEL_ALIGNMENT }, 89 { 0x0a558086, 0, 0, "Dell Intel P4600", QUIRK_INTEL_ALIGNMENT }, 90 { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY }, 91 { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY }, 92 { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY }, 93 { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY }, 94 { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY }, 95 { 0x07f015ad, 0, 0, "VMware NVMe Controller" }, 96 { 0x2003106b, 0, 0, "Apple S3X NVMe Controller" }, 97 { 0x00000000, 0, 0, NULL } 98 }; 99 100 static int 101 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) 102 { 103 if (devid != ep->devid) 104 return 0; 105 106 if (!ep->match_subdevice) 107 return 1; 108 109 if (subdevice == ep->subdevice) 110 return 1; 111 else 112 return 0; 113 } 114 115 static int 116 nvme_pci_probe (device_t device) 117 { 118 struct nvme_controller *ctrlr = DEVICE2SOFTC(device); 119 struct _pcsid *ep; 120 uint32_t devid; 121 uint16_t subdevice; 122 123 devid = pci_get_devid(device); 124 subdevice = pci_get_subdevice(device); 125 ep = pci_ids; 126 127 while (ep->devid) { 128 if (nvme_match(devid, subdevice, ep)) 129 break; 130 ++ep; 131 } 132 if (ep->devid) 133 ctrlr->quirks = ep->quirks; 134 135 if (ep->desc) { 136 device_set_desc(device, ep->desc); 137 return (BUS_PROBE_DEFAULT); 138 } 139 140 #if defined(PCIS_STORAGE_NVM) 141 if (pci_get_class(device) == PCIC_STORAGE && 142 pci_get_subclass(device) == PCIS_STORAGE_NVM && 143 pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) { 144 device_set_desc(device, "Generic NVMe Device"); 145 return (BUS_PROBE_GENERIC); 146 } 147 #endif 148 149 return (ENXIO); 150 } 151 152 static int 153 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 154 { 155 156 ctrlr->resource_id = PCIR_BAR(0); 157 158 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 159 &ctrlr->resource_id, RF_ACTIVE); 160 161 if(ctrlr->resource == NULL) { 162 nvme_printf(ctrlr, "unable to allocate pci resource\n"); 163 return (ENOMEM); 164 } 165 166 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 167 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 168 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 169 170 /* 171 * The NVMe spec allows for the MSI-X table to be placed behind 172 * BAR 4/5, separate from the control/doorbell registers. Always 173 * try to map this bar, because it must be mapped prior to calling 174 * pci_alloc_msix(). If the table isn't behind BAR 4/5, 175 * bus_alloc_resource() will just return NULL which is OK. 176 */ 177 ctrlr->bar4_resource_id = PCIR_BAR(4); 178 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 179 &ctrlr->bar4_resource_id, RF_ACTIVE); 180 181 return (0); 182 } 183 184 static int 185 nvme_pci_attach(device_t dev) 186 { 187 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 188 int status; 189 190 ctrlr->dev = dev; 191 status = nvme_ctrlr_allocate_bar(ctrlr); 192 if (status != 0) 193 goto bad; 194 pci_enable_busmaster(dev); 195 status = nvme_ctrlr_setup_interrupts(ctrlr); 196 if (status != 0) 197 goto bad; 198 return nvme_attach(dev); 199 bad: 200 if (ctrlr->resource != NULL) { 201 bus_release_resource(dev, SYS_RES_MEMORY, 202 ctrlr->resource_id, ctrlr->resource); 203 } 204 205 if (ctrlr->bar4_resource != NULL) { 206 bus_release_resource(dev, SYS_RES_MEMORY, 207 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 208 } 209 210 if (ctrlr->tag) 211 bus_teardown_intr(dev, ctrlr->res, ctrlr->tag); 212 213 if (ctrlr->res) 214 bus_release_resource(dev, SYS_RES_IRQ, 215 rman_get_rid(ctrlr->res), ctrlr->res); 216 217 if (ctrlr->msi_count > 0) 218 pci_release_msi(dev); 219 220 return status; 221 } 222 223 static int 224 nvme_pci_detach(device_t dev) 225 { 226 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 227 int rv; 228 229 rv = nvme_detach(dev); 230 if (ctrlr->msi_count > 0) 231 pci_release_msi(dev); 232 pci_disable_busmaster(dev); 233 return (rv); 234 } 235 236 static int 237 nvme_ctrlr_setup_shared(struct nvme_controller *ctrlr, int rid) 238 { 239 int error; 240 241 ctrlr->num_io_queues = 1; 242 ctrlr->rid = rid; 243 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 244 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 245 if (ctrlr->res == NULL) { 246 nvme_printf(ctrlr, "unable to allocate shared interrupt\n"); 247 return (ENOMEM); 248 } 249 250 error = bus_setup_intr(ctrlr->dev, ctrlr->res, 251 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_shared_handler, 252 ctrlr, &ctrlr->tag); 253 if (error) { 254 nvme_printf(ctrlr, "unable to setup shared interrupt\n"); 255 return (error); 256 } 257 258 return (0); 259 } 260 261 static int 262 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) 263 { 264 device_t dev; 265 int force_intx, num_io_queues, per_cpu_io_queues; 266 int min_cpus_per_ioq; 267 int num_vectors_requested; 268 269 dev = ctrlr->dev; 270 271 force_intx = 0; 272 TUNABLE_INT_FETCH("hw.nvme.force_intx", &force_intx); 273 if (force_intx) 274 return (nvme_ctrlr_setup_shared(ctrlr, 0)); 275 276 if (pci_msix_count(dev) == 0) 277 goto msi; 278 279 /* 280 * Try to allocate one MSI-X per core for I/O queues, plus one 281 * for admin queue, but accept single shared MSI-X if have to. 282 * Fall back to MSI if can't get any MSI-X. 283 */ 284 num_io_queues = mp_ncpus; 285 TUNABLE_INT_FETCH("hw.nvme.num_io_queues", &num_io_queues); 286 if (num_io_queues < 1 || num_io_queues > mp_ncpus) 287 num_io_queues = mp_ncpus; 288 289 per_cpu_io_queues = 1; 290 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 291 if (per_cpu_io_queues == 0) 292 num_io_queues = 1; 293 294 min_cpus_per_ioq = smp_threads_per_core; 295 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); 296 if (min_cpus_per_ioq > 1) { 297 num_io_queues = min(num_io_queues, 298 max(1, mp_ncpus / min_cpus_per_ioq)); 299 } 300 301 num_io_queues = min(num_io_queues, max(1, pci_msix_count(dev) - 1)); 302 303 again: 304 if (num_io_queues > vm_ndomains) 305 num_io_queues -= num_io_queues % vm_ndomains; 306 num_vectors_requested = min(num_io_queues + 1, pci_msix_count(dev)); 307 ctrlr->msi_count = num_vectors_requested; 308 if (pci_alloc_msix(dev, &ctrlr->msi_count) != 0) { 309 nvme_printf(ctrlr, "unable to allocate MSI-X\n"); 310 ctrlr->msi_count = 0; 311 goto msi; 312 } 313 if (ctrlr->msi_count == 1) 314 return (nvme_ctrlr_setup_shared(ctrlr, 1)); 315 if (ctrlr->msi_count != num_vectors_requested) { 316 pci_release_msi(dev); 317 num_io_queues = ctrlr->msi_count - 1; 318 goto again; 319 } 320 321 ctrlr->num_io_queues = num_io_queues; 322 return (0); 323 324 msi: 325 /* 326 * Try to allocate 2 MSIs (admin and I/O queues), but accept single 327 * shared if have to. Fall back to INTx if can't get any MSI. 328 */ 329 ctrlr->msi_count = min(pci_msi_count(dev), 2); 330 if (ctrlr->msi_count > 0) { 331 if (pci_alloc_msi(dev, &ctrlr->msi_count) != 0) { 332 nvme_printf(ctrlr, "unable to allocate MSI\n"); 333 ctrlr->msi_count = 0; 334 } else if (ctrlr->msi_count == 2) { 335 ctrlr->num_io_queues = 1; 336 return (0); 337 } 338 } 339 return (nvme_ctrlr_setup_shared(ctrlr, ctrlr->msi_count > 0 ? 1 : 0)); 340 } 341 342 static int 343 nvme_pci_suspend(device_t dev) 344 { 345 struct nvme_controller *ctrlr; 346 347 ctrlr = DEVICE2SOFTC(dev); 348 return (nvme_ctrlr_suspend(ctrlr)); 349 } 350 351 static int 352 nvme_pci_resume(device_t dev) 353 { 354 struct nvme_controller *ctrlr; 355 356 ctrlr = DEVICE2SOFTC(dev); 357 return (nvme_ctrlr_resume(ctrlr)); 358 } 359