1 /*- 2 * Copyright (C) 2012-2016 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 #include <vm/vm.h> 38 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 42 #include "nvme_private.h" 43 44 static int nvme_pci_probe(device_t); 45 static int nvme_pci_attach(device_t); 46 static int nvme_pci_detach(device_t); 47 static int nvme_pci_suspend(device_t); 48 static int nvme_pci_resume(device_t); 49 50 static int nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); 51 52 static device_method_t nvme_pci_methods[] = { 53 /* Device interface */ 54 DEVMETHOD(device_probe, nvme_pci_probe), 55 DEVMETHOD(device_attach, nvme_pci_attach), 56 DEVMETHOD(device_detach, nvme_pci_detach), 57 DEVMETHOD(device_suspend, nvme_pci_suspend), 58 DEVMETHOD(device_resume, nvme_pci_resume), 59 DEVMETHOD(device_shutdown, nvme_shutdown), 60 { 0, 0 } 61 }; 62 63 static driver_t nvme_pci_driver = { 64 "nvme", 65 nvme_pci_methods, 66 sizeof(struct nvme_controller), 67 }; 68 69 DRIVER_MODULE(nvme, pci, nvme_pci_driver, NULL, NULL); 70 71 static struct _pcsid 72 { 73 uint32_t devid; 74 int match_subdevice; 75 uint16_t subdevice; 76 const char *desc; 77 uint32_t quirks; 78 } pci_ids[] = { 79 { 0x01118086, 0, 0, "NVMe Controller" }, 80 { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, 81 { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, 82 { 0x09538086, 1, 0x3702, "DC P3700 SSD" }, 83 { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, 84 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, 85 { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, 86 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, 87 { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, 88 { 0x09538086, 0, 0, "Intel DC PC3500", QUIRK_INTEL_ALIGNMENT }, 89 { 0x0a538086, 0, 0, "Intel DC PC3520", QUIRK_INTEL_ALIGNMENT }, 90 { 0x0a548086, 0, 0, "Intel DC PC4500", QUIRK_INTEL_ALIGNMENT }, 91 { 0x0a558086, 0, 0, "Dell Intel P4600", QUIRK_INTEL_ALIGNMENT }, 92 { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY }, 93 { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY }, 94 { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY }, 95 { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY }, 96 { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY }, 97 { 0x07f015ad, 0, 0, "VMware NVMe Controller" }, 98 { 0x2003106b, 0, 0, "Apple S3X NVMe Controller" }, 99 { 0x00000000, 0, 0, NULL } 100 }; 101 102 static int 103 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) 104 { 105 if (devid != ep->devid) 106 return 0; 107 108 if (!ep->match_subdevice) 109 return 1; 110 111 if (subdevice == ep->subdevice) 112 return 1; 113 else 114 return 0; 115 } 116 117 static int 118 nvme_pci_probe (device_t device) 119 { 120 struct nvme_controller *ctrlr = DEVICE2SOFTC(device); 121 struct _pcsid *ep; 122 uint32_t devid; 123 uint16_t subdevice; 124 125 devid = pci_get_devid(device); 126 subdevice = pci_get_subdevice(device); 127 ep = pci_ids; 128 129 while (ep->devid) { 130 if (nvme_match(devid, subdevice, ep)) 131 break; 132 ++ep; 133 } 134 if (ep->devid) 135 ctrlr->quirks = ep->quirks; 136 137 if (ep->desc) { 138 device_set_desc(device, ep->desc); 139 return (BUS_PROBE_DEFAULT); 140 } 141 142 #if defined(PCIS_STORAGE_NVM) 143 if (pci_get_class(device) == PCIC_STORAGE && 144 pci_get_subclass(device) == PCIS_STORAGE_NVM && 145 pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) { 146 device_set_desc(device, "Generic NVMe Device"); 147 return (BUS_PROBE_GENERIC); 148 } 149 #endif 150 151 return (ENXIO); 152 } 153 154 static int 155 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 156 { 157 158 ctrlr->resource_id = PCIR_BAR(0); 159 160 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 161 &ctrlr->resource_id, RF_ACTIVE); 162 163 if(ctrlr->resource == NULL) { 164 nvme_printf(ctrlr, "unable to allocate pci resource\n"); 165 return (ENOMEM); 166 } 167 168 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 169 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 170 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 171 172 /* 173 * The NVMe spec allows for the MSI-X table to be placed behind 174 * BAR 4/5, separate from the control/doorbell registers. Always 175 * try to map this bar, because it must be mapped prior to calling 176 * pci_alloc_msix(). If the table isn't behind BAR 4/5, 177 * bus_alloc_resource() will just return NULL which is OK. 178 */ 179 ctrlr->bar4_resource_id = PCIR_BAR(4); 180 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 181 &ctrlr->bar4_resource_id, RF_ACTIVE); 182 183 return (0); 184 } 185 186 static int 187 nvme_pci_attach(device_t dev) 188 { 189 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 190 int status; 191 192 ctrlr->dev = dev; 193 status = nvme_ctrlr_allocate_bar(ctrlr); 194 if (status != 0) 195 goto bad; 196 pci_enable_busmaster(dev); 197 status = nvme_ctrlr_setup_interrupts(ctrlr); 198 if (status != 0) 199 goto bad; 200 return nvme_attach(dev); 201 bad: 202 if (ctrlr->resource != NULL) { 203 bus_release_resource(dev, SYS_RES_MEMORY, 204 ctrlr->resource_id, ctrlr->resource); 205 } 206 207 if (ctrlr->bar4_resource != NULL) { 208 bus_release_resource(dev, SYS_RES_MEMORY, 209 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 210 } 211 212 if (ctrlr->tag) 213 bus_teardown_intr(dev, ctrlr->res, ctrlr->tag); 214 215 if (ctrlr->res) 216 bus_release_resource(dev, SYS_RES_IRQ, 217 rman_get_rid(ctrlr->res), ctrlr->res); 218 219 if (ctrlr->msi_count > 0) 220 pci_release_msi(dev); 221 222 return status; 223 } 224 225 static int 226 nvme_pci_detach(device_t dev) 227 { 228 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 229 int rv; 230 231 rv = nvme_detach(dev); 232 if (ctrlr->msi_count > 0) 233 pci_release_msi(dev); 234 pci_disable_busmaster(dev); 235 return (rv); 236 } 237 238 static int 239 nvme_ctrlr_setup_shared(struct nvme_controller *ctrlr, int rid) 240 { 241 int error; 242 243 ctrlr->num_io_queues = 1; 244 ctrlr->rid = rid; 245 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 246 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 247 if (ctrlr->res == NULL) { 248 nvme_printf(ctrlr, "unable to allocate shared interrupt\n"); 249 return (ENOMEM); 250 } 251 252 error = bus_setup_intr(ctrlr->dev, ctrlr->res, 253 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_shared_handler, 254 ctrlr, &ctrlr->tag); 255 if (error) { 256 nvme_printf(ctrlr, "unable to setup shared interrupt\n"); 257 return (error); 258 } 259 260 return (0); 261 } 262 263 static int 264 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) 265 { 266 device_t dev; 267 int force_intx, num_io_queues, per_cpu_io_queues; 268 int min_cpus_per_ioq; 269 int num_vectors_requested; 270 271 dev = ctrlr->dev; 272 273 force_intx = 0; 274 TUNABLE_INT_FETCH("hw.nvme.force_intx", &force_intx); 275 if (force_intx) 276 return (nvme_ctrlr_setup_shared(ctrlr, 0)); 277 278 if (pci_msix_count(dev) == 0) 279 goto msi; 280 281 /* 282 * Try to allocate one MSI-X per core for I/O queues, plus one 283 * for admin queue, but accept single shared MSI-X if have to. 284 * Fall back to MSI if can't get any MSI-X. 285 */ 286 num_io_queues = mp_ncpus; 287 TUNABLE_INT_FETCH("hw.nvme.num_io_queues", &num_io_queues); 288 if (num_io_queues < 1 || num_io_queues > mp_ncpus) 289 num_io_queues = mp_ncpus; 290 291 per_cpu_io_queues = 1; 292 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 293 if (per_cpu_io_queues == 0) 294 num_io_queues = 1; 295 296 min_cpus_per_ioq = smp_threads_per_core; 297 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); 298 if (min_cpus_per_ioq > 1) { 299 num_io_queues = min(num_io_queues, 300 max(1, mp_ncpus / min_cpus_per_ioq)); 301 } 302 303 num_io_queues = min(num_io_queues, max(1, pci_msix_count(dev) - 1)); 304 305 again: 306 if (num_io_queues > vm_ndomains) 307 num_io_queues -= num_io_queues % vm_ndomains; 308 num_vectors_requested = min(num_io_queues + 1, pci_msix_count(dev)); 309 ctrlr->msi_count = num_vectors_requested; 310 if (pci_alloc_msix(dev, &ctrlr->msi_count) != 0) { 311 nvme_printf(ctrlr, "unable to allocate MSI-X\n"); 312 ctrlr->msi_count = 0; 313 goto msi; 314 } 315 if (ctrlr->msi_count == 1) 316 return (nvme_ctrlr_setup_shared(ctrlr, 1)); 317 if (ctrlr->msi_count != num_vectors_requested) { 318 pci_release_msi(dev); 319 num_io_queues = ctrlr->msi_count - 1; 320 goto again; 321 } 322 323 ctrlr->num_io_queues = num_io_queues; 324 return (0); 325 326 msi: 327 /* 328 * Try to allocate 2 MSIs (admin and I/O queues), but accept single 329 * shared if have to. Fall back to INTx if can't get any MSI. 330 */ 331 ctrlr->msi_count = min(pci_msi_count(dev), 2); 332 if (ctrlr->msi_count > 0) { 333 if (pci_alloc_msi(dev, &ctrlr->msi_count) != 0) { 334 nvme_printf(ctrlr, "unable to allocate MSI\n"); 335 ctrlr->msi_count = 0; 336 } else if (ctrlr->msi_count == 2) { 337 ctrlr->num_io_queues = 1; 338 return (0); 339 } 340 } 341 return (nvme_ctrlr_setup_shared(ctrlr, ctrlr->msi_count > 0 ? 1 : 0)); 342 } 343 344 static int 345 nvme_pci_suspend(device_t dev) 346 { 347 struct nvme_controller *ctrlr; 348 349 ctrlr = DEVICE2SOFTC(dev); 350 return (nvme_ctrlr_suspend(ctrlr)); 351 } 352 353 static int 354 nvme_pci_resume(device_t dev) 355 { 356 struct nvme_controller *ctrlr; 357 358 ctrlr = DEVICE2SOFTC(dev); 359 return (nvme_ctrlr_resume(ctrlr)); 360 } 361