xref: /freebsd/sys/dev/nvme/nvme_pci.c (revision 8651679a5c022f780d48a11d08e105a357e9fd75)
1 /*-
2  * Copyright (C) 2012-2016 Intel Corporation
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/buf.h>
33 #include <sys/bus.h>
34 #include <sys/conf.h>
35 #include <sys/proc.h>
36 #include <sys/smp.h>
37 
38 #include <dev/pci/pcireg.h>
39 #include <dev/pci/pcivar.h>
40 
41 #include "nvme_private.h"
42 
43 static int    nvme_pci_probe(device_t);
44 static int    nvme_pci_attach(device_t);
45 static int    nvme_pci_detach(device_t);
46 
47 static void nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr);
48 
49 static device_method_t nvme_pci_methods[] = {
50 	/* Device interface */
51 	DEVMETHOD(device_probe,     nvme_pci_probe),
52 	DEVMETHOD(device_attach,    nvme_pci_attach),
53 	DEVMETHOD(device_detach,    nvme_pci_detach),
54 	DEVMETHOD(device_shutdown,  nvme_shutdown),
55 	{ 0, 0 }
56 };
57 
58 static driver_t nvme_pci_driver = {
59 	"nvme",
60 	nvme_pci_methods,
61 	sizeof(struct nvme_controller),
62 };
63 
64 DRIVER_MODULE(nvme, pci, nvme_pci_driver, nvme_devclass, NULL, 0);
65 MODULE_VERSION(nvme, 1);
66 MODULE_DEPEND(nvme, cam, 1, 1, 1);
67 
68 static struct _pcsid
69 {
70 	uint32_t	devid;
71 	int		match_subdevice;
72 	uint16_t	subdevice;
73 	const char	*desc;
74 	uint32_t	quirks;
75 } pci_ids[] = {
76 	{ 0x01118086,		0, 0, "NVMe Controller"  },
77 	{ IDT32_PCI_ID,		0, 0, "IDT NVMe Controller (32 channel)"  },
78 	{ IDT8_PCI_ID,		0, 0, "IDT NVMe Controller (8 channel)" },
79 	{ 0x09538086,		1, 0x3702, "DC P3700 SSD" },
80 	{ 0x09538086,		1, 0x3703, "DC P3700 SSD [2.5\" SFF]" },
81 	{ 0x09538086,		1, 0x3704, "DC P3500 SSD [Add-in Card]" },
82 	{ 0x09538086,		1, 0x3705, "DC P3500 SSD [2.5\" SFF]" },
83 	{ 0x09538086,		1, 0x3709, "DC P3600 SSD [Add-in Card]" },
84 	{ 0x09538086,		1, 0x370a, "DC P3600 SSD [2.5\" SFF]" },
85 	{ 0x00031c58,		0, 0, "HGST SN100",	QUIRK_DELAY_B4_CHK_RDY },
86 	{ 0x00231c58,		0, 0, "WDC SN200",	QUIRK_DELAY_B4_CHK_RDY },
87 	{ 0x05401c5f,		0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY },
88 	{ 0xa821144d,		0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY },
89 	{ 0xa822144d,		0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY },
90 	{ 0x00000000,		0, 0, NULL  }
91 };
92 
93 
94 static int
95 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep)
96 {
97 	if (devid != ep->devid)
98 		return 0;
99 
100 	if (!ep->match_subdevice)
101 		return 1;
102 
103 	if (subdevice == ep->subdevice)
104 		return 1;
105 	else
106 		return 0;
107 }
108 
109 static int
110 nvme_pci_probe (device_t device)
111 {
112 	struct nvme_controller *ctrlr = DEVICE2SOFTC(device);
113 	struct _pcsid	*ep;
114 	uint32_t	devid;
115 	uint16_t	subdevice;
116 
117 	devid = pci_get_devid(device);
118 	subdevice = pci_get_subdevice(device);
119 	ep = pci_ids;
120 
121 	while (ep->devid) {
122 		if (nvme_match(devid, subdevice, ep))
123 			break;
124 		++ep;
125 	}
126 	if (ep->devid)
127 		ctrlr->quirks = ep->quirks;
128 
129 	if (ep->desc) {
130 		device_set_desc(device, ep->desc);
131 		return (BUS_PROBE_DEFAULT);
132 	}
133 
134 #if defined(PCIS_STORAGE_NVM)
135 	if (pci_get_class(device)    == PCIC_STORAGE &&
136 	    pci_get_subclass(device) == PCIS_STORAGE_NVM &&
137 	    pci_get_progif(device)   == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) {
138 		device_set_desc(device, "Generic NVMe Device");
139 		return (BUS_PROBE_GENERIC);
140 	}
141 #endif
142 
143 	return (ENXIO);
144 }
145 
146 static int
147 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr)
148 {
149 
150 	ctrlr->resource_id = PCIR_BAR(0);
151 
152 	ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
153 	    &ctrlr->resource_id, RF_ACTIVE);
154 
155 	if(ctrlr->resource == NULL) {
156 		nvme_printf(ctrlr, "unable to allocate pci resource\n");
157 		return (ENOMEM);
158 	}
159 
160 	ctrlr->bus_tag = rman_get_bustag(ctrlr->resource);
161 	ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource);
162 	ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle;
163 
164 	/*
165 	 * The NVMe spec allows for the MSI-X table to be placed behind
166 	 *  BAR 4/5, separate from the control/doorbell registers.  Always
167 	 *  try to map this bar, because it must be mapped prior to calling
168 	 *  pci_alloc_msix().  If the table isn't behind BAR 4/5,
169 	 *  bus_alloc_resource() will just return NULL which is OK.
170 	 */
171 	ctrlr->bar4_resource_id = PCIR_BAR(4);
172 	ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
173 	    &ctrlr->bar4_resource_id, RF_ACTIVE);
174 
175 	return (0);
176 }
177 
178 static int
179 nvme_pci_attach(device_t dev)
180 {
181 	struct nvme_controller*ctrlr = DEVICE2SOFTC(dev);
182 	int status;
183 
184 	ctrlr->dev = dev;
185 	status = nvme_ctrlr_allocate_bar(ctrlr);
186 	if (status != 0)
187 		goto bad;
188 	pci_enable_busmaster(dev);
189 	nvme_ctrlr_setup_interrupts(ctrlr);
190 	return nvme_attach(dev);
191 bad:
192 	if (ctrlr->resource != NULL) {
193 		bus_release_resource(dev, SYS_RES_MEMORY,
194 		    ctrlr->resource_id, ctrlr->resource);
195 	}
196 
197 	if (ctrlr->bar4_resource != NULL) {
198 		bus_release_resource(dev, SYS_RES_MEMORY,
199 		    ctrlr->bar4_resource_id, ctrlr->bar4_resource);
200 	}
201 
202 	if (ctrlr->tag)
203 		bus_teardown_intr(dev, ctrlr->res, ctrlr->tag);
204 
205 	if (ctrlr->res)
206 		bus_release_resource(dev, SYS_RES_IRQ,
207 		    rman_get_rid(ctrlr->res), ctrlr->res);
208 
209 	if (ctrlr->msix_enabled)
210 		pci_release_msi(dev);
211 
212 	return status;
213 }
214 
215 static int
216 nvme_pci_detach(device_t dev)
217 {
218 	struct nvme_controller*ctrlr = DEVICE2SOFTC(dev);
219 	int rv;
220 
221 	rv = nvme_detach(dev);
222 	if (ctrlr->msix_enabled)
223 		pci_release_msi(dev);
224 	pci_disable_busmaster(dev);
225 	return (rv);
226 }
227 
228 static int
229 nvme_ctrlr_configure_intx(struct nvme_controller *ctrlr)
230 {
231 
232 	ctrlr->msix_enabled = 0;
233 	ctrlr->num_io_queues = 1;
234 	ctrlr->num_cpus_per_ioq = mp_ncpus;
235 	ctrlr->rid = 0;
236 	ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ,
237 	    &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE);
238 
239 	if (ctrlr->res == NULL) {
240 		nvme_printf(ctrlr, "unable to allocate shared IRQ\n");
241 		return (ENOMEM);
242 	}
243 
244 	bus_setup_intr(ctrlr->dev, ctrlr->res,
245 	    INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler,
246 	    ctrlr, &ctrlr->tag);
247 
248 	if (ctrlr->tag == NULL) {
249 		nvme_printf(ctrlr, "unable to setup intx handler\n");
250 		return (ENOMEM);
251 	}
252 
253 	return (0);
254 }
255 
256 static void
257 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr)
258 {
259 	device_t	dev;
260 	int		per_cpu_io_queues;
261 	int		min_cpus_per_ioq;
262 	int		num_vectors_requested, num_vectors_allocated;
263 	int		num_vectors_available;
264 
265 	dev = ctrlr->dev;
266 	min_cpus_per_ioq = 1;
267 	TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq);
268 
269 	if (min_cpus_per_ioq < 1) {
270 		min_cpus_per_ioq = 1;
271 	} else if (min_cpus_per_ioq > mp_ncpus) {
272 		min_cpus_per_ioq = mp_ncpus;
273 	}
274 
275 	per_cpu_io_queues = 1;
276 	TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues);
277 
278 	if (per_cpu_io_queues == 0) {
279 		min_cpus_per_ioq = mp_ncpus;
280 	}
281 
282 	ctrlr->force_intx = 0;
283 	TUNABLE_INT_FETCH("hw.nvme.force_intx", &ctrlr->force_intx);
284 
285 	/*
286 	 * FreeBSD currently cannot allocate more than about 190 vectors at
287 	 *  boot, meaning that systems with high core count and many devices
288 	 *  requesting per-CPU interrupt vectors will not get their full
289 	 *  allotment.  So first, try to allocate as many as we may need to
290 	 *  understand what is available, then immediately release them.
291 	 *  Then figure out how many of those we will actually use, based on
292 	 *  assigning an equal number of cores to each I/O queue.
293 	 */
294 
295 	/* One vector for per core I/O queue, plus one vector for admin queue. */
296 	num_vectors_available = min(pci_msix_count(dev), mp_ncpus + 1);
297 	if (pci_alloc_msix(dev, &num_vectors_available) != 0) {
298 		num_vectors_available = 0;
299 	}
300 	pci_release_msi(dev);
301 
302 	if (ctrlr->force_intx || num_vectors_available < 2) {
303 		nvme_ctrlr_configure_intx(ctrlr);
304 		return;
305 	}
306 
307 	/*
308 	 * Do not use all vectors for I/O queues - one must be saved for the
309 	 *  admin queue.
310 	 */
311 	ctrlr->num_cpus_per_ioq = max(min_cpus_per_ioq,
312 	    howmany(mp_ncpus, num_vectors_available - 1));
313 
314 	ctrlr->num_io_queues = howmany(mp_ncpus, ctrlr->num_cpus_per_ioq);
315 	num_vectors_requested = ctrlr->num_io_queues + 1;
316 	num_vectors_allocated = num_vectors_requested;
317 
318 	/*
319 	 * Now just allocate the number of vectors we need.  This should
320 	 *  succeed, since we previously called pci_alloc_msix()
321 	 *  successfully returning at least this many vectors, but just to
322 	 *  be safe, if something goes wrong just revert to INTx.
323 	 */
324 	if (pci_alloc_msix(dev, &num_vectors_allocated) != 0) {
325 		nvme_ctrlr_configure_intx(ctrlr);
326 		return;
327 	}
328 
329 	if (num_vectors_allocated < num_vectors_requested) {
330 		pci_release_msi(dev);
331 		nvme_ctrlr_configure_intx(ctrlr);
332 		return;
333 	}
334 
335 	ctrlr->msix_enabled = 1;
336 }
337