1 /*- 2 * Copyright (C) 2012-2016 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 #include <vm/vm.h> 38 39 #include <dev/pci/pcireg.h> 40 #include <dev/pci/pcivar.h> 41 42 #include "nvme_private.h" 43 44 static int nvme_pci_probe(device_t); 45 static int nvme_pci_attach(device_t); 46 static int nvme_pci_detach(device_t); 47 static int nvme_pci_suspend(device_t); 48 static int nvme_pci_resume(device_t); 49 50 static int nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr); 51 52 static device_method_t nvme_pci_methods[] = { 53 /* Device interface */ 54 DEVMETHOD(device_probe, nvme_pci_probe), 55 DEVMETHOD(device_attach, nvme_pci_attach), 56 DEVMETHOD(device_detach, nvme_pci_detach), 57 DEVMETHOD(device_suspend, nvme_pci_suspend), 58 DEVMETHOD(device_resume, nvme_pci_resume), 59 DEVMETHOD(device_shutdown, nvme_shutdown), 60 { 0, 0 } 61 }; 62 63 static driver_t nvme_pci_driver = { 64 "nvme", 65 nvme_pci_methods, 66 sizeof(struct nvme_controller), 67 }; 68 69 DRIVER_MODULE(nvme, pci, nvme_pci_driver, NULL, NULL); 70 71 static struct _pcsid 72 { 73 uint32_t devid; 74 int match_subdevice; 75 uint16_t subdevice; 76 const char *desc; 77 uint32_t quirks; 78 } pci_ids[] = { 79 { 0x01118086, 0, 0, "NVMe Controller" }, 80 { IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" }, 81 { IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" }, 82 { 0x09538086, 1, 0x3702, "DC P3700 SSD" }, 83 { 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" }, 84 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" }, 85 { 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" }, 86 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" }, 87 { 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" }, 88 { 0x09538086, 0, 0, "Intel DC PC3500", QUIRK_INTEL_ALIGNMENT }, 89 { 0x0a538086, 0, 0, "Intel DC PC3520", QUIRK_INTEL_ALIGNMENT }, 90 { 0x0a548086, 0, 0, "Intel DC PC4500", QUIRK_INTEL_ALIGNMENT }, 91 { 0x0a558086, 0, 0, "Dell Intel P4600", QUIRK_INTEL_ALIGNMENT }, 92 { 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY }, 93 { 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY }, 94 { 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY }, 95 { 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY }, 96 { 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY }, 97 { 0x07f015ad, 0, 0, "VMware NVMe Controller" }, 98 { 0x00000000, 0, 0, NULL } 99 }; 100 101 static int 102 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) 103 { 104 if (devid != ep->devid) 105 return 0; 106 107 if (!ep->match_subdevice) 108 return 1; 109 110 if (subdevice == ep->subdevice) 111 return 1; 112 else 113 return 0; 114 } 115 116 static int 117 nvme_pci_probe (device_t device) 118 { 119 struct nvme_controller *ctrlr = DEVICE2SOFTC(device); 120 struct _pcsid *ep; 121 uint32_t devid; 122 uint16_t subdevice; 123 124 devid = pci_get_devid(device); 125 subdevice = pci_get_subdevice(device); 126 ep = pci_ids; 127 128 while (ep->devid) { 129 if (nvme_match(devid, subdevice, ep)) 130 break; 131 ++ep; 132 } 133 if (ep->devid) 134 ctrlr->quirks = ep->quirks; 135 136 if (ep->desc) { 137 device_set_desc(device, ep->desc); 138 return (BUS_PROBE_DEFAULT); 139 } 140 141 #if defined(PCIS_STORAGE_NVM) 142 if (pci_get_class(device) == PCIC_STORAGE && 143 pci_get_subclass(device) == PCIS_STORAGE_NVM && 144 pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) { 145 device_set_desc(device, "Generic NVMe Device"); 146 return (BUS_PROBE_GENERIC); 147 } 148 #endif 149 150 return (ENXIO); 151 } 152 153 static int 154 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 155 { 156 157 ctrlr->resource_id = PCIR_BAR(0); 158 159 ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 160 &ctrlr->resource_id, RF_ACTIVE); 161 162 if(ctrlr->resource == NULL) { 163 nvme_printf(ctrlr, "unable to allocate pci resource\n"); 164 return (ENOMEM); 165 } 166 167 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 168 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 169 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 170 171 /* 172 * The NVMe spec allows for the MSI-X table to be placed behind 173 * BAR 4/5, separate from the control/doorbell registers. Always 174 * try to map this bar, because it must be mapped prior to calling 175 * pci_alloc_msix(). If the table isn't behind BAR 4/5, 176 * bus_alloc_resource() will just return NULL which is OK. 177 */ 178 ctrlr->bar4_resource_id = PCIR_BAR(4); 179 ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY, 180 &ctrlr->bar4_resource_id, RF_ACTIVE); 181 182 return (0); 183 } 184 185 static int 186 nvme_pci_attach(device_t dev) 187 { 188 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 189 int status; 190 191 ctrlr->dev = dev; 192 status = nvme_ctrlr_allocate_bar(ctrlr); 193 if (status != 0) 194 goto bad; 195 pci_enable_busmaster(dev); 196 status = nvme_ctrlr_setup_interrupts(ctrlr); 197 if (status != 0) 198 goto bad; 199 return nvme_attach(dev); 200 bad: 201 if (ctrlr->resource != NULL) { 202 bus_release_resource(dev, SYS_RES_MEMORY, 203 ctrlr->resource_id, ctrlr->resource); 204 } 205 206 if (ctrlr->bar4_resource != NULL) { 207 bus_release_resource(dev, SYS_RES_MEMORY, 208 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 209 } 210 211 if (ctrlr->tag) 212 bus_teardown_intr(dev, ctrlr->res, ctrlr->tag); 213 214 if (ctrlr->res) 215 bus_release_resource(dev, SYS_RES_IRQ, 216 rman_get_rid(ctrlr->res), ctrlr->res); 217 218 if (ctrlr->msi_count > 0) 219 pci_release_msi(dev); 220 221 return status; 222 } 223 224 static int 225 nvme_pci_detach(device_t dev) 226 { 227 struct nvme_controller*ctrlr = DEVICE2SOFTC(dev); 228 int rv; 229 230 rv = nvme_detach(dev); 231 if (ctrlr->msi_count > 0) 232 pci_release_msi(dev); 233 pci_disable_busmaster(dev); 234 return (rv); 235 } 236 237 static int 238 nvme_ctrlr_setup_shared(struct nvme_controller *ctrlr, int rid) 239 { 240 int error; 241 242 ctrlr->num_io_queues = 1; 243 ctrlr->rid = rid; 244 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 245 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 246 if (ctrlr->res == NULL) { 247 nvme_printf(ctrlr, "unable to allocate shared interrupt\n"); 248 return (ENOMEM); 249 } 250 251 error = bus_setup_intr(ctrlr->dev, ctrlr->res, 252 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_shared_handler, 253 ctrlr, &ctrlr->tag); 254 if (error) { 255 nvme_printf(ctrlr, "unable to setup shared interrupt\n"); 256 return (error); 257 } 258 259 return (0); 260 } 261 262 static int 263 nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr) 264 { 265 device_t dev; 266 int force_intx, num_io_queues, per_cpu_io_queues; 267 int min_cpus_per_ioq; 268 int num_vectors_requested; 269 270 dev = ctrlr->dev; 271 272 force_intx = 0; 273 TUNABLE_INT_FETCH("hw.nvme.force_intx", &force_intx); 274 if (force_intx) 275 return (nvme_ctrlr_setup_shared(ctrlr, 0)); 276 277 if (pci_msix_count(dev) == 0) 278 goto msi; 279 280 /* 281 * Try to allocate one MSI-X per core for I/O queues, plus one 282 * for admin queue, but accept single shared MSI-X if have to. 283 * Fall back to MSI if can't get any MSI-X. 284 */ 285 num_io_queues = mp_ncpus; 286 TUNABLE_INT_FETCH("hw.nvme.num_io_queues", &num_io_queues); 287 if (num_io_queues < 1 || num_io_queues > mp_ncpus) 288 num_io_queues = mp_ncpus; 289 290 per_cpu_io_queues = 1; 291 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 292 if (per_cpu_io_queues == 0) 293 num_io_queues = 1; 294 295 min_cpus_per_ioq = smp_threads_per_core; 296 TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq); 297 if (min_cpus_per_ioq > 1) { 298 num_io_queues = min(num_io_queues, 299 max(1, mp_ncpus / min_cpus_per_ioq)); 300 } 301 302 num_io_queues = min(num_io_queues, max(1, pci_msix_count(dev) - 1)); 303 304 again: 305 if (num_io_queues > vm_ndomains) 306 num_io_queues -= num_io_queues % vm_ndomains; 307 num_vectors_requested = min(num_io_queues + 1, pci_msix_count(dev)); 308 ctrlr->msi_count = num_vectors_requested; 309 if (pci_alloc_msix(dev, &ctrlr->msi_count) != 0) { 310 nvme_printf(ctrlr, "unable to allocate MSI-X\n"); 311 ctrlr->msi_count = 0; 312 goto msi; 313 } 314 if (ctrlr->msi_count == 1) 315 return (nvme_ctrlr_setup_shared(ctrlr, 1)); 316 if (ctrlr->msi_count != num_vectors_requested) { 317 pci_release_msi(dev); 318 num_io_queues = ctrlr->msi_count - 1; 319 goto again; 320 } 321 322 ctrlr->num_io_queues = num_io_queues; 323 return (0); 324 325 msi: 326 /* 327 * Try to allocate 2 MSIs (admin and I/O queues), but accept single 328 * shared if have to. Fall back to INTx if can't get any MSI. 329 */ 330 ctrlr->msi_count = min(pci_msi_count(dev), 2); 331 if (ctrlr->msi_count > 0) { 332 if (pci_alloc_msi(dev, &ctrlr->msi_count) != 0) { 333 nvme_printf(ctrlr, "unable to allocate MSI\n"); 334 ctrlr->msi_count = 0; 335 } else if (ctrlr->msi_count == 2) { 336 ctrlr->num_io_queues = 1; 337 return (0); 338 } 339 } 340 return (nvme_ctrlr_setup_shared(ctrlr, ctrlr->msi_count > 0 ? 1 : 0)); 341 } 342 343 static int 344 nvme_pci_suspend(device_t dev) 345 { 346 struct nvme_controller *ctrlr; 347 348 ctrlr = DEVICE2SOFTC(dev); 349 return (nvme_ctrlr_suspend(ctrlr)); 350 } 351 352 static int 353 nvme_pci_resume(device_t dev) 354 { 355 struct nvme_controller *ctrlr; 356 357 ctrlr = DEVICE2SOFTC(dev); 358 return (nvme_ctrlr_resume(ctrlr)); 359 } 360