1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2016 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_cam.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/buf.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/ioccom.h> 40 #include <sys/proc.h> 41 #include <sys/smp.h> 42 #include <sys/uio.h> 43 #include <sys/sbuf.h> 44 #include <sys/endian.h> 45 #include <machine/stdarg.h> 46 #include <vm/vm.h> 47 48 #include "nvme_private.h" 49 50 #define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */ 51 52 static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 53 struct nvme_async_event_request *aer); 54 55 static void 56 nvme_ctrlr_devctl_log(struct nvme_controller *ctrlr, const char *type, const char *msg, ...) 57 { 58 struct sbuf sb; 59 va_list ap; 60 int error; 61 62 if (sbuf_new(&sb, NULL, 0, SBUF_AUTOEXTEND | SBUF_NOWAIT) == NULL) 63 return; 64 sbuf_printf(&sb, "%s: ", device_get_nameunit(ctrlr->dev)); 65 va_start(ap, msg); 66 sbuf_vprintf(&sb, msg, ap); 67 va_end(ap); 68 error = sbuf_finish(&sb); 69 if (error == 0) 70 printf("%s\n", sbuf_data(&sb)); 71 72 sbuf_clear(&sb); 73 sbuf_printf(&sb, "name=\"%s\" reason=\"", device_get_nameunit(ctrlr->dev)); 74 va_start(ap, msg); 75 sbuf_vprintf(&sb, msg, ap); 76 va_end(ap); 77 sbuf_printf(&sb, "\""); 78 error = sbuf_finish(&sb); 79 if (error == 0) 80 devctl_notify("nvme", "controller", type, sbuf_data(&sb)); 81 sbuf_delete(&sb); 82 } 83 84 static int 85 nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr) 86 { 87 struct nvme_qpair *qpair; 88 uint32_t num_entries; 89 int error; 90 91 qpair = &ctrlr->adminq; 92 qpair->id = 0; 93 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1; 94 qpair->domain = ctrlr->domain; 95 96 num_entries = NVME_ADMIN_ENTRIES; 97 TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries); 98 /* 99 * If admin_entries was overridden to an invalid value, revert it 100 * back to our default value. 101 */ 102 if (num_entries < NVME_MIN_ADMIN_ENTRIES || 103 num_entries > NVME_MAX_ADMIN_ENTRIES) { 104 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d " 105 "specified\n", num_entries); 106 num_entries = NVME_ADMIN_ENTRIES; 107 } 108 109 /* 110 * The admin queue's max xfer size is treated differently than the 111 * max I/O xfer size. 16KB is sufficient here - maybe even less? 112 */ 113 error = nvme_qpair_construct(qpair, num_entries, NVME_ADMIN_TRACKERS, 114 ctrlr); 115 return (error); 116 } 117 118 #define QP(ctrlr, c) ((c) * (ctrlr)->num_io_queues / mp_ncpus) 119 120 static int 121 nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr) 122 { 123 struct nvme_qpair *qpair; 124 uint32_t cap_lo; 125 uint16_t mqes; 126 int c, error, i, n; 127 int num_entries, num_trackers, max_entries; 128 129 /* 130 * NVMe spec sets a hard limit of 64K max entries, but devices may 131 * specify a smaller limit, so we need to check the MQES field in the 132 * capabilities register. We have to cap the number of entries to the 133 * current stride allows for in BAR 0/1, otherwise the remainder entries 134 * are inaccessable. MQES should reflect this, and this is just a 135 * fail-safe. 136 */ 137 max_entries = 138 (rman_get_size(ctrlr->resource) - nvme_mmio_offsetof(doorbell[0])) / 139 (1 << (ctrlr->dstrd + 1)); 140 num_entries = NVME_IO_ENTRIES; 141 TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries); 142 cap_lo = nvme_mmio_read_4(ctrlr, cap_lo); 143 mqes = NVME_CAP_LO_MQES(cap_lo); 144 num_entries = min(num_entries, mqes + 1); 145 num_entries = min(num_entries, max_entries); 146 147 num_trackers = NVME_IO_TRACKERS; 148 TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers); 149 150 num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS); 151 num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS); 152 /* 153 * No need to have more trackers than entries in the submit queue. Note 154 * also that for a queue size of N, we can only have (N-1) commands 155 * outstanding, hence the "-1" here. 156 */ 157 num_trackers = min(num_trackers, (num_entries-1)); 158 159 /* 160 * Our best estimate for the maximum number of I/Os that we should 161 * normally have in flight at one time. This should be viewed as a hint, 162 * not a hard limit and will need to be revisited when the upper layers 163 * of the storage system grows multi-queue support. 164 */ 165 ctrlr->max_hw_pend_io = num_trackers * ctrlr->num_io_queues * 3 / 4; 166 167 ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair), 168 M_NVME, M_ZERO | M_WAITOK); 169 170 for (i = c = n = 0; i < ctrlr->num_io_queues; i++, c += n) { 171 qpair = &ctrlr->ioq[i]; 172 173 /* 174 * Admin queue has ID=0. IO queues start at ID=1 - 175 * hence the 'i+1' here. 176 */ 177 qpair->id = i + 1; 178 if (ctrlr->num_io_queues > 1) { 179 /* Find number of CPUs served by this queue. */ 180 for (n = 1; QP(ctrlr, c + n) == i; n++) 181 ; 182 /* Shuffle multiple NVMe devices between CPUs. */ 183 qpair->cpu = c + (device_get_unit(ctrlr->dev)+n/2) % n; 184 qpair->domain = pcpu_find(qpair->cpu)->pc_domain; 185 } else { 186 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1; 187 qpair->domain = ctrlr->domain; 188 } 189 190 /* 191 * For I/O queues, use the controller-wide max_xfer_size 192 * calculated in nvme_attach(). 193 */ 194 error = nvme_qpair_construct(qpair, num_entries, num_trackers, 195 ctrlr); 196 if (error) 197 return (error); 198 199 /* 200 * Do not bother binding interrupts if we only have one I/O 201 * interrupt thread for this controller. 202 */ 203 if (ctrlr->num_io_queues > 1) 204 bus_bind_intr(ctrlr->dev, qpair->res, qpair->cpu); 205 } 206 207 return (0); 208 } 209 210 static void 211 nvme_ctrlr_fail(struct nvme_controller *ctrlr) 212 { 213 int i; 214 215 ctrlr->is_failed = true; 216 nvme_admin_qpair_disable(&ctrlr->adminq); 217 nvme_qpair_fail(&ctrlr->adminq); 218 if (ctrlr->ioq != NULL) { 219 for (i = 0; i < ctrlr->num_io_queues; i++) { 220 nvme_io_qpair_disable(&ctrlr->ioq[i]); 221 nvme_qpair_fail(&ctrlr->ioq[i]); 222 } 223 } 224 nvme_notify_fail_consumers(ctrlr); 225 } 226 227 void 228 nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 229 struct nvme_request *req) 230 { 231 232 mtx_lock(&ctrlr->lock); 233 STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq); 234 mtx_unlock(&ctrlr->lock); 235 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task); 236 } 237 238 static void 239 nvme_ctrlr_fail_req_task(void *arg, int pending) 240 { 241 struct nvme_controller *ctrlr = arg; 242 struct nvme_request *req; 243 244 mtx_lock(&ctrlr->lock); 245 while ((req = STAILQ_FIRST(&ctrlr->fail_req)) != NULL) { 246 STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq); 247 mtx_unlock(&ctrlr->lock); 248 nvme_qpair_manual_complete_request(req->qpair, req, 249 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST); 250 mtx_lock(&ctrlr->lock); 251 } 252 mtx_unlock(&ctrlr->lock); 253 } 254 255 static int 256 nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr, int desired_val) 257 { 258 int timeout = ticks + (uint64_t)ctrlr->ready_timeout_in_ms * hz / 1000; 259 uint32_t csts; 260 261 while (1) { 262 csts = nvme_mmio_read_4(ctrlr, csts); 263 if (csts == NVME_GONE) /* Hot unplug. */ 264 return (ENXIO); 265 if (((csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK) 266 == desired_val) 267 break; 268 if (timeout - ticks < 0) { 269 nvme_printf(ctrlr, "controller ready did not become %d " 270 "within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms); 271 return (ENXIO); 272 } 273 pause("nvmerdy", 1); 274 } 275 276 return (0); 277 } 278 279 static int 280 nvme_ctrlr_disable(struct nvme_controller *ctrlr) 281 { 282 uint32_t cc; 283 uint32_t csts; 284 uint8_t en, rdy; 285 int err; 286 287 cc = nvme_mmio_read_4(ctrlr, cc); 288 csts = nvme_mmio_read_4(ctrlr, csts); 289 290 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; 291 rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK; 292 293 /* 294 * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1 295 * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when 296 * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY 297 * isn't the desired value. Short circuit if we're already disabled. 298 */ 299 if (en == 1) { 300 if (rdy == 0) { 301 /* EN == 1, wait for RDY == 1 or fail */ 302 err = nvme_ctrlr_wait_for_ready(ctrlr, 1); 303 if (err != 0) 304 return (err); 305 } 306 } else { 307 /* EN == 0 already wait for RDY == 0 */ 308 if (rdy == 0) 309 return (0); 310 else 311 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 312 } 313 314 cc &= ~NVME_CC_REG_EN_MASK; 315 nvme_mmio_write_4(ctrlr, cc, cc); 316 /* 317 * Some drives have issues with accessing the mmio after we 318 * disable, so delay for a bit after we write the bit to 319 * cope with these issues. 320 */ 321 if (ctrlr->quirks & QUIRK_DELAY_B4_CHK_RDY) 322 pause("nvmeR", B4_CHK_RDY_DELAY_MS * hz / 1000); 323 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 324 } 325 326 static int 327 nvme_ctrlr_enable(struct nvme_controller *ctrlr) 328 { 329 uint32_t cc; 330 uint32_t csts; 331 uint32_t aqa; 332 uint32_t qsize; 333 uint8_t en, rdy; 334 int err; 335 336 cc = nvme_mmio_read_4(ctrlr, cc); 337 csts = nvme_mmio_read_4(ctrlr, csts); 338 339 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; 340 rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK; 341 342 /* 343 * See note in nvme_ctrlr_disable. Short circuit if we're already enabled. 344 */ 345 if (en == 1) { 346 if (rdy == 1) 347 return (0); 348 else 349 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 350 } else { 351 /* EN == 0 already wait for RDY == 0 or fail */ 352 err = nvme_ctrlr_wait_for_ready(ctrlr, 0); 353 if (err != 0) 354 return (err); 355 } 356 357 nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr); 358 DELAY(5000); 359 nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr); 360 DELAY(5000); 361 362 /* acqs and asqs are 0-based. */ 363 qsize = ctrlr->adminq.num_entries - 1; 364 365 aqa = 0; 366 aqa = (qsize & NVME_AQA_REG_ACQS_MASK) << NVME_AQA_REG_ACQS_SHIFT; 367 aqa |= (qsize & NVME_AQA_REG_ASQS_MASK) << NVME_AQA_REG_ASQS_SHIFT; 368 nvme_mmio_write_4(ctrlr, aqa, aqa); 369 DELAY(5000); 370 371 /* Initialization values for CC */ 372 cc = 0; 373 cc |= 1 << NVME_CC_REG_EN_SHIFT; 374 cc |= 0 << NVME_CC_REG_CSS_SHIFT; 375 cc |= 0 << NVME_CC_REG_AMS_SHIFT; 376 cc |= 0 << NVME_CC_REG_SHN_SHIFT; 377 cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */ 378 cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */ 379 380 /* This evaluates to 0, which is according to spec. */ 381 cc |= (PAGE_SIZE >> 13) << NVME_CC_REG_MPS_SHIFT; 382 383 nvme_mmio_write_4(ctrlr, cc, cc); 384 385 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 386 } 387 388 static void 389 nvme_ctrlr_disable_qpairs(struct nvme_controller *ctrlr) 390 { 391 int i; 392 393 nvme_admin_qpair_disable(&ctrlr->adminq); 394 /* 395 * I/O queues are not allocated before the initial HW 396 * reset, so do not try to disable them. Use is_initialized 397 * to determine if this is the initial HW reset. 398 */ 399 if (ctrlr->is_initialized) { 400 for (i = 0; i < ctrlr->num_io_queues; i++) 401 nvme_io_qpair_disable(&ctrlr->ioq[i]); 402 } 403 } 404 405 static int 406 nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr) 407 { 408 int err; 409 410 TSENTER(); 411 nvme_ctrlr_disable_qpairs(ctrlr); 412 413 pause("nvmehwreset", hz / 10); 414 415 err = nvme_ctrlr_disable(ctrlr); 416 if (err != 0) 417 return err; 418 err = nvme_ctrlr_enable(ctrlr); 419 TSEXIT(); 420 return (err); 421 } 422 423 void 424 nvme_ctrlr_reset(struct nvme_controller *ctrlr) 425 { 426 int cmpset; 427 428 cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1); 429 430 if (cmpset == 0 || ctrlr->is_failed) 431 /* 432 * Controller is already resetting or has failed. Return 433 * immediately since there is no need to kick off another 434 * reset in these cases. 435 */ 436 return; 437 438 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task); 439 } 440 441 static int 442 nvme_ctrlr_identify(struct nvme_controller *ctrlr) 443 { 444 struct nvme_completion_poll_status status; 445 446 status.done = 0; 447 nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata, 448 nvme_completion_poll_cb, &status); 449 nvme_completion_poll(&status); 450 if (nvme_completion_is_error(&status.cpl)) { 451 nvme_printf(ctrlr, "nvme_identify_controller failed!\n"); 452 return (ENXIO); 453 } 454 455 /* Convert data to host endian */ 456 nvme_controller_data_swapbytes(&ctrlr->cdata); 457 458 /* 459 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 460 * controller supports. 461 */ 462 if (ctrlr->cdata.mdts > 0) 463 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size, 464 ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts))); 465 466 return (0); 467 } 468 469 static int 470 nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr) 471 { 472 struct nvme_completion_poll_status status; 473 int cq_allocated, sq_allocated; 474 475 status.done = 0; 476 nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues, 477 nvme_completion_poll_cb, &status); 478 nvme_completion_poll(&status); 479 if (nvme_completion_is_error(&status.cpl)) { 480 nvme_printf(ctrlr, "nvme_ctrlr_set_num_qpairs failed!\n"); 481 return (ENXIO); 482 } 483 484 /* 485 * Data in cdw0 is 0-based. 486 * Lower 16-bits indicate number of submission queues allocated. 487 * Upper 16-bits indicate number of completion queues allocated. 488 */ 489 sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1; 490 cq_allocated = (status.cpl.cdw0 >> 16) + 1; 491 492 /* 493 * Controller may allocate more queues than we requested, 494 * so use the minimum of the number requested and what was 495 * actually allocated. 496 */ 497 ctrlr->num_io_queues = min(ctrlr->num_io_queues, sq_allocated); 498 ctrlr->num_io_queues = min(ctrlr->num_io_queues, cq_allocated); 499 if (ctrlr->num_io_queues > vm_ndomains) 500 ctrlr->num_io_queues -= ctrlr->num_io_queues % vm_ndomains; 501 502 return (0); 503 } 504 505 static int 506 nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr) 507 { 508 struct nvme_completion_poll_status status; 509 struct nvme_qpair *qpair; 510 int i; 511 512 for (i = 0; i < ctrlr->num_io_queues; i++) { 513 qpair = &ctrlr->ioq[i]; 514 515 status.done = 0; 516 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair, 517 nvme_completion_poll_cb, &status); 518 nvme_completion_poll(&status); 519 if (nvme_completion_is_error(&status.cpl)) { 520 nvme_printf(ctrlr, "nvme_create_io_cq failed!\n"); 521 return (ENXIO); 522 } 523 524 status.done = 0; 525 nvme_ctrlr_cmd_create_io_sq(ctrlr, qpair, 526 nvme_completion_poll_cb, &status); 527 nvme_completion_poll(&status); 528 if (nvme_completion_is_error(&status.cpl)) { 529 nvme_printf(ctrlr, "nvme_create_io_sq failed!\n"); 530 return (ENXIO); 531 } 532 } 533 534 return (0); 535 } 536 537 static int 538 nvme_ctrlr_delete_qpairs(struct nvme_controller *ctrlr) 539 { 540 struct nvme_completion_poll_status status; 541 struct nvme_qpair *qpair; 542 543 for (int i = 0; i < ctrlr->num_io_queues; i++) { 544 qpair = &ctrlr->ioq[i]; 545 546 status.done = 0; 547 nvme_ctrlr_cmd_delete_io_sq(ctrlr, qpair, 548 nvme_completion_poll_cb, &status); 549 nvme_completion_poll(&status); 550 if (nvme_completion_is_error(&status.cpl)) { 551 nvme_printf(ctrlr, "nvme_destroy_io_sq failed!\n"); 552 return (ENXIO); 553 } 554 555 status.done = 0; 556 nvme_ctrlr_cmd_delete_io_cq(ctrlr, qpair, 557 nvme_completion_poll_cb, &status); 558 nvme_completion_poll(&status); 559 if (nvme_completion_is_error(&status.cpl)) { 560 nvme_printf(ctrlr, "nvme_destroy_io_cq failed!\n"); 561 return (ENXIO); 562 } 563 } 564 565 return (0); 566 } 567 568 static int 569 nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr) 570 { 571 struct nvme_namespace *ns; 572 uint32_t i; 573 574 for (i = 0; i < min(ctrlr->cdata.nn, NVME_MAX_NAMESPACES); i++) { 575 ns = &ctrlr->ns[i]; 576 nvme_ns_construct(ns, i+1, ctrlr); 577 } 578 579 return (0); 580 } 581 582 static bool 583 is_log_page_id_valid(uint8_t page_id) 584 { 585 586 switch (page_id) { 587 case NVME_LOG_ERROR: 588 case NVME_LOG_HEALTH_INFORMATION: 589 case NVME_LOG_FIRMWARE_SLOT: 590 case NVME_LOG_CHANGED_NAMESPACE: 591 case NVME_LOG_COMMAND_EFFECT: 592 case NVME_LOG_RES_NOTIFICATION: 593 case NVME_LOG_SANITIZE_STATUS: 594 return (true); 595 } 596 597 return (false); 598 } 599 600 static uint32_t 601 nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id) 602 { 603 uint32_t log_page_size; 604 605 switch (page_id) { 606 case NVME_LOG_ERROR: 607 log_page_size = min( 608 sizeof(struct nvme_error_information_entry) * 609 (ctrlr->cdata.elpe + 1), NVME_MAX_AER_LOG_SIZE); 610 break; 611 case NVME_LOG_HEALTH_INFORMATION: 612 log_page_size = sizeof(struct nvme_health_information_page); 613 break; 614 case NVME_LOG_FIRMWARE_SLOT: 615 log_page_size = sizeof(struct nvme_firmware_page); 616 break; 617 case NVME_LOG_CHANGED_NAMESPACE: 618 log_page_size = sizeof(struct nvme_ns_list); 619 break; 620 case NVME_LOG_COMMAND_EFFECT: 621 log_page_size = sizeof(struct nvme_command_effects_page); 622 break; 623 case NVME_LOG_RES_NOTIFICATION: 624 log_page_size = sizeof(struct nvme_res_notification_page); 625 break; 626 case NVME_LOG_SANITIZE_STATUS: 627 log_page_size = sizeof(struct nvme_sanitize_status_page); 628 break; 629 default: 630 log_page_size = 0; 631 break; 632 } 633 634 return (log_page_size); 635 } 636 637 static void 638 nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr, 639 uint8_t state) 640 { 641 642 if (state & NVME_CRIT_WARN_ST_AVAILABLE_SPARE) 643 nvme_ctrlr_devctl_log(ctrlr, "critical", 644 "available spare space below threshold"); 645 646 if (state & NVME_CRIT_WARN_ST_TEMPERATURE) 647 nvme_ctrlr_devctl_log(ctrlr, "critical", 648 "temperature above threshold"); 649 650 if (state & NVME_CRIT_WARN_ST_DEVICE_RELIABILITY) 651 nvme_ctrlr_devctl_log(ctrlr, "critical", 652 "device reliability degraded"); 653 654 if (state & NVME_CRIT_WARN_ST_READ_ONLY) 655 nvme_ctrlr_devctl_log(ctrlr, "critical", 656 "media placed in read only mode"); 657 658 if (state & NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP) 659 nvme_ctrlr_devctl_log(ctrlr, "critical", 660 "volatile memory backup device failed"); 661 662 if (state & NVME_CRIT_WARN_ST_RESERVED_MASK) 663 nvme_ctrlr_devctl_log(ctrlr, "critical", 664 "unknown critical warning(s): state = 0x%02x", state); 665 } 666 667 static void 668 nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl) 669 { 670 struct nvme_async_event_request *aer = arg; 671 struct nvme_health_information_page *health_info; 672 struct nvme_ns_list *nsl; 673 struct nvme_error_information_entry *err; 674 int i; 675 676 /* 677 * If the log page fetch for some reason completed with an error, 678 * don't pass log page data to the consumers. In practice, this case 679 * should never happen. 680 */ 681 if (nvme_completion_is_error(cpl)) 682 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 683 aer->log_page_id, NULL, 0); 684 else { 685 /* Convert data to host endian */ 686 switch (aer->log_page_id) { 687 case NVME_LOG_ERROR: 688 err = (struct nvme_error_information_entry *)aer->log_page_buffer; 689 for (i = 0; i < (aer->ctrlr->cdata.elpe + 1); i++) 690 nvme_error_information_entry_swapbytes(err++); 691 break; 692 case NVME_LOG_HEALTH_INFORMATION: 693 nvme_health_information_page_swapbytes( 694 (struct nvme_health_information_page *)aer->log_page_buffer); 695 break; 696 case NVME_LOG_FIRMWARE_SLOT: 697 nvme_firmware_page_swapbytes( 698 (struct nvme_firmware_page *)aer->log_page_buffer); 699 break; 700 case NVME_LOG_CHANGED_NAMESPACE: 701 nvme_ns_list_swapbytes( 702 (struct nvme_ns_list *)aer->log_page_buffer); 703 break; 704 case NVME_LOG_COMMAND_EFFECT: 705 nvme_command_effects_page_swapbytes( 706 (struct nvme_command_effects_page *)aer->log_page_buffer); 707 break; 708 case NVME_LOG_RES_NOTIFICATION: 709 nvme_res_notification_page_swapbytes( 710 (struct nvme_res_notification_page *)aer->log_page_buffer); 711 break; 712 case NVME_LOG_SANITIZE_STATUS: 713 nvme_sanitize_status_page_swapbytes( 714 (struct nvme_sanitize_status_page *)aer->log_page_buffer); 715 break; 716 case INTEL_LOG_TEMP_STATS: 717 intel_log_temp_stats_swapbytes( 718 (struct intel_log_temp_stats *)aer->log_page_buffer); 719 break; 720 default: 721 break; 722 } 723 724 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) { 725 health_info = (struct nvme_health_information_page *) 726 aer->log_page_buffer; 727 nvme_ctrlr_log_critical_warnings(aer->ctrlr, 728 health_info->critical_warning); 729 /* 730 * Critical warnings reported through the 731 * SMART/health log page are persistent, so 732 * clear the associated bits in the async event 733 * config so that we do not receive repeated 734 * notifications for the same event. 735 */ 736 aer->ctrlr->async_event_config &= 737 ~health_info->critical_warning; 738 nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr, 739 aer->ctrlr->async_event_config, NULL, NULL); 740 } else if (aer->log_page_id == NVME_LOG_CHANGED_NAMESPACE && 741 !nvme_use_nvd) { 742 nsl = (struct nvme_ns_list *)aer->log_page_buffer; 743 for (i = 0; i < nitems(nsl->ns) && nsl->ns[i] != 0; i++) { 744 if (nsl->ns[i] > NVME_MAX_NAMESPACES) 745 break; 746 nvme_notify_ns(aer->ctrlr, nsl->ns[i]); 747 } 748 } 749 750 /* 751 * Pass the cpl data from the original async event completion, 752 * not the log page fetch. 753 */ 754 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 755 aer->log_page_id, aer->log_page_buffer, aer->log_page_size); 756 } 757 758 /* 759 * Repost another asynchronous event request to replace the one 760 * that just completed. 761 */ 762 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 763 } 764 765 static void 766 nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl) 767 { 768 struct nvme_async_event_request *aer = arg; 769 770 if (nvme_completion_is_error(cpl)) { 771 /* 772 * Do not retry failed async event requests. This avoids 773 * infinite loops where a new async event request is submitted 774 * to replace the one just failed, only to fail again and 775 * perpetuate the loop. 776 */ 777 return; 778 } 779 780 /* Associated log page is in bits 23:16 of completion entry dw0. */ 781 aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16; 782 783 nvme_printf(aer->ctrlr, "async event occurred (type 0x%x, info 0x%02x," 784 " page 0x%02x)\n", (cpl->cdw0 & 0x07), (cpl->cdw0 & 0xFF00) >> 8, 785 aer->log_page_id); 786 787 if (is_log_page_id_valid(aer->log_page_id)) { 788 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr, 789 aer->log_page_id); 790 memcpy(&aer->cpl, cpl, sizeof(*cpl)); 791 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id, 792 NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer, 793 aer->log_page_size, nvme_ctrlr_async_event_log_page_cb, 794 aer); 795 /* Wait to notify consumers until after log page is fetched. */ 796 } else { 797 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id, 798 NULL, 0); 799 800 /* 801 * Repost another asynchronous event request to replace the one 802 * that just completed. 803 */ 804 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 805 } 806 } 807 808 static void 809 nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 810 struct nvme_async_event_request *aer) 811 { 812 struct nvme_request *req; 813 814 aer->ctrlr = ctrlr; 815 req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer); 816 aer->req = req; 817 818 /* 819 * Disable timeout here, since asynchronous event requests should by 820 * nature never be timed out. 821 */ 822 req->timeout = false; 823 req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST; 824 nvme_ctrlr_submit_admin_request(ctrlr, req); 825 } 826 827 static void 828 nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr) 829 { 830 struct nvme_completion_poll_status status; 831 struct nvme_async_event_request *aer; 832 uint32_t i; 833 834 ctrlr->async_event_config = NVME_CRIT_WARN_ST_AVAILABLE_SPARE | 835 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY | 836 NVME_CRIT_WARN_ST_READ_ONLY | 837 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP; 838 if (ctrlr->cdata.ver >= NVME_REV(1, 2)) 839 ctrlr->async_event_config |= NVME_ASYNC_EVENT_NS_ATTRIBUTE | 840 NVME_ASYNC_EVENT_FW_ACTIVATE; 841 842 status.done = 0; 843 nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD, 844 0, NULL, 0, nvme_completion_poll_cb, &status); 845 nvme_completion_poll(&status); 846 if (nvme_completion_is_error(&status.cpl) || 847 (status.cpl.cdw0 & 0xFFFF) == 0xFFFF || 848 (status.cpl.cdw0 & 0xFFFF) == 0x0000) { 849 nvme_printf(ctrlr, "temperature threshold not supported\n"); 850 } else 851 ctrlr->async_event_config |= NVME_CRIT_WARN_ST_TEMPERATURE; 852 853 nvme_ctrlr_cmd_set_async_event_config(ctrlr, 854 ctrlr->async_event_config, NULL, NULL); 855 856 /* aerl is a zero-based value, so we need to add 1 here. */ 857 ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1)); 858 859 for (i = 0; i < ctrlr->num_aers; i++) { 860 aer = &ctrlr->aer[i]; 861 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 862 } 863 } 864 865 static void 866 nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr) 867 { 868 869 ctrlr->int_coal_time = 0; 870 TUNABLE_INT_FETCH("hw.nvme.int_coal_time", 871 &ctrlr->int_coal_time); 872 873 ctrlr->int_coal_threshold = 0; 874 TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold", 875 &ctrlr->int_coal_threshold); 876 877 nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time, 878 ctrlr->int_coal_threshold, NULL, NULL); 879 } 880 881 static void 882 nvme_ctrlr_hmb_free(struct nvme_controller *ctrlr) 883 { 884 struct nvme_hmb_chunk *hmbc; 885 int i; 886 887 if (ctrlr->hmb_desc_paddr) { 888 bus_dmamap_unload(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map); 889 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr, 890 ctrlr->hmb_desc_map); 891 ctrlr->hmb_desc_paddr = 0; 892 } 893 if (ctrlr->hmb_desc_tag) { 894 bus_dma_tag_destroy(ctrlr->hmb_desc_tag); 895 ctrlr->hmb_desc_tag = NULL; 896 } 897 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 898 hmbc = &ctrlr->hmb_chunks[i]; 899 bus_dmamap_unload(ctrlr->hmb_tag, hmbc->hmbc_map); 900 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr, 901 hmbc->hmbc_map); 902 } 903 ctrlr->hmb_nchunks = 0; 904 if (ctrlr->hmb_tag) { 905 bus_dma_tag_destroy(ctrlr->hmb_tag); 906 ctrlr->hmb_tag = NULL; 907 } 908 if (ctrlr->hmb_chunks) { 909 free(ctrlr->hmb_chunks, M_NVME); 910 ctrlr->hmb_chunks = NULL; 911 } 912 } 913 914 static void 915 nvme_ctrlr_hmb_alloc(struct nvme_controller *ctrlr) 916 { 917 struct nvme_hmb_chunk *hmbc; 918 size_t pref, min, minc, size; 919 int err, i; 920 uint64_t max; 921 922 /* Limit HMB to 5% of RAM size per device by default. */ 923 max = (uint64_t)physmem * PAGE_SIZE / 20; 924 TUNABLE_UINT64_FETCH("hw.nvme.hmb_max", &max); 925 926 min = (long long unsigned)ctrlr->cdata.hmmin * 4096; 927 if (max == 0 || max < min) 928 return; 929 pref = MIN((long long unsigned)ctrlr->cdata.hmpre * 4096, max); 930 minc = MAX(ctrlr->cdata.hmminds * 4096, PAGE_SIZE); 931 if (min > 0 && ctrlr->cdata.hmmaxd > 0) 932 minc = MAX(minc, min / ctrlr->cdata.hmmaxd); 933 ctrlr->hmb_chunk = pref; 934 935 again: 936 ctrlr->hmb_chunk = roundup2(ctrlr->hmb_chunk, PAGE_SIZE); 937 ctrlr->hmb_nchunks = howmany(pref, ctrlr->hmb_chunk); 938 if (ctrlr->cdata.hmmaxd > 0 && ctrlr->hmb_nchunks > ctrlr->cdata.hmmaxd) 939 ctrlr->hmb_nchunks = ctrlr->cdata.hmmaxd; 940 ctrlr->hmb_chunks = malloc(sizeof(struct nvme_hmb_chunk) * 941 ctrlr->hmb_nchunks, M_NVME, M_WAITOK); 942 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 943 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 944 ctrlr->hmb_chunk, 1, ctrlr->hmb_chunk, 0, NULL, NULL, &ctrlr->hmb_tag); 945 if (err != 0) { 946 nvme_printf(ctrlr, "HMB tag create failed %d\n", err); 947 nvme_ctrlr_hmb_free(ctrlr); 948 return; 949 } 950 951 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 952 hmbc = &ctrlr->hmb_chunks[i]; 953 if (bus_dmamem_alloc(ctrlr->hmb_tag, 954 (void **)&hmbc->hmbc_vaddr, BUS_DMA_NOWAIT, 955 &hmbc->hmbc_map)) { 956 nvme_printf(ctrlr, "failed to alloc HMB\n"); 957 break; 958 } 959 if (bus_dmamap_load(ctrlr->hmb_tag, hmbc->hmbc_map, 960 hmbc->hmbc_vaddr, ctrlr->hmb_chunk, nvme_single_map, 961 &hmbc->hmbc_paddr, BUS_DMA_NOWAIT) != 0) { 962 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr, 963 hmbc->hmbc_map); 964 nvme_printf(ctrlr, "failed to load HMB\n"); 965 break; 966 } 967 bus_dmamap_sync(ctrlr->hmb_tag, hmbc->hmbc_map, 968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 969 } 970 971 if (i < ctrlr->hmb_nchunks && i * ctrlr->hmb_chunk < min && 972 ctrlr->hmb_chunk / 2 >= minc) { 973 ctrlr->hmb_nchunks = i; 974 nvme_ctrlr_hmb_free(ctrlr); 975 ctrlr->hmb_chunk /= 2; 976 goto again; 977 } 978 ctrlr->hmb_nchunks = i; 979 if (ctrlr->hmb_nchunks * ctrlr->hmb_chunk < min) { 980 nvme_ctrlr_hmb_free(ctrlr); 981 return; 982 } 983 984 size = sizeof(struct nvme_hmb_desc) * ctrlr->hmb_nchunks; 985 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 986 16, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 987 size, 1, size, 0, NULL, NULL, &ctrlr->hmb_desc_tag); 988 if (err != 0) { 989 nvme_printf(ctrlr, "HMB desc tag create failed %d\n", err); 990 nvme_ctrlr_hmb_free(ctrlr); 991 return; 992 } 993 if (bus_dmamem_alloc(ctrlr->hmb_desc_tag, 994 (void **)&ctrlr->hmb_desc_vaddr, BUS_DMA_WAITOK, 995 &ctrlr->hmb_desc_map)) { 996 nvme_printf(ctrlr, "failed to alloc HMB desc\n"); 997 nvme_ctrlr_hmb_free(ctrlr); 998 return; 999 } 1000 if (bus_dmamap_load(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map, 1001 ctrlr->hmb_desc_vaddr, size, nvme_single_map, 1002 &ctrlr->hmb_desc_paddr, BUS_DMA_NOWAIT) != 0) { 1003 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr, 1004 ctrlr->hmb_desc_map); 1005 nvme_printf(ctrlr, "failed to load HMB desc\n"); 1006 nvme_ctrlr_hmb_free(ctrlr); 1007 return; 1008 } 1009 1010 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 1011 ctrlr->hmb_desc_vaddr[i].addr = 1012 htole64(ctrlr->hmb_chunks[i].hmbc_paddr); 1013 ctrlr->hmb_desc_vaddr[i].size = htole32(ctrlr->hmb_chunk / 4096); 1014 } 1015 bus_dmamap_sync(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map, 1016 BUS_DMASYNC_PREWRITE); 1017 1018 nvme_printf(ctrlr, "Allocated %lluMB host memory buffer\n", 1019 (long long unsigned)ctrlr->hmb_nchunks * ctrlr->hmb_chunk 1020 / 1024 / 1024); 1021 } 1022 1023 static void 1024 nvme_ctrlr_hmb_enable(struct nvme_controller *ctrlr, bool enable, bool memret) 1025 { 1026 struct nvme_completion_poll_status status; 1027 uint32_t cdw11; 1028 1029 cdw11 = 0; 1030 if (enable) 1031 cdw11 |= 1; 1032 if (memret) 1033 cdw11 |= 2; 1034 status.done = 0; 1035 nvme_ctrlr_cmd_set_feature(ctrlr, NVME_FEAT_HOST_MEMORY_BUFFER, cdw11, 1036 ctrlr->hmb_nchunks * ctrlr->hmb_chunk / 4096, ctrlr->hmb_desc_paddr, 1037 ctrlr->hmb_desc_paddr >> 32, ctrlr->hmb_nchunks, NULL, 0, 1038 nvme_completion_poll_cb, &status); 1039 nvme_completion_poll(&status); 1040 if (nvme_completion_is_error(&status.cpl)) 1041 nvme_printf(ctrlr, "nvme_ctrlr_hmb_enable failed!\n"); 1042 } 1043 1044 static void 1045 nvme_ctrlr_start(void *ctrlr_arg, bool resetting) 1046 { 1047 struct nvme_controller *ctrlr = ctrlr_arg; 1048 uint32_t old_num_io_queues; 1049 int i; 1050 1051 TSENTER(); 1052 1053 /* 1054 * Only reset adminq here when we are restarting the 1055 * controller after a reset. During initialization, 1056 * we have already submitted admin commands to get 1057 * the number of I/O queues supported, so cannot reset 1058 * the adminq again here. 1059 */ 1060 if (resetting) { 1061 nvme_qpair_reset(&ctrlr->adminq); 1062 nvme_admin_qpair_enable(&ctrlr->adminq); 1063 } 1064 1065 if (ctrlr->ioq != NULL) { 1066 for (i = 0; i < ctrlr->num_io_queues; i++) 1067 nvme_qpair_reset(&ctrlr->ioq[i]); 1068 } 1069 1070 /* 1071 * If it was a reset on initialization command timeout, just 1072 * return here, letting initialization code fail gracefully. 1073 */ 1074 if (resetting && !ctrlr->is_initialized) 1075 return; 1076 1077 if (resetting && nvme_ctrlr_identify(ctrlr) != 0) { 1078 nvme_ctrlr_fail(ctrlr); 1079 return; 1080 } 1081 1082 /* 1083 * The number of qpairs are determined during controller initialization, 1084 * including using NVMe SET_FEATURES/NUMBER_OF_QUEUES to determine the 1085 * HW limit. We call SET_FEATURES again here so that it gets called 1086 * after any reset for controllers that depend on the driver to 1087 * explicit specify how many queues it will use. This value should 1088 * never change between resets, so panic if somehow that does happen. 1089 */ 1090 if (resetting) { 1091 old_num_io_queues = ctrlr->num_io_queues; 1092 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) { 1093 nvme_ctrlr_fail(ctrlr); 1094 return; 1095 } 1096 1097 if (old_num_io_queues != ctrlr->num_io_queues) { 1098 panic("num_io_queues changed from %u to %u", 1099 old_num_io_queues, ctrlr->num_io_queues); 1100 } 1101 } 1102 1103 if (ctrlr->cdata.hmpre > 0 && ctrlr->hmb_nchunks == 0) { 1104 nvme_ctrlr_hmb_alloc(ctrlr); 1105 if (ctrlr->hmb_nchunks > 0) 1106 nvme_ctrlr_hmb_enable(ctrlr, true, false); 1107 } else if (ctrlr->hmb_nchunks > 0) 1108 nvme_ctrlr_hmb_enable(ctrlr, true, true); 1109 1110 if (nvme_ctrlr_create_qpairs(ctrlr) != 0) { 1111 nvme_ctrlr_fail(ctrlr); 1112 return; 1113 } 1114 1115 if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) { 1116 nvme_ctrlr_fail(ctrlr); 1117 return; 1118 } 1119 1120 nvme_ctrlr_configure_aer(ctrlr); 1121 nvme_ctrlr_configure_int_coalescing(ctrlr); 1122 1123 for (i = 0; i < ctrlr->num_io_queues; i++) 1124 nvme_io_qpair_enable(&ctrlr->ioq[i]); 1125 TSEXIT(); 1126 } 1127 1128 void 1129 nvme_ctrlr_start_config_hook(void *arg) 1130 { 1131 struct nvme_controller *ctrlr = arg; 1132 1133 TSENTER(); 1134 1135 /* 1136 * Reset controller twice to ensure we do a transition from cc.en==1 to 1137 * cc.en==0. This is because we don't really know what status the 1138 * controller was left in when boot handed off to OS. Linux doesn't do 1139 * this, however. If we adopt that policy, see also nvme_ctrlr_resume(). 1140 */ 1141 if (nvme_ctrlr_hw_reset(ctrlr) != 0) { 1142 fail: 1143 nvme_ctrlr_fail(ctrlr); 1144 config_intrhook_disestablish(&ctrlr->config_hook); 1145 return; 1146 } 1147 1148 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1149 goto fail; 1150 1151 nvme_qpair_reset(&ctrlr->adminq); 1152 nvme_admin_qpair_enable(&ctrlr->adminq); 1153 1154 if (nvme_ctrlr_identify(ctrlr) == 0 && 1155 nvme_ctrlr_set_num_qpairs(ctrlr) == 0 && 1156 nvme_ctrlr_construct_io_qpairs(ctrlr) == 0) 1157 nvme_ctrlr_start(ctrlr, false); 1158 else 1159 goto fail; 1160 1161 nvme_sysctl_initialize_ctrlr(ctrlr); 1162 config_intrhook_disestablish(&ctrlr->config_hook); 1163 1164 ctrlr->is_initialized = 1; 1165 nvme_notify_new_controller(ctrlr); 1166 TSEXIT(); 1167 } 1168 1169 static void 1170 nvme_ctrlr_reset_task(void *arg, int pending) 1171 { 1172 struct nvme_controller *ctrlr = arg; 1173 int status; 1174 1175 nvme_ctrlr_devctl_log(ctrlr, "RESET", "resetting controller"); 1176 status = nvme_ctrlr_hw_reset(ctrlr); 1177 /* 1178 * Use pause instead of DELAY, so that we yield to any nvme interrupt 1179 * handlers on this CPU that were blocked on a qpair lock. We want 1180 * all nvme interrupts completed before proceeding with restarting the 1181 * controller. 1182 * 1183 * XXX - any way to guarantee the interrupt handlers have quiesced? 1184 */ 1185 pause("nvmereset", hz / 10); 1186 if (status == 0) 1187 nvme_ctrlr_start(ctrlr, true); 1188 else 1189 nvme_ctrlr_fail(ctrlr); 1190 1191 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1192 } 1193 1194 /* 1195 * Poll all the queues enabled on the device for completion. 1196 */ 1197 void 1198 nvme_ctrlr_poll(struct nvme_controller *ctrlr) 1199 { 1200 int i; 1201 1202 nvme_qpair_process_completions(&ctrlr->adminq); 1203 1204 for (i = 0; i < ctrlr->num_io_queues; i++) 1205 if (ctrlr->ioq && ctrlr->ioq[i].cpl) 1206 nvme_qpair_process_completions(&ctrlr->ioq[i]); 1207 } 1208 1209 /* 1210 * Poll the single-vector interrupt case: num_io_queues will be 1 and 1211 * there's only a single vector. While we're polling, we mask further 1212 * interrupts in the controller. 1213 */ 1214 void 1215 nvme_ctrlr_shared_handler(void *arg) 1216 { 1217 struct nvme_controller *ctrlr = arg; 1218 1219 nvme_mmio_write_4(ctrlr, intms, 1); 1220 nvme_ctrlr_poll(ctrlr); 1221 nvme_mmio_write_4(ctrlr, intmc, 1); 1222 } 1223 1224 static void 1225 nvme_pt_done(void *arg, const struct nvme_completion *cpl) 1226 { 1227 struct nvme_pt_command *pt = arg; 1228 struct mtx *mtx = pt->driver_lock; 1229 uint16_t status; 1230 1231 bzero(&pt->cpl, sizeof(pt->cpl)); 1232 pt->cpl.cdw0 = cpl->cdw0; 1233 1234 status = cpl->status; 1235 status &= ~NVME_STATUS_P_MASK; 1236 pt->cpl.status = status; 1237 1238 mtx_lock(mtx); 1239 pt->driver_lock = NULL; 1240 wakeup(pt); 1241 mtx_unlock(mtx); 1242 } 1243 1244 int 1245 nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1246 struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer, 1247 int is_admin_cmd) 1248 { 1249 struct nvme_request *req; 1250 struct mtx *mtx; 1251 struct buf *buf = NULL; 1252 int ret = 0; 1253 1254 if (pt->len > 0) { 1255 if (pt->len > ctrlr->max_xfer_size) { 1256 nvme_printf(ctrlr, "pt->len (%d) " 1257 "exceeds max_xfer_size (%d)\n", pt->len, 1258 ctrlr->max_xfer_size); 1259 return EIO; 1260 } 1261 if (is_user_buffer) { 1262 /* 1263 * Ensure the user buffer is wired for the duration of 1264 * this pass-through command. 1265 */ 1266 PHOLD(curproc); 1267 buf = uma_zalloc(pbuf_zone, M_WAITOK); 1268 buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE; 1269 if (vmapbuf(buf, pt->buf, pt->len, 1) < 0) { 1270 ret = EFAULT; 1271 goto err; 1272 } 1273 req = nvme_allocate_request_vaddr(buf->b_data, pt->len, 1274 nvme_pt_done, pt); 1275 } else 1276 req = nvme_allocate_request_vaddr(pt->buf, pt->len, 1277 nvme_pt_done, pt); 1278 } else 1279 req = nvme_allocate_request_null(nvme_pt_done, pt); 1280 1281 /* Assume user space already converted to little-endian */ 1282 req->cmd.opc = pt->cmd.opc; 1283 req->cmd.fuse = pt->cmd.fuse; 1284 req->cmd.rsvd2 = pt->cmd.rsvd2; 1285 req->cmd.rsvd3 = pt->cmd.rsvd3; 1286 req->cmd.cdw10 = pt->cmd.cdw10; 1287 req->cmd.cdw11 = pt->cmd.cdw11; 1288 req->cmd.cdw12 = pt->cmd.cdw12; 1289 req->cmd.cdw13 = pt->cmd.cdw13; 1290 req->cmd.cdw14 = pt->cmd.cdw14; 1291 req->cmd.cdw15 = pt->cmd.cdw15; 1292 1293 req->cmd.nsid = htole32(nsid); 1294 1295 mtx = mtx_pool_find(mtxpool_sleep, pt); 1296 pt->driver_lock = mtx; 1297 1298 if (is_admin_cmd) 1299 nvme_ctrlr_submit_admin_request(ctrlr, req); 1300 else 1301 nvme_ctrlr_submit_io_request(ctrlr, req); 1302 1303 mtx_lock(mtx); 1304 while (pt->driver_lock != NULL) 1305 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0); 1306 mtx_unlock(mtx); 1307 1308 err: 1309 if (buf != NULL) { 1310 uma_zfree(pbuf_zone, buf); 1311 PRELE(curproc); 1312 } 1313 1314 return (ret); 1315 } 1316 1317 static int 1318 nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag, 1319 struct thread *td) 1320 { 1321 struct nvme_controller *ctrlr; 1322 struct nvme_pt_command *pt; 1323 1324 ctrlr = cdev->si_drv1; 1325 1326 switch (cmd) { 1327 case NVME_RESET_CONTROLLER: 1328 nvme_ctrlr_reset(ctrlr); 1329 break; 1330 case NVME_PASSTHROUGH_CMD: 1331 pt = (struct nvme_pt_command *)arg; 1332 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, le32toh(pt->cmd.nsid), 1333 1 /* is_user_buffer */, 1 /* is_admin_cmd */)); 1334 case NVME_GET_NSID: 1335 { 1336 struct nvme_get_nsid *gnsid = (struct nvme_get_nsid *)arg; 1337 strncpy(gnsid->cdev, device_get_nameunit(ctrlr->dev), 1338 sizeof(gnsid->cdev)); 1339 gnsid->cdev[sizeof(gnsid->cdev) - 1] = '\0'; 1340 gnsid->nsid = 0; 1341 break; 1342 } 1343 case NVME_GET_MAX_XFER_SIZE: 1344 *(uint64_t *)arg = ctrlr->max_xfer_size; 1345 break; 1346 default: 1347 return (ENOTTY); 1348 } 1349 1350 return (0); 1351 } 1352 1353 static struct cdevsw nvme_ctrlr_cdevsw = { 1354 .d_version = D_VERSION, 1355 .d_flags = 0, 1356 .d_ioctl = nvme_ctrlr_ioctl 1357 }; 1358 1359 int 1360 nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev) 1361 { 1362 struct make_dev_args md_args; 1363 uint32_t cap_lo; 1364 uint32_t cap_hi; 1365 uint32_t to, vs, pmrcap; 1366 uint8_t mpsmin; 1367 int status, timeout_period; 1368 1369 ctrlr->dev = dev; 1370 1371 mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF); 1372 if (bus_get_domain(dev, &ctrlr->domain) != 0) 1373 ctrlr->domain = 0; 1374 1375 cap_lo = nvme_mmio_read_4(ctrlr, cap_lo); 1376 if (bootverbose) { 1377 device_printf(dev, "CapLo: 0x%08x: MQES %u%s%s%s%s, TO %u\n", 1378 cap_lo, NVME_CAP_LO_MQES(cap_lo), 1379 NVME_CAP_LO_CQR(cap_lo) ? ", CQR" : "", 1380 NVME_CAP_LO_AMS(cap_lo) ? ", AMS" : "", 1381 (NVME_CAP_LO_AMS(cap_lo) & 0x1) ? " WRRwUPC" : "", 1382 (NVME_CAP_LO_AMS(cap_lo) & 0x2) ? " VS" : "", 1383 NVME_CAP_LO_TO(cap_lo)); 1384 } 1385 cap_hi = nvme_mmio_read_4(ctrlr, cap_hi); 1386 if (bootverbose) { 1387 device_printf(dev, "CapHi: 0x%08x: DSTRD %u%s, CSS %x%s, " 1388 "MPSMIN %u, MPSMAX %u%s%s\n", cap_hi, 1389 NVME_CAP_HI_DSTRD(cap_hi), 1390 NVME_CAP_HI_NSSRS(cap_hi) ? ", NSSRS" : "", 1391 NVME_CAP_HI_CSS(cap_hi), 1392 NVME_CAP_HI_BPS(cap_hi) ? ", BPS" : "", 1393 NVME_CAP_HI_MPSMIN(cap_hi), 1394 NVME_CAP_HI_MPSMAX(cap_hi), 1395 NVME_CAP_HI_PMRS(cap_hi) ? ", PMRS" : "", 1396 NVME_CAP_HI_CMBS(cap_hi) ? ", CMBS" : ""); 1397 } 1398 if (bootverbose) { 1399 vs = nvme_mmio_read_4(ctrlr, vs); 1400 device_printf(dev, "Version: 0x%08x: %d.%d\n", vs, 1401 NVME_MAJOR(vs), NVME_MINOR(vs)); 1402 } 1403 if (bootverbose && NVME_CAP_HI_PMRS(cap_hi)) { 1404 pmrcap = nvme_mmio_read_4(ctrlr, pmrcap); 1405 device_printf(dev, "PMRCap: 0x%08x: BIR %u%s%s, PMRTU %u, " 1406 "PMRWBM %x, PMRTO %u%s\n", pmrcap, 1407 NVME_PMRCAP_BIR(pmrcap), 1408 NVME_PMRCAP_RDS(pmrcap) ? ", RDS" : "", 1409 NVME_PMRCAP_WDS(pmrcap) ? ", WDS" : "", 1410 NVME_PMRCAP_PMRTU(pmrcap), 1411 NVME_PMRCAP_PMRWBM(pmrcap), 1412 NVME_PMRCAP_PMRTO(pmrcap), 1413 NVME_PMRCAP_CMSS(pmrcap) ? ", CMSS" : ""); 1414 } 1415 1416 ctrlr->dstrd = NVME_CAP_HI_DSTRD(cap_hi) + 2; 1417 1418 mpsmin = NVME_CAP_HI_MPSMIN(cap_hi); 1419 ctrlr->min_page_size = 1 << (12 + mpsmin); 1420 1421 /* Get ready timeout value from controller, in units of 500ms. */ 1422 to = NVME_CAP_LO_TO(cap_lo) + 1; 1423 ctrlr->ready_timeout_in_ms = to * 500; 1424 1425 timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD; 1426 TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period); 1427 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD); 1428 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD); 1429 ctrlr->timeout_period = timeout_period; 1430 1431 nvme_retry_count = NVME_DEFAULT_RETRY_COUNT; 1432 TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count); 1433 1434 ctrlr->enable_aborts = 0; 1435 TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts); 1436 1437 ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE; 1438 if (nvme_ctrlr_construct_admin_qpair(ctrlr) != 0) 1439 return (ENXIO); 1440 1441 /* 1442 * Create 2 threads for the taskqueue. The reset thread will block when 1443 * it detects that the controller has failed until all I/O has been 1444 * failed up the stack. The fail_req task needs to be able to run in 1445 * this case to finish the request failure for some cases. 1446 * 1447 * We could partially solve this race by draining the failed requeust 1448 * queue before proceding to free the sim, though nothing would stop 1449 * new I/O from coming in after we do that drain, but before we reach 1450 * cam_sim_free, so this big hammer is used instead. 1451 */ 1452 ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK, 1453 taskqueue_thread_enqueue, &ctrlr->taskqueue); 1454 taskqueue_start_threads(&ctrlr->taskqueue, 2, PI_DISK, "nvme taskq"); 1455 1456 ctrlr->is_resetting = 0; 1457 ctrlr->is_initialized = 0; 1458 ctrlr->notification_sent = 0; 1459 TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr); 1460 TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr); 1461 STAILQ_INIT(&ctrlr->fail_req); 1462 ctrlr->is_failed = false; 1463 1464 make_dev_args_init(&md_args); 1465 md_args.mda_devsw = &nvme_ctrlr_cdevsw; 1466 md_args.mda_uid = UID_ROOT; 1467 md_args.mda_gid = GID_WHEEL; 1468 md_args.mda_mode = 0600; 1469 md_args.mda_unit = device_get_unit(dev); 1470 md_args.mda_si_drv1 = (void *)ctrlr; 1471 status = make_dev_s(&md_args, &ctrlr->cdev, "nvme%d", 1472 device_get_unit(dev)); 1473 if (status != 0) 1474 return (ENXIO); 1475 1476 return (0); 1477 } 1478 1479 void 1480 nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev) 1481 { 1482 int gone, i; 1483 1484 if (ctrlr->resource == NULL) 1485 goto nores; 1486 if (!mtx_initialized(&ctrlr->adminq.lock)) 1487 goto noadminq; 1488 1489 /* 1490 * Check whether it is a hot unplug or a clean driver detach. 1491 * If device is not there any more, skip any shutdown commands. 1492 */ 1493 gone = (nvme_mmio_read_4(ctrlr, csts) == NVME_GONE); 1494 if (gone) 1495 nvme_ctrlr_fail(ctrlr); 1496 else 1497 nvme_notify_fail_consumers(ctrlr); 1498 1499 for (i = 0; i < NVME_MAX_NAMESPACES; i++) 1500 nvme_ns_destruct(&ctrlr->ns[i]); 1501 1502 if (ctrlr->cdev) 1503 destroy_dev(ctrlr->cdev); 1504 1505 if (ctrlr->is_initialized) { 1506 if (!gone) { 1507 if (ctrlr->hmb_nchunks > 0) 1508 nvme_ctrlr_hmb_enable(ctrlr, false, false); 1509 nvme_ctrlr_delete_qpairs(ctrlr); 1510 } 1511 nvme_ctrlr_hmb_free(ctrlr); 1512 } 1513 if (ctrlr->ioq != NULL) { 1514 for (i = 0; i < ctrlr->num_io_queues; i++) 1515 nvme_io_qpair_destroy(&ctrlr->ioq[i]); 1516 free(ctrlr->ioq, M_NVME); 1517 } 1518 nvme_admin_qpair_destroy(&ctrlr->adminq); 1519 1520 /* 1521 * Notify the controller of a shutdown, even though this is due to 1522 * a driver unload, not a system shutdown (this path is not invoked 1523 * during shutdown). This ensures the controller receives a 1524 * shutdown notification in case the system is shutdown before 1525 * reloading the driver. 1526 */ 1527 if (!gone) 1528 nvme_ctrlr_shutdown(ctrlr); 1529 1530 if (!gone) 1531 nvme_ctrlr_disable(ctrlr); 1532 1533 noadminq: 1534 if (ctrlr->taskqueue) 1535 taskqueue_free(ctrlr->taskqueue); 1536 1537 if (ctrlr->tag) 1538 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag); 1539 1540 if (ctrlr->res) 1541 bus_release_resource(ctrlr->dev, SYS_RES_IRQ, 1542 rman_get_rid(ctrlr->res), ctrlr->res); 1543 1544 if (ctrlr->bar4_resource != NULL) { 1545 bus_release_resource(dev, SYS_RES_MEMORY, 1546 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 1547 } 1548 1549 bus_release_resource(dev, SYS_RES_MEMORY, 1550 ctrlr->resource_id, ctrlr->resource); 1551 1552 nores: 1553 mtx_destroy(&ctrlr->lock); 1554 } 1555 1556 void 1557 nvme_ctrlr_shutdown(struct nvme_controller *ctrlr) 1558 { 1559 uint32_t cc; 1560 uint32_t csts; 1561 int timeout; 1562 1563 cc = nvme_mmio_read_4(ctrlr, cc); 1564 cc &= ~(NVME_CC_REG_SHN_MASK << NVME_CC_REG_SHN_SHIFT); 1565 cc |= NVME_SHN_NORMAL << NVME_CC_REG_SHN_SHIFT; 1566 nvme_mmio_write_4(ctrlr, cc, cc); 1567 1568 timeout = ticks + (ctrlr->cdata.rtd3e == 0 ? 5 * hz : 1569 ((uint64_t)ctrlr->cdata.rtd3e * hz + 999999) / 1000000); 1570 while (1) { 1571 csts = nvme_mmio_read_4(ctrlr, csts); 1572 if (csts == NVME_GONE) /* Hot unplug. */ 1573 break; 1574 if (NVME_CSTS_GET_SHST(csts) == NVME_SHST_COMPLETE) 1575 break; 1576 if (timeout - ticks < 0) { 1577 nvme_printf(ctrlr, "shutdown timeout\n"); 1578 break; 1579 } 1580 pause("nvmeshut", 1); 1581 } 1582 } 1583 1584 void 1585 nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 1586 struct nvme_request *req) 1587 { 1588 1589 nvme_qpair_submit_request(&ctrlr->adminq, req); 1590 } 1591 1592 void 1593 nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 1594 struct nvme_request *req) 1595 { 1596 struct nvme_qpair *qpair; 1597 1598 qpair = &ctrlr->ioq[QP(ctrlr, curcpu)]; 1599 nvme_qpair_submit_request(qpair, req); 1600 } 1601 1602 device_t 1603 nvme_ctrlr_get_device(struct nvme_controller *ctrlr) 1604 { 1605 1606 return (ctrlr->dev); 1607 } 1608 1609 const struct nvme_controller_data * 1610 nvme_ctrlr_get_data(struct nvme_controller *ctrlr) 1611 { 1612 1613 return (&ctrlr->cdata); 1614 } 1615 1616 int 1617 nvme_ctrlr_suspend(struct nvme_controller *ctrlr) 1618 { 1619 int to = hz; 1620 1621 /* 1622 * Can't touch failed controllers, so it's already suspended. 1623 */ 1624 if (ctrlr->is_failed) 1625 return (0); 1626 1627 /* 1628 * We don't want the reset taskqueue running, since it does similar 1629 * things, so prevent it from running after we start. Wait for any reset 1630 * that may have been started to complete. The reset process we follow 1631 * will ensure that any new I/O will queue and be given to the hardware 1632 * after we resume (though there should be none). 1633 */ 1634 while (atomic_cmpset_32(&ctrlr->is_resetting, 0, 1) == 0 && to-- > 0) 1635 pause("nvmesusp", 1); 1636 if (to <= 0) { 1637 nvme_printf(ctrlr, 1638 "Competing reset task didn't finish. Try again later.\n"); 1639 return (EWOULDBLOCK); 1640 } 1641 1642 if (ctrlr->hmb_nchunks > 0) 1643 nvme_ctrlr_hmb_enable(ctrlr, false, false); 1644 1645 /* 1646 * Per Section 7.6.2 of NVMe spec 1.4, to properly suspend, we need to 1647 * delete the hardware I/O queues, and then shutdown. This properly 1648 * flushes any metadata the drive may have stored so it can survive 1649 * having its power removed and prevents the unsafe shutdown count from 1650 * incriminating. Once we delete the qpairs, we have to disable them 1651 * before shutting down. The delay is out of paranoia in 1652 * nvme_ctrlr_hw_reset, and is repeated here (though we should have no 1653 * pending I/O that the delay copes with). 1654 */ 1655 nvme_ctrlr_delete_qpairs(ctrlr); 1656 nvme_ctrlr_disable_qpairs(ctrlr); 1657 pause("nvmesusp", hz / 10); 1658 nvme_ctrlr_shutdown(ctrlr); 1659 1660 return (0); 1661 } 1662 1663 int 1664 nvme_ctrlr_resume(struct nvme_controller *ctrlr) 1665 { 1666 1667 /* 1668 * Can't touch failed controllers, so nothing to do to resume. 1669 */ 1670 if (ctrlr->is_failed) 1671 return (0); 1672 1673 /* 1674 * Have to reset the hardware twice, just like we do on attach. See 1675 * nmve_attach() for why. 1676 */ 1677 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1678 goto fail; 1679 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1680 goto fail; 1681 1682 /* 1683 * Now that we've reset the hardware, we can restart the controller. Any 1684 * I/O that was pending is requeued. Any admin commands are aborted with 1685 * an error. Once we've restarted, take the controller out of reset. 1686 */ 1687 nvme_ctrlr_start(ctrlr, true); 1688 (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1689 1690 return (0); 1691 fail: 1692 /* 1693 * Since we can't bring the controller out of reset, announce and fail 1694 * the controller. However, we have to return success for the resume 1695 * itself, due to questionable APIs. 1696 */ 1697 nvme_printf(ctrlr, "Failed to reset on resume, failing.\n"); 1698 nvme_ctrlr_fail(ctrlr); 1699 (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1700 return (0); 1701 } 1702