1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2016 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_cam.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/buf.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/ioccom.h> 40 #include <sys/proc.h> 41 #include <sys/smp.h> 42 #include <sys/uio.h> 43 #include <sys/endian.h> 44 #include <vm/vm.h> 45 46 #include "nvme_private.h" 47 48 #define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */ 49 50 static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 51 struct nvme_async_event_request *aer); 52 53 static int 54 nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr) 55 { 56 struct nvme_qpair *qpair; 57 uint32_t num_entries; 58 int error; 59 60 qpair = &ctrlr->adminq; 61 qpair->id = 0; 62 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1; 63 qpair->domain = ctrlr->domain; 64 65 num_entries = NVME_ADMIN_ENTRIES; 66 TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries); 67 /* 68 * If admin_entries was overridden to an invalid value, revert it 69 * back to our default value. 70 */ 71 if (num_entries < NVME_MIN_ADMIN_ENTRIES || 72 num_entries > NVME_MAX_ADMIN_ENTRIES) { 73 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d " 74 "specified\n", num_entries); 75 num_entries = NVME_ADMIN_ENTRIES; 76 } 77 78 /* 79 * The admin queue's max xfer size is treated differently than the 80 * max I/O xfer size. 16KB is sufficient here - maybe even less? 81 */ 82 error = nvme_qpair_construct(qpair, num_entries, NVME_ADMIN_TRACKERS, 83 ctrlr); 84 return (error); 85 } 86 87 #define QP(ctrlr, c) ((c) * (ctrlr)->num_io_queues / mp_ncpus) 88 89 static int 90 nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr) 91 { 92 struct nvme_qpair *qpair; 93 uint32_t cap_lo; 94 uint16_t mqes; 95 int c, error, i, n; 96 int num_entries, num_trackers, max_entries; 97 98 /* 99 * NVMe spec sets a hard limit of 64K max entries, but devices may 100 * specify a smaller limit, so we need to check the MQES field in the 101 * capabilities register. We have to cap the number of entries to the 102 * current stride allows for in BAR 0/1, otherwise the remainder entries 103 * are inaccessable. MQES should reflect this, and this is just a 104 * fail-safe. 105 */ 106 max_entries = 107 (rman_get_size(ctrlr->resource) - nvme_mmio_offsetof(doorbell[0])) / 108 (1 << (ctrlr->dstrd + 1)); 109 num_entries = NVME_IO_ENTRIES; 110 TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries); 111 cap_lo = nvme_mmio_read_4(ctrlr, cap_lo); 112 mqes = NVME_CAP_LO_MQES(cap_lo); 113 num_entries = min(num_entries, mqes + 1); 114 num_entries = min(num_entries, max_entries); 115 116 num_trackers = NVME_IO_TRACKERS; 117 TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers); 118 119 num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS); 120 num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS); 121 /* 122 * No need to have more trackers than entries in the submit queue. Note 123 * also that for a queue size of N, we can only have (N-1) commands 124 * outstanding, hence the "-1" here. 125 */ 126 num_trackers = min(num_trackers, (num_entries-1)); 127 128 /* 129 * Our best estimate for the maximum number of I/Os that we should 130 * normally have in flight at one time. This should be viewed as a hint, 131 * not a hard limit and will need to be revisited when the upper layers 132 * of the storage system grows multi-queue support. 133 */ 134 ctrlr->max_hw_pend_io = num_trackers * ctrlr->num_io_queues * 3 / 4; 135 136 ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair), 137 M_NVME, M_ZERO | M_WAITOK); 138 139 for (i = c = n = 0; i < ctrlr->num_io_queues; i++, c += n) { 140 qpair = &ctrlr->ioq[i]; 141 142 /* 143 * Admin queue has ID=0. IO queues start at ID=1 - 144 * hence the 'i+1' here. 145 */ 146 qpair->id = i + 1; 147 if (ctrlr->num_io_queues > 1) { 148 /* Find number of CPUs served by this queue. */ 149 for (n = 1; QP(ctrlr, c + n) == i; n++) 150 ; 151 /* Shuffle multiple NVMe devices between CPUs. */ 152 qpair->cpu = c + (device_get_unit(ctrlr->dev)+n/2) % n; 153 qpair->domain = pcpu_find(qpair->cpu)->pc_domain; 154 } else { 155 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1; 156 qpair->domain = ctrlr->domain; 157 } 158 159 /* 160 * For I/O queues, use the controller-wide max_xfer_size 161 * calculated in nvme_attach(). 162 */ 163 error = nvme_qpair_construct(qpair, num_entries, num_trackers, 164 ctrlr); 165 if (error) 166 return (error); 167 168 /* 169 * Do not bother binding interrupts if we only have one I/O 170 * interrupt thread for this controller. 171 */ 172 if (ctrlr->num_io_queues > 1) 173 bus_bind_intr(ctrlr->dev, qpair->res, qpair->cpu); 174 } 175 176 return (0); 177 } 178 179 static void 180 nvme_ctrlr_fail(struct nvme_controller *ctrlr) 181 { 182 int i; 183 184 ctrlr->is_failed = true; 185 nvme_admin_qpair_disable(&ctrlr->adminq); 186 nvme_qpair_fail(&ctrlr->adminq); 187 if (ctrlr->ioq != NULL) { 188 for (i = 0; i < ctrlr->num_io_queues; i++) { 189 nvme_io_qpair_disable(&ctrlr->ioq[i]); 190 nvme_qpair_fail(&ctrlr->ioq[i]); 191 } 192 } 193 nvme_notify_fail_consumers(ctrlr); 194 } 195 196 void 197 nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 198 struct nvme_request *req) 199 { 200 201 mtx_lock(&ctrlr->lock); 202 STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq); 203 mtx_unlock(&ctrlr->lock); 204 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task); 205 } 206 207 static void 208 nvme_ctrlr_fail_req_task(void *arg, int pending) 209 { 210 struct nvme_controller *ctrlr = arg; 211 struct nvme_request *req; 212 213 mtx_lock(&ctrlr->lock); 214 while ((req = STAILQ_FIRST(&ctrlr->fail_req)) != NULL) { 215 STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq); 216 mtx_unlock(&ctrlr->lock); 217 nvme_qpair_manual_complete_request(req->qpair, req, 218 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST); 219 mtx_lock(&ctrlr->lock); 220 } 221 mtx_unlock(&ctrlr->lock); 222 } 223 224 static int 225 nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr, int desired_val) 226 { 227 int ms_waited; 228 uint32_t csts; 229 230 ms_waited = 0; 231 while (1) { 232 csts = nvme_mmio_read_4(ctrlr, csts); 233 if (csts == 0xffffffff) /* Hot unplug. */ 234 return (ENXIO); 235 if (((csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK) 236 == desired_val) 237 break; 238 if (ms_waited++ > ctrlr->ready_timeout_in_ms) { 239 nvme_printf(ctrlr, "controller ready did not become %d " 240 "within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms); 241 return (ENXIO); 242 } 243 DELAY(1000); 244 } 245 246 return (0); 247 } 248 249 static int 250 nvme_ctrlr_disable(struct nvme_controller *ctrlr) 251 { 252 uint32_t cc; 253 uint32_t csts; 254 uint8_t en, rdy; 255 int err; 256 257 cc = nvme_mmio_read_4(ctrlr, cc); 258 csts = nvme_mmio_read_4(ctrlr, csts); 259 260 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; 261 rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK; 262 263 /* 264 * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1 265 * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when 266 * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY 267 * isn't the desired value. Short circuit if we're already disabled. 268 */ 269 if (en == 1) { 270 if (rdy == 0) { 271 /* EN == 1, wait for RDY == 1 or fail */ 272 err = nvme_ctrlr_wait_for_ready(ctrlr, 1); 273 if (err != 0) 274 return (err); 275 } 276 } else { 277 /* EN == 0 already wait for RDY == 0 */ 278 if (rdy == 0) 279 return (0); 280 else 281 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 282 } 283 284 cc &= ~NVME_CC_REG_EN_MASK; 285 nvme_mmio_write_4(ctrlr, cc, cc); 286 /* 287 * Some drives have issues with accessing the mmio after we 288 * disable, so delay for a bit after we write the bit to 289 * cope with these issues. 290 */ 291 if (ctrlr->quirks & QUIRK_DELAY_B4_CHK_RDY) 292 pause("nvmeR", B4_CHK_RDY_DELAY_MS * hz / 1000); 293 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 294 } 295 296 static int 297 nvme_ctrlr_enable(struct nvme_controller *ctrlr) 298 { 299 uint32_t cc; 300 uint32_t csts; 301 uint32_t aqa; 302 uint32_t qsize; 303 uint8_t en, rdy; 304 int err; 305 306 cc = nvme_mmio_read_4(ctrlr, cc); 307 csts = nvme_mmio_read_4(ctrlr, csts); 308 309 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; 310 rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK; 311 312 /* 313 * See note in nvme_ctrlr_disable. Short circuit if we're already enabled. 314 */ 315 if (en == 1) { 316 if (rdy == 1) 317 return (0); 318 else 319 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 320 } else { 321 /* EN == 0 already wait for RDY == 0 or fail */ 322 err = nvme_ctrlr_wait_for_ready(ctrlr, 0); 323 if (err != 0) 324 return (err); 325 } 326 327 nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr); 328 DELAY(5000); 329 nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr); 330 DELAY(5000); 331 332 /* acqs and asqs are 0-based. */ 333 qsize = ctrlr->adminq.num_entries - 1; 334 335 aqa = 0; 336 aqa = (qsize & NVME_AQA_REG_ACQS_MASK) << NVME_AQA_REG_ACQS_SHIFT; 337 aqa |= (qsize & NVME_AQA_REG_ASQS_MASK) << NVME_AQA_REG_ASQS_SHIFT; 338 nvme_mmio_write_4(ctrlr, aqa, aqa); 339 DELAY(5000); 340 341 /* Initialization values for CC */ 342 cc = 0; 343 cc |= 1 << NVME_CC_REG_EN_SHIFT; 344 cc |= 0 << NVME_CC_REG_CSS_SHIFT; 345 cc |= 0 << NVME_CC_REG_AMS_SHIFT; 346 cc |= 0 << NVME_CC_REG_SHN_SHIFT; 347 cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */ 348 cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */ 349 350 /* This evaluates to 0, which is according to spec. */ 351 cc |= (PAGE_SIZE >> 13) << NVME_CC_REG_MPS_SHIFT; 352 353 nvme_mmio_write_4(ctrlr, cc, cc); 354 355 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 356 } 357 358 static void 359 nvme_ctrlr_disable_qpairs(struct nvme_controller *ctrlr) 360 { 361 int i; 362 363 nvme_admin_qpair_disable(&ctrlr->adminq); 364 /* 365 * I/O queues are not allocated before the initial HW 366 * reset, so do not try to disable them. Use is_initialized 367 * to determine if this is the initial HW reset. 368 */ 369 if (ctrlr->is_initialized) { 370 for (i = 0; i < ctrlr->num_io_queues; i++) 371 nvme_io_qpair_disable(&ctrlr->ioq[i]); 372 } 373 } 374 375 int 376 nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr) 377 { 378 int err; 379 380 nvme_ctrlr_disable_qpairs(ctrlr); 381 382 DELAY(100*1000); 383 384 err = nvme_ctrlr_disable(ctrlr); 385 if (err != 0) 386 return err; 387 return (nvme_ctrlr_enable(ctrlr)); 388 } 389 390 void 391 nvme_ctrlr_reset(struct nvme_controller *ctrlr) 392 { 393 int cmpset; 394 395 cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1); 396 397 if (cmpset == 0 || ctrlr->is_failed) 398 /* 399 * Controller is already resetting or has failed. Return 400 * immediately since there is no need to kick off another 401 * reset in these cases. 402 */ 403 return; 404 405 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task); 406 } 407 408 static int 409 nvme_ctrlr_identify(struct nvme_controller *ctrlr) 410 { 411 struct nvme_completion_poll_status status; 412 413 status.done = 0; 414 nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata, 415 nvme_completion_poll_cb, &status); 416 nvme_completion_poll(&status); 417 if (nvme_completion_is_error(&status.cpl)) { 418 nvme_printf(ctrlr, "nvme_identify_controller failed!\n"); 419 return (ENXIO); 420 } 421 422 /* Convert data to host endian */ 423 nvme_controller_data_swapbytes(&ctrlr->cdata); 424 425 /* 426 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 427 * controller supports. 428 */ 429 if (ctrlr->cdata.mdts > 0) 430 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size, 431 ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts))); 432 433 return (0); 434 } 435 436 static int 437 nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr) 438 { 439 struct nvme_completion_poll_status status; 440 int cq_allocated, sq_allocated; 441 442 status.done = 0; 443 nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues, 444 nvme_completion_poll_cb, &status); 445 nvme_completion_poll(&status); 446 if (nvme_completion_is_error(&status.cpl)) { 447 nvme_printf(ctrlr, "nvme_ctrlr_set_num_qpairs failed!\n"); 448 return (ENXIO); 449 } 450 451 /* 452 * Data in cdw0 is 0-based. 453 * Lower 16-bits indicate number of submission queues allocated. 454 * Upper 16-bits indicate number of completion queues allocated. 455 */ 456 sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1; 457 cq_allocated = (status.cpl.cdw0 >> 16) + 1; 458 459 /* 460 * Controller may allocate more queues than we requested, 461 * so use the minimum of the number requested and what was 462 * actually allocated. 463 */ 464 ctrlr->num_io_queues = min(ctrlr->num_io_queues, sq_allocated); 465 ctrlr->num_io_queues = min(ctrlr->num_io_queues, cq_allocated); 466 if (ctrlr->num_io_queues > vm_ndomains) 467 ctrlr->num_io_queues -= ctrlr->num_io_queues % vm_ndomains; 468 469 return (0); 470 } 471 472 static int 473 nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr) 474 { 475 struct nvme_completion_poll_status status; 476 struct nvme_qpair *qpair; 477 int i; 478 479 for (i = 0; i < ctrlr->num_io_queues; i++) { 480 qpair = &ctrlr->ioq[i]; 481 482 status.done = 0; 483 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair, 484 nvme_completion_poll_cb, &status); 485 nvme_completion_poll(&status); 486 if (nvme_completion_is_error(&status.cpl)) { 487 nvme_printf(ctrlr, "nvme_create_io_cq failed!\n"); 488 return (ENXIO); 489 } 490 491 status.done = 0; 492 nvme_ctrlr_cmd_create_io_sq(qpair->ctrlr, qpair, 493 nvme_completion_poll_cb, &status); 494 nvme_completion_poll(&status); 495 if (nvme_completion_is_error(&status.cpl)) { 496 nvme_printf(ctrlr, "nvme_create_io_sq failed!\n"); 497 return (ENXIO); 498 } 499 } 500 501 return (0); 502 } 503 504 static int 505 nvme_ctrlr_delete_qpairs(struct nvme_controller *ctrlr) 506 { 507 struct nvme_completion_poll_status status; 508 struct nvme_qpair *qpair; 509 510 for (int i = 0; i < ctrlr->num_io_queues; i++) { 511 qpair = &ctrlr->ioq[i]; 512 513 status.done = 0; 514 nvme_ctrlr_cmd_delete_io_sq(ctrlr, qpair, 515 nvme_completion_poll_cb, &status); 516 nvme_completion_poll(&status); 517 if (nvme_completion_is_error(&status.cpl)) { 518 nvme_printf(ctrlr, "nvme_destroy_io_sq failed!\n"); 519 return (ENXIO); 520 } 521 522 status.done = 0; 523 nvme_ctrlr_cmd_delete_io_cq(ctrlr, qpair, 524 nvme_completion_poll_cb, &status); 525 nvme_completion_poll(&status); 526 if (nvme_completion_is_error(&status.cpl)) { 527 nvme_printf(ctrlr, "nvme_destroy_io_cq failed!\n"); 528 return (ENXIO); 529 } 530 } 531 532 return (0); 533 } 534 535 static int 536 nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr) 537 { 538 struct nvme_namespace *ns; 539 uint32_t i; 540 541 for (i = 0; i < min(ctrlr->cdata.nn, NVME_MAX_NAMESPACES); i++) { 542 ns = &ctrlr->ns[i]; 543 nvme_ns_construct(ns, i+1, ctrlr); 544 } 545 546 return (0); 547 } 548 549 static bool 550 is_log_page_id_valid(uint8_t page_id) 551 { 552 553 switch (page_id) { 554 case NVME_LOG_ERROR: 555 case NVME_LOG_HEALTH_INFORMATION: 556 case NVME_LOG_FIRMWARE_SLOT: 557 case NVME_LOG_CHANGED_NAMESPACE: 558 case NVME_LOG_COMMAND_EFFECT: 559 case NVME_LOG_RES_NOTIFICATION: 560 case NVME_LOG_SANITIZE_STATUS: 561 return (true); 562 } 563 564 return (false); 565 } 566 567 static uint32_t 568 nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id) 569 { 570 uint32_t log_page_size; 571 572 switch (page_id) { 573 case NVME_LOG_ERROR: 574 log_page_size = min( 575 sizeof(struct nvme_error_information_entry) * 576 (ctrlr->cdata.elpe + 1), NVME_MAX_AER_LOG_SIZE); 577 break; 578 case NVME_LOG_HEALTH_INFORMATION: 579 log_page_size = sizeof(struct nvme_health_information_page); 580 break; 581 case NVME_LOG_FIRMWARE_SLOT: 582 log_page_size = sizeof(struct nvme_firmware_page); 583 break; 584 case NVME_LOG_CHANGED_NAMESPACE: 585 log_page_size = sizeof(struct nvme_ns_list); 586 break; 587 case NVME_LOG_COMMAND_EFFECT: 588 log_page_size = sizeof(struct nvme_command_effects_page); 589 break; 590 case NVME_LOG_RES_NOTIFICATION: 591 log_page_size = sizeof(struct nvme_res_notification_page); 592 break; 593 case NVME_LOG_SANITIZE_STATUS: 594 log_page_size = sizeof(struct nvme_sanitize_status_page); 595 break; 596 default: 597 log_page_size = 0; 598 break; 599 } 600 601 return (log_page_size); 602 } 603 604 static void 605 nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr, 606 uint8_t state) 607 { 608 609 if (state & NVME_CRIT_WARN_ST_AVAILABLE_SPARE) 610 nvme_printf(ctrlr, "available spare space below threshold\n"); 611 612 if (state & NVME_CRIT_WARN_ST_TEMPERATURE) 613 nvme_printf(ctrlr, "temperature above threshold\n"); 614 615 if (state & NVME_CRIT_WARN_ST_DEVICE_RELIABILITY) 616 nvme_printf(ctrlr, "device reliability degraded\n"); 617 618 if (state & NVME_CRIT_WARN_ST_READ_ONLY) 619 nvme_printf(ctrlr, "media placed in read only mode\n"); 620 621 if (state & NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP) 622 nvme_printf(ctrlr, "volatile memory backup device failed\n"); 623 624 if (state & NVME_CRIT_WARN_ST_RESERVED_MASK) 625 nvme_printf(ctrlr, 626 "unknown critical warning(s): state = 0x%02x\n", state); 627 } 628 629 static void 630 nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl) 631 { 632 struct nvme_async_event_request *aer = arg; 633 struct nvme_health_information_page *health_info; 634 struct nvme_ns_list *nsl; 635 struct nvme_error_information_entry *err; 636 int i; 637 638 /* 639 * If the log page fetch for some reason completed with an error, 640 * don't pass log page data to the consumers. In practice, this case 641 * should never happen. 642 */ 643 if (nvme_completion_is_error(cpl)) 644 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 645 aer->log_page_id, NULL, 0); 646 else { 647 /* Convert data to host endian */ 648 switch (aer->log_page_id) { 649 case NVME_LOG_ERROR: 650 err = (struct nvme_error_information_entry *)aer->log_page_buffer; 651 for (i = 0; i < (aer->ctrlr->cdata.elpe + 1); i++) 652 nvme_error_information_entry_swapbytes(err++); 653 break; 654 case NVME_LOG_HEALTH_INFORMATION: 655 nvme_health_information_page_swapbytes( 656 (struct nvme_health_information_page *)aer->log_page_buffer); 657 break; 658 case NVME_LOG_FIRMWARE_SLOT: 659 nvme_firmware_page_swapbytes( 660 (struct nvme_firmware_page *)aer->log_page_buffer); 661 break; 662 case NVME_LOG_CHANGED_NAMESPACE: 663 nvme_ns_list_swapbytes( 664 (struct nvme_ns_list *)aer->log_page_buffer); 665 break; 666 case NVME_LOG_COMMAND_EFFECT: 667 nvme_command_effects_page_swapbytes( 668 (struct nvme_command_effects_page *)aer->log_page_buffer); 669 break; 670 case NVME_LOG_RES_NOTIFICATION: 671 nvme_res_notification_page_swapbytes( 672 (struct nvme_res_notification_page *)aer->log_page_buffer); 673 break; 674 case NVME_LOG_SANITIZE_STATUS: 675 nvme_sanitize_status_page_swapbytes( 676 (struct nvme_sanitize_status_page *)aer->log_page_buffer); 677 break; 678 case INTEL_LOG_TEMP_STATS: 679 intel_log_temp_stats_swapbytes( 680 (struct intel_log_temp_stats *)aer->log_page_buffer); 681 break; 682 default: 683 break; 684 } 685 686 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) { 687 health_info = (struct nvme_health_information_page *) 688 aer->log_page_buffer; 689 nvme_ctrlr_log_critical_warnings(aer->ctrlr, 690 health_info->critical_warning); 691 /* 692 * Critical warnings reported through the 693 * SMART/health log page are persistent, so 694 * clear the associated bits in the async event 695 * config so that we do not receive repeated 696 * notifications for the same event. 697 */ 698 aer->ctrlr->async_event_config &= 699 ~health_info->critical_warning; 700 nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr, 701 aer->ctrlr->async_event_config, NULL, NULL); 702 } else if (aer->log_page_id == NVME_LOG_CHANGED_NAMESPACE && 703 !nvme_use_nvd) { 704 nsl = (struct nvme_ns_list *)aer->log_page_buffer; 705 for (i = 0; i < nitems(nsl->ns) && nsl->ns[i] != 0; i++) { 706 if (nsl->ns[i] > NVME_MAX_NAMESPACES) 707 break; 708 nvme_notify_ns(aer->ctrlr, nsl->ns[i]); 709 } 710 } 711 712 713 /* 714 * Pass the cpl data from the original async event completion, 715 * not the log page fetch. 716 */ 717 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 718 aer->log_page_id, aer->log_page_buffer, aer->log_page_size); 719 } 720 721 /* 722 * Repost another asynchronous event request to replace the one 723 * that just completed. 724 */ 725 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 726 } 727 728 static void 729 nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl) 730 { 731 struct nvme_async_event_request *aer = arg; 732 733 if (nvme_completion_is_error(cpl)) { 734 /* 735 * Do not retry failed async event requests. This avoids 736 * infinite loops where a new async event request is submitted 737 * to replace the one just failed, only to fail again and 738 * perpetuate the loop. 739 */ 740 return; 741 } 742 743 /* Associated log page is in bits 23:16 of completion entry dw0. */ 744 aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16; 745 746 nvme_printf(aer->ctrlr, "async event occurred (type 0x%x, info 0x%02x," 747 " page 0x%02x)\n", (cpl->cdw0 & 0x07), (cpl->cdw0 & 0xFF00) >> 8, 748 aer->log_page_id); 749 750 if (is_log_page_id_valid(aer->log_page_id)) { 751 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr, 752 aer->log_page_id); 753 memcpy(&aer->cpl, cpl, sizeof(*cpl)); 754 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id, 755 NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer, 756 aer->log_page_size, nvme_ctrlr_async_event_log_page_cb, 757 aer); 758 /* Wait to notify consumers until after log page is fetched. */ 759 } else { 760 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id, 761 NULL, 0); 762 763 /* 764 * Repost another asynchronous event request to replace the one 765 * that just completed. 766 */ 767 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 768 } 769 } 770 771 static void 772 nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 773 struct nvme_async_event_request *aer) 774 { 775 struct nvme_request *req; 776 777 aer->ctrlr = ctrlr; 778 req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer); 779 aer->req = req; 780 781 /* 782 * Disable timeout here, since asynchronous event requests should by 783 * nature never be timed out. 784 */ 785 req->timeout = false; 786 req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST; 787 nvme_ctrlr_submit_admin_request(ctrlr, req); 788 } 789 790 static void 791 nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr) 792 { 793 struct nvme_completion_poll_status status; 794 struct nvme_async_event_request *aer; 795 uint32_t i; 796 797 ctrlr->async_event_config = NVME_CRIT_WARN_ST_AVAILABLE_SPARE | 798 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY | 799 NVME_CRIT_WARN_ST_READ_ONLY | 800 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP; 801 if (ctrlr->cdata.ver >= NVME_REV(1, 2)) 802 ctrlr->async_event_config |= 0x300; 803 804 status.done = 0; 805 nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD, 806 0, NULL, 0, nvme_completion_poll_cb, &status); 807 nvme_completion_poll(&status); 808 if (nvme_completion_is_error(&status.cpl) || 809 (status.cpl.cdw0 & 0xFFFF) == 0xFFFF || 810 (status.cpl.cdw0 & 0xFFFF) == 0x0000) { 811 nvme_printf(ctrlr, "temperature threshold not supported\n"); 812 } else 813 ctrlr->async_event_config |= NVME_CRIT_WARN_ST_TEMPERATURE; 814 815 nvme_ctrlr_cmd_set_async_event_config(ctrlr, 816 ctrlr->async_event_config, NULL, NULL); 817 818 /* aerl is a zero-based value, so we need to add 1 here. */ 819 ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1)); 820 821 for (i = 0; i < ctrlr->num_aers; i++) { 822 aer = &ctrlr->aer[i]; 823 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 824 } 825 } 826 827 static void 828 nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr) 829 { 830 831 ctrlr->int_coal_time = 0; 832 TUNABLE_INT_FETCH("hw.nvme.int_coal_time", 833 &ctrlr->int_coal_time); 834 835 ctrlr->int_coal_threshold = 0; 836 TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold", 837 &ctrlr->int_coal_threshold); 838 839 nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time, 840 ctrlr->int_coal_threshold, NULL, NULL); 841 } 842 843 static void 844 nvme_ctrlr_hmb_free(struct nvme_controller *ctrlr) 845 { 846 struct nvme_hmb_chunk *hmbc; 847 int i; 848 849 if (ctrlr->hmb_desc_paddr) { 850 bus_dmamap_unload(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map); 851 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr, 852 ctrlr->hmb_desc_map); 853 ctrlr->hmb_desc_paddr = 0; 854 } 855 if (ctrlr->hmb_desc_tag) { 856 bus_dma_tag_destroy(ctrlr->hmb_desc_tag); 857 ctrlr->hmb_desc_tag = NULL; 858 } 859 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 860 hmbc = &ctrlr->hmb_chunks[i]; 861 bus_dmamap_unload(ctrlr->hmb_tag, hmbc->hmbc_map); 862 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr, 863 hmbc->hmbc_map); 864 } 865 ctrlr->hmb_nchunks = 0; 866 if (ctrlr->hmb_tag) { 867 bus_dma_tag_destroy(ctrlr->hmb_tag); 868 ctrlr->hmb_tag = NULL; 869 } 870 if (ctrlr->hmb_chunks) { 871 free(ctrlr->hmb_chunks, M_NVME); 872 ctrlr->hmb_chunks = NULL; 873 } 874 } 875 876 static void 877 nvme_ctrlr_hmb_alloc(struct nvme_controller *ctrlr) 878 { 879 struct nvme_hmb_chunk *hmbc; 880 size_t pref, min, minc, size; 881 int err, i; 882 uint64_t max; 883 884 /* Limit HMB to 5% of RAM size per device by default. */ 885 max = (uint64_t)physmem * PAGE_SIZE / 20; 886 TUNABLE_UINT64_FETCH("hw.nvme.hmb_max", &max); 887 888 min = (long long unsigned)ctrlr->cdata.hmmin * 4096; 889 if (max == 0 || max < min) 890 return; 891 pref = MIN((long long unsigned)ctrlr->cdata.hmpre * 4096, max); 892 minc = MAX(ctrlr->cdata.hmminds * 4096, PAGE_SIZE); 893 if (min > 0 && ctrlr->cdata.hmmaxd > 0) 894 minc = MAX(minc, min / ctrlr->cdata.hmmaxd); 895 ctrlr->hmb_chunk = pref; 896 897 again: 898 ctrlr->hmb_chunk = roundup2(ctrlr->hmb_chunk, PAGE_SIZE); 899 ctrlr->hmb_nchunks = howmany(pref, ctrlr->hmb_chunk); 900 if (ctrlr->cdata.hmmaxd > 0 && ctrlr->hmb_nchunks > ctrlr->cdata.hmmaxd) 901 ctrlr->hmb_nchunks = ctrlr->cdata.hmmaxd; 902 ctrlr->hmb_chunks = malloc(sizeof(struct nvme_hmb_chunk) * 903 ctrlr->hmb_nchunks, M_NVME, M_WAITOK); 904 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 905 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 906 ctrlr->hmb_chunk, 1, ctrlr->hmb_chunk, 0, NULL, NULL, &ctrlr->hmb_tag); 907 if (err != 0) { 908 nvme_printf(ctrlr, "HMB tag create failed %d\n", err); 909 nvme_ctrlr_hmb_free(ctrlr); 910 return; 911 } 912 913 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 914 hmbc = &ctrlr->hmb_chunks[i]; 915 if (bus_dmamem_alloc(ctrlr->hmb_tag, 916 (void **)&hmbc->hmbc_vaddr, BUS_DMA_NOWAIT, 917 &hmbc->hmbc_map)) { 918 nvme_printf(ctrlr, "failed to alloc HMB\n"); 919 break; 920 } 921 if (bus_dmamap_load(ctrlr->hmb_tag, hmbc->hmbc_map, 922 hmbc->hmbc_vaddr, ctrlr->hmb_chunk, nvme_single_map, 923 &hmbc->hmbc_paddr, BUS_DMA_NOWAIT) != 0) { 924 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr, 925 hmbc->hmbc_map); 926 nvme_printf(ctrlr, "failed to load HMB\n"); 927 break; 928 } 929 bus_dmamap_sync(ctrlr->hmb_tag, hmbc->hmbc_map, 930 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 931 } 932 933 if (i < ctrlr->hmb_nchunks && i * ctrlr->hmb_chunk < min && 934 ctrlr->hmb_chunk / 2 >= minc) { 935 ctrlr->hmb_nchunks = i; 936 nvme_ctrlr_hmb_free(ctrlr); 937 ctrlr->hmb_chunk /= 2; 938 goto again; 939 } 940 ctrlr->hmb_nchunks = i; 941 if (ctrlr->hmb_nchunks * ctrlr->hmb_chunk < min) { 942 nvme_ctrlr_hmb_free(ctrlr); 943 return; 944 } 945 946 size = sizeof(struct nvme_hmb_desc) * ctrlr->hmb_nchunks; 947 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 948 16, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 949 size, 1, size, 0, NULL, NULL, &ctrlr->hmb_desc_tag); 950 if (err != 0) { 951 nvme_printf(ctrlr, "HMB desc tag create failed %d\n", err); 952 nvme_ctrlr_hmb_free(ctrlr); 953 return; 954 } 955 if (bus_dmamem_alloc(ctrlr->hmb_desc_tag, 956 (void **)&ctrlr->hmb_desc_vaddr, BUS_DMA_WAITOK, 957 &ctrlr->hmb_desc_map)) { 958 nvme_printf(ctrlr, "failed to alloc HMB desc\n"); 959 nvme_ctrlr_hmb_free(ctrlr); 960 return; 961 } 962 if (bus_dmamap_load(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map, 963 ctrlr->hmb_desc_vaddr, size, nvme_single_map, 964 &ctrlr->hmb_desc_paddr, BUS_DMA_NOWAIT) != 0) { 965 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr, 966 ctrlr->hmb_desc_map); 967 nvme_printf(ctrlr, "failed to load HMB desc\n"); 968 nvme_ctrlr_hmb_free(ctrlr); 969 return; 970 } 971 972 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 973 ctrlr->hmb_desc_vaddr[i].addr = 974 htole64(ctrlr->hmb_chunks[i].hmbc_paddr); 975 ctrlr->hmb_desc_vaddr[i].size = htole32(ctrlr->hmb_chunk / 4096); 976 } 977 bus_dmamap_sync(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map, 978 BUS_DMASYNC_PREWRITE); 979 980 nvme_printf(ctrlr, "Allocated %lluMB host memory buffer\n", 981 (long long unsigned)ctrlr->hmb_nchunks * ctrlr->hmb_chunk 982 / 1024 / 1024); 983 } 984 985 static void 986 nvme_ctrlr_hmb_enable(struct nvme_controller *ctrlr, bool enable, bool memret) 987 { 988 struct nvme_completion_poll_status status; 989 uint32_t cdw11; 990 991 cdw11 = 0; 992 if (enable) 993 cdw11 |= 1; 994 if (memret) 995 cdw11 |= 2; 996 status.done = 0; 997 nvme_ctrlr_cmd_set_feature(ctrlr, NVME_FEAT_HOST_MEMORY_BUFFER, cdw11, 998 ctrlr->hmb_nchunks * ctrlr->hmb_chunk / 4096, ctrlr->hmb_desc_paddr, 999 ctrlr->hmb_desc_paddr >> 32, ctrlr->hmb_nchunks, NULL, 0, 1000 nvme_completion_poll_cb, &status); 1001 nvme_completion_poll(&status); 1002 if (nvme_completion_is_error(&status.cpl)) 1003 nvme_printf(ctrlr, "nvme_ctrlr_hmb_enable failed!\n"); 1004 } 1005 1006 static void 1007 nvme_ctrlr_start(void *ctrlr_arg, bool resetting) 1008 { 1009 struct nvme_controller *ctrlr = ctrlr_arg; 1010 uint32_t old_num_io_queues; 1011 int i; 1012 1013 /* 1014 * Only reset adminq here when we are restarting the 1015 * controller after a reset. During initialization, 1016 * we have already submitted admin commands to get 1017 * the number of I/O queues supported, so cannot reset 1018 * the adminq again here. 1019 */ 1020 if (resetting) 1021 nvme_qpair_reset(&ctrlr->adminq); 1022 1023 for (i = 0; i < ctrlr->num_io_queues; i++) 1024 nvme_qpair_reset(&ctrlr->ioq[i]); 1025 1026 nvme_admin_qpair_enable(&ctrlr->adminq); 1027 1028 if (nvme_ctrlr_identify(ctrlr) != 0) { 1029 nvme_ctrlr_fail(ctrlr); 1030 return; 1031 } 1032 1033 /* 1034 * The number of qpairs are determined during controller initialization, 1035 * including using NVMe SET_FEATURES/NUMBER_OF_QUEUES to determine the 1036 * HW limit. We call SET_FEATURES again here so that it gets called 1037 * after any reset for controllers that depend on the driver to 1038 * explicit specify how many queues it will use. This value should 1039 * never change between resets, so panic if somehow that does happen. 1040 */ 1041 if (resetting) { 1042 old_num_io_queues = ctrlr->num_io_queues; 1043 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) { 1044 nvme_ctrlr_fail(ctrlr); 1045 return; 1046 } 1047 1048 if (old_num_io_queues != ctrlr->num_io_queues) { 1049 panic("num_io_queues changed from %u to %u", 1050 old_num_io_queues, ctrlr->num_io_queues); 1051 } 1052 } 1053 1054 if (ctrlr->cdata.hmpre > 0 && ctrlr->hmb_nchunks == 0) { 1055 nvme_ctrlr_hmb_alloc(ctrlr); 1056 if (ctrlr->hmb_nchunks > 0) 1057 nvme_ctrlr_hmb_enable(ctrlr, true, false); 1058 } else if (ctrlr->hmb_nchunks > 0) 1059 nvme_ctrlr_hmb_enable(ctrlr, true, true); 1060 1061 if (nvme_ctrlr_create_qpairs(ctrlr) != 0) { 1062 nvme_ctrlr_fail(ctrlr); 1063 return; 1064 } 1065 1066 if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) { 1067 nvme_ctrlr_fail(ctrlr); 1068 return; 1069 } 1070 1071 nvme_ctrlr_configure_aer(ctrlr); 1072 nvme_ctrlr_configure_int_coalescing(ctrlr); 1073 1074 for (i = 0; i < ctrlr->num_io_queues; i++) 1075 nvme_io_qpair_enable(&ctrlr->ioq[i]); 1076 } 1077 1078 void 1079 nvme_ctrlr_start_config_hook(void *arg) 1080 { 1081 struct nvme_controller *ctrlr = arg; 1082 int status; 1083 1084 /* 1085 * Reset controller twice to ensure we do a transition from cc.en==1 to 1086 * cc.en==0. This is because we don't really know what status the 1087 * controller was left in when boot handed off to OS. Linux doesn't do 1088 * this, however. If we adopt that policy, see also nvme_ctrlr_resume(). 1089 */ 1090 status = nvme_ctrlr_hw_reset(ctrlr); 1091 if (status != 0) { 1092 nvme_ctrlr_fail(ctrlr); 1093 return; 1094 } 1095 1096 status = nvme_ctrlr_hw_reset(ctrlr); 1097 if (status != 0) { 1098 nvme_ctrlr_fail(ctrlr); 1099 return; 1100 } 1101 1102 nvme_qpair_reset(&ctrlr->adminq); 1103 nvme_admin_qpair_enable(&ctrlr->adminq); 1104 1105 if (nvme_ctrlr_set_num_qpairs(ctrlr) == 0 && 1106 nvme_ctrlr_construct_io_qpairs(ctrlr) == 0) 1107 nvme_ctrlr_start(ctrlr, false); 1108 else 1109 nvme_ctrlr_fail(ctrlr); 1110 1111 nvme_sysctl_initialize_ctrlr(ctrlr); 1112 config_intrhook_disestablish(&ctrlr->config_hook); 1113 1114 ctrlr->is_initialized = 1; 1115 nvme_notify_new_controller(ctrlr); 1116 } 1117 1118 static void 1119 nvme_ctrlr_reset_task(void *arg, int pending) 1120 { 1121 struct nvme_controller *ctrlr = arg; 1122 int status; 1123 1124 nvme_printf(ctrlr, "resetting controller\n"); 1125 status = nvme_ctrlr_hw_reset(ctrlr); 1126 /* 1127 * Use pause instead of DELAY, so that we yield to any nvme interrupt 1128 * handlers on this CPU that were blocked on a qpair lock. We want 1129 * all nvme interrupts completed before proceeding with restarting the 1130 * controller. 1131 * 1132 * XXX - any way to guarantee the interrupt handlers have quiesced? 1133 */ 1134 pause("nvmereset", hz / 10); 1135 if (status == 0) 1136 nvme_ctrlr_start(ctrlr, true); 1137 else 1138 nvme_ctrlr_fail(ctrlr); 1139 1140 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1141 } 1142 1143 /* 1144 * Poll all the queues enabled on the device for completion. 1145 */ 1146 void 1147 nvme_ctrlr_poll(struct nvme_controller *ctrlr) 1148 { 1149 int i; 1150 1151 nvme_qpair_process_completions(&ctrlr->adminq); 1152 1153 for (i = 0; i < ctrlr->num_io_queues; i++) 1154 if (ctrlr->ioq && ctrlr->ioq[i].cpl) 1155 nvme_qpair_process_completions(&ctrlr->ioq[i]); 1156 } 1157 1158 /* 1159 * Poll the single-vector interrupt case: num_io_queues will be 1 and 1160 * there's only a single vector. While we're polling, we mask further 1161 * interrupts in the controller. 1162 */ 1163 void 1164 nvme_ctrlr_intx_handler(void *arg) 1165 { 1166 struct nvme_controller *ctrlr = arg; 1167 1168 nvme_mmio_write_4(ctrlr, intms, 1); 1169 nvme_ctrlr_poll(ctrlr); 1170 nvme_mmio_write_4(ctrlr, intmc, 1); 1171 } 1172 1173 static void 1174 nvme_pt_done(void *arg, const struct nvme_completion *cpl) 1175 { 1176 struct nvme_pt_command *pt = arg; 1177 struct mtx *mtx = pt->driver_lock; 1178 uint16_t status; 1179 1180 bzero(&pt->cpl, sizeof(pt->cpl)); 1181 pt->cpl.cdw0 = cpl->cdw0; 1182 1183 status = cpl->status; 1184 status &= ~NVME_STATUS_P_MASK; 1185 pt->cpl.status = status; 1186 1187 mtx_lock(mtx); 1188 pt->driver_lock = NULL; 1189 wakeup(pt); 1190 mtx_unlock(mtx); 1191 } 1192 1193 int 1194 nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1195 struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer, 1196 int is_admin_cmd) 1197 { 1198 struct nvme_request *req; 1199 struct mtx *mtx; 1200 struct buf *buf = NULL; 1201 int ret = 0; 1202 vm_offset_t addr, end; 1203 1204 if (pt->len > 0) { 1205 /* 1206 * vmapbuf calls vm_fault_quick_hold_pages which only maps full 1207 * pages. Ensure this request has fewer than MAXPHYS bytes when 1208 * extended to full pages. 1209 */ 1210 addr = (vm_offset_t)pt->buf; 1211 end = round_page(addr + pt->len); 1212 addr = trunc_page(addr); 1213 if (end - addr > MAXPHYS) 1214 return EIO; 1215 1216 if (pt->len > ctrlr->max_xfer_size) { 1217 nvme_printf(ctrlr, "pt->len (%d) " 1218 "exceeds max_xfer_size (%d)\n", pt->len, 1219 ctrlr->max_xfer_size); 1220 return EIO; 1221 } 1222 if (is_user_buffer) { 1223 /* 1224 * Ensure the user buffer is wired for the duration of 1225 * this pass-through command. 1226 */ 1227 PHOLD(curproc); 1228 buf = uma_zalloc(pbuf_zone, M_WAITOK); 1229 buf->b_data = pt->buf; 1230 buf->b_bufsize = pt->len; 1231 buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE; 1232 if (vmapbuf(buf, 1) < 0) { 1233 ret = EFAULT; 1234 goto err; 1235 } 1236 req = nvme_allocate_request_vaddr(buf->b_data, pt->len, 1237 nvme_pt_done, pt); 1238 } else 1239 req = nvme_allocate_request_vaddr(pt->buf, pt->len, 1240 nvme_pt_done, pt); 1241 } else 1242 req = nvme_allocate_request_null(nvme_pt_done, pt); 1243 1244 /* Assume user space already converted to little-endian */ 1245 req->cmd.opc = pt->cmd.opc; 1246 req->cmd.fuse = pt->cmd.fuse; 1247 req->cmd.rsvd2 = pt->cmd.rsvd2; 1248 req->cmd.rsvd3 = pt->cmd.rsvd3; 1249 req->cmd.cdw10 = pt->cmd.cdw10; 1250 req->cmd.cdw11 = pt->cmd.cdw11; 1251 req->cmd.cdw12 = pt->cmd.cdw12; 1252 req->cmd.cdw13 = pt->cmd.cdw13; 1253 req->cmd.cdw14 = pt->cmd.cdw14; 1254 req->cmd.cdw15 = pt->cmd.cdw15; 1255 1256 req->cmd.nsid = htole32(nsid); 1257 1258 mtx = mtx_pool_find(mtxpool_sleep, pt); 1259 pt->driver_lock = mtx; 1260 1261 if (is_admin_cmd) 1262 nvme_ctrlr_submit_admin_request(ctrlr, req); 1263 else 1264 nvme_ctrlr_submit_io_request(ctrlr, req); 1265 1266 mtx_lock(mtx); 1267 while (pt->driver_lock != NULL) 1268 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0); 1269 mtx_unlock(mtx); 1270 1271 err: 1272 if (buf != NULL) { 1273 uma_zfree(pbuf_zone, buf); 1274 PRELE(curproc); 1275 } 1276 1277 return (ret); 1278 } 1279 1280 static int 1281 nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag, 1282 struct thread *td) 1283 { 1284 struct nvme_controller *ctrlr; 1285 struct nvme_pt_command *pt; 1286 1287 ctrlr = cdev->si_drv1; 1288 1289 switch (cmd) { 1290 case NVME_RESET_CONTROLLER: 1291 nvme_ctrlr_reset(ctrlr); 1292 break; 1293 case NVME_PASSTHROUGH_CMD: 1294 pt = (struct nvme_pt_command *)arg; 1295 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, le32toh(pt->cmd.nsid), 1296 1 /* is_user_buffer */, 1 /* is_admin_cmd */)); 1297 case NVME_GET_NSID: 1298 { 1299 struct nvme_get_nsid *gnsid = (struct nvme_get_nsid *)arg; 1300 strncpy(gnsid->cdev, device_get_nameunit(ctrlr->dev), 1301 sizeof(gnsid->cdev)); 1302 gnsid->nsid = 0; 1303 break; 1304 } 1305 default: 1306 return (ENOTTY); 1307 } 1308 1309 return (0); 1310 } 1311 1312 static struct cdevsw nvme_ctrlr_cdevsw = { 1313 .d_version = D_VERSION, 1314 .d_flags = 0, 1315 .d_ioctl = nvme_ctrlr_ioctl 1316 }; 1317 1318 int 1319 nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev) 1320 { 1321 struct make_dev_args md_args; 1322 uint32_t cap_lo; 1323 uint32_t cap_hi; 1324 uint32_t to; 1325 uint8_t mpsmin; 1326 int status, timeout_period; 1327 1328 ctrlr->dev = dev; 1329 1330 mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF); 1331 if (bus_get_domain(dev, &ctrlr->domain) != 0) 1332 ctrlr->domain = 0; 1333 1334 cap_hi = nvme_mmio_read_4(ctrlr, cap_hi); 1335 ctrlr->dstrd = NVME_CAP_HI_DSTRD(cap_hi) + 2; 1336 1337 mpsmin = NVME_CAP_HI_MPSMIN(cap_hi); 1338 ctrlr->min_page_size = 1 << (12 + mpsmin); 1339 1340 /* Get ready timeout value from controller, in units of 500ms. */ 1341 cap_lo = nvme_mmio_read_4(ctrlr, cap_lo); 1342 to = NVME_CAP_LO_TO(cap_lo) + 1; 1343 ctrlr->ready_timeout_in_ms = to * 500; 1344 1345 timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD; 1346 TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period); 1347 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD); 1348 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD); 1349 ctrlr->timeout_period = timeout_period; 1350 1351 nvme_retry_count = NVME_DEFAULT_RETRY_COUNT; 1352 TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count); 1353 1354 ctrlr->enable_aborts = 0; 1355 TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts); 1356 1357 ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE; 1358 if (nvme_ctrlr_construct_admin_qpair(ctrlr) != 0) 1359 return (ENXIO); 1360 1361 ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK, 1362 taskqueue_thread_enqueue, &ctrlr->taskqueue); 1363 taskqueue_start_threads(&ctrlr->taskqueue, 1, PI_DISK, "nvme taskq"); 1364 1365 ctrlr->is_resetting = 0; 1366 ctrlr->is_initialized = 0; 1367 ctrlr->notification_sent = 0; 1368 TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr); 1369 TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr); 1370 STAILQ_INIT(&ctrlr->fail_req); 1371 ctrlr->is_failed = false; 1372 1373 make_dev_args_init(&md_args); 1374 md_args.mda_devsw = &nvme_ctrlr_cdevsw; 1375 md_args.mda_uid = UID_ROOT; 1376 md_args.mda_gid = GID_WHEEL; 1377 md_args.mda_mode = 0600; 1378 md_args.mda_unit = device_get_unit(dev); 1379 md_args.mda_si_drv1 = (void *)ctrlr; 1380 status = make_dev_s(&md_args, &ctrlr->cdev, "nvme%d", 1381 device_get_unit(dev)); 1382 if (status != 0) 1383 return (ENXIO); 1384 1385 return (0); 1386 } 1387 1388 void 1389 nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev) 1390 { 1391 int gone, i; 1392 1393 if (ctrlr->resource == NULL) 1394 goto nores; 1395 1396 /* 1397 * Check whether it is a hot unplug or a clean driver detach. 1398 * If device is not there any more, skip any shutdown commands. 1399 */ 1400 gone = (nvme_mmio_read_4(ctrlr, csts) == 0xffffffff); 1401 if (gone) 1402 nvme_ctrlr_fail(ctrlr); 1403 else 1404 nvme_notify_fail_consumers(ctrlr); 1405 1406 for (i = 0; i < NVME_MAX_NAMESPACES; i++) 1407 nvme_ns_destruct(&ctrlr->ns[i]); 1408 1409 if (ctrlr->cdev) 1410 destroy_dev(ctrlr->cdev); 1411 1412 if (ctrlr->is_initialized) { 1413 if (!gone) { 1414 if (ctrlr->hmb_nchunks > 0) 1415 nvme_ctrlr_hmb_enable(ctrlr, false, false); 1416 nvme_ctrlr_delete_qpairs(ctrlr); 1417 } 1418 for (i = 0; i < ctrlr->num_io_queues; i++) 1419 nvme_io_qpair_destroy(&ctrlr->ioq[i]); 1420 free(ctrlr->ioq, M_NVME); 1421 nvme_ctrlr_hmb_free(ctrlr); 1422 nvme_admin_qpair_destroy(&ctrlr->adminq); 1423 } 1424 1425 /* 1426 * Notify the controller of a shutdown, even though this is due to 1427 * a driver unload, not a system shutdown (this path is not invoked 1428 * during shutdown). This ensures the controller receives a 1429 * shutdown notification in case the system is shutdown before 1430 * reloading the driver. 1431 */ 1432 if (!gone) 1433 nvme_ctrlr_shutdown(ctrlr); 1434 1435 if (!gone) 1436 nvme_ctrlr_disable(ctrlr); 1437 1438 if (ctrlr->taskqueue) 1439 taskqueue_free(ctrlr->taskqueue); 1440 1441 if (ctrlr->tag) 1442 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag); 1443 1444 if (ctrlr->res) 1445 bus_release_resource(ctrlr->dev, SYS_RES_IRQ, 1446 rman_get_rid(ctrlr->res), ctrlr->res); 1447 1448 if (ctrlr->bar4_resource != NULL) { 1449 bus_release_resource(dev, SYS_RES_MEMORY, 1450 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 1451 } 1452 1453 bus_release_resource(dev, SYS_RES_MEMORY, 1454 ctrlr->resource_id, ctrlr->resource); 1455 1456 nores: 1457 mtx_destroy(&ctrlr->lock); 1458 } 1459 1460 void 1461 nvme_ctrlr_shutdown(struct nvme_controller *ctrlr) 1462 { 1463 uint32_t cc; 1464 uint32_t csts; 1465 int ticks = 0; 1466 1467 cc = nvme_mmio_read_4(ctrlr, cc); 1468 cc &= ~(NVME_CC_REG_SHN_MASK << NVME_CC_REG_SHN_SHIFT); 1469 cc |= NVME_SHN_NORMAL << NVME_CC_REG_SHN_SHIFT; 1470 nvme_mmio_write_4(ctrlr, cc, cc); 1471 1472 while (1) { 1473 csts = nvme_mmio_read_4(ctrlr, csts); 1474 if (csts == 0xffffffff) /* Hot unplug. */ 1475 break; 1476 if (NVME_CSTS_GET_SHST(csts) == NVME_SHST_COMPLETE) 1477 break; 1478 if (ticks++ > 5*hz) { 1479 nvme_printf(ctrlr, "did not complete shutdown within" 1480 " 5 seconds of notification\n"); 1481 break; 1482 } 1483 pause("nvme shn", 1); 1484 } 1485 } 1486 1487 void 1488 nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 1489 struct nvme_request *req) 1490 { 1491 1492 nvme_qpair_submit_request(&ctrlr->adminq, req); 1493 } 1494 1495 void 1496 nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 1497 struct nvme_request *req) 1498 { 1499 struct nvme_qpair *qpair; 1500 1501 qpair = &ctrlr->ioq[QP(ctrlr, curcpu)]; 1502 nvme_qpair_submit_request(qpair, req); 1503 } 1504 1505 device_t 1506 nvme_ctrlr_get_device(struct nvme_controller *ctrlr) 1507 { 1508 1509 return (ctrlr->dev); 1510 } 1511 1512 const struct nvme_controller_data * 1513 nvme_ctrlr_get_data(struct nvme_controller *ctrlr) 1514 { 1515 1516 return (&ctrlr->cdata); 1517 } 1518 1519 int 1520 nvme_ctrlr_suspend(struct nvme_controller *ctrlr) 1521 { 1522 int to = hz; 1523 1524 /* 1525 * Can't touch failed controllers, so it's already suspended. 1526 */ 1527 if (ctrlr->is_failed) 1528 return (0); 1529 1530 /* 1531 * We don't want the reset taskqueue running, since it does similar 1532 * things, so prevent it from running after we start. Wait for any reset 1533 * that may have been started to complete. The reset process we follow 1534 * will ensure that any new I/O will queue and be given to the hardware 1535 * after we resume (though there should be none). 1536 */ 1537 while (atomic_cmpset_32(&ctrlr->is_resetting, 0, 1) == 0 && to-- > 0) 1538 pause("nvmesusp", 1); 1539 if (to <= 0) { 1540 nvme_printf(ctrlr, 1541 "Competing reset task didn't finish. Try again later.\n"); 1542 return (EWOULDBLOCK); 1543 } 1544 1545 if (ctrlr->hmb_nchunks > 0) 1546 nvme_ctrlr_hmb_enable(ctrlr, false, false); 1547 1548 /* 1549 * Per Section 7.6.2 of NVMe spec 1.4, to properly suspend, we need to 1550 * delete the hardware I/O queues, and then shutdown. This properly 1551 * flushes any metadata the drive may have stored so it can survive 1552 * having its power removed and prevents the unsafe shutdown count from 1553 * incriminating. Once we delete the qpairs, we have to disable them 1554 * before shutting down. The delay is out of paranoia in 1555 * nvme_ctrlr_hw_reset, and is repeated here (though we should have no 1556 * pending I/O that the delay copes with). 1557 */ 1558 nvme_ctrlr_delete_qpairs(ctrlr); 1559 nvme_ctrlr_disable_qpairs(ctrlr); 1560 DELAY(100*1000); 1561 nvme_ctrlr_shutdown(ctrlr); 1562 1563 return (0); 1564 } 1565 1566 int 1567 nvme_ctrlr_resume(struct nvme_controller *ctrlr) 1568 { 1569 1570 /* 1571 * Can't touch failed controllers, so nothing to do to resume. 1572 */ 1573 if (ctrlr->is_failed) 1574 return (0); 1575 1576 /* 1577 * Have to reset the hardware twice, just like we do on attach. See 1578 * nmve_attach() for why. 1579 */ 1580 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1581 goto fail; 1582 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1583 goto fail; 1584 1585 /* 1586 * Now that we're reset the hardware, we can restart the controller. Any 1587 * I/O that was pending is requeued. Any admin commands are aborted with 1588 * an error. Once we've restarted, take the controller out of reset. 1589 */ 1590 nvme_ctrlr_start(ctrlr, true); 1591 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1592 1593 return (0); 1594 fail: 1595 /* 1596 * Since we can't bring the controller out of reset, announce and fail 1597 * the controller. However, we have to return success for the resume 1598 * itself, due to questionable APIs. 1599 */ 1600 nvme_printf(ctrlr, "Failed to reset on resume, failing.\n"); 1601 nvme_ctrlr_fail(ctrlr); 1602 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1603 return (0); 1604 } 1605