1 /*- 2 * Copyright (C) 2012-2014 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/buf.h> 33 #include <sys/bus.h> 34 #include <sys/conf.h> 35 #include <sys/ioccom.h> 36 #include <sys/proc.h> 37 #include <sys/smp.h> 38 #include <sys/uio.h> 39 40 #include <dev/pci/pcireg.h> 41 #include <dev/pci/pcivar.h> 42 43 #include "nvme_private.h" 44 45 static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 46 struct nvme_async_event_request *aer); 47 48 static int 49 nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr) 50 { 51 52 ctrlr->resource_id = PCIR_BAR(0); 53 54 ctrlr->resource = bus_alloc_resource(ctrlr->dev, SYS_RES_MEMORY, 55 &ctrlr->resource_id, 0, ~0, 1, RF_ACTIVE); 56 57 if(ctrlr->resource == NULL) { 58 nvme_printf(ctrlr, "unable to allocate pci resource\n"); 59 return (ENOMEM); 60 } 61 62 ctrlr->bus_tag = rman_get_bustag(ctrlr->resource); 63 ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource); 64 ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle; 65 66 /* 67 * The NVMe spec allows for the MSI-X table to be placed behind 68 * BAR 4/5, separate from the control/doorbell registers. Always 69 * try to map this bar, because it must be mapped prior to calling 70 * pci_alloc_msix(). If the table isn't behind BAR 4/5, 71 * bus_alloc_resource() will just return NULL which is OK. 72 */ 73 ctrlr->bar4_resource_id = PCIR_BAR(4); 74 ctrlr->bar4_resource = bus_alloc_resource(ctrlr->dev, SYS_RES_MEMORY, 75 &ctrlr->bar4_resource_id, 0, ~0, 1, RF_ACTIVE); 76 77 return (0); 78 } 79 80 static void 81 nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr) 82 { 83 struct nvme_qpair *qpair; 84 uint32_t num_entries; 85 86 qpair = &ctrlr->adminq; 87 88 num_entries = NVME_ADMIN_ENTRIES; 89 TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries); 90 /* 91 * If admin_entries was overridden to an invalid value, revert it 92 * back to our default value. 93 */ 94 if (num_entries < NVME_MIN_ADMIN_ENTRIES || 95 num_entries > NVME_MAX_ADMIN_ENTRIES) { 96 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d " 97 "specified\n", num_entries); 98 num_entries = NVME_ADMIN_ENTRIES; 99 } 100 101 /* 102 * The admin queue's max xfer size is treated differently than the 103 * max I/O xfer size. 16KB is sufficient here - maybe even less? 104 */ 105 nvme_qpair_construct(qpair, 106 0, /* qpair ID */ 107 0, /* vector */ 108 num_entries, 109 NVME_ADMIN_TRACKERS, 110 ctrlr); 111 } 112 113 static int 114 nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr) 115 { 116 struct nvme_qpair *qpair; 117 union cap_lo_register cap_lo; 118 int i, num_entries, num_trackers; 119 120 num_entries = NVME_IO_ENTRIES; 121 TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries); 122 123 /* 124 * NVMe spec sets a hard limit of 64K max entries, but 125 * devices may specify a smaller limit, so we need to check 126 * the MQES field in the capabilities register. 127 */ 128 cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo); 129 num_entries = min(num_entries, cap_lo.bits.mqes+1); 130 131 num_trackers = NVME_IO_TRACKERS; 132 TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers); 133 134 num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS); 135 num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS); 136 /* 137 * No need to have more trackers than entries in the submit queue. 138 * Note also that for a queue size of N, we can only have (N-1) 139 * commands outstanding, hence the "-1" here. 140 */ 141 num_trackers = min(num_trackers, (num_entries-1)); 142 143 ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair), 144 M_NVME, M_ZERO | M_WAITOK); 145 146 for (i = 0; i < ctrlr->num_io_queues; i++) { 147 qpair = &ctrlr->ioq[i]; 148 149 /* 150 * Admin queue has ID=0. IO queues start at ID=1 - 151 * hence the 'i+1' here. 152 * 153 * For I/O queues, use the controller-wide max_xfer_size 154 * calculated in nvme_attach(). 155 */ 156 nvme_qpair_construct(qpair, 157 i+1, /* qpair ID */ 158 ctrlr->msix_enabled ? i+1 : 0, /* vector */ 159 num_entries, 160 num_trackers, 161 ctrlr); 162 163 if (ctrlr->per_cpu_io_queues) 164 bus_bind_intr(ctrlr->dev, qpair->res, i); 165 } 166 167 return (0); 168 } 169 170 static void 171 nvme_ctrlr_fail(struct nvme_controller *ctrlr) 172 { 173 int i; 174 175 ctrlr->is_failed = TRUE; 176 nvme_qpair_fail(&ctrlr->adminq); 177 for (i = 0; i < ctrlr->num_io_queues; i++) 178 nvme_qpair_fail(&ctrlr->ioq[i]); 179 nvme_notify_fail_consumers(ctrlr); 180 } 181 182 void 183 nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 184 struct nvme_request *req) 185 { 186 187 mtx_lock(&ctrlr->lock); 188 STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq); 189 mtx_unlock(&ctrlr->lock); 190 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task); 191 } 192 193 static void 194 nvme_ctrlr_fail_req_task(void *arg, int pending) 195 { 196 struct nvme_controller *ctrlr = arg; 197 struct nvme_request *req; 198 199 mtx_lock(&ctrlr->lock); 200 while (!STAILQ_EMPTY(&ctrlr->fail_req)) { 201 req = STAILQ_FIRST(&ctrlr->fail_req); 202 STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq); 203 nvme_qpair_manual_complete_request(req->qpair, req, 204 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST, TRUE); 205 } 206 mtx_unlock(&ctrlr->lock); 207 } 208 209 static int 210 nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr) 211 { 212 int ms_waited; 213 union cc_register cc; 214 union csts_register csts; 215 216 cc.raw = nvme_mmio_read_4(ctrlr, cc); 217 csts.raw = nvme_mmio_read_4(ctrlr, csts); 218 219 if (!cc.bits.en) { 220 nvme_printf(ctrlr, "%s called with cc.en = 0\n", __func__); 221 return (ENXIO); 222 } 223 224 ms_waited = 0; 225 226 while (!csts.bits.rdy) { 227 DELAY(1000); 228 if (ms_waited++ > ctrlr->ready_timeout_in_ms) { 229 nvme_printf(ctrlr, "controller did not become ready " 230 "within %d ms\n", ctrlr->ready_timeout_in_ms); 231 return (ENXIO); 232 } 233 csts.raw = nvme_mmio_read_4(ctrlr, csts); 234 } 235 236 return (0); 237 } 238 239 static void 240 nvme_ctrlr_disable(struct nvme_controller *ctrlr) 241 { 242 union cc_register cc; 243 union csts_register csts; 244 245 cc.raw = nvme_mmio_read_4(ctrlr, cc); 246 csts.raw = nvme_mmio_read_4(ctrlr, csts); 247 248 if (cc.bits.en == 1 && csts.bits.rdy == 0) 249 nvme_ctrlr_wait_for_ready(ctrlr); 250 251 cc.bits.en = 0; 252 nvme_mmio_write_4(ctrlr, cc, cc.raw); 253 DELAY(5000); 254 } 255 256 static int 257 nvme_ctrlr_enable(struct nvme_controller *ctrlr) 258 { 259 union cc_register cc; 260 union csts_register csts; 261 union aqa_register aqa; 262 263 cc.raw = nvme_mmio_read_4(ctrlr, cc); 264 csts.raw = nvme_mmio_read_4(ctrlr, csts); 265 266 if (cc.bits.en == 1) { 267 if (csts.bits.rdy == 1) 268 return (0); 269 else 270 return (nvme_ctrlr_wait_for_ready(ctrlr)); 271 } 272 273 nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr); 274 DELAY(5000); 275 nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr); 276 DELAY(5000); 277 278 aqa.raw = 0; 279 /* acqs and asqs are 0-based. */ 280 aqa.bits.acqs = ctrlr->adminq.num_entries-1; 281 aqa.bits.asqs = ctrlr->adminq.num_entries-1; 282 nvme_mmio_write_4(ctrlr, aqa, aqa.raw); 283 DELAY(5000); 284 285 cc.bits.en = 1; 286 cc.bits.css = 0; 287 cc.bits.ams = 0; 288 cc.bits.shn = 0; 289 cc.bits.iosqes = 6; /* SQ entry size == 64 == 2^6 */ 290 cc.bits.iocqes = 4; /* CQ entry size == 16 == 2^4 */ 291 292 /* This evaluates to 0, which is according to spec. */ 293 cc.bits.mps = (PAGE_SIZE >> 13); 294 295 nvme_mmio_write_4(ctrlr, cc, cc.raw); 296 DELAY(5000); 297 298 return (nvme_ctrlr_wait_for_ready(ctrlr)); 299 } 300 301 int 302 nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr) 303 { 304 int i; 305 306 nvme_admin_qpair_disable(&ctrlr->adminq); 307 for (i = 0; i < ctrlr->num_io_queues; i++) 308 nvme_io_qpair_disable(&ctrlr->ioq[i]); 309 310 DELAY(100*1000); 311 312 nvme_ctrlr_disable(ctrlr); 313 return (nvme_ctrlr_enable(ctrlr)); 314 } 315 316 void 317 nvme_ctrlr_reset(struct nvme_controller *ctrlr) 318 { 319 int cmpset; 320 321 cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1); 322 323 if (cmpset == 0 || ctrlr->is_failed) 324 /* 325 * Controller is already resetting or has failed. Return 326 * immediately since there is no need to kick off another 327 * reset in these cases. 328 */ 329 return; 330 331 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task); 332 } 333 334 static int 335 nvme_ctrlr_identify(struct nvme_controller *ctrlr) 336 { 337 struct nvme_completion_poll_status status; 338 339 status.done = FALSE; 340 nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata, 341 nvme_completion_poll_cb, &status); 342 while (status.done == FALSE) 343 pause("nvme", 1); 344 if (nvme_completion_is_error(&status.cpl)) { 345 nvme_printf(ctrlr, "nvme_identify_controller failed!\n"); 346 return (ENXIO); 347 } 348 349 /* 350 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 351 * controller supports. 352 */ 353 if (ctrlr->cdata.mdts > 0) 354 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size, 355 ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts))); 356 357 return (0); 358 } 359 360 static int 361 nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr) 362 { 363 struct nvme_completion_poll_status status; 364 int cq_allocated, i, sq_allocated; 365 366 status.done = FALSE; 367 nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues, 368 nvme_completion_poll_cb, &status); 369 while (status.done == FALSE) 370 pause("nvme", 1); 371 if (nvme_completion_is_error(&status.cpl)) { 372 nvme_printf(ctrlr, "nvme_set_num_queues failed!\n"); 373 return (ENXIO); 374 } 375 376 /* 377 * Data in cdw0 is 0-based. 378 * Lower 16-bits indicate number of submission queues allocated. 379 * Upper 16-bits indicate number of completion queues allocated. 380 */ 381 sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1; 382 cq_allocated = (status.cpl.cdw0 >> 16) + 1; 383 384 /* 385 * Check that the controller was able to allocate the number of 386 * queues we requested. If not, revert to one IO queue pair. 387 */ 388 if (sq_allocated < ctrlr->num_io_queues || 389 cq_allocated < ctrlr->num_io_queues) { 390 391 /* 392 * Destroy extra IO queue pairs that were created at 393 * controller construction time but are no longer 394 * needed. This will only happen when a controller 395 * supports fewer queues than MSI-X vectors. This 396 * is not the normal case, but does occur with the 397 * Chatham prototype board. 398 */ 399 for (i = 1; i < ctrlr->num_io_queues; i++) 400 nvme_io_qpair_destroy(&ctrlr->ioq[i]); 401 402 ctrlr->num_io_queues = 1; 403 ctrlr->per_cpu_io_queues = 0; 404 } 405 406 return (0); 407 } 408 409 static int 410 nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr) 411 { 412 struct nvme_completion_poll_status status; 413 struct nvme_qpair *qpair; 414 int i; 415 416 for (i = 0; i < ctrlr->num_io_queues; i++) { 417 qpair = &ctrlr->ioq[i]; 418 419 status.done = FALSE; 420 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair, qpair->vector, 421 nvme_completion_poll_cb, &status); 422 while (status.done == FALSE) 423 pause("nvme", 1); 424 if (nvme_completion_is_error(&status.cpl)) { 425 nvme_printf(ctrlr, "nvme_create_io_cq failed!\n"); 426 return (ENXIO); 427 } 428 429 status.done = FALSE; 430 nvme_ctrlr_cmd_create_io_sq(qpair->ctrlr, qpair, 431 nvme_completion_poll_cb, &status); 432 while (status.done == FALSE) 433 pause("nvme", 1); 434 if (nvme_completion_is_error(&status.cpl)) { 435 nvme_printf(ctrlr, "nvme_create_io_sq failed!\n"); 436 return (ENXIO); 437 } 438 } 439 440 return (0); 441 } 442 443 static int 444 nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr) 445 { 446 struct nvme_namespace *ns; 447 int i, status; 448 449 for (i = 0; i < ctrlr->cdata.nn; i++) { 450 ns = &ctrlr->ns[i]; 451 status = nvme_ns_construct(ns, i+1, ctrlr); 452 if (status != 0) 453 return (status); 454 } 455 456 return (0); 457 } 458 459 static boolean_t 460 is_log_page_id_valid(uint8_t page_id) 461 { 462 463 switch (page_id) { 464 case NVME_LOG_ERROR: 465 case NVME_LOG_HEALTH_INFORMATION: 466 case NVME_LOG_FIRMWARE_SLOT: 467 return (TRUE); 468 } 469 470 return (FALSE); 471 } 472 473 static uint32_t 474 nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id) 475 { 476 uint32_t log_page_size; 477 478 switch (page_id) { 479 case NVME_LOG_ERROR: 480 log_page_size = min( 481 sizeof(struct nvme_error_information_entry) * 482 ctrlr->cdata.elpe, 483 NVME_MAX_AER_LOG_SIZE); 484 break; 485 case NVME_LOG_HEALTH_INFORMATION: 486 log_page_size = sizeof(struct nvme_health_information_page); 487 break; 488 case NVME_LOG_FIRMWARE_SLOT: 489 log_page_size = sizeof(struct nvme_firmware_page); 490 break; 491 default: 492 log_page_size = 0; 493 break; 494 } 495 496 return (log_page_size); 497 } 498 499 static void 500 nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr, 501 union nvme_critical_warning_state state) 502 { 503 504 if (state.bits.available_spare == 1) 505 nvme_printf(ctrlr, "available spare space below threshold\n"); 506 507 if (state.bits.temperature == 1) 508 nvme_printf(ctrlr, "temperature above threshold\n"); 509 510 if (state.bits.device_reliability == 1) 511 nvme_printf(ctrlr, "device reliability degraded\n"); 512 513 if (state.bits.read_only == 1) 514 nvme_printf(ctrlr, "media placed in read only mode\n"); 515 516 if (state.bits.volatile_memory_backup == 1) 517 nvme_printf(ctrlr, "volatile memory backup device failed\n"); 518 519 if (state.bits.reserved != 0) 520 nvme_printf(ctrlr, 521 "unknown critical warning(s): state = 0x%02x\n", state.raw); 522 } 523 524 static void 525 nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl) 526 { 527 struct nvme_async_event_request *aer = arg; 528 struct nvme_health_information_page *health_info; 529 530 /* 531 * If the log page fetch for some reason completed with an error, 532 * don't pass log page data to the consumers. In practice, this case 533 * should never happen. 534 */ 535 if (nvme_completion_is_error(cpl)) 536 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 537 aer->log_page_id, NULL, 0); 538 else { 539 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) { 540 health_info = (struct nvme_health_information_page *) 541 aer->log_page_buffer; 542 nvme_ctrlr_log_critical_warnings(aer->ctrlr, 543 health_info->critical_warning); 544 /* 545 * Critical warnings reported through the 546 * SMART/health log page are persistent, so 547 * clear the associated bits in the async event 548 * config so that we do not receive repeated 549 * notifications for the same event. 550 */ 551 aer->ctrlr->async_event_config.raw &= 552 ~health_info->critical_warning.raw; 553 nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr, 554 aer->ctrlr->async_event_config, NULL, NULL); 555 } 556 557 558 /* 559 * Pass the cpl data from the original async event completion, 560 * not the log page fetch. 561 */ 562 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 563 aer->log_page_id, aer->log_page_buffer, aer->log_page_size); 564 } 565 566 /* 567 * Repost another asynchronous event request to replace the one 568 * that just completed. 569 */ 570 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 571 } 572 573 static void 574 nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl) 575 { 576 struct nvme_async_event_request *aer = arg; 577 578 if (nvme_completion_is_error(cpl)) { 579 /* 580 * Do not retry failed async event requests. This avoids 581 * infinite loops where a new async event request is submitted 582 * to replace the one just failed, only to fail again and 583 * perpetuate the loop. 584 */ 585 return; 586 } 587 588 /* Associated log page is in bits 23:16 of completion entry dw0. */ 589 aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16; 590 591 nvme_printf(aer->ctrlr, "async event occurred (log page id=0x%x)\n", 592 aer->log_page_id); 593 594 if (is_log_page_id_valid(aer->log_page_id)) { 595 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr, 596 aer->log_page_id); 597 memcpy(&aer->cpl, cpl, sizeof(*cpl)); 598 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id, 599 NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer, 600 aer->log_page_size, nvme_ctrlr_async_event_log_page_cb, 601 aer); 602 /* Wait to notify consumers until after log page is fetched. */ 603 } else { 604 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id, 605 NULL, 0); 606 607 /* 608 * Repost another asynchronous event request to replace the one 609 * that just completed. 610 */ 611 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 612 } 613 } 614 615 static void 616 nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 617 struct nvme_async_event_request *aer) 618 { 619 struct nvme_request *req; 620 621 aer->ctrlr = ctrlr; 622 req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer); 623 aer->req = req; 624 625 /* 626 * Disable timeout here, since asynchronous event requests should by 627 * nature never be timed out. 628 */ 629 req->timeout = FALSE; 630 req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST; 631 nvme_ctrlr_submit_admin_request(ctrlr, req); 632 } 633 634 static void 635 nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr) 636 { 637 struct nvme_completion_poll_status status; 638 struct nvme_async_event_request *aer; 639 uint32_t i; 640 641 ctrlr->async_event_config.raw = 0xFF; 642 ctrlr->async_event_config.bits.reserved = 0; 643 644 status.done = FALSE; 645 nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD, 646 0, NULL, 0, nvme_completion_poll_cb, &status); 647 while (status.done == FALSE) 648 pause("nvme", 1); 649 if (nvme_completion_is_error(&status.cpl) || 650 (status.cpl.cdw0 & 0xFFFF) == 0xFFFF || 651 (status.cpl.cdw0 & 0xFFFF) == 0x0000) { 652 nvme_printf(ctrlr, "temperature threshold not supported\n"); 653 ctrlr->async_event_config.bits.temperature = 0; 654 } 655 656 nvme_ctrlr_cmd_set_async_event_config(ctrlr, 657 ctrlr->async_event_config, NULL, NULL); 658 659 /* aerl is a zero-based value, so we need to add 1 here. */ 660 ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1)); 661 662 for (i = 0; i < ctrlr->num_aers; i++) { 663 aer = &ctrlr->aer[i]; 664 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 665 } 666 } 667 668 static void 669 nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr) 670 { 671 672 ctrlr->int_coal_time = 0; 673 TUNABLE_INT_FETCH("hw.nvme.int_coal_time", 674 &ctrlr->int_coal_time); 675 676 ctrlr->int_coal_threshold = 0; 677 TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold", 678 &ctrlr->int_coal_threshold); 679 680 nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time, 681 ctrlr->int_coal_threshold, NULL, NULL); 682 } 683 684 static void 685 nvme_ctrlr_start(void *ctrlr_arg) 686 { 687 struct nvme_controller *ctrlr = ctrlr_arg; 688 int i; 689 690 nvme_qpair_reset(&ctrlr->adminq); 691 for (i = 0; i < ctrlr->num_io_queues; i++) 692 nvme_qpair_reset(&ctrlr->ioq[i]); 693 694 nvme_admin_qpair_enable(&ctrlr->adminq); 695 696 if (nvme_ctrlr_identify(ctrlr) != 0) { 697 nvme_ctrlr_fail(ctrlr); 698 return; 699 } 700 701 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) { 702 nvme_ctrlr_fail(ctrlr); 703 return; 704 } 705 706 if (nvme_ctrlr_create_qpairs(ctrlr) != 0) { 707 nvme_ctrlr_fail(ctrlr); 708 return; 709 } 710 711 if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) { 712 nvme_ctrlr_fail(ctrlr); 713 return; 714 } 715 716 nvme_ctrlr_configure_aer(ctrlr); 717 nvme_ctrlr_configure_int_coalescing(ctrlr); 718 719 for (i = 0; i < ctrlr->num_io_queues; i++) 720 nvme_io_qpair_enable(&ctrlr->ioq[i]); 721 } 722 723 void 724 nvme_ctrlr_start_config_hook(void *arg) 725 { 726 struct nvme_controller *ctrlr = arg; 727 728 nvme_ctrlr_start(ctrlr); 729 config_intrhook_disestablish(&ctrlr->config_hook); 730 731 ctrlr->is_initialized = 1; 732 nvme_notify_new_controller(ctrlr); 733 } 734 735 static void 736 nvme_ctrlr_reset_task(void *arg, int pending) 737 { 738 struct nvme_controller *ctrlr = arg; 739 int status; 740 741 nvme_printf(ctrlr, "resetting controller\n"); 742 status = nvme_ctrlr_hw_reset(ctrlr); 743 /* 744 * Use pause instead of DELAY, so that we yield to any nvme interrupt 745 * handlers on this CPU that were blocked on a qpair lock. We want 746 * all nvme interrupts completed before proceeding with restarting the 747 * controller. 748 * 749 * XXX - any way to guarantee the interrupt handlers have quiesced? 750 */ 751 pause("nvmereset", hz / 10); 752 if (status == 0) 753 nvme_ctrlr_start(ctrlr); 754 else 755 nvme_ctrlr_fail(ctrlr); 756 757 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 758 } 759 760 static void 761 nvme_ctrlr_intx_handler(void *arg) 762 { 763 struct nvme_controller *ctrlr = arg; 764 765 nvme_mmio_write_4(ctrlr, intms, 1); 766 767 nvme_qpair_process_completions(&ctrlr->adminq); 768 769 if (ctrlr->ioq[0].cpl) 770 nvme_qpair_process_completions(&ctrlr->ioq[0]); 771 772 nvme_mmio_write_4(ctrlr, intmc, 1); 773 } 774 775 static int 776 nvme_ctrlr_configure_intx(struct nvme_controller *ctrlr) 777 { 778 779 ctrlr->num_io_queues = 1; 780 ctrlr->per_cpu_io_queues = 0; 781 ctrlr->rid = 0; 782 ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ, 783 &ctrlr->rid, RF_SHAREABLE | RF_ACTIVE); 784 785 if (ctrlr->res == NULL) { 786 nvme_printf(ctrlr, "unable to allocate shared IRQ\n"); 787 return (ENOMEM); 788 } 789 790 bus_setup_intr(ctrlr->dev, ctrlr->res, 791 INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_intx_handler, 792 ctrlr, &ctrlr->tag); 793 794 if (ctrlr->tag == NULL) { 795 nvme_printf(ctrlr, "unable to setup intx handler\n"); 796 return (ENOMEM); 797 } 798 799 return (0); 800 } 801 802 static void 803 nvme_pt_done(void *arg, const struct nvme_completion *cpl) 804 { 805 struct nvme_pt_command *pt = arg; 806 807 bzero(&pt->cpl, sizeof(pt->cpl)); 808 pt->cpl.cdw0 = cpl->cdw0; 809 pt->cpl.status = cpl->status; 810 pt->cpl.status.p = 0; 811 812 mtx_lock(pt->driver_lock); 813 wakeup(pt); 814 mtx_unlock(pt->driver_lock); 815 } 816 817 int 818 nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 819 struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer, 820 int is_admin_cmd) 821 { 822 struct nvme_request *req; 823 struct mtx *mtx; 824 struct buf *buf = NULL; 825 int ret = 0; 826 827 if (pt->len > 0) { 828 if (pt->len > ctrlr->max_xfer_size) { 829 nvme_printf(ctrlr, "pt->len (%d) " 830 "exceeds max_xfer_size (%d)\n", pt->len, 831 ctrlr->max_xfer_size); 832 return EIO; 833 } 834 if (is_user_buffer) { 835 /* 836 * Ensure the user buffer is wired for the duration of 837 * this passthrough command. 838 */ 839 PHOLD(curproc); 840 buf = getpbuf(NULL); 841 buf->b_saveaddr = buf->b_data; 842 buf->b_data = pt->buf; 843 buf->b_bufsize = pt->len; 844 buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE; 845 #ifdef NVME_UNMAPPED_BIO_SUPPORT 846 if (vmapbuf(buf, 1) < 0) { 847 #else 848 if (vmapbuf(buf) < 0) { 849 #endif 850 ret = EFAULT; 851 goto err; 852 } 853 req = nvme_allocate_request_vaddr(buf->b_data, pt->len, 854 nvme_pt_done, pt); 855 } else 856 req = nvme_allocate_request_vaddr(pt->buf, pt->len, 857 nvme_pt_done, pt); 858 } else 859 req = nvme_allocate_request_null(nvme_pt_done, pt); 860 861 req->cmd.opc = pt->cmd.opc; 862 req->cmd.cdw10 = pt->cmd.cdw10; 863 req->cmd.cdw11 = pt->cmd.cdw11; 864 req->cmd.cdw12 = pt->cmd.cdw12; 865 req->cmd.cdw13 = pt->cmd.cdw13; 866 req->cmd.cdw14 = pt->cmd.cdw14; 867 req->cmd.cdw15 = pt->cmd.cdw15; 868 869 req->cmd.nsid = nsid; 870 871 if (is_admin_cmd) 872 mtx = &ctrlr->lock; 873 else 874 mtx = &ctrlr->ns[nsid-1].lock; 875 876 mtx_lock(mtx); 877 pt->driver_lock = mtx; 878 879 if (is_admin_cmd) 880 nvme_ctrlr_submit_admin_request(ctrlr, req); 881 else 882 nvme_ctrlr_submit_io_request(ctrlr, req); 883 884 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0); 885 mtx_unlock(mtx); 886 887 pt->driver_lock = NULL; 888 889 err: 890 if (buf != NULL) { 891 relpbuf(buf, NULL); 892 PRELE(curproc); 893 } 894 895 return (ret); 896 } 897 898 static int 899 nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag, 900 struct thread *td) 901 { 902 struct nvme_controller *ctrlr; 903 struct nvme_pt_command *pt; 904 905 ctrlr = cdev->si_drv1; 906 907 switch (cmd) { 908 case NVME_RESET_CONTROLLER: 909 nvme_ctrlr_reset(ctrlr); 910 break; 911 case NVME_PASSTHROUGH_CMD: 912 pt = (struct nvme_pt_command *)arg; 913 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, pt->cmd.nsid, 914 1 /* is_user_buffer */, 1 /* is_admin_cmd */)); 915 default: 916 return (ENOTTY); 917 } 918 919 return (0); 920 } 921 922 static struct cdevsw nvme_ctrlr_cdevsw = { 923 .d_version = D_VERSION, 924 .d_flags = 0, 925 .d_ioctl = nvme_ctrlr_ioctl 926 }; 927 928 int 929 nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev) 930 { 931 union cap_lo_register cap_lo; 932 union cap_hi_register cap_hi; 933 int i, num_vectors, per_cpu_io_queues, rid; 934 int status, timeout_period; 935 936 ctrlr->dev = dev; 937 938 mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF); 939 940 status = nvme_ctrlr_allocate_bar(ctrlr); 941 942 if (status != 0) 943 return (status); 944 945 /* 946 * Software emulators may set the doorbell stride to something 947 * other than zero, but this driver is not set up to handle that. 948 */ 949 cap_hi.raw = nvme_mmio_read_4(ctrlr, cap_hi); 950 if (cap_hi.bits.dstrd != 0) 951 return (ENXIO); 952 953 ctrlr->min_page_size = 1 << (12 + cap_hi.bits.mpsmin); 954 955 /* Get ready timeout value from controller, in units of 500ms. */ 956 cap_lo.raw = nvme_mmio_read_4(ctrlr, cap_lo); 957 ctrlr->ready_timeout_in_ms = cap_lo.bits.to * 500; 958 959 timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD; 960 TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period); 961 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD); 962 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD); 963 ctrlr->timeout_period = timeout_period; 964 965 nvme_retry_count = NVME_DEFAULT_RETRY_COUNT; 966 TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count); 967 968 per_cpu_io_queues = 1; 969 TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues); 970 ctrlr->per_cpu_io_queues = per_cpu_io_queues ? TRUE : FALSE; 971 972 if (ctrlr->per_cpu_io_queues) 973 ctrlr->num_io_queues = mp_ncpus; 974 else 975 ctrlr->num_io_queues = 1; 976 977 ctrlr->force_intx = 0; 978 TUNABLE_INT_FETCH("hw.nvme.force_intx", &ctrlr->force_intx); 979 980 ctrlr->enable_aborts = 0; 981 TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts); 982 983 ctrlr->msix_enabled = 1; 984 985 if (ctrlr->force_intx) { 986 ctrlr->msix_enabled = 0; 987 goto intx; 988 } 989 990 /* One vector per IO queue, plus one vector for admin queue. */ 991 num_vectors = ctrlr->num_io_queues + 1; 992 993 /* 994 * If we cannot even allocate 2 vectors (one for admin, one for 995 * I/O), then revert to INTx. 996 */ 997 if (pci_msix_count(dev) < 2) { 998 ctrlr->msix_enabled = 0; 999 goto intx; 1000 } else if (pci_msix_count(dev) < num_vectors) { 1001 ctrlr->per_cpu_io_queues = FALSE; 1002 ctrlr->num_io_queues = 1; 1003 num_vectors = 2; /* one for admin, one for I/O */ 1004 } 1005 1006 if (pci_alloc_msix(dev, &num_vectors) != 0) { 1007 ctrlr->msix_enabled = 0; 1008 goto intx; 1009 } 1010 1011 /* 1012 * On earlier FreeBSD releases, there are reports that 1013 * pci_alloc_msix() can return successfully with all vectors 1014 * requested, but a subsequent bus_alloc_resource_any() 1015 * for one of those vectors fails. This issue occurs more 1016 * readily with multiple devices using per-CPU vectors. 1017 * To workaround this issue, try to allocate the resources now, 1018 * and fall back to INTx if we cannot allocate all of them. 1019 * This issue cannot be reproduced on more recent versions of 1020 * FreeBSD which have increased the maximum number of MSI-X 1021 * vectors, but adding the workaround makes it easier for 1022 * vendors wishing to import this driver into kernels based on 1023 * older versions of FreeBSD. 1024 */ 1025 for (i = 0; i < num_vectors; i++) { 1026 rid = i + 1; 1027 ctrlr->msi_res[i] = bus_alloc_resource_any(ctrlr->dev, 1028 SYS_RES_IRQ, &rid, RF_ACTIVE); 1029 1030 if (ctrlr->msi_res[i] == NULL) { 1031 ctrlr->msix_enabled = 0; 1032 while (i > 0) { 1033 i--; 1034 bus_release_resource(ctrlr->dev, 1035 SYS_RES_IRQ, 1036 rman_get_rid(ctrlr->msi_res[i]), 1037 ctrlr->msi_res[i]); 1038 } 1039 pci_release_msi(dev); 1040 nvme_printf(ctrlr, "could not obtain all MSI-X " 1041 "resources, reverting to intx\n"); 1042 break; 1043 } 1044 } 1045 1046 intx: 1047 1048 if (!ctrlr->msix_enabled) 1049 nvme_ctrlr_configure_intx(ctrlr); 1050 1051 ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE; 1052 nvme_ctrlr_construct_admin_qpair(ctrlr); 1053 status = nvme_ctrlr_construct_io_qpairs(ctrlr); 1054 1055 if (status != 0) 1056 return (status); 1057 1058 ctrlr->cdev = make_dev(&nvme_ctrlr_cdevsw, device_get_unit(dev), 1059 UID_ROOT, GID_WHEEL, 0600, "nvme%d", device_get_unit(dev)); 1060 1061 if (ctrlr->cdev == NULL) 1062 return (ENXIO); 1063 1064 ctrlr->cdev->si_drv1 = (void *)ctrlr; 1065 1066 ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK, 1067 taskqueue_thread_enqueue, &ctrlr->taskqueue); 1068 taskqueue_start_threads(&ctrlr->taskqueue, 1, PI_DISK, "nvme taskq"); 1069 1070 ctrlr->is_resetting = 0; 1071 ctrlr->is_initialized = 0; 1072 ctrlr->notification_sent = 0; 1073 TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr); 1074 1075 TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr); 1076 STAILQ_INIT(&ctrlr->fail_req); 1077 ctrlr->is_failed = FALSE; 1078 1079 return (0); 1080 } 1081 1082 void 1083 nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev) 1084 { 1085 int i; 1086 1087 /* 1088 * Notify the controller of a shutdown, even though this is due to 1089 * a driver unload, not a system shutdown (this path is not invoked 1090 * during shutdown). This ensures the controller receives a 1091 * shutdown notification in case the system is shutdown before 1092 * reloading the driver. 1093 */ 1094 nvme_ctrlr_shutdown(ctrlr); 1095 1096 nvme_ctrlr_disable(ctrlr); 1097 taskqueue_free(ctrlr->taskqueue); 1098 1099 for (i = 0; i < NVME_MAX_NAMESPACES; i++) 1100 nvme_ns_destruct(&ctrlr->ns[i]); 1101 1102 if (ctrlr->cdev) 1103 destroy_dev(ctrlr->cdev); 1104 1105 for (i = 0; i < ctrlr->num_io_queues; i++) { 1106 nvme_io_qpair_destroy(&ctrlr->ioq[i]); 1107 } 1108 1109 free(ctrlr->ioq, M_NVME); 1110 1111 nvme_admin_qpair_destroy(&ctrlr->adminq); 1112 1113 if (ctrlr->resource != NULL) { 1114 bus_release_resource(dev, SYS_RES_MEMORY, 1115 ctrlr->resource_id, ctrlr->resource); 1116 } 1117 1118 if (ctrlr->bar4_resource != NULL) { 1119 bus_release_resource(dev, SYS_RES_MEMORY, 1120 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 1121 } 1122 1123 if (ctrlr->tag) 1124 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag); 1125 1126 if (ctrlr->res) 1127 bus_release_resource(ctrlr->dev, SYS_RES_IRQ, 1128 rman_get_rid(ctrlr->res), ctrlr->res); 1129 1130 if (ctrlr->msix_enabled) 1131 pci_release_msi(dev); 1132 } 1133 1134 void 1135 nvme_ctrlr_shutdown(struct nvme_controller *ctrlr) 1136 { 1137 union cc_register cc; 1138 union csts_register csts; 1139 int ticks = 0; 1140 1141 cc.raw = nvme_mmio_read_4(ctrlr, cc); 1142 cc.bits.shn = NVME_SHN_NORMAL; 1143 nvme_mmio_write_4(ctrlr, cc, cc.raw); 1144 csts.raw = nvme_mmio_read_4(ctrlr, csts); 1145 while ((csts.bits.shst != NVME_SHST_COMPLETE) && (ticks++ < 5*hz)) { 1146 pause("nvme shn", 1); 1147 csts.raw = nvme_mmio_read_4(ctrlr, csts); 1148 } 1149 if (csts.bits.shst != NVME_SHST_COMPLETE) 1150 nvme_printf(ctrlr, "did not complete shutdown within 5 seconds " 1151 "of notification\n"); 1152 } 1153 1154 void 1155 nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 1156 struct nvme_request *req) 1157 { 1158 1159 nvme_qpair_submit_request(&ctrlr->adminq, req); 1160 } 1161 1162 void 1163 nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 1164 struct nvme_request *req) 1165 { 1166 struct nvme_qpair *qpair; 1167 1168 if (ctrlr->per_cpu_io_queues) 1169 qpair = &ctrlr->ioq[curcpu]; 1170 else 1171 qpair = &ctrlr->ioq[0]; 1172 1173 nvme_qpair_submit_request(qpair, req); 1174 } 1175 1176 device_t 1177 nvme_ctrlr_get_device(struct nvme_controller *ctrlr) 1178 { 1179 1180 return (ctrlr->dev); 1181 } 1182 1183 const struct nvme_controller_data * 1184 nvme_ctrlr_get_data(struct nvme_controller *ctrlr) 1185 { 1186 1187 return (&ctrlr->cdata); 1188 } 1189