1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2016 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_cam.h" 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/buf.h> 37 #include <sys/bus.h> 38 #include <sys/conf.h> 39 #include <sys/ioccom.h> 40 #include <sys/proc.h> 41 #include <sys/smp.h> 42 #include <sys/uio.h> 43 #include <sys/sbuf.h> 44 #include <sys/endian.h> 45 #include <machine/stdarg.h> 46 #include <vm/vm.h> 47 48 #include "nvme_private.h" 49 50 #define B4_CHK_RDY_DELAY_MS 2300 /* work around controller bug */ 51 52 static void nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 53 struct nvme_async_event_request *aer); 54 55 static void 56 nvme_ctrlr_devctl_log(struct nvme_controller *ctrlr, const char *type, const char *msg, ...) 57 { 58 struct sbuf sb; 59 va_list ap; 60 int error; 61 62 if (sbuf_new(&sb, NULL, 0, SBUF_AUTOEXTEND | SBUF_NOWAIT) == NULL) 63 return; 64 sbuf_printf(&sb, "%s: ", device_get_nameunit(ctrlr->dev)); 65 va_start(ap, msg); 66 sbuf_vprintf(&sb, msg, ap); 67 va_end(ap); 68 error = sbuf_finish(&sb); 69 if (error == 0) 70 printf("%s\n", sbuf_data(&sb)); 71 72 sbuf_clear(&sb); 73 sbuf_printf(&sb, "name=\"%s\" reason=\"", device_get_nameunit(ctrlr->dev)); 74 va_start(ap, msg); 75 sbuf_vprintf(&sb, msg, ap); 76 va_end(ap); 77 sbuf_printf(&sb, "\""); 78 error = sbuf_finish(&sb); 79 if (error == 0) 80 devctl_notify("nvme", "controller", type, sbuf_data(&sb)); 81 sbuf_delete(&sb); 82 } 83 84 static int 85 nvme_ctrlr_construct_admin_qpair(struct nvme_controller *ctrlr) 86 { 87 struct nvme_qpair *qpair; 88 uint32_t num_entries; 89 int error; 90 91 qpair = &ctrlr->adminq; 92 qpair->id = 0; 93 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1; 94 qpair->domain = ctrlr->domain; 95 96 num_entries = NVME_ADMIN_ENTRIES; 97 TUNABLE_INT_FETCH("hw.nvme.admin_entries", &num_entries); 98 /* 99 * If admin_entries was overridden to an invalid value, revert it 100 * back to our default value. 101 */ 102 if (num_entries < NVME_MIN_ADMIN_ENTRIES || 103 num_entries > NVME_MAX_ADMIN_ENTRIES) { 104 nvme_printf(ctrlr, "invalid hw.nvme.admin_entries=%d " 105 "specified\n", num_entries); 106 num_entries = NVME_ADMIN_ENTRIES; 107 } 108 109 /* 110 * The admin queue's max xfer size is treated differently than the 111 * max I/O xfer size. 16KB is sufficient here - maybe even less? 112 */ 113 error = nvme_qpair_construct(qpair, num_entries, NVME_ADMIN_TRACKERS, 114 ctrlr); 115 return (error); 116 } 117 118 #define QP(ctrlr, c) ((c) * (ctrlr)->num_io_queues / mp_ncpus) 119 120 static int 121 nvme_ctrlr_construct_io_qpairs(struct nvme_controller *ctrlr) 122 { 123 struct nvme_qpair *qpair; 124 uint32_t cap_lo; 125 uint16_t mqes; 126 int c, error, i, n; 127 int num_entries, num_trackers, max_entries; 128 129 /* 130 * NVMe spec sets a hard limit of 64K max entries, but devices may 131 * specify a smaller limit, so we need to check the MQES field in the 132 * capabilities register. We have to cap the number of entries to the 133 * current stride allows for in BAR 0/1, otherwise the remainder entries 134 * are inaccessable. MQES should reflect this, and this is just a 135 * fail-safe. 136 */ 137 max_entries = 138 (rman_get_size(ctrlr->resource) - nvme_mmio_offsetof(doorbell[0])) / 139 (1 << (ctrlr->dstrd + 1)); 140 num_entries = NVME_IO_ENTRIES; 141 TUNABLE_INT_FETCH("hw.nvme.io_entries", &num_entries); 142 cap_lo = nvme_mmio_read_4(ctrlr, cap_lo); 143 mqes = NVME_CAP_LO_MQES(cap_lo); 144 num_entries = min(num_entries, mqes + 1); 145 num_entries = min(num_entries, max_entries); 146 147 num_trackers = NVME_IO_TRACKERS; 148 TUNABLE_INT_FETCH("hw.nvme.io_trackers", &num_trackers); 149 150 num_trackers = max(num_trackers, NVME_MIN_IO_TRACKERS); 151 num_trackers = min(num_trackers, NVME_MAX_IO_TRACKERS); 152 /* 153 * No need to have more trackers than entries in the submit queue. Note 154 * also that for a queue size of N, we can only have (N-1) commands 155 * outstanding, hence the "-1" here. 156 */ 157 num_trackers = min(num_trackers, (num_entries-1)); 158 159 /* 160 * Our best estimate for the maximum number of I/Os that we should 161 * normally have in flight at one time. This should be viewed as a hint, 162 * not a hard limit and will need to be revisited when the upper layers 163 * of the storage system grows multi-queue support. 164 */ 165 ctrlr->max_hw_pend_io = num_trackers * ctrlr->num_io_queues * 3 / 4; 166 167 ctrlr->ioq = malloc(ctrlr->num_io_queues * sizeof(struct nvme_qpair), 168 M_NVME, M_ZERO | M_WAITOK); 169 170 for (i = c = n = 0; i < ctrlr->num_io_queues; i++, c += n) { 171 qpair = &ctrlr->ioq[i]; 172 173 /* 174 * Admin queue has ID=0. IO queues start at ID=1 - 175 * hence the 'i+1' here. 176 */ 177 qpair->id = i + 1; 178 if (ctrlr->num_io_queues > 1) { 179 /* Find number of CPUs served by this queue. */ 180 for (n = 1; QP(ctrlr, c + n) == i; n++) 181 ; 182 /* Shuffle multiple NVMe devices between CPUs. */ 183 qpair->cpu = c + (device_get_unit(ctrlr->dev)+n/2) % n; 184 qpair->domain = pcpu_find(qpair->cpu)->pc_domain; 185 } else { 186 qpair->cpu = CPU_FFS(&cpuset_domain[ctrlr->domain]) - 1; 187 qpair->domain = ctrlr->domain; 188 } 189 190 /* 191 * For I/O queues, use the controller-wide max_xfer_size 192 * calculated in nvme_attach(). 193 */ 194 error = nvme_qpair_construct(qpair, num_entries, num_trackers, 195 ctrlr); 196 if (error) 197 return (error); 198 199 /* 200 * Do not bother binding interrupts if we only have one I/O 201 * interrupt thread for this controller. 202 */ 203 if (ctrlr->num_io_queues > 1) 204 bus_bind_intr(ctrlr->dev, qpair->res, qpair->cpu); 205 } 206 207 return (0); 208 } 209 210 static void 211 nvme_ctrlr_fail(struct nvme_controller *ctrlr) 212 { 213 int i; 214 215 ctrlr->is_failed = true; 216 nvme_admin_qpair_disable(&ctrlr->adminq); 217 nvme_qpair_fail(&ctrlr->adminq); 218 if (ctrlr->ioq != NULL) { 219 for (i = 0; i < ctrlr->num_io_queues; i++) { 220 nvme_io_qpair_disable(&ctrlr->ioq[i]); 221 nvme_qpair_fail(&ctrlr->ioq[i]); 222 } 223 } 224 nvme_notify_fail_consumers(ctrlr); 225 } 226 227 void 228 nvme_ctrlr_post_failed_request(struct nvme_controller *ctrlr, 229 struct nvme_request *req) 230 { 231 232 mtx_lock(&ctrlr->lock); 233 STAILQ_INSERT_TAIL(&ctrlr->fail_req, req, stailq); 234 mtx_unlock(&ctrlr->lock); 235 if (!ctrlr->is_dying) 236 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->fail_req_task); 237 } 238 239 static void 240 nvme_ctrlr_fail_req_task(void *arg, int pending) 241 { 242 struct nvme_controller *ctrlr = arg; 243 struct nvme_request *req; 244 245 mtx_lock(&ctrlr->lock); 246 while ((req = STAILQ_FIRST(&ctrlr->fail_req)) != NULL) { 247 STAILQ_REMOVE_HEAD(&ctrlr->fail_req, stailq); 248 mtx_unlock(&ctrlr->lock); 249 nvme_qpair_manual_complete_request(req->qpair, req, 250 NVME_SCT_GENERIC, NVME_SC_ABORTED_BY_REQUEST); 251 mtx_lock(&ctrlr->lock); 252 } 253 mtx_unlock(&ctrlr->lock); 254 } 255 256 static int 257 nvme_ctrlr_wait_for_ready(struct nvme_controller *ctrlr, int desired_val) 258 { 259 int timeout = ticks + (uint64_t)ctrlr->ready_timeout_in_ms * hz / 1000; 260 uint32_t csts; 261 262 while (1) { 263 csts = nvme_mmio_read_4(ctrlr, csts); 264 if (csts == NVME_GONE) /* Hot unplug. */ 265 return (ENXIO); 266 if (((csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK) 267 == desired_val) 268 break; 269 if (timeout - ticks < 0) { 270 nvme_printf(ctrlr, "controller ready did not become %d " 271 "within %d ms\n", desired_val, ctrlr->ready_timeout_in_ms); 272 return (ENXIO); 273 } 274 pause("nvmerdy", 1); 275 } 276 277 return (0); 278 } 279 280 static int 281 nvme_ctrlr_disable(struct nvme_controller *ctrlr) 282 { 283 uint32_t cc; 284 uint32_t csts; 285 uint8_t en, rdy; 286 int err; 287 288 cc = nvme_mmio_read_4(ctrlr, cc); 289 csts = nvme_mmio_read_4(ctrlr, csts); 290 291 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; 292 rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK; 293 294 /* 295 * Per 3.1.5 in NVME 1.3 spec, transitioning CC.EN from 0 to 1 296 * when CSTS.RDY is 1 or transitioning CC.EN from 1 to 0 when 297 * CSTS.RDY is 0 "has undefined results" So make sure that CSTS.RDY 298 * isn't the desired value. Short circuit if we're already disabled. 299 */ 300 if (en == 1) { 301 if (rdy == 0) { 302 /* EN == 1, wait for RDY == 1 or fail */ 303 err = nvme_ctrlr_wait_for_ready(ctrlr, 1); 304 if (err != 0) 305 return (err); 306 } 307 } else { 308 /* EN == 0 already wait for RDY == 0 */ 309 if (rdy == 0) 310 return (0); 311 else 312 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 313 } 314 315 cc &= ~NVME_CC_REG_EN_MASK; 316 nvme_mmio_write_4(ctrlr, cc, cc); 317 /* 318 * Some drives have issues with accessing the mmio after we 319 * disable, so delay for a bit after we write the bit to 320 * cope with these issues. 321 */ 322 if (ctrlr->quirks & QUIRK_DELAY_B4_CHK_RDY) 323 pause("nvmeR", B4_CHK_RDY_DELAY_MS * hz / 1000); 324 return (nvme_ctrlr_wait_for_ready(ctrlr, 0)); 325 } 326 327 static int 328 nvme_ctrlr_enable(struct nvme_controller *ctrlr) 329 { 330 uint32_t cc; 331 uint32_t csts; 332 uint32_t aqa; 333 uint32_t qsize; 334 uint8_t en, rdy; 335 int err; 336 337 cc = nvme_mmio_read_4(ctrlr, cc); 338 csts = nvme_mmio_read_4(ctrlr, csts); 339 340 en = (cc >> NVME_CC_REG_EN_SHIFT) & NVME_CC_REG_EN_MASK; 341 rdy = (csts >> NVME_CSTS_REG_RDY_SHIFT) & NVME_CSTS_REG_RDY_MASK; 342 343 /* 344 * See note in nvme_ctrlr_disable. Short circuit if we're already enabled. 345 */ 346 if (en == 1) { 347 if (rdy == 1) 348 return (0); 349 else 350 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 351 } else { 352 /* EN == 0 already wait for RDY == 0 or fail */ 353 err = nvme_ctrlr_wait_for_ready(ctrlr, 0); 354 if (err != 0) 355 return (err); 356 } 357 358 nvme_mmio_write_8(ctrlr, asq, ctrlr->adminq.cmd_bus_addr); 359 DELAY(5000); 360 nvme_mmio_write_8(ctrlr, acq, ctrlr->adminq.cpl_bus_addr); 361 DELAY(5000); 362 363 /* acqs and asqs are 0-based. */ 364 qsize = ctrlr->adminq.num_entries - 1; 365 366 aqa = 0; 367 aqa = (qsize & NVME_AQA_REG_ACQS_MASK) << NVME_AQA_REG_ACQS_SHIFT; 368 aqa |= (qsize & NVME_AQA_REG_ASQS_MASK) << NVME_AQA_REG_ASQS_SHIFT; 369 nvme_mmio_write_4(ctrlr, aqa, aqa); 370 DELAY(5000); 371 372 /* Initialization values for CC */ 373 cc = 0; 374 cc |= 1 << NVME_CC_REG_EN_SHIFT; 375 cc |= 0 << NVME_CC_REG_CSS_SHIFT; 376 cc |= 0 << NVME_CC_REG_AMS_SHIFT; 377 cc |= 0 << NVME_CC_REG_SHN_SHIFT; 378 cc |= 6 << NVME_CC_REG_IOSQES_SHIFT; /* SQ entry size == 64 == 2^6 */ 379 cc |= 4 << NVME_CC_REG_IOCQES_SHIFT; /* CQ entry size == 16 == 2^4 */ 380 381 /* This evaluates to 0, which is according to spec. */ 382 cc |= (PAGE_SIZE >> 13) << NVME_CC_REG_MPS_SHIFT; 383 384 nvme_mmio_write_4(ctrlr, cc, cc); 385 386 return (nvme_ctrlr_wait_for_ready(ctrlr, 1)); 387 } 388 389 static void 390 nvme_ctrlr_disable_qpairs(struct nvme_controller *ctrlr) 391 { 392 int i; 393 394 nvme_admin_qpair_disable(&ctrlr->adminq); 395 /* 396 * I/O queues are not allocated before the initial HW 397 * reset, so do not try to disable them. Use is_initialized 398 * to determine if this is the initial HW reset. 399 */ 400 if (ctrlr->is_initialized) { 401 for (i = 0; i < ctrlr->num_io_queues; i++) 402 nvme_io_qpair_disable(&ctrlr->ioq[i]); 403 } 404 } 405 406 static int 407 nvme_ctrlr_hw_reset(struct nvme_controller *ctrlr) 408 { 409 int err; 410 411 TSENTER(); 412 nvme_ctrlr_disable_qpairs(ctrlr); 413 414 pause("nvmehwreset", hz / 10); 415 416 err = nvme_ctrlr_disable(ctrlr); 417 if (err != 0) 418 return err; 419 err = nvme_ctrlr_enable(ctrlr); 420 TSEXIT(); 421 return (err); 422 } 423 424 void 425 nvme_ctrlr_reset(struct nvme_controller *ctrlr) 426 { 427 int cmpset; 428 429 cmpset = atomic_cmpset_32(&ctrlr->is_resetting, 0, 1); 430 431 if (cmpset == 0 || ctrlr->is_failed) 432 /* 433 * Controller is already resetting or has failed. Return 434 * immediately since there is no need to kick off another 435 * reset in these cases. 436 */ 437 return; 438 439 if (!ctrlr->is_dying) 440 taskqueue_enqueue(ctrlr->taskqueue, &ctrlr->reset_task); 441 } 442 443 static int 444 nvme_ctrlr_identify(struct nvme_controller *ctrlr) 445 { 446 struct nvme_completion_poll_status status; 447 448 status.done = 0; 449 nvme_ctrlr_cmd_identify_controller(ctrlr, &ctrlr->cdata, 450 nvme_completion_poll_cb, &status); 451 nvme_completion_poll(&status); 452 if (nvme_completion_is_error(&status.cpl)) { 453 nvme_printf(ctrlr, "nvme_identify_controller failed!\n"); 454 return (ENXIO); 455 } 456 457 /* Convert data to host endian */ 458 nvme_controller_data_swapbytes(&ctrlr->cdata); 459 460 /* 461 * Use MDTS to ensure our default max_xfer_size doesn't exceed what the 462 * controller supports. 463 */ 464 if (ctrlr->cdata.mdts > 0) 465 ctrlr->max_xfer_size = min(ctrlr->max_xfer_size, 466 ctrlr->min_page_size * (1 << (ctrlr->cdata.mdts))); 467 468 return (0); 469 } 470 471 static int 472 nvme_ctrlr_set_num_qpairs(struct nvme_controller *ctrlr) 473 { 474 struct nvme_completion_poll_status status; 475 int cq_allocated, sq_allocated; 476 477 status.done = 0; 478 nvme_ctrlr_cmd_set_num_queues(ctrlr, ctrlr->num_io_queues, 479 nvme_completion_poll_cb, &status); 480 nvme_completion_poll(&status); 481 if (nvme_completion_is_error(&status.cpl)) { 482 nvme_printf(ctrlr, "nvme_ctrlr_set_num_qpairs failed!\n"); 483 return (ENXIO); 484 } 485 486 /* 487 * Data in cdw0 is 0-based. 488 * Lower 16-bits indicate number of submission queues allocated. 489 * Upper 16-bits indicate number of completion queues allocated. 490 */ 491 sq_allocated = (status.cpl.cdw0 & 0xFFFF) + 1; 492 cq_allocated = (status.cpl.cdw0 >> 16) + 1; 493 494 /* 495 * Controller may allocate more queues than we requested, 496 * so use the minimum of the number requested and what was 497 * actually allocated. 498 */ 499 ctrlr->num_io_queues = min(ctrlr->num_io_queues, sq_allocated); 500 ctrlr->num_io_queues = min(ctrlr->num_io_queues, cq_allocated); 501 if (ctrlr->num_io_queues > vm_ndomains) 502 ctrlr->num_io_queues -= ctrlr->num_io_queues % vm_ndomains; 503 504 return (0); 505 } 506 507 static int 508 nvme_ctrlr_create_qpairs(struct nvme_controller *ctrlr) 509 { 510 struct nvme_completion_poll_status status; 511 struct nvme_qpair *qpair; 512 int i; 513 514 for (i = 0; i < ctrlr->num_io_queues; i++) { 515 qpair = &ctrlr->ioq[i]; 516 517 status.done = 0; 518 nvme_ctrlr_cmd_create_io_cq(ctrlr, qpair, 519 nvme_completion_poll_cb, &status); 520 nvme_completion_poll(&status); 521 if (nvme_completion_is_error(&status.cpl)) { 522 nvme_printf(ctrlr, "nvme_create_io_cq failed!\n"); 523 return (ENXIO); 524 } 525 526 status.done = 0; 527 nvme_ctrlr_cmd_create_io_sq(ctrlr, qpair, 528 nvme_completion_poll_cb, &status); 529 nvme_completion_poll(&status); 530 if (nvme_completion_is_error(&status.cpl)) { 531 nvme_printf(ctrlr, "nvme_create_io_sq failed!\n"); 532 return (ENXIO); 533 } 534 } 535 536 return (0); 537 } 538 539 static int 540 nvme_ctrlr_delete_qpairs(struct nvme_controller *ctrlr) 541 { 542 struct nvme_completion_poll_status status; 543 struct nvme_qpair *qpair; 544 545 for (int i = 0; i < ctrlr->num_io_queues; i++) { 546 qpair = &ctrlr->ioq[i]; 547 548 status.done = 0; 549 nvme_ctrlr_cmd_delete_io_sq(ctrlr, qpair, 550 nvme_completion_poll_cb, &status); 551 nvme_completion_poll(&status); 552 if (nvme_completion_is_error(&status.cpl)) { 553 nvme_printf(ctrlr, "nvme_destroy_io_sq failed!\n"); 554 return (ENXIO); 555 } 556 557 status.done = 0; 558 nvme_ctrlr_cmd_delete_io_cq(ctrlr, qpair, 559 nvme_completion_poll_cb, &status); 560 nvme_completion_poll(&status); 561 if (nvme_completion_is_error(&status.cpl)) { 562 nvme_printf(ctrlr, "nvme_destroy_io_cq failed!\n"); 563 return (ENXIO); 564 } 565 } 566 567 return (0); 568 } 569 570 static int 571 nvme_ctrlr_construct_namespaces(struct nvme_controller *ctrlr) 572 { 573 struct nvme_namespace *ns; 574 uint32_t i; 575 576 for (i = 0; i < min(ctrlr->cdata.nn, NVME_MAX_NAMESPACES); i++) { 577 ns = &ctrlr->ns[i]; 578 nvme_ns_construct(ns, i+1, ctrlr); 579 } 580 581 return (0); 582 } 583 584 static bool 585 is_log_page_id_valid(uint8_t page_id) 586 { 587 588 switch (page_id) { 589 case NVME_LOG_ERROR: 590 case NVME_LOG_HEALTH_INFORMATION: 591 case NVME_LOG_FIRMWARE_SLOT: 592 case NVME_LOG_CHANGED_NAMESPACE: 593 case NVME_LOG_COMMAND_EFFECT: 594 case NVME_LOG_RES_NOTIFICATION: 595 case NVME_LOG_SANITIZE_STATUS: 596 return (true); 597 } 598 599 return (false); 600 } 601 602 static uint32_t 603 nvme_ctrlr_get_log_page_size(struct nvme_controller *ctrlr, uint8_t page_id) 604 { 605 uint32_t log_page_size; 606 607 switch (page_id) { 608 case NVME_LOG_ERROR: 609 log_page_size = min( 610 sizeof(struct nvme_error_information_entry) * 611 (ctrlr->cdata.elpe + 1), NVME_MAX_AER_LOG_SIZE); 612 break; 613 case NVME_LOG_HEALTH_INFORMATION: 614 log_page_size = sizeof(struct nvme_health_information_page); 615 break; 616 case NVME_LOG_FIRMWARE_SLOT: 617 log_page_size = sizeof(struct nvme_firmware_page); 618 break; 619 case NVME_LOG_CHANGED_NAMESPACE: 620 log_page_size = sizeof(struct nvme_ns_list); 621 break; 622 case NVME_LOG_COMMAND_EFFECT: 623 log_page_size = sizeof(struct nvme_command_effects_page); 624 break; 625 case NVME_LOG_RES_NOTIFICATION: 626 log_page_size = sizeof(struct nvme_res_notification_page); 627 break; 628 case NVME_LOG_SANITIZE_STATUS: 629 log_page_size = sizeof(struct nvme_sanitize_status_page); 630 break; 631 default: 632 log_page_size = 0; 633 break; 634 } 635 636 return (log_page_size); 637 } 638 639 static void 640 nvme_ctrlr_log_critical_warnings(struct nvme_controller *ctrlr, 641 uint8_t state) 642 { 643 644 if (state & NVME_CRIT_WARN_ST_AVAILABLE_SPARE) 645 nvme_ctrlr_devctl_log(ctrlr, "critical", 646 "available spare space below threshold"); 647 648 if (state & NVME_CRIT_WARN_ST_TEMPERATURE) 649 nvme_ctrlr_devctl_log(ctrlr, "critical", 650 "temperature above threshold"); 651 652 if (state & NVME_CRIT_WARN_ST_DEVICE_RELIABILITY) 653 nvme_ctrlr_devctl_log(ctrlr, "critical", 654 "device reliability degraded"); 655 656 if (state & NVME_CRIT_WARN_ST_READ_ONLY) 657 nvme_ctrlr_devctl_log(ctrlr, "critical", 658 "media placed in read only mode"); 659 660 if (state & NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP) 661 nvme_ctrlr_devctl_log(ctrlr, "critical", 662 "volatile memory backup device failed"); 663 664 if (state & NVME_CRIT_WARN_ST_RESERVED_MASK) 665 nvme_ctrlr_devctl_log(ctrlr, "critical", 666 "unknown critical warning(s): state = 0x%02x", state); 667 } 668 669 static void 670 nvme_ctrlr_async_event_log_page_cb(void *arg, const struct nvme_completion *cpl) 671 { 672 struct nvme_async_event_request *aer = arg; 673 struct nvme_health_information_page *health_info; 674 struct nvme_ns_list *nsl; 675 struct nvme_error_information_entry *err; 676 int i; 677 678 /* 679 * If the log page fetch for some reason completed with an error, 680 * don't pass log page data to the consumers. In practice, this case 681 * should never happen. 682 */ 683 if (nvme_completion_is_error(cpl)) 684 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 685 aer->log_page_id, NULL, 0); 686 else { 687 /* Convert data to host endian */ 688 switch (aer->log_page_id) { 689 case NVME_LOG_ERROR: 690 err = (struct nvme_error_information_entry *)aer->log_page_buffer; 691 for (i = 0; i < (aer->ctrlr->cdata.elpe + 1); i++) 692 nvme_error_information_entry_swapbytes(err++); 693 break; 694 case NVME_LOG_HEALTH_INFORMATION: 695 nvme_health_information_page_swapbytes( 696 (struct nvme_health_information_page *)aer->log_page_buffer); 697 break; 698 case NVME_LOG_FIRMWARE_SLOT: 699 nvme_firmware_page_swapbytes( 700 (struct nvme_firmware_page *)aer->log_page_buffer); 701 break; 702 case NVME_LOG_CHANGED_NAMESPACE: 703 nvme_ns_list_swapbytes( 704 (struct nvme_ns_list *)aer->log_page_buffer); 705 break; 706 case NVME_LOG_COMMAND_EFFECT: 707 nvme_command_effects_page_swapbytes( 708 (struct nvme_command_effects_page *)aer->log_page_buffer); 709 break; 710 case NVME_LOG_RES_NOTIFICATION: 711 nvme_res_notification_page_swapbytes( 712 (struct nvme_res_notification_page *)aer->log_page_buffer); 713 break; 714 case NVME_LOG_SANITIZE_STATUS: 715 nvme_sanitize_status_page_swapbytes( 716 (struct nvme_sanitize_status_page *)aer->log_page_buffer); 717 break; 718 case INTEL_LOG_TEMP_STATS: 719 intel_log_temp_stats_swapbytes( 720 (struct intel_log_temp_stats *)aer->log_page_buffer); 721 break; 722 default: 723 break; 724 } 725 726 if (aer->log_page_id == NVME_LOG_HEALTH_INFORMATION) { 727 health_info = (struct nvme_health_information_page *) 728 aer->log_page_buffer; 729 nvme_ctrlr_log_critical_warnings(aer->ctrlr, 730 health_info->critical_warning); 731 /* 732 * Critical warnings reported through the 733 * SMART/health log page are persistent, so 734 * clear the associated bits in the async event 735 * config so that we do not receive repeated 736 * notifications for the same event. 737 */ 738 aer->ctrlr->async_event_config &= 739 ~health_info->critical_warning; 740 nvme_ctrlr_cmd_set_async_event_config(aer->ctrlr, 741 aer->ctrlr->async_event_config, NULL, NULL); 742 } else if (aer->log_page_id == NVME_LOG_CHANGED_NAMESPACE && 743 !nvme_use_nvd) { 744 nsl = (struct nvme_ns_list *)aer->log_page_buffer; 745 for (i = 0; i < nitems(nsl->ns) && nsl->ns[i] != 0; i++) { 746 if (nsl->ns[i] > NVME_MAX_NAMESPACES) 747 break; 748 nvme_notify_ns(aer->ctrlr, nsl->ns[i]); 749 } 750 } 751 752 /* 753 * Pass the cpl data from the original async event completion, 754 * not the log page fetch. 755 */ 756 nvme_notify_async_consumers(aer->ctrlr, &aer->cpl, 757 aer->log_page_id, aer->log_page_buffer, aer->log_page_size); 758 } 759 760 /* 761 * Repost another asynchronous event request to replace the one 762 * that just completed. 763 */ 764 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 765 } 766 767 static void 768 nvme_ctrlr_async_event_cb(void *arg, const struct nvme_completion *cpl) 769 { 770 struct nvme_async_event_request *aer = arg; 771 772 if (nvme_completion_is_error(cpl)) { 773 /* 774 * Do not retry failed async event requests. This avoids 775 * infinite loops where a new async event request is submitted 776 * to replace the one just failed, only to fail again and 777 * perpetuate the loop. 778 */ 779 return; 780 } 781 782 /* Associated log page is in bits 23:16 of completion entry dw0. */ 783 aer->log_page_id = (cpl->cdw0 & 0xFF0000) >> 16; 784 785 nvme_printf(aer->ctrlr, "async event occurred (type 0x%x, info 0x%02x," 786 " page 0x%02x)\n", (cpl->cdw0 & 0x07), (cpl->cdw0 & 0xFF00) >> 8, 787 aer->log_page_id); 788 789 if (is_log_page_id_valid(aer->log_page_id)) { 790 aer->log_page_size = nvme_ctrlr_get_log_page_size(aer->ctrlr, 791 aer->log_page_id); 792 memcpy(&aer->cpl, cpl, sizeof(*cpl)); 793 nvme_ctrlr_cmd_get_log_page(aer->ctrlr, aer->log_page_id, 794 NVME_GLOBAL_NAMESPACE_TAG, aer->log_page_buffer, 795 aer->log_page_size, nvme_ctrlr_async_event_log_page_cb, 796 aer); 797 /* Wait to notify consumers until after log page is fetched. */ 798 } else { 799 nvme_notify_async_consumers(aer->ctrlr, cpl, aer->log_page_id, 800 NULL, 0); 801 802 /* 803 * Repost another asynchronous event request to replace the one 804 * that just completed. 805 */ 806 nvme_ctrlr_construct_and_submit_aer(aer->ctrlr, aer); 807 } 808 } 809 810 static void 811 nvme_ctrlr_construct_and_submit_aer(struct nvme_controller *ctrlr, 812 struct nvme_async_event_request *aer) 813 { 814 struct nvme_request *req; 815 816 aer->ctrlr = ctrlr; 817 req = nvme_allocate_request_null(nvme_ctrlr_async_event_cb, aer); 818 aer->req = req; 819 820 /* 821 * Disable timeout here, since asynchronous event requests should by 822 * nature never be timed out. 823 */ 824 req->timeout = false; 825 req->cmd.opc = NVME_OPC_ASYNC_EVENT_REQUEST; 826 nvme_ctrlr_submit_admin_request(ctrlr, req); 827 } 828 829 static void 830 nvme_ctrlr_configure_aer(struct nvme_controller *ctrlr) 831 { 832 struct nvme_completion_poll_status status; 833 struct nvme_async_event_request *aer; 834 uint32_t i; 835 836 ctrlr->async_event_config = NVME_CRIT_WARN_ST_AVAILABLE_SPARE | 837 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY | 838 NVME_CRIT_WARN_ST_READ_ONLY | 839 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP; 840 if (ctrlr->cdata.ver >= NVME_REV(1, 2)) 841 ctrlr->async_event_config |= NVME_ASYNC_EVENT_NS_ATTRIBUTE | 842 NVME_ASYNC_EVENT_FW_ACTIVATE; 843 844 status.done = 0; 845 nvme_ctrlr_cmd_get_feature(ctrlr, NVME_FEAT_TEMPERATURE_THRESHOLD, 846 0, NULL, 0, nvme_completion_poll_cb, &status); 847 nvme_completion_poll(&status); 848 if (nvme_completion_is_error(&status.cpl) || 849 (status.cpl.cdw0 & 0xFFFF) == 0xFFFF || 850 (status.cpl.cdw0 & 0xFFFF) == 0x0000) { 851 nvme_printf(ctrlr, "temperature threshold not supported\n"); 852 } else 853 ctrlr->async_event_config |= NVME_CRIT_WARN_ST_TEMPERATURE; 854 855 nvme_ctrlr_cmd_set_async_event_config(ctrlr, 856 ctrlr->async_event_config, NULL, NULL); 857 858 /* aerl is a zero-based value, so we need to add 1 here. */ 859 ctrlr->num_aers = min(NVME_MAX_ASYNC_EVENTS, (ctrlr->cdata.aerl+1)); 860 861 for (i = 0; i < ctrlr->num_aers; i++) { 862 aer = &ctrlr->aer[i]; 863 nvme_ctrlr_construct_and_submit_aer(ctrlr, aer); 864 } 865 } 866 867 static void 868 nvme_ctrlr_configure_int_coalescing(struct nvme_controller *ctrlr) 869 { 870 871 ctrlr->int_coal_time = 0; 872 TUNABLE_INT_FETCH("hw.nvme.int_coal_time", 873 &ctrlr->int_coal_time); 874 875 ctrlr->int_coal_threshold = 0; 876 TUNABLE_INT_FETCH("hw.nvme.int_coal_threshold", 877 &ctrlr->int_coal_threshold); 878 879 nvme_ctrlr_cmd_set_interrupt_coalescing(ctrlr, ctrlr->int_coal_time, 880 ctrlr->int_coal_threshold, NULL, NULL); 881 } 882 883 static void 884 nvme_ctrlr_hmb_free(struct nvme_controller *ctrlr) 885 { 886 struct nvme_hmb_chunk *hmbc; 887 int i; 888 889 if (ctrlr->hmb_desc_paddr) { 890 bus_dmamap_unload(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map); 891 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr, 892 ctrlr->hmb_desc_map); 893 ctrlr->hmb_desc_paddr = 0; 894 } 895 if (ctrlr->hmb_desc_tag) { 896 bus_dma_tag_destroy(ctrlr->hmb_desc_tag); 897 ctrlr->hmb_desc_tag = NULL; 898 } 899 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 900 hmbc = &ctrlr->hmb_chunks[i]; 901 bus_dmamap_unload(ctrlr->hmb_tag, hmbc->hmbc_map); 902 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr, 903 hmbc->hmbc_map); 904 } 905 ctrlr->hmb_nchunks = 0; 906 if (ctrlr->hmb_tag) { 907 bus_dma_tag_destroy(ctrlr->hmb_tag); 908 ctrlr->hmb_tag = NULL; 909 } 910 if (ctrlr->hmb_chunks) { 911 free(ctrlr->hmb_chunks, M_NVME); 912 ctrlr->hmb_chunks = NULL; 913 } 914 } 915 916 static void 917 nvme_ctrlr_hmb_alloc(struct nvme_controller *ctrlr) 918 { 919 struct nvme_hmb_chunk *hmbc; 920 size_t pref, min, minc, size; 921 int err, i; 922 uint64_t max; 923 924 /* Limit HMB to 5% of RAM size per device by default. */ 925 max = (uint64_t)physmem * PAGE_SIZE / 20; 926 TUNABLE_UINT64_FETCH("hw.nvme.hmb_max", &max); 927 928 min = (long long unsigned)ctrlr->cdata.hmmin * 4096; 929 if (max == 0 || max < min) 930 return; 931 pref = MIN((long long unsigned)ctrlr->cdata.hmpre * 4096, max); 932 minc = MAX(ctrlr->cdata.hmminds * 4096, PAGE_SIZE); 933 if (min > 0 && ctrlr->cdata.hmmaxd > 0) 934 minc = MAX(minc, min / ctrlr->cdata.hmmaxd); 935 ctrlr->hmb_chunk = pref; 936 937 again: 938 ctrlr->hmb_chunk = roundup2(ctrlr->hmb_chunk, PAGE_SIZE); 939 ctrlr->hmb_nchunks = howmany(pref, ctrlr->hmb_chunk); 940 if (ctrlr->cdata.hmmaxd > 0 && ctrlr->hmb_nchunks > ctrlr->cdata.hmmaxd) 941 ctrlr->hmb_nchunks = ctrlr->cdata.hmmaxd; 942 ctrlr->hmb_chunks = malloc(sizeof(struct nvme_hmb_chunk) * 943 ctrlr->hmb_nchunks, M_NVME, M_WAITOK); 944 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 945 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 946 ctrlr->hmb_chunk, 1, ctrlr->hmb_chunk, 0, NULL, NULL, &ctrlr->hmb_tag); 947 if (err != 0) { 948 nvme_printf(ctrlr, "HMB tag create failed %d\n", err); 949 nvme_ctrlr_hmb_free(ctrlr); 950 return; 951 } 952 953 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 954 hmbc = &ctrlr->hmb_chunks[i]; 955 if (bus_dmamem_alloc(ctrlr->hmb_tag, 956 (void **)&hmbc->hmbc_vaddr, BUS_DMA_NOWAIT, 957 &hmbc->hmbc_map)) { 958 nvme_printf(ctrlr, "failed to alloc HMB\n"); 959 break; 960 } 961 if (bus_dmamap_load(ctrlr->hmb_tag, hmbc->hmbc_map, 962 hmbc->hmbc_vaddr, ctrlr->hmb_chunk, nvme_single_map, 963 &hmbc->hmbc_paddr, BUS_DMA_NOWAIT) != 0) { 964 bus_dmamem_free(ctrlr->hmb_tag, hmbc->hmbc_vaddr, 965 hmbc->hmbc_map); 966 nvme_printf(ctrlr, "failed to load HMB\n"); 967 break; 968 } 969 bus_dmamap_sync(ctrlr->hmb_tag, hmbc->hmbc_map, 970 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 971 } 972 973 if (i < ctrlr->hmb_nchunks && i * ctrlr->hmb_chunk < min && 974 ctrlr->hmb_chunk / 2 >= minc) { 975 ctrlr->hmb_nchunks = i; 976 nvme_ctrlr_hmb_free(ctrlr); 977 ctrlr->hmb_chunk /= 2; 978 goto again; 979 } 980 ctrlr->hmb_nchunks = i; 981 if (ctrlr->hmb_nchunks * ctrlr->hmb_chunk < min) { 982 nvme_ctrlr_hmb_free(ctrlr); 983 return; 984 } 985 986 size = sizeof(struct nvme_hmb_desc) * ctrlr->hmb_nchunks; 987 err = bus_dma_tag_create(bus_get_dma_tag(ctrlr->dev), 988 16, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 989 size, 1, size, 0, NULL, NULL, &ctrlr->hmb_desc_tag); 990 if (err != 0) { 991 nvme_printf(ctrlr, "HMB desc tag create failed %d\n", err); 992 nvme_ctrlr_hmb_free(ctrlr); 993 return; 994 } 995 if (bus_dmamem_alloc(ctrlr->hmb_desc_tag, 996 (void **)&ctrlr->hmb_desc_vaddr, BUS_DMA_WAITOK, 997 &ctrlr->hmb_desc_map)) { 998 nvme_printf(ctrlr, "failed to alloc HMB desc\n"); 999 nvme_ctrlr_hmb_free(ctrlr); 1000 return; 1001 } 1002 if (bus_dmamap_load(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map, 1003 ctrlr->hmb_desc_vaddr, size, nvme_single_map, 1004 &ctrlr->hmb_desc_paddr, BUS_DMA_NOWAIT) != 0) { 1005 bus_dmamem_free(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_vaddr, 1006 ctrlr->hmb_desc_map); 1007 nvme_printf(ctrlr, "failed to load HMB desc\n"); 1008 nvme_ctrlr_hmb_free(ctrlr); 1009 return; 1010 } 1011 1012 for (i = 0; i < ctrlr->hmb_nchunks; i++) { 1013 ctrlr->hmb_desc_vaddr[i].addr = 1014 htole64(ctrlr->hmb_chunks[i].hmbc_paddr); 1015 ctrlr->hmb_desc_vaddr[i].size = htole32(ctrlr->hmb_chunk / 4096); 1016 } 1017 bus_dmamap_sync(ctrlr->hmb_desc_tag, ctrlr->hmb_desc_map, 1018 BUS_DMASYNC_PREWRITE); 1019 1020 nvme_printf(ctrlr, "Allocated %lluMB host memory buffer\n", 1021 (long long unsigned)ctrlr->hmb_nchunks * ctrlr->hmb_chunk 1022 / 1024 / 1024); 1023 } 1024 1025 static void 1026 nvme_ctrlr_hmb_enable(struct nvme_controller *ctrlr, bool enable, bool memret) 1027 { 1028 struct nvme_completion_poll_status status; 1029 uint32_t cdw11; 1030 1031 cdw11 = 0; 1032 if (enable) 1033 cdw11 |= 1; 1034 if (memret) 1035 cdw11 |= 2; 1036 status.done = 0; 1037 nvme_ctrlr_cmd_set_feature(ctrlr, NVME_FEAT_HOST_MEMORY_BUFFER, cdw11, 1038 ctrlr->hmb_nchunks * ctrlr->hmb_chunk / 4096, ctrlr->hmb_desc_paddr, 1039 ctrlr->hmb_desc_paddr >> 32, ctrlr->hmb_nchunks, NULL, 0, 1040 nvme_completion_poll_cb, &status); 1041 nvme_completion_poll(&status); 1042 if (nvme_completion_is_error(&status.cpl)) 1043 nvme_printf(ctrlr, "nvme_ctrlr_hmb_enable failed!\n"); 1044 } 1045 1046 static void 1047 nvme_ctrlr_start(void *ctrlr_arg, bool resetting) 1048 { 1049 struct nvme_controller *ctrlr = ctrlr_arg; 1050 uint32_t old_num_io_queues; 1051 int i; 1052 1053 TSENTER(); 1054 1055 /* 1056 * Only reset adminq here when we are restarting the 1057 * controller after a reset. During initialization, 1058 * we have already submitted admin commands to get 1059 * the number of I/O queues supported, so cannot reset 1060 * the adminq again here. 1061 */ 1062 if (resetting) { 1063 nvme_qpair_reset(&ctrlr->adminq); 1064 nvme_admin_qpair_enable(&ctrlr->adminq); 1065 } 1066 1067 if (ctrlr->ioq != NULL) { 1068 for (i = 0; i < ctrlr->num_io_queues; i++) 1069 nvme_qpair_reset(&ctrlr->ioq[i]); 1070 } 1071 1072 /* 1073 * If it was a reset on initialization command timeout, just 1074 * return here, letting initialization code fail gracefully. 1075 */ 1076 if (resetting && !ctrlr->is_initialized) 1077 return; 1078 1079 if (resetting && nvme_ctrlr_identify(ctrlr) != 0) { 1080 nvme_ctrlr_fail(ctrlr); 1081 return; 1082 } 1083 1084 /* 1085 * The number of qpairs are determined during controller initialization, 1086 * including using NVMe SET_FEATURES/NUMBER_OF_QUEUES to determine the 1087 * HW limit. We call SET_FEATURES again here so that it gets called 1088 * after any reset for controllers that depend on the driver to 1089 * explicit specify how many queues it will use. This value should 1090 * never change between resets, so panic if somehow that does happen. 1091 */ 1092 if (resetting) { 1093 old_num_io_queues = ctrlr->num_io_queues; 1094 if (nvme_ctrlr_set_num_qpairs(ctrlr) != 0) { 1095 nvme_ctrlr_fail(ctrlr); 1096 return; 1097 } 1098 1099 if (old_num_io_queues != ctrlr->num_io_queues) { 1100 panic("num_io_queues changed from %u to %u", 1101 old_num_io_queues, ctrlr->num_io_queues); 1102 } 1103 } 1104 1105 if (ctrlr->cdata.hmpre > 0 && ctrlr->hmb_nchunks == 0) { 1106 nvme_ctrlr_hmb_alloc(ctrlr); 1107 if (ctrlr->hmb_nchunks > 0) 1108 nvme_ctrlr_hmb_enable(ctrlr, true, false); 1109 } else if (ctrlr->hmb_nchunks > 0) 1110 nvme_ctrlr_hmb_enable(ctrlr, true, true); 1111 1112 if (nvme_ctrlr_create_qpairs(ctrlr) != 0) { 1113 nvme_ctrlr_fail(ctrlr); 1114 return; 1115 } 1116 1117 if (nvme_ctrlr_construct_namespaces(ctrlr) != 0) { 1118 nvme_ctrlr_fail(ctrlr); 1119 return; 1120 } 1121 1122 nvme_ctrlr_configure_aer(ctrlr); 1123 nvme_ctrlr_configure_int_coalescing(ctrlr); 1124 1125 for (i = 0; i < ctrlr->num_io_queues; i++) 1126 nvme_io_qpair_enable(&ctrlr->ioq[i]); 1127 TSEXIT(); 1128 } 1129 1130 void 1131 nvme_ctrlr_start_config_hook(void *arg) 1132 { 1133 struct nvme_controller *ctrlr = arg; 1134 1135 TSENTER(); 1136 1137 /* 1138 * Reset controller twice to ensure we do a transition from cc.en==1 to 1139 * cc.en==0. This is because we don't really know what status the 1140 * controller was left in when boot handed off to OS. Linux doesn't do 1141 * this, however. If we adopt that policy, see also nvme_ctrlr_resume(). 1142 */ 1143 if (nvme_ctrlr_hw_reset(ctrlr) != 0) { 1144 fail: 1145 nvme_ctrlr_fail(ctrlr); 1146 config_intrhook_disestablish(&ctrlr->config_hook); 1147 return; 1148 } 1149 1150 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1151 goto fail; 1152 1153 nvme_qpair_reset(&ctrlr->adminq); 1154 nvme_admin_qpair_enable(&ctrlr->adminq); 1155 1156 if (nvme_ctrlr_identify(ctrlr) == 0 && 1157 nvme_ctrlr_set_num_qpairs(ctrlr) == 0 && 1158 nvme_ctrlr_construct_io_qpairs(ctrlr) == 0) 1159 nvme_ctrlr_start(ctrlr, false); 1160 else 1161 goto fail; 1162 1163 nvme_sysctl_initialize_ctrlr(ctrlr); 1164 config_intrhook_disestablish(&ctrlr->config_hook); 1165 1166 ctrlr->is_initialized = 1; 1167 nvme_notify_new_controller(ctrlr); 1168 TSEXIT(); 1169 } 1170 1171 static void 1172 nvme_ctrlr_reset_task(void *arg, int pending) 1173 { 1174 struct nvme_controller *ctrlr = arg; 1175 int status; 1176 1177 nvme_ctrlr_devctl_log(ctrlr, "RESET", "resetting controller"); 1178 status = nvme_ctrlr_hw_reset(ctrlr); 1179 /* 1180 * Use pause instead of DELAY, so that we yield to any nvme interrupt 1181 * handlers on this CPU that were blocked on a qpair lock. We want 1182 * all nvme interrupts completed before proceeding with restarting the 1183 * controller. 1184 * 1185 * XXX - any way to guarantee the interrupt handlers have quiesced? 1186 */ 1187 pause("nvmereset", hz / 10); 1188 if (status == 0) 1189 nvme_ctrlr_start(ctrlr, true); 1190 else 1191 nvme_ctrlr_fail(ctrlr); 1192 1193 atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1194 } 1195 1196 /* 1197 * Poll all the queues enabled on the device for completion. 1198 */ 1199 void 1200 nvme_ctrlr_poll(struct nvme_controller *ctrlr) 1201 { 1202 int i; 1203 1204 nvme_qpair_process_completions(&ctrlr->adminq); 1205 1206 for (i = 0; i < ctrlr->num_io_queues; i++) 1207 if (ctrlr->ioq && ctrlr->ioq[i].cpl) 1208 nvme_qpair_process_completions(&ctrlr->ioq[i]); 1209 } 1210 1211 /* 1212 * Poll the single-vector interrupt case: num_io_queues will be 1 and 1213 * there's only a single vector. While we're polling, we mask further 1214 * interrupts in the controller. 1215 */ 1216 void 1217 nvme_ctrlr_shared_handler(void *arg) 1218 { 1219 struct nvme_controller *ctrlr = arg; 1220 1221 nvme_mmio_write_4(ctrlr, intms, 1); 1222 nvme_ctrlr_poll(ctrlr); 1223 nvme_mmio_write_4(ctrlr, intmc, 1); 1224 } 1225 1226 static void 1227 nvme_pt_done(void *arg, const struct nvme_completion *cpl) 1228 { 1229 struct nvme_pt_command *pt = arg; 1230 struct mtx *mtx = pt->driver_lock; 1231 uint16_t status; 1232 1233 bzero(&pt->cpl, sizeof(pt->cpl)); 1234 pt->cpl.cdw0 = cpl->cdw0; 1235 1236 status = cpl->status; 1237 status &= ~NVME_STATUS_P_MASK; 1238 pt->cpl.status = status; 1239 1240 mtx_lock(mtx); 1241 pt->driver_lock = NULL; 1242 wakeup(pt); 1243 mtx_unlock(mtx); 1244 } 1245 1246 int 1247 nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1248 struct nvme_pt_command *pt, uint32_t nsid, int is_user_buffer, 1249 int is_admin_cmd) 1250 { 1251 struct nvme_request *req; 1252 struct mtx *mtx; 1253 struct buf *buf = NULL; 1254 int ret = 0; 1255 1256 if (pt->len > 0) { 1257 if (pt->len > ctrlr->max_xfer_size) { 1258 nvme_printf(ctrlr, "pt->len (%d) " 1259 "exceeds max_xfer_size (%d)\n", pt->len, 1260 ctrlr->max_xfer_size); 1261 return EIO; 1262 } 1263 if (is_user_buffer) { 1264 /* 1265 * Ensure the user buffer is wired for the duration of 1266 * this pass-through command. 1267 */ 1268 PHOLD(curproc); 1269 buf = uma_zalloc(pbuf_zone, M_WAITOK); 1270 buf->b_iocmd = pt->is_read ? BIO_READ : BIO_WRITE; 1271 if (vmapbuf(buf, pt->buf, pt->len, 1) < 0) { 1272 ret = EFAULT; 1273 goto err; 1274 } 1275 req = nvme_allocate_request_vaddr(buf->b_data, pt->len, 1276 nvme_pt_done, pt); 1277 } else 1278 req = nvme_allocate_request_vaddr(pt->buf, pt->len, 1279 nvme_pt_done, pt); 1280 } else 1281 req = nvme_allocate_request_null(nvme_pt_done, pt); 1282 1283 /* Assume user space already converted to little-endian */ 1284 req->cmd.opc = pt->cmd.opc; 1285 req->cmd.fuse = pt->cmd.fuse; 1286 req->cmd.rsvd2 = pt->cmd.rsvd2; 1287 req->cmd.rsvd3 = pt->cmd.rsvd3; 1288 req->cmd.cdw10 = pt->cmd.cdw10; 1289 req->cmd.cdw11 = pt->cmd.cdw11; 1290 req->cmd.cdw12 = pt->cmd.cdw12; 1291 req->cmd.cdw13 = pt->cmd.cdw13; 1292 req->cmd.cdw14 = pt->cmd.cdw14; 1293 req->cmd.cdw15 = pt->cmd.cdw15; 1294 1295 req->cmd.nsid = htole32(nsid); 1296 1297 mtx = mtx_pool_find(mtxpool_sleep, pt); 1298 pt->driver_lock = mtx; 1299 1300 if (is_admin_cmd) 1301 nvme_ctrlr_submit_admin_request(ctrlr, req); 1302 else 1303 nvme_ctrlr_submit_io_request(ctrlr, req); 1304 1305 mtx_lock(mtx); 1306 while (pt->driver_lock != NULL) 1307 mtx_sleep(pt, mtx, PRIBIO, "nvme_pt", 0); 1308 mtx_unlock(mtx); 1309 1310 err: 1311 if (buf != NULL) { 1312 uma_zfree(pbuf_zone, buf); 1313 PRELE(curproc); 1314 } 1315 1316 return (ret); 1317 } 1318 1319 static int 1320 nvme_ctrlr_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int flag, 1321 struct thread *td) 1322 { 1323 struct nvme_controller *ctrlr; 1324 struct nvme_pt_command *pt; 1325 1326 ctrlr = cdev->si_drv1; 1327 1328 switch (cmd) { 1329 case NVME_RESET_CONTROLLER: 1330 nvme_ctrlr_reset(ctrlr); 1331 break; 1332 case NVME_PASSTHROUGH_CMD: 1333 pt = (struct nvme_pt_command *)arg; 1334 return (nvme_ctrlr_passthrough_cmd(ctrlr, pt, le32toh(pt->cmd.nsid), 1335 1 /* is_user_buffer */, 1 /* is_admin_cmd */)); 1336 case NVME_GET_NSID: 1337 { 1338 struct nvme_get_nsid *gnsid = (struct nvme_get_nsid *)arg; 1339 strncpy(gnsid->cdev, device_get_nameunit(ctrlr->dev), 1340 sizeof(gnsid->cdev)); 1341 gnsid->cdev[sizeof(gnsid->cdev) - 1] = '\0'; 1342 gnsid->nsid = 0; 1343 break; 1344 } 1345 case NVME_GET_MAX_XFER_SIZE: 1346 *(uint64_t *)arg = ctrlr->max_xfer_size; 1347 break; 1348 default: 1349 return (ENOTTY); 1350 } 1351 1352 return (0); 1353 } 1354 1355 static struct cdevsw nvme_ctrlr_cdevsw = { 1356 .d_version = D_VERSION, 1357 .d_flags = 0, 1358 .d_ioctl = nvme_ctrlr_ioctl 1359 }; 1360 1361 int 1362 nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev) 1363 { 1364 struct make_dev_args md_args; 1365 uint32_t cap_lo; 1366 uint32_t cap_hi; 1367 uint32_t to, vs, pmrcap; 1368 uint8_t mpsmin; 1369 int status, timeout_period; 1370 1371 ctrlr->dev = dev; 1372 1373 mtx_init(&ctrlr->lock, "nvme ctrlr lock", NULL, MTX_DEF); 1374 if (bus_get_domain(dev, &ctrlr->domain) != 0) 1375 ctrlr->domain = 0; 1376 1377 cap_lo = nvme_mmio_read_4(ctrlr, cap_lo); 1378 if (bootverbose) { 1379 device_printf(dev, "CapLo: 0x%08x: MQES %u%s%s%s%s, TO %u\n", 1380 cap_lo, NVME_CAP_LO_MQES(cap_lo), 1381 NVME_CAP_LO_CQR(cap_lo) ? ", CQR" : "", 1382 NVME_CAP_LO_AMS(cap_lo) ? ", AMS" : "", 1383 (NVME_CAP_LO_AMS(cap_lo) & 0x1) ? " WRRwUPC" : "", 1384 (NVME_CAP_LO_AMS(cap_lo) & 0x2) ? " VS" : "", 1385 NVME_CAP_LO_TO(cap_lo)); 1386 } 1387 cap_hi = nvme_mmio_read_4(ctrlr, cap_hi); 1388 if (bootverbose) { 1389 device_printf(dev, "CapHi: 0x%08x: DSTRD %u%s, CSS %x%s, " 1390 "MPSMIN %u, MPSMAX %u%s%s\n", cap_hi, 1391 NVME_CAP_HI_DSTRD(cap_hi), 1392 NVME_CAP_HI_NSSRS(cap_hi) ? ", NSSRS" : "", 1393 NVME_CAP_HI_CSS(cap_hi), 1394 NVME_CAP_HI_BPS(cap_hi) ? ", BPS" : "", 1395 NVME_CAP_HI_MPSMIN(cap_hi), 1396 NVME_CAP_HI_MPSMAX(cap_hi), 1397 NVME_CAP_HI_PMRS(cap_hi) ? ", PMRS" : "", 1398 NVME_CAP_HI_CMBS(cap_hi) ? ", CMBS" : ""); 1399 } 1400 if (bootverbose) { 1401 vs = nvme_mmio_read_4(ctrlr, vs); 1402 device_printf(dev, "Version: 0x%08x: %d.%d\n", vs, 1403 NVME_MAJOR(vs), NVME_MINOR(vs)); 1404 } 1405 if (bootverbose && NVME_CAP_HI_PMRS(cap_hi)) { 1406 pmrcap = nvme_mmio_read_4(ctrlr, pmrcap); 1407 device_printf(dev, "PMRCap: 0x%08x: BIR %u%s%s, PMRTU %u, " 1408 "PMRWBM %x, PMRTO %u%s\n", pmrcap, 1409 NVME_PMRCAP_BIR(pmrcap), 1410 NVME_PMRCAP_RDS(pmrcap) ? ", RDS" : "", 1411 NVME_PMRCAP_WDS(pmrcap) ? ", WDS" : "", 1412 NVME_PMRCAP_PMRTU(pmrcap), 1413 NVME_PMRCAP_PMRWBM(pmrcap), 1414 NVME_PMRCAP_PMRTO(pmrcap), 1415 NVME_PMRCAP_CMSS(pmrcap) ? ", CMSS" : ""); 1416 } 1417 1418 ctrlr->dstrd = NVME_CAP_HI_DSTRD(cap_hi) + 2; 1419 1420 mpsmin = NVME_CAP_HI_MPSMIN(cap_hi); 1421 ctrlr->min_page_size = 1 << (12 + mpsmin); 1422 1423 /* Get ready timeout value from controller, in units of 500ms. */ 1424 to = NVME_CAP_LO_TO(cap_lo) + 1; 1425 ctrlr->ready_timeout_in_ms = to * 500; 1426 1427 timeout_period = NVME_DEFAULT_TIMEOUT_PERIOD; 1428 TUNABLE_INT_FETCH("hw.nvme.timeout_period", &timeout_period); 1429 timeout_period = min(timeout_period, NVME_MAX_TIMEOUT_PERIOD); 1430 timeout_period = max(timeout_period, NVME_MIN_TIMEOUT_PERIOD); 1431 ctrlr->timeout_period = timeout_period; 1432 1433 nvme_retry_count = NVME_DEFAULT_RETRY_COUNT; 1434 TUNABLE_INT_FETCH("hw.nvme.retry_count", &nvme_retry_count); 1435 1436 ctrlr->enable_aborts = 0; 1437 TUNABLE_INT_FETCH("hw.nvme.enable_aborts", &ctrlr->enable_aborts); 1438 1439 ctrlr->max_xfer_size = NVME_MAX_XFER_SIZE; 1440 if (nvme_ctrlr_construct_admin_qpair(ctrlr) != 0) 1441 return (ENXIO); 1442 1443 /* 1444 * Create 2 threads for the taskqueue. The reset thread will block when 1445 * it detects that the controller has failed until all I/O has been 1446 * failed up the stack. The fail_req task needs to be able to run in 1447 * this case to finish the request failure for some cases. 1448 * 1449 * We could partially solve this race by draining the failed requeust 1450 * queue before proceding to free the sim, though nothing would stop 1451 * new I/O from coming in after we do that drain, but before we reach 1452 * cam_sim_free, so this big hammer is used instead. 1453 */ 1454 ctrlr->taskqueue = taskqueue_create("nvme_taskq", M_WAITOK, 1455 taskqueue_thread_enqueue, &ctrlr->taskqueue); 1456 taskqueue_start_threads(&ctrlr->taskqueue, 2, PI_DISK, "nvme taskq"); 1457 1458 ctrlr->is_resetting = 0; 1459 ctrlr->is_initialized = 0; 1460 ctrlr->notification_sent = 0; 1461 TASK_INIT(&ctrlr->reset_task, 0, nvme_ctrlr_reset_task, ctrlr); 1462 TASK_INIT(&ctrlr->fail_req_task, 0, nvme_ctrlr_fail_req_task, ctrlr); 1463 STAILQ_INIT(&ctrlr->fail_req); 1464 ctrlr->is_failed = false; 1465 1466 make_dev_args_init(&md_args); 1467 md_args.mda_devsw = &nvme_ctrlr_cdevsw; 1468 md_args.mda_uid = UID_ROOT; 1469 md_args.mda_gid = GID_WHEEL; 1470 md_args.mda_mode = 0600; 1471 md_args.mda_unit = device_get_unit(dev); 1472 md_args.mda_si_drv1 = (void *)ctrlr; 1473 status = make_dev_s(&md_args, &ctrlr->cdev, "nvme%d", 1474 device_get_unit(dev)); 1475 if (status != 0) 1476 return (ENXIO); 1477 1478 return (0); 1479 } 1480 1481 void 1482 nvme_ctrlr_destruct(struct nvme_controller *ctrlr, device_t dev) 1483 { 1484 int gone, i; 1485 1486 ctrlr->is_dying = true; 1487 1488 if (ctrlr->resource == NULL) 1489 goto nores; 1490 if (!mtx_initialized(&ctrlr->adminq.lock)) 1491 goto noadminq; 1492 1493 /* 1494 * Check whether it is a hot unplug or a clean driver detach. 1495 * If device is not there any more, skip any shutdown commands. 1496 */ 1497 gone = (nvme_mmio_read_4(ctrlr, csts) == NVME_GONE); 1498 if (gone) 1499 nvme_ctrlr_fail(ctrlr); 1500 else 1501 nvme_notify_fail_consumers(ctrlr); 1502 1503 for (i = 0; i < NVME_MAX_NAMESPACES; i++) 1504 nvme_ns_destruct(&ctrlr->ns[i]); 1505 1506 if (ctrlr->cdev) 1507 destroy_dev(ctrlr->cdev); 1508 1509 if (ctrlr->is_initialized) { 1510 if (!gone) { 1511 if (ctrlr->hmb_nchunks > 0) 1512 nvme_ctrlr_hmb_enable(ctrlr, false, false); 1513 nvme_ctrlr_delete_qpairs(ctrlr); 1514 } 1515 nvme_ctrlr_hmb_free(ctrlr); 1516 } 1517 if (ctrlr->ioq != NULL) { 1518 for (i = 0; i < ctrlr->num_io_queues; i++) 1519 nvme_io_qpair_destroy(&ctrlr->ioq[i]); 1520 free(ctrlr->ioq, M_NVME); 1521 } 1522 nvme_admin_qpair_destroy(&ctrlr->adminq); 1523 1524 /* 1525 * Notify the controller of a shutdown, even though this is due to 1526 * a driver unload, not a system shutdown (this path is not invoked 1527 * during shutdown). This ensures the controller receives a 1528 * shutdown notification in case the system is shutdown before 1529 * reloading the driver. 1530 */ 1531 if (!gone) 1532 nvme_ctrlr_shutdown(ctrlr); 1533 1534 if (!gone) 1535 nvme_ctrlr_disable(ctrlr); 1536 1537 noadminq: 1538 if (ctrlr->taskqueue) 1539 taskqueue_free(ctrlr->taskqueue); 1540 1541 if (ctrlr->tag) 1542 bus_teardown_intr(ctrlr->dev, ctrlr->res, ctrlr->tag); 1543 1544 if (ctrlr->res) 1545 bus_release_resource(ctrlr->dev, SYS_RES_IRQ, 1546 rman_get_rid(ctrlr->res), ctrlr->res); 1547 1548 if (ctrlr->bar4_resource != NULL) { 1549 bus_release_resource(dev, SYS_RES_MEMORY, 1550 ctrlr->bar4_resource_id, ctrlr->bar4_resource); 1551 } 1552 1553 bus_release_resource(dev, SYS_RES_MEMORY, 1554 ctrlr->resource_id, ctrlr->resource); 1555 1556 nores: 1557 mtx_destroy(&ctrlr->lock); 1558 } 1559 1560 void 1561 nvme_ctrlr_shutdown(struct nvme_controller *ctrlr) 1562 { 1563 uint32_t cc; 1564 uint32_t csts; 1565 int timeout; 1566 1567 cc = nvme_mmio_read_4(ctrlr, cc); 1568 cc &= ~(NVME_CC_REG_SHN_MASK << NVME_CC_REG_SHN_SHIFT); 1569 cc |= NVME_SHN_NORMAL << NVME_CC_REG_SHN_SHIFT; 1570 nvme_mmio_write_4(ctrlr, cc, cc); 1571 1572 timeout = ticks + (ctrlr->cdata.rtd3e == 0 ? 5 * hz : 1573 ((uint64_t)ctrlr->cdata.rtd3e * hz + 999999) / 1000000); 1574 while (1) { 1575 csts = nvme_mmio_read_4(ctrlr, csts); 1576 if (csts == NVME_GONE) /* Hot unplug. */ 1577 break; 1578 if (NVME_CSTS_GET_SHST(csts) == NVME_SHST_COMPLETE) 1579 break; 1580 if (timeout - ticks < 0) { 1581 nvme_printf(ctrlr, "shutdown timeout\n"); 1582 break; 1583 } 1584 pause("nvmeshut", 1); 1585 } 1586 } 1587 1588 void 1589 nvme_ctrlr_submit_admin_request(struct nvme_controller *ctrlr, 1590 struct nvme_request *req) 1591 { 1592 1593 nvme_qpair_submit_request(&ctrlr->adminq, req); 1594 } 1595 1596 void 1597 nvme_ctrlr_submit_io_request(struct nvme_controller *ctrlr, 1598 struct nvme_request *req) 1599 { 1600 struct nvme_qpair *qpair; 1601 1602 qpair = &ctrlr->ioq[QP(ctrlr, curcpu)]; 1603 nvme_qpair_submit_request(qpair, req); 1604 } 1605 1606 device_t 1607 nvme_ctrlr_get_device(struct nvme_controller *ctrlr) 1608 { 1609 1610 return (ctrlr->dev); 1611 } 1612 1613 const struct nvme_controller_data * 1614 nvme_ctrlr_get_data(struct nvme_controller *ctrlr) 1615 { 1616 1617 return (&ctrlr->cdata); 1618 } 1619 1620 int 1621 nvme_ctrlr_suspend(struct nvme_controller *ctrlr) 1622 { 1623 int to = hz; 1624 1625 /* 1626 * Can't touch failed controllers, so it's already suspended. 1627 */ 1628 if (ctrlr->is_failed) 1629 return (0); 1630 1631 /* 1632 * We don't want the reset taskqueue running, since it does similar 1633 * things, so prevent it from running after we start. Wait for any reset 1634 * that may have been started to complete. The reset process we follow 1635 * will ensure that any new I/O will queue and be given to the hardware 1636 * after we resume (though there should be none). 1637 */ 1638 while (atomic_cmpset_32(&ctrlr->is_resetting, 0, 1) == 0 && to-- > 0) 1639 pause("nvmesusp", 1); 1640 if (to <= 0) { 1641 nvme_printf(ctrlr, 1642 "Competing reset task didn't finish. Try again later.\n"); 1643 return (EWOULDBLOCK); 1644 } 1645 1646 if (ctrlr->hmb_nchunks > 0) 1647 nvme_ctrlr_hmb_enable(ctrlr, false, false); 1648 1649 /* 1650 * Per Section 7.6.2 of NVMe spec 1.4, to properly suspend, we need to 1651 * delete the hardware I/O queues, and then shutdown. This properly 1652 * flushes any metadata the drive may have stored so it can survive 1653 * having its power removed and prevents the unsafe shutdown count from 1654 * incriminating. Once we delete the qpairs, we have to disable them 1655 * before shutting down. The delay is out of paranoia in 1656 * nvme_ctrlr_hw_reset, and is repeated here (though we should have no 1657 * pending I/O that the delay copes with). 1658 */ 1659 nvme_ctrlr_delete_qpairs(ctrlr); 1660 nvme_ctrlr_disable_qpairs(ctrlr); 1661 pause("nvmesusp", hz / 10); 1662 nvme_ctrlr_shutdown(ctrlr); 1663 1664 return (0); 1665 } 1666 1667 int 1668 nvme_ctrlr_resume(struct nvme_controller *ctrlr) 1669 { 1670 1671 /* 1672 * Can't touch failed controllers, so nothing to do to resume. 1673 */ 1674 if (ctrlr->is_failed) 1675 return (0); 1676 1677 /* 1678 * Have to reset the hardware twice, just like we do on attach. See 1679 * nmve_attach() for why. 1680 */ 1681 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1682 goto fail; 1683 if (nvme_ctrlr_hw_reset(ctrlr) != 0) 1684 goto fail; 1685 1686 /* 1687 * Now that we've reset the hardware, we can restart the controller. Any 1688 * I/O that was pending is requeued. Any admin commands are aborted with 1689 * an error. Once we've restarted, take the controller out of reset. 1690 */ 1691 nvme_ctrlr_start(ctrlr, true); 1692 (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1693 1694 return (0); 1695 fail: 1696 /* 1697 * Since we can't bring the controller out of reset, announce and fail 1698 * the controller. However, we have to return success for the resume 1699 * itself, due to questionable APIs. 1700 */ 1701 nvme_printf(ctrlr, "Failed to reset on resume, failing.\n"); 1702 nvme_ctrlr_fail(ctrlr); 1703 (void)atomic_cmpset_32(&ctrlr->is_resetting, 1, 0); 1704 return (0); 1705 } 1706