1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __NVME_H__ 30 #define __NVME_H__ 31 32 #ifdef _KERNEL 33 #include <sys/types.h> 34 #endif 35 36 #include <sys/param.h> 37 #include <sys/endian.h> 38 39 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 40 #define NVME_RESET_CONTROLLER _IO('n', 1) 41 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid) 42 #define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t) 43 44 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 45 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 46 47 /* 48 * Macros to deal with NVME revisions, as defined VS register 49 */ 50 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 51 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 52 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 53 54 /* 55 * Use to mark a command to apply to all namespaces, or to retrieve global 56 * log pages. 57 */ 58 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 59 60 /* Host memory buffer sizes are always in 4096 byte chunks */ 61 #define NVME_HMB_UNITS 4096 62 63 /* Many items are expressed in terms of power of two times MPS */ 64 #define NVME_MPS_SHIFT 12 65 66 /* Register field definitions */ 67 #define NVME_CAP_LO_REG_MQES_SHIFT (0) 68 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 69 #define NVME_CAP_LO_REG_CQR_SHIFT (16) 70 #define NVME_CAP_LO_REG_CQR_MASK (0x1) 71 #define NVME_CAP_LO_REG_AMS_SHIFT (17) 72 #define NVME_CAP_LO_REG_AMS_MASK (0x3) 73 #define NVME_CAP_LO_REG_TO_SHIFT (24) 74 #define NVME_CAP_LO_REG_TO_MASK (0xFF) 75 #define NVME_CAP_LO_MQES(x) \ 76 NVMEV(NVME_CAP_LO_REG_MQES, x) 77 #define NVME_CAP_LO_CQR(x) \ 78 NVMEV(NVME_CAP_LO_REG_CQR, x) 79 #define NVME_CAP_LO_AMS(x) \ 80 NVMEV(NVME_CAP_LO_REG_AMS, x) 81 #define NVME_CAP_LO_TO(x) \ 82 NVMEV(NVME_CAP_LO_REG_TO, x) 83 84 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0) 85 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF) 86 #define NVME_CAP_HI_REG_NSSRS_SHIFT (4) 87 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1) 88 #define NVME_CAP_HI_REG_CSS_SHIFT (5) 89 #define NVME_CAP_HI_REG_CSS_MASK (0xff) 90 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5) 91 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1) 92 #define NVME_CAP_HI_REG_BPS_SHIFT (13) 93 #define NVME_CAP_HI_REG_BPS_MASK (0x1) 94 #define NVME_CAP_HI_REG_CPS_SHIFT (14) 95 #define NVME_CAP_HI_REG_CPS_MASK (0x3) 96 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16) 97 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF) 98 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20) 99 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF) 100 #define NVME_CAP_HI_REG_PMRS_SHIFT (24) 101 #define NVME_CAP_HI_REG_PMRS_MASK (0x1) 102 #define NVME_CAP_HI_REG_CMBS_SHIFT (25) 103 #define NVME_CAP_HI_REG_CMBS_MASK (0x1) 104 #define NVME_CAP_HI_REG_NSSS_SHIFT (26) 105 #define NVME_CAP_HI_REG_NSSS_MASK (0x1) 106 #define NVME_CAP_HI_REG_CRWMS_SHIFT (27) 107 #define NVME_CAP_HI_REG_CRWMS_MASK (0x1) 108 #define NVME_CAP_HI_REG_CRIMS_SHIFT (28) 109 #define NVME_CAP_HI_REG_CRIMS_MASK (0x1) 110 #define NVME_CAP_HI_DSTRD(x) \ 111 NVMEV(NVME_CAP_HI_REG_DSTRD, x) 112 #define NVME_CAP_HI_NSSRS(x) \ 113 NVMEV(NVME_CAP_HI_REG_NSSRS, x) 114 #define NVME_CAP_HI_CSS(x) \ 115 NVMEV(NVME_CAP_HI_REG_CSS, x) 116 #define NVME_CAP_HI_CSS_NVM(x) \ 117 NVMEV(NVME_CAP_HI_REG_CSS_NVM, x) 118 #define NVME_CAP_HI_BPS(x) \ 119 NVMEV(NVME_CAP_HI_REG_BPS, x) 120 #define NVME_CAP_HI_CPS(x) \ 121 NVMEV(NVME_CAP_HI_REG_CPS, x) 122 #define NVME_CAP_HI_MPSMIN(x) \ 123 NVMEV(NVME_CAP_HI_REG_MPSMIN, x) 124 #define NVME_CAP_HI_MPSMAX(x) \ 125 NVMEV(NVME_CAP_HI_REG_MPSMAX, x) 126 #define NVME_CAP_HI_PMRS(x) \ 127 NVMEV(NVME_CAP_HI_REG_PMRS, x) 128 #define NVME_CAP_HI_CMBS(x) \ 129 NVMEV(NVME_CAP_HI_REG_CMBS, x) 130 #define NVME_CAP_HI_NSSS(x) \ 131 NVMEV(NVME_CAP_HI_REG_NSSS, x) 132 #define NVME_CAP_HI_CRWMS(x) \ 133 NVMEV(NVME_CAP_HI_REG_CRWMS, x) 134 #define NVME_CAP_HI_CRIMS(x) \ 135 NVMEV(NVME_CAP_HI_REG_CRIMS, x) 136 137 #define NVME_CC_REG_EN_SHIFT (0) 138 #define NVME_CC_REG_EN_MASK (0x1) 139 #define NVME_CC_REG_CSS_SHIFT (4) 140 #define NVME_CC_REG_CSS_MASK (0x7) 141 #define NVME_CC_REG_MPS_SHIFT (7) 142 #define NVME_CC_REG_MPS_MASK (0xF) 143 #define NVME_CC_REG_AMS_SHIFT (11) 144 #define NVME_CC_REG_AMS_MASK (0x7) 145 #define NVME_CC_REG_SHN_SHIFT (14) 146 #define NVME_CC_REG_SHN_MASK (0x3) 147 #define NVME_CC_REG_IOSQES_SHIFT (16) 148 #define NVME_CC_REG_IOSQES_MASK (0xF) 149 #define NVME_CC_REG_IOCQES_SHIFT (20) 150 #define NVME_CC_REG_IOCQES_MASK (0xF) 151 #define NVME_CC_REG_CRIME_SHIFT (24) 152 #define NVME_CC_REG_CRIME_MASK (0x1) 153 154 #define NVME_CSTS_REG_RDY_SHIFT (0) 155 #define NVME_CSTS_REG_RDY_MASK (0x1) 156 #define NVME_CSTS_REG_CFS_SHIFT (1) 157 #define NVME_CSTS_REG_CFS_MASK (0x1) 158 #define NVME_CSTS_REG_SHST_SHIFT (2) 159 #define NVME_CSTS_REG_SHST_MASK (0x3) 160 #define NVME_CSTS_REG_NVSRO_SHIFT (4) 161 #define NVME_CSTS_REG_NVSRO_MASK (0x1) 162 #define NVME_CSTS_REG_PP_SHIFT (5) 163 #define NVME_CSTS_REG_PP_MASK (0x1) 164 #define NVME_CSTS_REG_ST_SHIFT (6) 165 #define NVME_CSTS_REG_ST_MASK (0x1) 166 167 #define NVME_CSTS_GET_SHST(csts) \ 168 NVMEV(NVME_CSTS_REG_SHST, csts) 169 170 #define NVME_AQA_REG_ASQS_SHIFT (0) 171 #define NVME_AQA_REG_ASQS_MASK (0xFFF) 172 #define NVME_AQA_REG_ACQS_SHIFT (16) 173 #define NVME_AQA_REG_ACQS_MASK (0xFFF) 174 175 #define NVME_PMRCAP_REG_RDS_SHIFT (3) 176 #define NVME_PMRCAP_REG_RDS_MASK (0x1) 177 #define NVME_PMRCAP_REG_WDS_SHIFT (4) 178 #define NVME_PMRCAP_REG_WDS_MASK (0x1) 179 #define NVME_PMRCAP_REG_BIR_SHIFT (5) 180 #define NVME_PMRCAP_REG_BIR_MASK (0x7) 181 #define NVME_PMRCAP_REG_PMRTU_SHIFT (8) 182 #define NVME_PMRCAP_REG_PMRTU_MASK (0x3) 183 #define NVME_PMRCAP_REG_PMRWBM_SHIFT (10) 184 #define NVME_PMRCAP_REG_PMRWBM_MASK (0xf) 185 #define NVME_PMRCAP_REG_PMRTO_SHIFT (16) 186 #define NVME_PMRCAP_REG_PMRTO_MASK (0xff) 187 #define NVME_PMRCAP_REG_CMSS_SHIFT (24) 188 #define NVME_PMRCAP_REG_CMSS_MASK (0x1) 189 190 #define NVME_PMRCAP_RDS(x) \ 191 NVMEV(NVME_PMRCAP_REG_RDS, x) 192 #define NVME_PMRCAP_WDS(x) \ 193 NVMEV(NVME_PMRCAP_REG_WDS, x) 194 #define NVME_PMRCAP_BIR(x) \ 195 NVMEV(NVME_PMRCAP_REG_BIR, x) 196 #define NVME_PMRCAP_PMRTU(x) \ 197 NVMEV(NVME_PMRCAP_REG_PMRTU, x) 198 #define NVME_PMRCAP_PMRWBM(x) \ 199 NVMEV(NVME_PMRCAP_REG_PMRWBM, x) 200 #define NVME_PMRCAP_PMRTO(x) \ 201 NVMEV(NVME_PMRCAP_REG_PMRTO, x) 202 #define NVME_PMRCAP_CMSS(x) \ 203 NVMEV(NVME_PMRCAP_REG_CMSS, x) 204 205 /* Command field definitions */ 206 207 #define NVME_CMD_FUSE_SHIFT (8) 208 #define NVME_CMD_FUSE_MASK (0x3) 209 210 #define NVME_STATUS_P_SHIFT (0) 211 #define NVME_STATUS_P_MASK (0x1) 212 #define NVME_STATUS_SC_SHIFT (1) 213 #define NVME_STATUS_SC_MASK (0xFF) 214 #define NVME_STATUS_SCT_SHIFT (9) 215 #define NVME_STATUS_SCT_MASK (0x7) 216 #define NVME_STATUS_CRD_SHIFT (12) 217 #define NVME_STATUS_CRD_MASK (0x3) 218 #define NVME_STATUS_M_SHIFT (14) 219 #define NVME_STATUS_M_MASK (0x1) 220 #define NVME_STATUS_DNR_SHIFT (15) 221 #define NVME_STATUS_DNR_MASK (0x1) 222 223 #define NVME_STATUS_GET_P(st) \ 224 NVMEV(NVME_STATUS_P, st) 225 #define NVME_STATUS_GET_SC(st) \ 226 NVMEV(NVME_STATUS_SC, st) 227 #define NVME_STATUS_GET_SCT(st) \ 228 NVMEV(NVME_STATUS_SCT, st) 229 #define NVME_STATUS_GET_CRD(st) \ 230 NVMEV(NVME_STATUS_CRD, st) 231 #define NVME_STATUS_GET_M(st) \ 232 NVMEV(NVME_STATUS_M, st) 233 #define NVME_STATUS_GET_DNR(st) \ 234 NVMEV(NVME_STATUS_DNR, st) 235 236 #define NVME_PWR_ST_MPS_SHIFT (0) 237 #define NVME_PWR_ST_MPS_MASK (0x1) 238 #define NVME_PWR_ST_NOPS_SHIFT (1) 239 #define NVME_PWR_ST_NOPS_MASK (0x1) 240 #define NVME_PWR_ST_RRT_SHIFT (0) 241 #define NVME_PWR_ST_RRT_MASK (0x1F) 242 #define NVME_PWR_ST_RRL_SHIFT (0) 243 #define NVME_PWR_ST_RRL_MASK (0x1F) 244 #define NVME_PWR_ST_RWT_SHIFT (0) 245 #define NVME_PWR_ST_RWT_MASK (0x1F) 246 #define NVME_PWR_ST_RWL_SHIFT (0) 247 #define NVME_PWR_ST_RWL_MASK (0x1F) 248 #define NVME_PWR_ST_IPS_SHIFT (6) 249 #define NVME_PWR_ST_IPS_MASK (0x3) 250 #define NVME_PWR_ST_APW_SHIFT (0) 251 #define NVME_PWR_ST_APW_MASK (0x7) 252 #define NVME_PWR_ST_APS_SHIFT (6) 253 #define NVME_PWR_ST_APS_MASK (0x3) 254 255 /** Controller Multi-path I/O and Namespace Sharing Capabilities */ 256 /* More then one port */ 257 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0) 258 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1) 259 /* More then one controller */ 260 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1) 261 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1) 262 /* SR-IOV Virtual Function */ 263 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2) 264 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1) 265 /* Asymmetric Namespace Access Reporting */ 266 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3) 267 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1) 268 269 /** OAES - Optional Asynchronous Events Supported */ 270 /* supports Namespace Attribute Notices event */ 271 #define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8) 272 #define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1) 273 /* supports Firmware Activation Notices event */ 274 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9) 275 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1) 276 /* supports Asymmetric Namespace Access Change Notices event */ 277 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11) 278 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1) 279 /* supports Predictable Latency Event Aggregate Log Change Notices event */ 280 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12) 281 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1) 282 /* supports LBA Status Information Notices event */ 283 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13) 284 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1) 285 /* supports Endurance Group Event Aggregate Log Page Changes Notices event */ 286 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14) 287 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1) 288 /* supports Normal NVM Subsystem Shutdown event */ 289 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15) 290 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1) 291 /* supports Zone Descriptor Changed Notices event */ 292 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27) 293 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1) 294 /* supports Discovery Log Page Change Notification event */ 295 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31) 296 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1) 297 298 /** OACS - optional admin command support */ 299 /* supports security send/receive commands */ 300 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0) 301 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1) 302 /* supports format nvm command */ 303 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1) 304 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1) 305 /* supports firmware activate/download commands */ 306 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2) 307 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1) 308 /* supports namespace management commands */ 309 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3) 310 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1) 311 /* supports Device Self-test command */ 312 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4) 313 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1) 314 /* supports Directives */ 315 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5) 316 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1) 317 /* supports NVMe-MI Send/Receive */ 318 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6) 319 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1) 320 /* supports Virtualization Management */ 321 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7) 322 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1) 323 /* supports Doorbell Buffer Config */ 324 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8) 325 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1) 326 /* supports Get LBA Status */ 327 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9) 328 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1) 329 330 /** firmware updates */ 331 /* first slot is read-only */ 332 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0) 333 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1) 334 /* number of firmware slots */ 335 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1) 336 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7) 337 /* firmware activation without reset */ 338 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4) 339 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1) 340 341 /** log page attributes */ 342 /* per namespace smart/health log page */ 343 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0) 344 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1) 345 346 /** AVSCC - admin vendor specific command configuration */ 347 /* admin vendor specific commands use spec format */ 348 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0) 349 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1) 350 351 /** Autonomous Power State Transition Attributes */ 352 /* Autonomous Power State Transitions supported */ 353 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0) 354 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1) 355 356 /** Sanitize Capabilities */ 357 /* Crypto Erase Support */ 358 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0) 359 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1) 360 /* Block Erase Support */ 361 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1) 362 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1) 363 /* Overwrite Support */ 364 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2) 365 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1) 366 /* No-Deallocate Inhibited */ 367 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29) 368 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1) 369 /* No-Deallocate Modifies Media After Sanitize */ 370 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30) 371 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3) 372 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0) 373 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1) 374 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2) 375 376 /** submission queue entry size */ 377 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0) 378 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF) 379 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4) 380 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF) 381 382 /** completion queue entry size */ 383 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0) 384 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF) 385 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4) 386 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF) 387 388 /** optional nvm command support */ 389 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0) 390 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1) 391 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1) 392 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1) 393 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2) 394 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1) 395 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3) 396 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1) 397 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4) 398 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1) 399 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5) 400 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1) 401 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6) 402 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1) 403 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7) 404 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1) 405 406 /** Fused Operation Support */ 407 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0) 408 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1) 409 410 /** Format NVM Attributes */ 411 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0) 412 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1) 413 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1) 414 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1) 415 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2) 416 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1) 417 418 /** volatile write cache */ 419 /* volatile write cache present */ 420 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0) 421 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1) 422 /* flush all namespaces supported */ 423 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1) 424 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3) 425 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0) 426 #define NVME_CTRLR_DATA_VWC_ALL_NO (2) 427 #define NVME_CTRLR_DATA_VWC_ALL_YES (3) 428 429 /** namespace features */ 430 /* thin provisioning */ 431 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0) 432 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1) 433 /* NAWUN, NAWUPF, and NACWU fields are valid */ 434 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1) 435 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1) 436 /* Deallocated or Unwritten Logical Block errors supported */ 437 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2) 438 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1) 439 /* NGUID and EUI64 fields are not reusable */ 440 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3) 441 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1) 442 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */ 443 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4) 444 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1) 445 446 /** formatted lba size */ 447 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0) 448 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF) 449 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4) 450 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1) 451 452 /** metadata capabilities */ 453 /* metadata can be transferred as part of data prp list */ 454 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0) 455 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1) 456 /* metadata can be transferred with separate metadata pointer */ 457 #define NVME_NS_DATA_MC_POINTER_SHIFT (1) 458 #define NVME_NS_DATA_MC_POINTER_MASK (0x1) 459 460 /** end-to-end data protection capabilities */ 461 /* protection information type 1 */ 462 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0) 463 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1) 464 /* protection information type 2 */ 465 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1) 466 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1) 467 /* protection information type 3 */ 468 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2) 469 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1) 470 /* first eight bytes of metadata */ 471 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3) 472 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1) 473 /* last eight bytes of metadata */ 474 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4) 475 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1) 476 477 /** end-to-end data protection type settings */ 478 /* protection information type */ 479 #define NVME_NS_DATA_DPS_PIT_SHIFT (0) 480 #define NVME_NS_DATA_DPS_PIT_MASK (0x7) 481 /* 1 == protection info transferred at start of metadata */ 482 /* 0 == protection info transferred at end of metadata */ 483 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3) 484 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1) 485 486 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 487 /* the namespace may be attached to two or more controllers */ 488 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0) 489 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1) 490 491 /** Reservation Capabilities */ 492 /* Persist Through Power Loss */ 493 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0) 494 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1) 495 /* supports the Write Exclusive */ 496 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1) 497 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1) 498 /* supports the Exclusive Access */ 499 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2) 500 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1) 501 /* supports the Write Exclusive – Registrants Only */ 502 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3) 503 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1) 504 /* supports the Exclusive Access - Registrants Only */ 505 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4) 506 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1) 507 /* supports the Write Exclusive – All Registrants */ 508 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5) 509 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1) 510 /* supports the Exclusive Access - All Registrants */ 511 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6) 512 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1) 513 /* Ignore Existing Key is used as defined in revision 1.3 or later */ 514 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7) 515 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1) 516 517 /** Format Progress Indicator */ 518 /* percentage of the Format NVM command that remains to be completed */ 519 #define NVME_NS_DATA_FPI_PERC_SHIFT (0) 520 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f) 521 /* namespace supports the Format Progress Indicator */ 522 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7) 523 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1) 524 525 /** Deallocate Logical Block Features */ 526 /* deallocated logical block read behavior */ 527 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0) 528 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07) 529 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00) 530 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01) 531 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02) 532 /* supports the Deallocate bit in the Write Zeroes */ 533 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3) 534 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01) 535 /* Guard field for deallocated logical blocks is set to the CRC */ 536 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4) 537 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01) 538 539 /** lba format support */ 540 /* metadata size */ 541 #define NVME_NS_DATA_LBAF_MS_SHIFT (0) 542 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF) 543 /* lba data size */ 544 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16) 545 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF) 546 /* relative performance */ 547 #define NVME_NS_DATA_LBAF_RP_SHIFT (24) 548 #define NVME_NS_DATA_LBAF_RP_MASK (0x3) 549 550 enum nvme_critical_warning_state { 551 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1, 552 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2, 553 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4, 554 NVME_CRIT_WARN_ST_READ_ONLY = 0x8, 555 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10, 556 NVME_CRIT_WARN_ST_PERSISTENT_MEMORY_REGION = 0x20, 557 }; 558 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xC0) 559 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE (0x100) 560 #define NVME_ASYNC_EVENT_FW_ACTIVATE (0x200) 561 562 /* slot for current FW */ 563 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0) 564 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7) 565 566 /* Commands Supported and Effects */ 567 #define NVME_CE_PAGE_CSUP_SHIFT (0) 568 #define NVME_CE_PAGE_CSUP_MASK (0x1) 569 #define NVME_CE_PAGE_LBCC_SHIFT (1) 570 #define NVME_CE_PAGE_LBCC_MASK (0x1) 571 #define NVME_CE_PAGE_NCC_SHIFT (2) 572 #define NVME_CE_PAGE_NCC_MASK (0x1) 573 #define NVME_CE_PAGE_NIC_SHIFT (3) 574 #define NVME_CE_PAGE_NIC_MASK (0x1) 575 #define NVME_CE_PAGE_CCC_SHIFT (4) 576 #define NVME_CE_PAGE_CCC_MASK (0x1) 577 #define NVME_CE_PAGE_CSE_SHIFT (16) 578 #define NVME_CE_PAGE_CSE_MASK (0x7) 579 #define NVME_CE_PAGE_UUID_SHIFT (19) 580 #define NVME_CE_PAGE_UUID_MASK (0x1) 581 582 /* Sanitize Status */ 583 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0) 584 #define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7) 585 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0) 586 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1) 587 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2) 588 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3) 589 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4) 590 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3) 591 #define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f) 592 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8) 593 #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1) 594 595 /* Features */ 596 /* Get Features */ 597 #define NVME_FEAT_GET_SEL_SHIFT (8) 598 #define NVME_FEAT_GET_SEL_MASK (0x7) 599 #define NVME_FEAT_GET_FID_SHIFT (0) 600 #define NVME_FEAT_GET_FID_MASK (0xff) 601 602 /* Set Features */ 603 #define NVME_FEAT_SET_SV_SHIFT (31) 604 #define NVME_FEAT_SET_SV_MASK (0x1) 605 #define NVME_FEAT_SET_FID_SHIFT (0) 606 #define NVME_FEAT_SET_FID_MASK (0xff) 607 608 /* Helper macro to combine *_MASK and *_SHIFT defines */ 609 #define NVMEM(name) (name##_MASK << name##_SHIFT) 610 611 /* Helper macro to extract value from x */ 612 #define NVMEV(name, x) (((x) >> name##_SHIFT) & name##_MASK) 613 614 /* Helper macro to construct a field value */ 615 #define NVMEF(name, x) (((x) & name##_MASK) << name##_SHIFT) 616 617 /* CC register SHN field values */ 618 enum shn_value { 619 NVME_SHN_NORMAL = 0x1, 620 NVME_SHN_ABRUPT = 0x2, 621 }; 622 623 /* CSTS register SHST field values */ 624 enum shst_value { 625 NVME_SHST_NORMAL = 0x0, 626 NVME_SHST_OCCURRING = 0x1, 627 NVME_SHST_COMPLETE = 0x2, 628 }; 629 630 struct nvme_registers { 631 uint32_t cap_lo; /* controller capabilities */ 632 uint32_t cap_hi; 633 uint32_t vs; /* version */ 634 uint32_t intms; /* interrupt mask set */ 635 uint32_t intmc; /* interrupt mask clear */ 636 uint32_t cc; /* controller configuration */ 637 uint32_t reserved1; 638 uint32_t csts; /* controller status */ 639 uint32_t nssr; /* NVM Subsystem Reset */ 640 uint32_t aqa; /* admin queue attributes */ 641 uint64_t asq; /* admin submission queue base addr */ 642 uint64_t acq; /* admin completion queue base addr */ 643 uint32_t cmbloc; /* Controller Memory Buffer Location */ 644 uint32_t cmbsz; /* Controller Memory Buffer Size */ 645 uint32_t bpinfo; /* Boot Partition Information */ 646 uint32_t bprsel; /* Boot Partition Read Select */ 647 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */ 648 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */ 649 uint32_t cmbsts; /* Controller Memory Buffer Status */ 650 uint32_t cmbebs; /* Controller Memory Buffer Elasticity Buffer Size */ 651 uint32_t cmbswtp;/* Controller Memory Buffer Sustained Write Throughput */ 652 uint32_t nssd; /* NVM Subsystem Shutdown */ 653 uint32_t crto; /* Controller Ready Timeouts */ 654 uint8_t reserved3[3476]; /* 6Ch - DFFh */ 655 uint32_t pmrcap; /* Persistent Memory Capabilities */ 656 uint32_t pmrctl; /* Persistent Memory Region Control */ 657 uint32_t pmrsts; /* Persistent Memory Region Status */ 658 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */ 659 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */ 660 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */ 661 uint32_t pmrmsc_hi; 662 uint8_t reserved4[484]; /* E1Ch - FFFh */ 663 struct { 664 uint32_t sq_tdbl; /* submission queue tail doorbell */ 665 uint32_t cq_hdbl; /* completion queue head doorbell */ 666 } doorbell[1]; 667 }; 668 669 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 670 671 struct nvme_command { 672 /* dword 0 */ 673 uint8_t opc; /* opcode */ 674 uint8_t fuse; /* fused operation */ 675 uint16_t cid; /* command identifier */ 676 677 /* dword 1 */ 678 uint32_t nsid; /* namespace identifier */ 679 680 /* dword 2-3 */ 681 uint32_t rsvd2; 682 uint32_t rsvd3; 683 684 /* dword 4-5 */ 685 uint64_t mptr; /* metadata pointer */ 686 687 /* dword 6-7 */ 688 uint64_t prp1; /* prp entry 1 */ 689 690 /* dword 8-9 */ 691 uint64_t prp2; /* prp entry 2 */ 692 693 /* dword 10-15 */ 694 uint32_t cdw10; /* command-specific */ 695 uint32_t cdw11; /* command-specific */ 696 uint32_t cdw12; /* command-specific */ 697 uint32_t cdw13; /* command-specific */ 698 uint32_t cdw14; /* command-specific */ 699 uint32_t cdw15; /* command-specific */ 700 }; 701 702 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 703 704 struct nvme_completion { 705 /* dword 0 */ 706 uint32_t cdw0; /* command-specific */ 707 708 /* dword 1 */ 709 uint32_t rsvd1; 710 711 /* dword 2 */ 712 uint16_t sqhd; /* submission queue head pointer */ 713 uint16_t sqid; /* submission queue identifier */ 714 715 /* dword 3 */ 716 uint16_t cid; /* command identifier */ 717 uint16_t status; 718 } __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */ 719 720 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 721 722 struct nvme_dsm_range { 723 uint32_t attributes; 724 uint32_t length; 725 uint64_t starting_lba; 726 }; 727 728 /* Largest DSM Trim that can be done */ 729 #define NVME_MAX_DSM_TRIM 4096 730 731 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 732 733 /* status code types */ 734 enum nvme_status_code_type { 735 NVME_SCT_GENERIC = 0x0, 736 NVME_SCT_COMMAND_SPECIFIC = 0x1, 737 NVME_SCT_MEDIA_ERROR = 0x2, 738 NVME_SCT_PATH_RELATED = 0x3, 739 /* 0x3-0x6 - reserved */ 740 NVME_SCT_VENDOR_SPECIFIC = 0x7, 741 }; 742 743 /* generic command status codes */ 744 enum nvme_generic_command_status_code { 745 NVME_SC_SUCCESS = 0x00, 746 NVME_SC_INVALID_OPCODE = 0x01, 747 NVME_SC_INVALID_FIELD = 0x02, 748 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 749 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 750 NVME_SC_ABORTED_POWER_LOSS = 0x05, 751 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 752 NVME_SC_ABORTED_BY_REQUEST = 0x07, 753 NVME_SC_ABORTED_SQ_DELETION = 0x08, 754 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 755 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 756 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 757 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 758 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 759 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 760 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 761 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 762 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 763 NVME_SC_INVALID_USE_OF_CMB = 0x12, 764 NVME_SC_PRP_OFFET_INVALID = 0x13, 765 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 766 NVME_SC_OPERATION_DENIED = 0x15, 767 NVME_SC_SGL_OFFSET_INVALID = 0x16, 768 /* 0x17 - reserved */ 769 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 770 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 771 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 772 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 773 NVME_SC_SANITIZE_FAILED = 0x1c, 774 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 775 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 776 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 777 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20, 778 NVME_SC_COMMAND_INTERRUPTED = 0x21, 779 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22, 780 781 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 782 NVME_SC_CAPACITY_EXCEEDED = 0x81, 783 NVME_SC_NAMESPACE_NOT_READY = 0x82, 784 NVME_SC_RESERVATION_CONFLICT = 0x83, 785 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 786 }; 787 788 /* command specific status codes */ 789 enum nvme_command_specific_status_code { 790 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 791 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 792 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 793 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 794 /* 0x04 - reserved */ 795 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 796 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 797 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 798 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 799 NVME_SC_INVALID_LOG_PAGE = 0x09, 800 NVME_SC_INVALID_FORMAT = 0x0a, 801 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 802 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 803 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 804 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 805 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 806 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 807 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 808 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 809 NVME_SC_FW_ACT_PROHIBITED = 0x13, 810 NVME_SC_OVERLAPPING_RANGE = 0x14, 811 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 812 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 813 /* 0x17 - reserved */ 814 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 815 NVME_SC_NS_IS_PRIVATE = 0x19, 816 NVME_SC_NS_NOT_ATTACHED = 0x1a, 817 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 818 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 819 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d, 820 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 821 NVME_SC_INVALID_CTRLR_ID = 0x1f, 822 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 823 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 824 NVME_SC_INVALID_RESOURCE_ID = 0x22, 825 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23, 826 NVME_SC_ANA_GROUP_ID_INVALID = 0x24, 827 NVME_SC_ANA_ATTACH_FAILED = 0x25, 828 829 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 830 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 831 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 832 }; 833 834 /* media error status codes */ 835 enum nvme_media_error_status_code { 836 NVME_SC_WRITE_FAULTS = 0x80, 837 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 838 NVME_SC_GUARD_CHECK_ERROR = 0x82, 839 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 840 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 841 NVME_SC_COMPARE_FAILURE = 0x85, 842 NVME_SC_ACCESS_DENIED = 0x86, 843 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 844 }; 845 846 /* path related status codes */ 847 enum nvme_path_related_status_code { 848 NVME_SC_INTERNAL_PATH_ERROR = 0x00, 849 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01, 850 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02, 851 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03, 852 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60, 853 NVME_SC_HOST_PATHING_ERROR = 0x70, 854 NVME_SC_COMMAND_ABORTED_BY_HOST = 0x71, 855 }; 856 857 /* admin opcodes */ 858 enum nvme_admin_opcode { 859 NVME_OPC_DELETE_IO_SQ = 0x00, 860 NVME_OPC_CREATE_IO_SQ = 0x01, 861 NVME_OPC_GET_LOG_PAGE = 0x02, 862 /* 0x03 - reserved */ 863 NVME_OPC_DELETE_IO_CQ = 0x04, 864 NVME_OPC_CREATE_IO_CQ = 0x05, 865 NVME_OPC_IDENTIFY = 0x06, 866 /* 0x07 - reserved */ 867 NVME_OPC_ABORT = 0x08, 868 NVME_OPC_SET_FEATURES = 0x09, 869 NVME_OPC_GET_FEATURES = 0x0a, 870 /* 0x0b - reserved */ 871 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 872 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 873 /* 0x0e-0x0f - reserved */ 874 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 875 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 876 /* 0x12-0x13 - reserved */ 877 NVME_OPC_DEVICE_SELF_TEST = 0x14, 878 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 879 /* 0x16-0x17 - reserved */ 880 NVME_OPC_KEEP_ALIVE = 0x18, 881 NVME_OPC_DIRECTIVE_SEND = 0x19, 882 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 883 /* 0x1b - reserved */ 884 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 885 NVME_OPC_NVME_MI_SEND = 0x1d, 886 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 887 /* 0x1f - reserved */ 888 NVME_OPC_CAPACITY_MANAGEMENT = 0x20, 889 /* 0x21-0x23 - reserved */ 890 NVME_OPC_LOCKDOWN = 0x24, 891 /* 0x25-0x7b - reserved */ 892 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 893 /* 0x7d-0x7e - reserved */ 894 NVME_OPC_FABRICS_COMMANDS = 0x7f, 895 896 NVME_OPC_FORMAT_NVM = 0x80, 897 NVME_OPC_SECURITY_SEND = 0x81, 898 NVME_OPC_SECURITY_RECEIVE = 0x82, 899 /* 0x83 - reserved */ 900 NVME_OPC_SANITIZE = 0x84, 901 /* 0x85 - reserved */ 902 NVME_OPC_GET_LBA_STATUS = 0x86, 903 }; 904 905 /* nvme nvm opcodes */ 906 enum nvme_nvm_opcode { 907 NVME_OPC_FLUSH = 0x00, 908 NVME_OPC_WRITE = 0x01, 909 NVME_OPC_READ = 0x02, 910 /* 0x03 - reserved */ 911 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 912 NVME_OPC_COMPARE = 0x05, 913 /* 0x06-0x07 - reserved */ 914 NVME_OPC_WRITE_ZEROES = 0x08, 915 NVME_OPC_DATASET_MANAGEMENT = 0x09, 916 /* 0x0a-0x0b - reserved */ 917 NVME_OPC_VERIFY = 0x0c, 918 NVME_OPC_RESERVATION_REGISTER = 0x0d, 919 NVME_OPC_RESERVATION_REPORT = 0x0e, 920 /* 0x0f-0x10 - reserved */ 921 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 922 /* 0x12-0x14 - reserved */ 923 NVME_OPC_RESERVATION_RELEASE = 0x15, 924 /* 0x16-0x18 - reserved */ 925 NVME_OPC_COPY = 0x19, 926 }; 927 928 enum nvme_feature { 929 /* 0x00 - reserved */ 930 NVME_FEAT_ARBITRATION = 0x01, 931 NVME_FEAT_POWER_MANAGEMENT = 0x02, 932 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 933 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 934 NVME_FEAT_ERROR_RECOVERY = 0x05, 935 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 936 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 937 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 938 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 939 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 940 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 941 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 942 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 943 NVME_FEAT_TIMESTAMP = 0x0E, 944 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 945 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 946 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 947 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12, 948 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13, 949 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14, 950 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15, 951 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16, 952 NVME_FEAT_SANITIZE_CONFIG = 0x17, 953 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18, 954 /* 0x19-0x77 - reserved */ 955 /* 0x78-0x7f - NVMe Management Interface */ 956 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 957 NVME_FEAT_HOST_IDENTIFIER = 0x81, 958 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82, 959 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83, 960 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84, 961 /* 0x85-0xBF - command set specific (reserved) */ 962 /* 0xC0-0xFF - vendor specific */ 963 }; 964 965 enum nvme_dsm_attribute { 966 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 967 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 968 NVME_DSM_ATTR_DEALLOCATE = 0x4, 969 }; 970 971 enum nvme_activate_action { 972 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 973 NVME_AA_REPLACE_ACTIVATE = 0x1, 974 NVME_AA_ACTIVATE = 0x2, 975 }; 976 977 struct nvme_power_state { 978 /** Maximum Power */ 979 uint16_t mp; /* Maximum Power */ 980 uint8_t ps_rsvd1; 981 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */ 982 983 uint32_t enlat; /* Entry Latency */ 984 uint32_t exlat; /* Exit Latency */ 985 986 uint8_t rrt; /* Relative Read Throughput */ 987 uint8_t rrl; /* Relative Read Latency */ 988 uint8_t rwt; /* Relative Write Throughput */ 989 uint8_t rwl; /* Relative Write Latency */ 990 991 uint16_t idlp; /* Idle Power */ 992 uint8_t ips; /* Idle Power Scale */ 993 uint8_t ps_rsvd8; 994 995 uint16_t actp; /* Active Power */ 996 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ 997 uint8_t ps_rsvd10[9]; 998 } __packed; 999 1000 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 1001 1002 #define NVME_SERIAL_NUMBER_LENGTH 20 1003 #define NVME_MODEL_NUMBER_LENGTH 40 1004 #define NVME_FIRMWARE_REVISION_LENGTH 8 1005 1006 struct nvme_controller_data { 1007 /* bytes 0-255: controller capabilities and features */ 1008 1009 /** pci vendor id */ 1010 uint16_t vid; 1011 1012 /** pci subsystem vendor id */ 1013 uint16_t ssvid; 1014 1015 /** serial number */ 1016 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 1017 1018 /** model number */ 1019 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 1020 1021 /** firmware revision */ 1022 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 1023 1024 /** recommended arbitration burst */ 1025 uint8_t rab; 1026 1027 /** ieee oui identifier */ 1028 uint8_t ieee[3]; 1029 1030 /** multi-interface capabilities */ 1031 uint8_t mic; 1032 1033 /** maximum data transfer size */ 1034 uint8_t mdts; 1035 1036 /** Controller ID */ 1037 uint16_t ctrlr_id; 1038 1039 /** Version */ 1040 uint32_t ver; 1041 1042 /** RTD3 Resume Latency */ 1043 uint32_t rtd3r; 1044 1045 /** RTD3 Enter Latency */ 1046 uint32_t rtd3e; 1047 1048 /** Optional Asynchronous Events Supported */ 1049 uint32_t oaes; /* bitfield really */ 1050 1051 /** Controller Attributes */ 1052 uint32_t ctratt; /* bitfield really */ 1053 1054 /** Read Recovery Levels Supported */ 1055 uint16_t rrls; 1056 1057 uint8_t reserved1[9]; 1058 1059 /** Controller Type */ 1060 uint8_t cntrltype; 1061 1062 /** FRU Globally Unique Identifier */ 1063 uint8_t fguid[16]; 1064 1065 /** Command Retry Delay Time 1 */ 1066 uint16_t crdt1; 1067 1068 /** Command Retry Delay Time 2 */ 1069 uint16_t crdt2; 1070 1071 /** Command Retry Delay Time 3 */ 1072 uint16_t crdt3; 1073 1074 uint8_t reserved2[122]; 1075 1076 /* bytes 256-511: admin command set attributes */ 1077 1078 /** optional admin command support */ 1079 uint16_t oacs; 1080 1081 /** abort command limit */ 1082 uint8_t acl; 1083 1084 /** asynchronous event request limit */ 1085 uint8_t aerl; 1086 1087 /** firmware updates */ 1088 uint8_t frmw; 1089 1090 /** log page attributes */ 1091 uint8_t lpa; 1092 1093 /** error log page entries */ 1094 uint8_t elpe; 1095 1096 /** number of power states supported */ 1097 uint8_t npss; 1098 1099 /** admin vendor specific command configuration */ 1100 uint8_t avscc; 1101 1102 /** Autonomous Power State Transition Attributes */ 1103 uint8_t apsta; 1104 1105 /** Warning Composite Temperature Threshold */ 1106 uint16_t wctemp; 1107 1108 /** Critical Composite Temperature Threshold */ 1109 uint16_t cctemp; 1110 1111 /** Maximum Time for Firmware Activation */ 1112 uint16_t mtfa; 1113 1114 /** Host Memory Buffer Preferred Size */ 1115 uint32_t hmpre; 1116 1117 /** Host Memory Buffer Minimum Size */ 1118 uint32_t hmmin; 1119 1120 /** Name space capabilities */ 1121 struct { 1122 /* if nsmgmt, report tnvmcap and unvmcap */ 1123 uint8_t tnvmcap[16]; 1124 uint8_t unvmcap[16]; 1125 } __packed untncap; 1126 1127 /** Replay Protected Memory Block Support */ 1128 uint32_t rpmbs; /* Really a bitfield */ 1129 1130 /** Extended Device Self-test Time */ 1131 uint16_t edstt; 1132 1133 /** Device Self-test Options */ 1134 uint8_t dsto; /* Really a bitfield */ 1135 1136 /** Firmware Update Granularity */ 1137 uint8_t fwug; 1138 1139 /** Keep Alive Support */ 1140 uint16_t kas; 1141 1142 /** Host Controlled Thermal Management Attributes */ 1143 uint16_t hctma; /* Really a bitfield */ 1144 1145 /** Minimum Thermal Management Temperature */ 1146 uint16_t mntmt; 1147 1148 /** Maximum Thermal Management Temperature */ 1149 uint16_t mxtmt; 1150 1151 /** Sanitize Capabilities */ 1152 uint32_t sanicap; /* Really a bitfield */ 1153 1154 /** Host Memory Buffer Minimum Descriptor Entry Size */ 1155 uint32_t hmminds; 1156 1157 /** Host Memory Maximum Descriptors Entries */ 1158 uint16_t hmmaxd; 1159 1160 /** NVM Set Identifier Maximum */ 1161 uint16_t nsetidmax; 1162 1163 /** Endurance Group Identifier Maximum */ 1164 uint16_t endgidmax; 1165 1166 /** ANA Transition Time */ 1167 uint8_t anatt; 1168 1169 /** Asymmetric Namespace Access Capabilities */ 1170 uint8_t anacap; 1171 1172 /** ANA Group Identifier Maximum */ 1173 uint32_t anagrpmax; 1174 1175 /** Number of ANA Group Identifiers */ 1176 uint32_t nanagrpid; 1177 1178 /** Persistent Event Log Size */ 1179 uint32_t pels; 1180 1181 uint8_t reserved3[156]; 1182 /* bytes 512-703: nvm command set attributes */ 1183 1184 /** submission queue entry size */ 1185 uint8_t sqes; 1186 1187 /** completion queue entry size */ 1188 uint8_t cqes; 1189 1190 /** Maximum Outstanding Commands */ 1191 uint16_t maxcmd; 1192 1193 /** number of namespaces */ 1194 uint32_t nn; 1195 1196 /** optional nvm command support */ 1197 uint16_t oncs; 1198 1199 /** fused operation support */ 1200 uint16_t fuses; 1201 1202 /** format nvm attributes */ 1203 uint8_t fna; 1204 1205 /** volatile write cache */ 1206 uint8_t vwc; 1207 1208 /** Atomic Write Unit Normal */ 1209 uint16_t awun; 1210 1211 /** Atomic Write Unit Power Fail */ 1212 uint16_t awupf; 1213 1214 /** NVM Vendor Specific Command Configuration */ 1215 uint8_t nvscc; 1216 1217 /** Namespace Write Protection Capabilities */ 1218 uint8_t nwpc; 1219 1220 /** Atomic Compare & Write Unit */ 1221 uint16_t acwu; 1222 uint16_t reserved6; 1223 1224 /** SGL Support */ 1225 uint32_t sgls; 1226 1227 /** Maximum Number of Allowed Namespaces */ 1228 uint32_t mnan; 1229 1230 /* bytes 540-767: Reserved */ 1231 uint8_t reserved7[224]; 1232 1233 /** NVM Subsystem NVMe Qualified Name */ 1234 uint8_t subnqn[256]; 1235 1236 /* bytes 1024-1791: Reserved */ 1237 uint8_t reserved8[768]; 1238 1239 /* bytes 1792-2047: NVMe over Fabrics specification */ 1240 uint8_t reserved9[256]; 1241 1242 /* bytes 2048-3071: power state descriptors */ 1243 struct nvme_power_state power_state[32]; 1244 1245 /* bytes 3072-4095: vendor specific */ 1246 uint8_t vs[1024]; 1247 } __packed __aligned(4); 1248 1249 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 1250 1251 struct nvme_namespace_data { 1252 /** namespace size */ 1253 uint64_t nsze; 1254 1255 /** namespace capacity */ 1256 uint64_t ncap; 1257 1258 /** namespace utilization */ 1259 uint64_t nuse; 1260 1261 /** namespace features */ 1262 uint8_t nsfeat; 1263 1264 /** number of lba formats */ 1265 uint8_t nlbaf; 1266 1267 /** formatted lba size */ 1268 uint8_t flbas; 1269 1270 /** metadata capabilities */ 1271 uint8_t mc; 1272 1273 /** end-to-end data protection capabilities */ 1274 uint8_t dpc; 1275 1276 /** end-to-end data protection type settings */ 1277 uint8_t dps; 1278 1279 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 1280 uint8_t nmic; 1281 1282 /** Reservation Capabilities */ 1283 uint8_t rescap; 1284 1285 /** Format Progress Indicator */ 1286 uint8_t fpi; 1287 1288 /** Deallocate Logical Block Features */ 1289 uint8_t dlfeat; 1290 1291 /** Namespace Atomic Write Unit Normal */ 1292 uint16_t nawun; 1293 1294 /** Namespace Atomic Write Unit Power Fail */ 1295 uint16_t nawupf; 1296 1297 /** Namespace Atomic Compare & Write Unit */ 1298 uint16_t nacwu; 1299 1300 /** Namespace Atomic Boundary Size Normal */ 1301 uint16_t nabsn; 1302 1303 /** Namespace Atomic Boundary Offset */ 1304 uint16_t nabo; 1305 1306 /** Namespace Atomic Boundary Size Power Fail */ 1307 uint16_t nabspf; 1308 1309 /** Namespace Optimal IO Boundary */ 1310 uint16_t noiob; 1311 1312 /** NVM Capacity */ 1313 uint8_t nvmcap[16]; 1314 1315 /** Namespace Preferred Write Granularity */ 1316 uint16_t npwg; 1317 1318 /** Namespace Preferred Write Alignment */ 1319 uint16_t npwa; 1320 1321 /** Namespace Preferred Deallocate Granularity */ 1322 uint16_t npdg; 1323 1324 /** Namespace Preferred Deallocate Alignment */ 1325 uint16_t npda; 1326 1327 /** Namespace Optimal Write Size */ 1328 uint16_t nows; 1329 1330 /* bytes 74-91: Reserved */ 1331 uint8_t reserved5[18]; 1332 1333 /** ANA Group Identifier */ 1334 uint32_t anagrpid; 1335 1336 /* bytes 96-98: Reserved */ 1337 uint8_t reserved6[3]; 1338 1339 /** Namespace Attributes */ 1340 uint8_t nsattr; 1341 1342 /** NVM Set Identifier */ 1343 uint16_t nvmsetid; 1344 1345 /** Endurance Group Identifier */ 1346 uint16_t endgid; 1347 1348 /** Namespace Globally Unique Identifier */ 1349 uint8_t nguid[16]; 1350 1351 /** IEEE Extended Unique Identifier */ 1352 uint8_t eui64[8]; 1353 1354 /** lba format support */ 1355 uint32_t lbaf[16]; 1356 1357 uint8_t reserved7[192]; 1358 1359 uint8_t vendor_specific[3712]; 1360 } __packed __aligned(4); 1361 1362 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 1363 1364 enum nvme_log_page { 1365 /* 0x00 - reserved */ 1366 NVME_LOG_ERROR = 0x01, 1367 NVME_LOG_HEALTH_INFORMATION = 0x02, 1368 NVME_LOG_FIRMWARE_SLOT = 0x03, 1369 NVME_LOG_CHANGED_NAMESPACE = 0x04, 1370 NVME_LOG_COMMAND_EFFECT = 0x05, 1371 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1372 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07, 1373 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08, 1374 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09, 1375 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a, 1376 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b, 1377 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c, 1378 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d, 1379 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e, 1380 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f, 1381 /* 0x06-0x7F - reserved */ 1382 /* 0x80-0xBF - I/O command set specific */ 1383 NVME_LOG_RES_NOTIFICATION = 0x80, 1384 NVME_LOG_SANITIZE_STATUS = 0x81, 1385 /* 0x82-0xBF - reserved */ 1386 /* 0xC0-0xFF - vendor specific */ 1387 1388 /* 1389 * The following are Intel Specific log pages, but they seem 1390 * to be widely implemented. 1391 */ 1392 INTEL_LOG_READ_LAT_LOG = 0xc1, 1393 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 1394 INTEL_LOG_TEMP_STATS = 0xc5, 1395 INTEL_LOG_ADD_SMART = 0xca, 1396 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 1397 1398 /* 1399 * HGST log page, with lots ofs sub pages. 1400 */ 1401 HGST_INFO_LOG = 0xc1, 1402 }; 1403 1404 struct nvme_error_information_entry { 1405 uint64_t error_count; 1406 uint16_t sqid; 1407 uint16_t cid; 1408 uint16_t status; 1409 uint16_t error_location; 1410 uint64_t lba; 1411 uint32_t nsid; 1412 uint8_t vendor_specific; 1413 uint8_t trtype; 1414 uint16_t reserved30; 1415 uint64_t csi; 1416 uint16_t ttsi; 1417 uint8_t reserved[22]; 1418 } __packed __aligned(4); 1419 1420 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 1421 1422 struct nvme_health_information_page { 1423 uint8_t critical_warning; 1424 uint16_t temperature; 1425 uint8_t available_spare; 1426 uint8_t available_spare_threshold; 1427 uint8_t percentage_used; 1428 1429 uint8_t reserved[26]; 1430 1431 /* 1432 * Note that the following are 128-bit values, but are 1433 * defined as an array of 2 64-bit values. 1434 */ 1435 /* Data Units Read is always in 512-byte units. */ 1436 uint64_t data_units_read[2]; 1437 /* Data Units Written is always in 512-byte units. */ 1438 uint64_t data_units_written[2]; 1439 /* For NVM command set, this includes Compare commands. */ 1440 uint64_t host_read_commands[2]; 1441 uint64_t host_write_commands[2]; 1442 /* Controller Busy Time is reported in minutes. */ 1443 uint64_t controller_busy_time[2]; 1444 uint64_t power_cycles[2]; 1445 uint64_t power_on_hours[2]; 1446 uint64_t unsafe_shutdowns[2]; 1447 uint64_t media_errors[2]; 1448 uint64_t num_error_info_log_entries[2]; 1449 uint32_t warning_temp_time; 1450 uint32_t error_temp_time; 1451 uint16_t temp_sensor[8]; 1452 /* Thermal Management Temperature 1 Transition Count */ 1453 uint32_t tmt1tc; 1454 /* Thermal Management Temperature 2 Transition Count */ 1455 uint32_t tmt2tc; 1456 /* Total Time For Thermal Management Temperature 1 */ 1457 uint32_t ttftmt1; 1458 /* Total Time For Thermal Management Temperature 2 */ 1459 uint32_t ttftmt2; 1460 1461 uint8_t reserved2[280]; 1462 } __packed __aligned(4); 1463 1464 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 1465 1466 struct nvme_firmware_page { 1467 uint8_t afi; 1468 uint8_t reserved[7]; 1469 /* revisions for 7 slots */ 1470 uint8_t revision[7][NVME_FIRMWARE_REVISION_LENGTH]; 1471 uint8_t reserved2[448]; 1472 } __packed __aligned(4); 1473 1474 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 1475 1476 struct nvme_ns_list { 1477 uint32_t ns[1024]; 1478 } __packed __aligned(4); 1479 1480 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list"); 1481 1482 struct nvme_command_effects_page { 1483 uint32_t acs[256]; 1484 uint32_t iocs[256]; 1485 uint8_t reserved[2048]; 1486 } __packed __aligned(4); 1487 1488 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096, 1489 "bad size for nvme_command_effects_page"); 1490 1491 struct nvme_device_self_test_page { 1492 uint8_t curr_operation; 1493 uint8_t curr_compl; 1494 uint8_t rsvd2[2]; 1495 struct { 1496 uint8_t status; 1497 uint8_t segment_num; 1498 uint8_t valid_diag_info; 1499 uint8_t rsvd3; 1500 uint64_t poh; 1501 uint32_t nsid; 1502 /* Define as an array to simplify alignment issues */ 1503 uint8_t failing_lba[8]; 1504 uint8_t status_code_type; 1505 uint8_t status_code; 1506 uint8_t vendor_specific[2]; 1507 } __packed result[20]; 1508 } __packed __aligned(4); 1509 1510 _Static_assert(sizeof(struct nvme_device_self_test_page) == 564, 1511 "bad size for nvme_device_self_test_page"); 1512 1513 struct nvme_res_notification_page { 1514 uint64_t log_page_count; 1515 uint8_t log_page_type; 1516 uint8_t available_log_pages; 1517 uint8_t reserved2; 1518 uint32_t nsid; 1519 uint8_t reserved[48]; 1520 } __packed __aligned(4); 1521 1522 _Static_assert(sizeof(struct nvme_res_notification_page) == 64, 1523 "bad size for nvme_res_notification_page"); 1524 1525 struct nvme_sanitize_status_page { 1526 uint16_t sprog; 1527 uint16_t sstat; 1528 uint32_t scdw10; 1529 uint32_t etfo; 1530 uint32_t etfbe; 1531 uint32_t etfce; 1532 uint32_t etfownd; 1533 uint32_t etfbewnd; 1534 uint32_t etfcewnd; 1535 uint8_t reserved[480]; 1536 } __packed __aligned(4); 1537 1538 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512, 1539 "bad size for nvme_sanitize_status_page"); 1540 1541 struct intel_log_temp_stats { 1542 uint64_t current; 1543 uint64_t overtemp_flag_last; 1544 uint64_t overtemp_flag_life; 1545 uint64_t max_temp; 1546 uint64_t min_temp; 1547 uint64_t _rsvd[5]; 1548 uint64_t max_oper_temp; 1549 uint64_t min_oper_temp; 1550 uint64_t est_offset; 1551 } __packed __aligned(4); 1552 1553 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 1554 1555 struct nvme_resv_reg_ctrlr { 1556 uint16_t ctrlr_id; /* Controller ID */ 1557 uint8_t rcsts; /* Reservation Status */ 1558 uint8_t reserved3[5]; 1559 uint64_t hostid; /* Host Identifier */ 1560 uint64_t rkey; /* Reservation Key */ 1561 } __packed __aligned(4); 1562 1563 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr"); 1564 1565 struct nvme_resv_reg_ctrlr_ext { 1566 uint16_t ctrlr_id; /* Controller ID */ 1567 uint8_t rcsts; /* Reservation Status */ 1568 uint8_t reserved3[5]; 1569 uint64_t rkey; /* Reservation Key */ 1570 uint64_t hostid[2]; /* Host Identifier */ 1571 uint8_t reserved32[32]; 1572 } __packed __aligned(4); 1573 1574 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext"); 1575 1576 struct nvme_resv_status { 1577 uint32_t gen; /* Generation */ 1578 uint8_t rtype; /* Reservation Type */ 1579 uint8_t regctl[2]; /* Number of Registered Controllers */ 1580 uint8_t reserved7[2]; 1581 uint8_t ptpls; /* Persist Through Power Loss State */ 1582 uint8_t reserved10[14]; 1583 struct nvme_resv_reg_ctrlr ctrlr[0]; 1584 } __packed __aligned(4); 1585 1586 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status"); 1587 1588 struct nvme_resv_status_ext { 1589 uint32_t gen; /* Generation */ 1590 uint8_t rtype; /* Reservation Type */ 1591 uint8_t regctl[2]; /* Number of Registered Controllers */ 1592 uint8_t reserved7[2]; 1593 uint8_t ptpls; /* Persist Through Power Loss State */ 1594 uint8_t reserved10[14]; 1595 uint8_t reserved24[40]; 1596 struct nvme_resv_reg_ctrlr_ext ctrlr[0]; 1597 } __packed __aligned(4); 1598 1599 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext"); 1600 1601 #define NVME_TEST_MAX_THREADS 128 1602 1603 struct nvme_io_test { 1604 enum nvme_nvm_opcode opc; 1605 uint32_t size; 1606 uint32_t time; /* in seconds */ 1607 uint32_t num_threads; 1608 uint32_t flags; 1609 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 1610 }; 1611 1612 enum nvme_io_test_flags { 1613 /* 1614 * Specifies whether dev_refthread/dev_relthread should be 1615 * called during NVME_BIO_TEST. Ignored for other test 1616 * types. 1617 */ 1618 NVME_TEST_FLAG_REFTHREAD = 0x1, 1619 }; 1620 1621 struct nvme_pt_command { 1622 /* 1623 * cmd is used to specify a passthrough command to a controller or 1624 * namespace. 1625 * 1626 * The following fields from cmd may be specified by the caller: 1627 * * opc (opcode) 1628 * * nsid (namespace id) - for admin commands only 1629 * * cdw10-cdw15 1630 * 1631 * Remaining fields must be set to 0 by the caller. 1632 */ 1633 struct nvme_command cmd; 1634 1635 /* 1636 * cpl returns completion status for the passthrough command 1637 * specified by cmd. 1638 * 1639 * The following fields will be filled out by the driver, for 1640 * consumption by the caller: 1641 * * cdw0 1642 * * status (except for phase) 1643 * 1644 * Remaining fields will be set to 0 by the driver. 1645 */ 1646 struct nvme_completion cpl; 1647 1648 /* buf is the data buffer associated with this passthrough command. */ 1649 void * buf; 1650 1651 /* 1652 * len is the length of the data buffer associated with this 1653 * passthrough command. 1654 */ 1655 uint32_t len; 1656 1657 /* 1658 * is_read = 1 if the passthrough command will read data into the 1659 * supplied buffer from the controller. 1660 * 1661 * is_read = 0 if the passthrough command will write data from the 1662 * supplied buffer to the controller. 1663 */ 1664 uint32_t is_read; 1665 1666 /* 1667 * driver_lock is used by the driver only. It must be set to 0 1668 * by the caller. 1669 */ 1670 struct mtx * driver_lock; 1671 }; 1672 1673 struct nvme_get_nsid { 1674 char cdev[SPECNAMELEN + 1]; 1675 uint32_t nsid; 1676 }; 1677 1678 struct nvme_hmb_desc { 1679 uint64_t addr; 1680 uint32_t size; 1681 uint32_t reserved; 1682 }; 1683 1684 #define nvme_completion_is_error(cpl) \ 1685 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0) 1686 1687 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1688 1689 #ifdef _KERNEL 1690 1691 struct bio; 1692 struct thread; 1693 1694 struct nvme_namespace; 1695 struct nvme_controller; 1696 struct nvme_consumer; 1697 1698 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1699 1700 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1701 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1702 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1703 uint32_t, void *, uint32_t); 1704 typedef void (*nvme_cons_fail_fn_t)(void *); 1705 1706 enum nvme_namespace_flags { 1707 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1708 NVME_NS_FLUSH_SUPPORTED = 0x2, 1709 }; 1710 1711 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1712 struct nvme_pt_command *pt, 1713 uint32_t nsid, int is_user_buffer, 1714 int is_admin_cmd); 1715 1716 /* Admin functions */ 1717 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1718 uint8_t feature, uint32_t cdw11, 1719 uint32_t cdw12, uint32_t cdw13, 1720 uint32_t cdw14, uint32_t cdw15, 1721 void *payload, uint32_t payload_size, 1722 nvme_cb_fn_t cb_fn, void *cb_arg); 1723 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1724 uint8_t feature, uint32_t cdw11, 1725 void *payload, uint32_t payload_size, 1726 nvme_cb_fn_t cb_fn, void *cb_arg); 1727 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1728 uint8_t log_page, uint32_t nsid, 1729 void *payload, uint32_t payload_size, 1730 nvme_cb_fn_t cb_fn, void *cb_arg); 1731 1732 /* NVM I/O functions */ 1733 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1734 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1735 void *cb_arg); 1736 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1737 nvme_cb_fn_t cb_fn, void *cb_arg); 1738 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1739 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1740 void *cb_arg); 1741 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1742 nvme_cb_fn_t cb_fn, void *cb_arg); 1743 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1744 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1745 void *cb_arg); 1746 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1747 void *cb_arg); 1748 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1749 size_t len); 1750 1751 /* Registration functions */ 1752 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1753 nvme_cons_ctrlr_fn_t ctrlr_fn, 1754 nvme_cons_async_fn_t async_fn, 1755 nvme_cons_fail_fn_t fail_fn); 1756 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1757 1758 /* Controller helper functions */ 1759 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1760 const struct nvme_controller_data * 1761 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1762 static inline bool 1763 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd) 1764 { 1765 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */ 1766 return (NVMEV(NVME_CTRLR_DATA_ONCS_DSM, cd->oncs) != 0); 1767 } 1768 1769 /* Namespace helper functions */ 1770 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1771 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1772 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1773 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1774 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1775 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1776 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1777 const struct nvme_namespace_data * 1778 nvme_ns_get_data(struct nvme_namespace *ns); 1779 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1780 1781 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1782 nvme_cb_fn_t cb_fn); 1783 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd, 1784 caddr_t arg, int flag, struct thread *td); 1785 1786 /* 1787 * Command building helper functions -- shared with CAM 1788 * These functions assume allocator zeros out cmd structure 1789 * CAM's xpt_get_ccb and the request allocator for nvme both 1790 * do zero'd allocations. 1791 */ 1792 static inline 1793 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1794 { 1795 1796 cmd->opc = NVME_OPC_FLUSH; 1797 cmd->nsid = htole32(nsid); 1798 } 1799 1800 static inline 1801 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1802 uint64_t lba, uint32_t count) 1803 { 1804 cmd->opc = rwcmd; 1805 cmd->nsid = htole32(nsid); 1806 cmd->cdw10 = htole32(lba & 0xffffffffu); 1807 cmd->cdw11 = htole32(lba >> 32); 1808 cmd->cdw12 = htole32(count-1); 1809 } 1810 1811 static inline 1812 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1813 uint64_t lba, uint32_t count) 1814 { 1815 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1816 } 1817 1818 static inline 1819 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1820 uint64_t lba, uint32_t count) 1821 { 1822 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1823 } 1824 1825 static inline 1826 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1827 uint32_t num_ranges) 1828 { 1829 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1830 cmd->nsid = htole32(nsid); 1831 cmd->cdw10 = htole32(num_ranges - 1); 1832 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE); 1833 } 1834 1835 extern int nvme_use_nvd; 1836 1837 #endif /* _KERNEL */ 1838 1839 /* Endianess conversion functions for NVMe structs */ 1840 static inline 1841 void nvme_completion_swapbytes(struct nvme_completion *s __unused) 1842 { 1843 #if _BYTE_ORDER != _LITTLE_ENDIAN 1844 1845 s->cdw0 = le32toh(s->cdw0); 1846 /* omit rsvd1 */ 1847 s->sqhd = le16toh(s->sqhd); 1848 s->sqid = le16toh(s->sqid); 1849 /* omit cid */ 1850 s->status = le16toh(s->status); 1851 #endif 1852 } 1853 1854 static inline 1855 void nvme_power_state_swapbytes(struct nvme_power_state *s __unused) 1856 { 1857 #if _BYTE_ORDER != _LITTLE_ENDIAN 1858 1859 s->mp = le16toh(s->mp); 1860 s->enlat = le32toh(s->enlat); 1861 s->exlat = le32toh(s->exlat); 1862 s->idlp = le16toh(s->idlp); 1863 s->actp = le16toh(s->actp); 1864 #endif 1865 } 1866 1867 static inline 1868 void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused) 1869 { 1870 #if _BYTE_ORDER != _LITTLE_ENDIAN 1871 int i; 1872 1873 s->vid = le16toh(s->vid); 1874 s->ssvid = le16toh(s->ssvid); 1875 s->ctrlr_id = le16toh(s->ctrlr_id); 1876 s->ver = le32toh(s->ver); 1877 s->rtd3r = le32toh(s->rtd3r); 1878 s->rtd3e = le32toh(s->rtd3e); 1879 s->oaes = le32toh(s->oaes); 1880 s->ctratt = le32toh(s->ctratt); 1881 s->rrls = le16toh(s->rrls); 1882 s->crdt1 = le16toh(s->crdt1); 1883 s->crdt2 = le16toh(s->crdt2); 1884 s->crdt3 = le16toh(s->crdt3); 1885 s->oacs = le16toh(s->oacs); 1886 s->wctemp = le16toh(s->wctemp); 1887 s->cctemp = le16toh(s->cctemp); 1888 s->mtfa = le16toh(s->mtfa); 1889 s->hmpre = le32toh(s->hmpre); 1890 s->hmmin = le32toh(s->hmmin); 1891 s->rpmbs = le32toh(s->rpmbs); 1892 s->edstt = le16toh(s->edstt); 1893 s->kas = le16toh(s->kas); 1894 s->hctma = le16toh(s->hctma); 1895 s->mntmt = le16toh(s->mntmt); 1896 s->mxtmt = le16toh(s->mxtmt); 1897 s->sanicap = le32toh(s->sanicap); 1898 s->hmminds = le32toh(s->hmminds); 1899 s->hmmaxd = le16toh(s->hmmaxd); 1900 s->nsetidmax = le16toh(s->nsetidmax); 1901 s->endgidmax = le16toh(s->endgidmax); 1902 s->anagrpmax = le32toh(s->anagrpmax); 1903 s->nanagrpid = le32toh(s->nanagrpid); 1904 s->pels = le32toh(s->pels); 1905 s->maxcmd = le16toh(s->maxcmd); 1906 s->nn = le32toh(s->nn); 1907 s->oncs = le16toh(s->oncs); 1908 s->fuses = le16toh(s->fuses); 1909 s->awun = le16toh(s->awun); 1910 s->awupf = le16toh(s->awupf); 1911 s->acwu = le16toh(s->acwu); 1912 s->sgls = le32toh(s->sgls); 1913 s->mnan = le32toh(s->mnan); 1914 for (i = 0; i < 32; i++) 1915 nvme_power_state_swapbytes(&s->power_state[i]); 1916 #endif 1917 } 1918 1919 static inline 1920 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused) 1921 { 1922 #if _BYTE_ORDER != _LITTLE_ENDIAN 1923 int i; 1924 1925 s->nsze = le64toh(s->nsze); 1926 s->ncap = le64toh(s->ncap); 1927 s->nuse = le64toh(s->nuse); 1928 s->nawun = le16toh(s->nawun); 1929 s->nawupf = le16toh(s->nawupf); 1930 s->nacwu = le16toh(s->nacwu); 1931 s->nabsn = le16toh(s->nabsn); 1932 s->nabo = le16toh(s->nabo); 1933 s->nabspf = le16toh(s->nabspf); 1934 s->noiob = le16toh(s->noiob); 1935 s->npwg = le16toh(s->npwg); 1936 s->npwa = le16toh(s->npwa); 1937 s->npdg = le16toh(s->npdg); 1938 s->npda = le16toh(s->npda); 1939 s->nows = le16toh(s->nows); 1940 s->anagrpid = le32toh(s->anagrpid); 1941 s->nvmsetid = le16toh(s->nvmsetid); 1942 s->endgid = le16toh(s->endgid); 1943 for (i = 0; i < 16; i++) 1944 s->lbaf[i] = le32toh(s->lbaf[i]); 1945 #endif 1946 } 1947 1948 static inline 1949 void nvme_error_information_entry_swapbytes( 1950 struct nvme_error_information_entry *s __unused) 1951 { 1952 #if _BYTE_ORDER != _LITTLE_ENDIAN 1953 1954 s->error_count = le64toh(s->error_count); 1955 s->sqid = le16toh(s->sqid); 1956 s->cid = le16toh(s->cid); 1957 s->status = le16toh(s->status); 1958 s->error_location = le16toh(s->error_location); 1959 s->lba = le64toh(s->lba); 1960 s->nsid = le32toh(s->nsid); 1961 s->csi = le64toh(s->csi); 1962 s->ttsi = le16toh(s->ttsi); 1963 #endif 1964 } 1965 1966 static inline 1967 void nvme_le128toh(void *p __unused) 1968 { 1969 #if _BYTE_ORDER != _LITTLE_ENDIAN 1970 /* Swap 16 bytes in place */ 1971 char *tmp = (char*)p; 1972 char b; 1973 int i; 1974 for (i = 0; i < 8; i++) { 1975 b = tmp[i]; 1976 tmp[i] = tmp[15-i]; 1977 tmp[15-i] = b; 1978 } 1979 #endif 1980 } 1981 1982 static inline 1983 void nvme_health_information_page_swapbytes( 1984 struct nvme_health_information_page *s __unused) 1985 { 1986 #if _BYTE_ORDER != _LITTLE_ENDIAN 1987 int i; 1988 1989 s->temperature = le16toh(s->temperature); 1990 nvme_le128toh((void *)s->data_units_read); 1991 nvme_le128toh((void *)s->data_units_written); 1992 nvme_le128toh((void *)s->host_read_commands); 1993 nvme_le128toh((void *)s->host_write_commands); 1994 nvme_le128toh((void *)s->controller_busy_time); 1995 nvme_le128toh((void *)s->power_cycles); 1996 nvme_le128toh((void *)s->power_on_hours); 1997 nvme_le128toh((void *)s->unsafe_shutdowns); 1998 nvme_le128toh((void *)s->media_errors); 1999 nvme_le128toh((void *)s->num_error_info_log_entries); 2000 s->warning_temp_time = le32toh(s->warning_temp_time); 2001 s->error_temp_time = le32toh(s->error_temp_time); 2002 for (i = 0; i < 8; i++) 2003 s->temp_sensor[i] = le16toh(s->temp_sensor[i]); 2004 s->tmt1tc = le32toh(s->tmt1tc); 2005 s->tmt2tc = le32toh(s->tmt2tc); 2006 s->ttftmt1 = le32toh(s->ttftmt1); 2007 s->ttftmt2 = le32toh(s->ttftmt2); 2008 #endif 2009 } 2010 2011 static inline 2012 void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused) 2013 { 2014 #if _BYTE_ORDER != _LITTLE_ENDIAN 2015 int i; 2016 2017 for (i = 0; i < 1024; i++) 2018 s->ns[i] = le32toh(s->ns[i]); 2019 #endif 2020 } 2021 2022 static inline 2023 void nvme_command_effects_page_swapbytes( 2024 struct nvme_command_effects_page *s __unused) 2025 { 2026 #if _BYTE_ORDER != _LITTLE_ENDIAN 2027 int i; 2028 2029 for (i = 0; i < 256; i++) 2030 s->acs[i] = le32toh(s->acs[i]); 2031 for (i = 0; i < 256; i++) 2032 s->iocs[i] = le32toh(s->iocs[i]); 2033 #endif 2034 } 2035 2036 static inline 2037 void nvme_res_notification_page_swapbytes( 2038 struct nvme_res_notification_page *s __unused) 2039 { 2040 #if _BYTE_ORDER != _LITTLE_ENDIAN 2041 s->log_page_count = le64toh(s->log_page_count); 2042 s->nsid = le32toh(s->nsid); 2043 #endif 2044 } 2045 2046 static inline 2047 void nvme_sanitize_status_page_swapbytes( 2048 struct nvme_sanitize_status_page *s __unused) 2049 { 2050 #if _BYTE_ORDER != _LITTLE_ENDIAN 2051 s->sprog = le16toh(s->sprog); 2052 s->sstat = le16toh(s->sstat); 2053 s->scdw10 = le32toh(s->scdw10); 2054 s->etfo = le32toh(s->etfo); 2055 s->etfbe = le32toh(s->etfbe); 2056 s->etfce = le32toh(s->etfce); 2057 s->etfownd = le32toh(s->etfownd); 2058 s->etfbewnd = le32toh(s->etfbewnd); 2059 s->etfcewnd = le32toh(s->etfcewnd); 2060 #endif 2061 } 2062 2063 static inline 2064 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s __unused) 2065 { 2066 #if _BYTE_ORDER != _LITTLE_ENDIAN 2067 2068 s->current = le64toh(s->current); 2069 s->overtemp_flag_last = le64toh(s->overtemp_flag_last); 2070 s->overtemp_flag_life = le64toh(s->overtemp_flag_life); 2071 s->max_temp = le64toh(s->max_temp); 2072 s->min_temp = le64toh(s->min_temp); 2073 /* omit _rsvd[] */ 2074 s->max_oper_temp = le64toh(s->max_oper_temp); 2075 s->min_oper_temp = le64toh(s->min_oper_temp); 2076 s->est_offset = le64toh(s->est_offset); 2077 #endif 2078 } 2079 2080 static inline 2081 void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused, 2082 size_t size __unused) 2083 { 2084 #if _BYTE_ORDER != _LITTLE_ENDIAN 2085 size_t i, n; 2086 2087 s->gen = le32toh(s->gen); 2088 n = (s->regctl[1] << 8) | s->regctl[0]; 2089 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0])); 2090 for (i = 0; i < n; i++) { 2091 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id); 2092 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid); 2093 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey); 2094 } 2095 #endif 2096 } 2097 2098 static inline 2099 void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused, 2100 size_t size __unused) 2101 { 2102 #if _BYTE_ORDER != _LITTLE_ENDIAN 2103 size_t i, n; 2104 2105 s->gen = le32toh(s->gen); 2106 n = (s->regctl[1] << 8) | s->regctl[0]; 2107 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0])); 2108 for (i = 0; i < n; i++) { 2109 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id); 2110 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey); 2111 nvme_le128toh((void *)s->ctrlr[i].hostid); 2112 } 2113 #endif 2114 } 2115 2116 static inline void 2117 nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused) 2118 { 2119 #if _BYTE_ORDER != _LITTLE_ENDIAN 2120 uint8_t *tmp; 2121 uint32_t r, i; 2122 uint8_t b; 2123 2124 for (r = 0; r < 20; r++) { 2125 s->result[r].poh = le64toh(s->result[r].poh); 2126 s->result[r].nsid = le32toh(s->result[r].nsid); 2127 /* Unaligned 64-bit loads fail on some architectures */ 2128 tmp = s->result[r].failing_lba; 2129 for (i = 0; i < 4; i++) { 2130 b = tmp[i]; 2131 tmp[i] = tmp[7-i]; 2132 tmp[7-i] = b; 2133 } 2134 } 2135 #endif 2136 } 2137 #endif /* __NVME_H__ */ 2138