1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_H__ 32 #define __NVME_H__ 33 34 #ifdef _KERNEL 35 #include <sys/types.h> 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/endian.h> 40 41 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 42 #define NVME_RESET_CONTROLLER _IO('n', 1) 43 44 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 45 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 46 47 /* 48 * Macros to deal with NVME revisions, as defined VS register 49 */ 50 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 51 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 52 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 53 54 /* 55 * Use to mark a command to apply to all namespaces, or to retrieve global 56 * log pages. 57 */ 58 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 59 60 /* Cap nvme to 1MB transfers driver explodes with larger sizes */ 61 #define NVME_MAX_XFER_SIZE (MAXPHYS < (1<<20) ? MAXPHYS : (1<<20)) 62 63 /* Register field definitions */ 64 #define NVME_CAP_LO_REG_MQES_SHIFT (0) 65 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 66 #define NVME_CAP_LO_REG_CQR_SHIFT (16) 67 #define NVME_CAP_LO_REG_CQR_MASK (0x1) 68 #define NVME_CAP_LO_REG_AMS_SHIFT (17) 69 #define NVME_CAP_LO_REG_AMS_MASK (0x3) 70 #define NVME_CAP_LO_REG_TO_SHIFT (24) 71 #define NVME_CAP_LO_REG_TO_MASK (0xFF) 72 #define NVME_CAP_LO_MQES(x) \ 73 (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK) 74 #define NVME_CAP_LO_CQR(x) \ 75 (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK) 76 #define NVME_CAP_LO_AMS(x) \ 77 (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK) 78 #define NVME_CAP_LO_TO(x) \ 79 (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK) 80 81 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0) 82 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF) 83 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5) 84 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1) 85 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16) 86 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF) 87 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20) 88 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF) 89 #define NVME_CAP_HI_DSTRD(x) \ 90 (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK) 91 #define NVME_CAP_HI_CSS_NVM(x) \ 92 (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK) 93 #define NVME_CAP_HI_MPSMIN(x) \ 94 (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK) 95 #define NVME_CAP_HI_MPSMAX(x) \ 96 (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK) 97 98 #define NVME_CC_REG_EN_SHIFT (0) 99 #define NVME_CC_REG_EN_MASK (0x1) 100 #define NVME_CC_REG_CSS_SHIFT (4) 101 #define NVME_CC_REG_CSS_MASK (0x7) 102 #define NVME_CC_REG_MPS_SHIFT (7) 103 #define NVME_CC_REG_MPS_MASK (0xF) 104 #define NVME_CC_REG_AMS_SHIFT (11) 105 #define NVME_CC_REG_AMS_MASK (0x7) 106 #define NVME_CC_REG_SHN_SHIFT (14) 107 #define NVME_CC_REG_SHN_MASK (0x3) 108 #define NVME_CC_REG_IOSQES_SHIFT (16) 109 #define NVME_CC_REG_IOSQES_MASK (0xF) 110 #define NVME_CC_REG_IOCQES_SHIFT (20) 111 #define NVME_CC_REG_IOCQES_MASK (0xF) 112 113 #define NVME_CSTS_REG_RDY_SHIFT (0) 114 #define NVME_CSTS_REG_RDY_MASK (0x1) 115 #define NVME_CSTS_REG_CFS_SHIFT (1) 116 #define NVME_CSTS_REG_CFS_MASK (0x1) 117 #define NVME_CSTS_REG_SHST_SHIFT (2) 118 #define NVME_CSTS_REG_SHST_MASK (0x3) 119 120 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK) 121 122 #define NVME_AQA_REG_ASQS_SHIFT (0) 123 #define NVME_AQA_REG_ASQS_MASK (0xFFF) 124 #define NVME_AQA_REG_ACQS_SHIFT (16) 125 #define NVME_AQA_REG_ACQS_MASK (0xFFF) 126 127 /* Command field definitions */ 128 129 #define NVME_CMD_FUSE_SHIFT (8) 130 #define NVME_CMD_FUSE_MASK (0x3) 131 132 #define NVME_STATUS_P_SHIFT (0) 133 #define NVME_STATUS_P_MASK (0x1) 134 #define NVME_STATUS_SC_SHIFT (1) 135 #define NVME_STATUS_SC_MASK (0xFF) 136 #define NVME_STATUS_SCT_SHIFT (9) 137 #define NVME_STATUS_SCT_MASK (0x7) 138 #define NVME_STATUS_M_SHIFT (14) 139 #define NVME_STATUS_M_MASK (0x1) 140 #define NVME_STATUS_DNR_SHIFT (15) 141 #define NVME_STATUS_DNR_MASK (0x1) 142 143 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 144 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 145 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) 146 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 147 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 148 149 #define NVME_PWR_ST_MPS_SHIFT (0) 150 #define NVME_PWR_ST_MPS_MASK (0x1) 151 #define NVME_PWR_ST_NOPS_SHIFT (1) 152 #define NVME_PWR_ST_NOPS_MASK (0x1) 153 #define NVME_PWR_ST_RRT_SHIFT (0) 154 #define NVME_PWR_ST_RRT_MASK (0x1F) 155 #define NVME_PWR_ST_RRL_SHIFT (0) 156 #define NVME_PWR_ST_RRL_MASK (0x1F) 157 #define NVME_PWR_ST_RWT_SHIFT (0) 158 #define NVME_PWR_ST_RWT_MASK (0x1F) 159 #define NVME_PWR_ST_RWL_SHIFT (0) 160 #define NVME_PWR_ST_RWL_MASK (0x1F) 161 #define NVME_PWR_ST_IPS_SHIFT (6) 162 #define NVME_PWR_ST_IPS_MASK (0x3) 163 #define NVME_PWR_ST_APW_SHIFT (0) 164 #define NVME_PWR_ST_APW_MASK (0x7) 165 #define NVME_PWR_ST_APS_SHIFT (6) 166 #define NVME_PWR_ST_APS_MASK (0x3) 167 168 /** Controller Multi-path I/O and Namespace Sharing Capabilities */ 169 /* More then one port */ 170 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0) 171 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1) 172 /* More then one controller */ 173 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1) 174 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1) 175 /* SR-IOV Virtual Function */ 176 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2) 177 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1) 178 179 /** OACS - optional admin command support */ 180 /* supports security send/receive commands */ 181 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0) 182 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1) 183 /* supports format nvm command */ 184 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1) 185 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1) 186 /* supports firmware activate/download commands */ 187 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2) 188 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1) 189 /* supports namespace management commands */ 190 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3) 191 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1) 192 /* supports Device Self-test command */ 193 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4) 194 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1) 195 /* supports Directives */ 196 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5) 197 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1) 198 /* supports NVMe-MI Send/Receive */ 199 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6) 200 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1) 201 /* supports Virtualization Management */ 202 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7) 203 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1) 204 /* supports Doorbell Buffer Config */ 205 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8) 206 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1) 207 208 /** firmware updates */ 209 /* first slot is read-only */ 210 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0) 211 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1) 212 /* number of firmware slots */ 213 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1) 214 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7) 215 216 /** log page attributes */ 217 /* per namespace smart/health log page */ 218 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0) 219 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1) 220 221 /** AVSCC - admin vendor specific command configuration */ 222 /* admin vendor specific commands use spec format */ 223 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0) 224 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1) 225 226 /** Autonomous Power State Transition Attributes */ 227 /* Autonomous Power State Transitions supported */ 228 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0) 229 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1) 230 231 /** submission queue entry size */ 232 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0) 233 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF) 234 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4) 235 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF) 236 237 /** completion queue entry size */ 238 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0) 239 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF) 240 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4) 241 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF) 242 243 /** optional nvm command support */ 244 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0) 245 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1) 246 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1) 247 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1) 248 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2) 249 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1) 250 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3) 251 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1) 252 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4) 253 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1) 254 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5) 255 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1) 256 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6) 257 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1) 258 259 /** Fused Operation Support */ 260 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0) 261 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1) 262 263 /** Format NVM Attributes */ 264 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0) 265 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1) 266 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1) 267 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1) 268 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2) 269 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1) 270 271 /** volatile write cache */ 272 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0) 273 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1) 274 275 /** namespace features */ 276 /* thin provisioning */ 277 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0) 278 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1) 279 /* NAWUN, NAWUPF, and NACWU fields are valid */ 280 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1) 281 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1) 282 /* Deallocated or Unwritten Logical Block errors supported */ 283 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2) 284 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1) 285 /* NGUID and EUI64 fields are not reusable */ 286 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3) 287 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1) 288 289 /** formatted lba size */ 290 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0) 291 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF) 292 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4) 293 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1) 294 295 /** metadata capabilities */ 296 /* metadata can be transferred as part of data prp list */ 297 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0) 298 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1) 299 /* metadata can be transferred with separate metadata pointer */ 300 #define NVME_NS_DATA_MC_POINTER_SHIFT (1) 301 #define NVME_NS_DATA_MC_POINTER_MASK (0x1) 302 303 /** end-to-end data protection capabilities */ 304 /* protection information type 1 */ 305 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0) 306 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1) 307 /* protection information type 2 */ 308 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1) 309 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1) 310 /* protection information type 3 */ 311 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2) 312 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1) 313 /* first eight bytes of metadata */ 314 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3) 315 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1) 316 /* last eight bytes of metadata */ 317 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4) 318 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1) 319 320 /** end-to-end data protection type settings */ 321 /* protection information type */ 322 #define NVME_NS_DATA_DPS_PIT_SHIFT (0) 323 #define NVME_NS_DATA_DPS_PIT_MASK (0x7) 324 /* 1 == protection info transferred at start of metadata */ 325 /* 0 == protection info transferred at end of metadata */ 326 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3) 327 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1) 328 329 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 330 /* the namespace may be attached to two or more controllers */ 331 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0) 332 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1) 333 334 /** Reservation Capabilities */ 335 /* Persist Through Power Loss */ 336 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0) 337 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1) 338 /* supports the Write Exclusive */ 339 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1) 340 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1) 341 /* supports the Exclusive Access */ 342 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2) 343 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1) 344 /* supports the Write Exclusive – Registrants Only */ 345 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3) 346 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1) 347 /* supports the Exclusive Access - Registrants Only */ 348 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4) 349 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1) 350 /* supports the Write Exclusive – All Registrants */ 351 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5) 352 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1) 353 /* supports the Exclusive Access - All Registrants */ 354 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6) 355 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1) 356 /* Ignore Existing Key is used as defined in revision 1.3 or later */ 357 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7) 358 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1) 359 360 /** Format Progress Indicator */ 361 /* percentage of the Format NVM command that remains to be completed */ 362 #define NVME_NS_DATA_FPI_PERC_SHIFT (0) 363 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f) 364 /* namespace supports the Format Progress Indicator */ 365 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7) 366 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1) 367 368 /** Deallocate Logical Block Features */ 369 /* deallocated logical block read behavior */ 370 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0) 371 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07) 372 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00) 373 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01) 374 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02) 375 /* supports the Deallocate bit in the Write Zeroes */ 376 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3) 377 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01) 378 /* Guard field for deallocated logical blocks is set to the CRC */ 379 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4) 380 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01) 381 382 /** lba format support */ 383 /* metadata size */ 384 #define NVME_NS_DATA_LBAF_MS_SHIFT (0) 385 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF) 386 /* lba data size */ 387 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16) 388 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF) 389 /* relative performance */ 390 #define NVME_NS_DATA_LBAF_RP_SHIFT (24) 391 #define NVME_NS_DATA_LBAF_RP_MASK (0x3) 392 393 enum nvme_critical_warning_state { 394 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1, 395 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2, 396 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4, 397 NVME_CRIT_WARN_ST_READ_ONLY = 0x8, 398 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10, 399 }; 400 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0) 401 402 /* slot for current FW */ 403 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0) 404 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7) 405 406 /* CC register SHN field values */ 407 enum shn_value { 408 NVME_SHN_NORMAL = 0x1, 409 NVME_SHN_ABRUPT = 0x2, 410 }; 411 412 /* CSTS register SHST field values */ 413 enum shst_value { 414 NVME_SHST_NORMAL = 0x0, 415 NVME_SHST_OCCURRING = 0x1, 416 NVME_SHST_COMPLETE = 0x2, 417 }; 418 419 struct nvme_registers 420 { 421 /** controller capabilities */ 422 uint32_t cap_lo; 423 uint32_t cap_hi; 424 425 uint32_t vs; /* version */ 426 uint32_t intms; /* interrupt mask set */ 427 uint32_t intmc; /* interrupt mask clear */ 428 429 /** controller configuration */ 430 uint32_t cc; 431 432 uint32_t reserved1; 433 434 /** controller status */ 435 uint32_t csts; 436 437 uint32_t reserved2; 438 439 /** admin queue attributes */ 440 uint32_t aqa; 441 442 uint64_t asq; /* admin submission queue base addr */ 443 uint64_t acq; /* admin completion queue base addr */ 444 uint32_t reserved3[0x3f2]; 445 446 struct { 447 uint32_t sq_tdbl; /* submission queue tail doorbell */ 448 uint32_t cq_hdbl; /* completion queue head doorbell */ 449 } doorbell[1] __packed; 450 } __packed; 451 452 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 453 454 struct nvme_command 455 { 456 /* dword 0 */ 457 uint8_t opc; /* opcode */ 458 uint8_t fuse; /* fused operation */ 459 uint16_t cid; /* command identifier */ 460 461 /* dword 1 */ 462 uint32_t nsid; /* namespace identifier */ 463 464 /* dword 2-3 */ 465 uint32_t rsvd2; 466 uint32_t rsvd3; 467 468 /* dword 4-5 */ 469 uint64_t mptr; /* metadata pointer */ 470 471 /* dword 6-7 */ 472 uint64_t prp1; /* prp entry 1 */ 473 474 /* dword 8-9 */ 475 uint64_t prp2; /* prp entry 2 */ 476 477 /* dword 10-15 */ 478 uint32_t cdw10; /* command-specific */ 479 uint32_t cdw11; /* command-specific */ 480 uint32_t cdw12; /* command-specific */ 481 uint32_t cdw13; /* command-specific */ 482 uint32_t cdw14; /* command-specific */ 483 uint32_t cdw15; /* command-specific */ 484 } __packed; 485 486 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 487 488 struct nvme_completion { 489 490 /* dword 0 */ 491 uint32_t cdw0; /* command-specific */ 492 493 /* dword 1 */ 494 uint32_t rsvd1; 495 496 /* dword 2 */ 497 uint16_t sqhd; /* submission queue head pointer */ 498 uint16_t sqid; /* submission queue identifier */ 499 500 /* dword 3 */ 501 uint16_t cid; /* command identifier */ 502 uint16_t status; 503 } __packed; 504 505 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 506 507 struct nvme_dsm_range { 508 uint32_t attributes; 509 uint32_t length; 510 uint64_t starting_lba; 511 } __packed; 512 513 /* Largest DSM Trim that can be done */ 514 #define NVME_MAX_DSM_TRIM 4096 515 516 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 517 518 /* status code types */ 519 enum nvme_status_code_type { 520 NVME_SCT_GENERIC = 0x0, 521 NVME_SCT_COMMAND_SPECIFIC = 0x1, 522 NVME_SCT_MEDIA_ERROR = 0x2, 523 /* 0x3-0x6 - reserved */ 524 NVME_SCT_VENDOR_SPECIFIC = 0x7, 525 }; 526 527 /* generic command status codes */ 528 enum nvme_generic_command_status_code { 529 NVME_SC_SUCCESS = 0x00, 530 NVME_SC_INVALID_OPCODE = 0x01, 531 NVME_SC_INVALID_FIELD = 0x02, 532 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 533 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 534 NVME_SC_ABORTED_POWER_LOSS = 0x05, 535 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 536 NVME_SC_ABORTED_BY_REQUEST = 0x07, 537 NVME_SC_ABORTED_SQ_DELETION = 0x08, 538 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 539 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 540 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 541 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 542 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 543 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 544 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 545 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 546 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 547 NVME_SC_INVALID_USE_OF_CMB = 0x12, 548 NVME_SC_PRP_OFFET_INVALID = 0x13, 549 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 550 NVME_SC_OPERATION_DENIED = 0x15, 551 NVME_SC_SGL_OFFSET_INVALID = 0x16, 552 /* 0x17 - reserved */ 553 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 554 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 555 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 556 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 557 NVME_SC_SANITIZE_FAILED = 0x1c, 558 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 559 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 560 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 561 562 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 563 NVME_SC_CAPACITY_EXCEEDED = 0x81, 564 NVME_SC_NAMESPACE_NOT_READY = 0x82, 565 NVME_SC_RESERVATION_CONFLICT = 0x83, 566 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 567 }; 568 569 /* command specific status codes */ 570 enum nvme_command_specific_status_code { 571 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 572 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 573 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 574 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 575 /* 0x04 - reserved */ 576 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 577 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 578 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 579 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 580 NVME_SC_INVALID_LOG_PAGE = 0x09, 581 NVME_SC_INVALID_FORMAT = 0x0a, 582 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 583 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 584 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 585 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 586 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 587 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 588 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 589 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 590 NVME_SC_FW_ACT_PROHIBITED = 0x13, 591 NVME_SC_OVERLAPPING_RANGE = 0x14, 592 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 593 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 594 /* 0x17 - reserved */ 595 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 596 NVME_SC_NS_IS_PRIVATE = 0x19, 597 NVME_SC_NS_NOT_ATTACHED = 0x1a, 598 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 599 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 600 NVME_SC_SELT_TEST_IN_PROGRESS = 0x1d, 601 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 602 NVME_SC_INVALID_CTRLR_ID = 0x1f, 603 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 604 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 605 NVME_SC_INVALID_RESOURCE_ID = 0x22, 606 607 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 608 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 609 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 610 }; 611 612 /* media error status codes */ 613 enum nvme_media_error_status_code { 614 NVME_SC_WRITE_FAULTS = 0x80, 615 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 616 NVME_SC_GUARD_CHECK_ERROR = 0x82, 617 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 618 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 619 NVME_SC_COMPARE_FAILURE = 0x85, 620 NVME_SC_ACCESS_DENIED = 0x86, 621 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 622 }; 623 624 /* admin opcodes */ 625 enum nvme_admin_opcode { 626 NVME_OPC_DELETE_IO_SQ = 0x00, 627 NVME_OPC_CREATE_IO_SQ = 0x01, 628 NVME_OPC_GET_LOG_PAGE = 0x02, 629 /* 0x03 - reserved */ 630 NVME_OPC_DELETE_IO_CQ = 0x04, 631 NVME_OPC_CREATE_IO_CQ = 0x05, 632 NVME_OPC_IDENTIFY = 0x06, 633 /* 0x07 - reserved */ 634 NVME_OPC_ABORT = 0x08, 635 NVME_OPC_SET_FEATURES = 0x09, 636 NVME_OPC_GET_FEATURES = 0x0a, 637 /* 0x0b - reserved */ 638 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 639 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 640 /* 0x0e-0x0f - reserved */ 641 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 642 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 643 NVME_OPC_DEVICE_SELF_TEST = 0x14, 644 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 645 NVME_OPC_KEEP_ALIVE = 0x18, 646 NVME_OPC_DIRECTIVE_SEND = 0x19, 647 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 648 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 649 NVME_OPC_NVME_MI_SEND = 0x1d, 650 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 651 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 652 653 NVME_OPC_FORMAT_NVM = 0x80, 654 NVME_OPC_SECURITY_SEND = 0x81, 655 NVME_OPC_SECURITY_RECEIVE = 0x82, 656 NVME_OPC_SANITIZE = 0x84, 657 }; 658 659 /* nvme nvm opcodes */ 660 enum nvme_nvm_opcode { 661 NVME_OPC_FLUSH = 0x00, 662 NVME_OPC_WRITE = 0x01, 663 NVME_OPC_READ = 0x02, 664 /* 0x03 - reserved */ 665 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 666 NVME_OPC_COMPARE = 0x05, 667 /* 0x06 - reserved */ 668 NVME_OPC_WRITE_ZEROES = 0x08, 669 /* 0x07 - reserved */ 670 NVME_OPC_DATASET_MANAGEMENT = 0x09, 671 /* 0x0a-0x0c - reserved */ 672 NVME_OPC_RESERVATION_REGISTER = 0x0d, 673 NVME_OPC_RESERVATION_REPORT = 0x0e, 674 /* 0x0f-0x10 - reserved */ 675 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 676 /* 0x12-0x14 - reserved */ 677 NVME_OPC_RESERVATION_RELEASE = 0x15, 678 }; 679 680 enum nvme_feature { 681 /* 0x00 - reserved */ 682 NVME_FEAT_ARBITRATION = 0x01, 683 NVME_FEAT_POWER_MANAGEMENT = 0x02, 684 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 685 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 686 NVME_FEAT_ERROR_RECOVERY = 0x05, 687 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 688 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 689 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 690 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 691 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 692 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 693 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 694 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 695 NVME_FEAT_TIMESTAMP = 0x0E, 696 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 697 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 698 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 699 /* 0x12-0x77 - reserved */ 700 /* 0x78-0x7f - NVMe Management Interface */ 701 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 702 /* 0x81-0xBF - command set specific (reserved) */ 703 /* 0xC0-0xFF - vendor specific */ 704 }; 705 706 enum nvme_dsm_attribute { 707 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 708 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 709 NVME_DSM_ATTR_DEALLOCATE = 0x4, 710 }; 711 712 enum nvme_activate_action { 713 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 714 NVME_AA_REPLACE_ACTIVATE = 0x1, 715 NVME_AA_ACTIVATE = 0x2, 716 }; 717 718 struct nvme_power_state { 719 /** Maximum Power */ 720 uint16_t mp; /* Maximum Power */ 721 uint8_t ps_rsvd1; 722 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */ 723 724 uint32_t enlat; /* Entry Latency */ 725 uint32_t exlat; /* Exit Latency */ 726 727 uint8_t rrt; /* Relative Read Throughput */ 728 uint8_t rrl; /* Relative Read Latency */ 729 uint8_t rwt; /* Relative Write Throughput */ 730 uint8_t rwl; /* Relative Write Latency */ 731 732 uint16_t idlp; /* Idle Power */ 733 uint8_t ips; /* Idle Power Scale */ 734 uint8_t ps_rsvd8; 735 736 uint16_t actp; /* Active Power */ 737 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ 738 uint8_t ps_rsvd10[9]; 739 } __packed; 740 741 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 742 743 #define NVME_SERIAL_NUMBER_LENGTH 20 744 #define NVME_MODEL_NUMBER_LENGTH 40 745 #define NVME_FIRMWARE_REVISION_LENGTH 8 746 747 struct nvme_controller_data { 748 749 /* bytes 0-255: controller capabilities and features */ 750 751 /** pci vendor id */ 752 uint16_t vid; 753 754 /** pci subsystem vendor id */ 755 uint16_t ssvid; 756 757 /** serial number */ 758 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 759 760 /** model number */ 761 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 762 763 /** firmware revision */ 764 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 765 766 /** recommended arbitration burst */ 767 uint8_t rab; 768 769 /** ieee oui identifier */ 770 uint8_t ieee[3]; 771 772 /** multi-interface capabilities */ 773 uint8_t mic; 774 775 /** maximum data transfer size */ 776 uint8_t mdts; 777 778 /** Controller ID */ 779 uint16_t ctrlr_id; 780 781 /** Version */ 782 uint32_t ver; 783 784 /** RTD3 Resume Latency */ 785 uint32_t rtd3r; 786 787 /** RTD3 Enter Latency */ 788 uint32_t rtd3e; 789 790 /** Optional Asynchronous Events Supported */ 791 uint32_t oaes; /* bitfield really */ 792 793 /** Controller Attributes */ 794 uint32_t ctratt; /* bitfield really */ 795 796 uint8_t reserved1[12]; 797 798 /** FRU Globally Unique Identifier */ 799 uint8_t fguid[16]; 800 801 uint8_t reserved2[128]; 802 803 /* bytes 256-511: admin command set attributes */ 804 805 /** optional admin command support */ 806 uint16_t oacs; 807 808 /** abort command limit */ 809 uint8_t acl; 810 811 /** asynchronous event request limit */ 812 uint8_t aerl; 813 814 /** firmware updates */ 815 uint8_t frmw; 816 817 /** log page attributes */ 818 uint8_t lpa; 819 820 /** error log page entries */ 821 uint8_t elpe; 822 823 /** number of power states supported */ 824 uint8_t npss; 825 826 /** admin vendor specific command configuration */ 827 uint8_t avscc; 828 829 /** Autonomous Power State Transition Attributes */ 830 uint8_t apsta; 831 832 /** Warning Composite Temperature Threshold */ 833 uint16_t wctemp; 834 835 /** Critical Composite Temperature Threshold */ 836 uint16_t cctemp; 837 838 /** Maximum Time for Firmware Activation */ 839 uint16_t mtfa; 840 841 /** Host Memory Buffer Preferred Size */ 842 uint32_t hmpre; 843 844 /** Host Memory Buffer Minimum Size */ 845 uint32_t hmmin; 846 847 /** Name space capabilities */ 848 struct { 849 /* if nsmgmt, report tnvmcap and unvmcap */ 850 uint8_t tnvmcap[16]; 851 uint8_t unvmcap[16]; 852 } __packed untncap; 853 854 /** Replay Protected Memory Block Support */ 855 uint32_t rpmbs; /* Really a bitfield */ 856 857 /** Extended Device Self-test Time */ 858 uint16_t edstt; 859 860 /** Device Self-test Options */ 861 uint8_t dsto; /* Really a bitfield */ 862 863 /** Firmware Update Granularity */ 864 uint8_t fwug; 865 866 /** Keep Alive Support */ 867 uint16_t kas; 868 869 /** Host Controlled Thermal Management Attributes */ 870 uint16_t hctma; /* Really a bitfield */ 871 872 /** Minimum Thermal Management Temperature */ 873 uint16_t mntmt; 874 875 /** Maximum Thermal Management Temperature */ 876 uint16_t mxtmt; 877 878 /** Sanitize Capabilities */ 879 uint32_t sanicap; /* Really a bitfield */ 880 881 uint8_t reserved3[180]; 882 /* bytes 512-703: nvm command set attributes */ 883 884 /** submission queue entry size */ 885 uint8_t sqes; 886 887 /** completion queue entry size */ 888 uint8_t cqes; 889 890 /** Maximum Outstanding Commands */ 891 uint16_t maxcmd; 892 893 /** number of namespaces */ 894 uint32_t nn; 895 896 /** optional nvm command support */ 897 uint16_t oncs; 898 899 /** fused operation support */ 900 uint16_t fuses; 901 902 /** format nvm attributes */ 903 uint8_t fna; 904 905 /** volatile write cache */ 906 uint8_t vwc; 907 908 /** Atomic Write Unit Normal */ 909 uint16_t awun; 910 911 /** Atomic Write Unit Power Fail */ 912 uint16_t awupf; 913 914 /** NVM Vendor Specific Command Configuration */ 915 uint8_t nvscc; 916 uint8_t reserved5; 917 918 /** Atomic Compare & Write Unit */ 919 uint16_t acwu; 920 uint16_t reserved6; 921 922 /** SGL Support */ 923 uint32_t sgls; 924 925 /* bytes 540-767: Reserved */ 926 uint8_t reserved7[228]; 927 928 /** NVM Subsystem NVMe Qualified Name */ 929 uint8_t subnqn[256]; 930 931 /* bytes 1024-1791: Reserved */ 932 uint8_t reserved8[768]; 933 934 /* bytes 1792-2047: NVMe over Fabrics specification */ 935 uint8_t reserved9[256]; 936 937 /* bytes 2048-3071: power state descriptors */ 938 struct nvme_power_state power_state[32]; 939 940 /* bytes 3072-4095: vendor specific */ 941 uint8_t vs[1024]; 942 } __packed __aligned(4); 943 944 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 945 946 struct nvme_namespace_data { 947 948 /** namespace size */ 949 uint64_t nsze; 950 951 /** namespace capacity */ 952 uint64_t ncap; 953 954 /** namespace utilization */ 955 uint64_t nuse; 956 957 /** namespace features */ 958 uint8_t nsfeat; 959 960 /** number of lba formats */ 961 uint8_t nlbaf; 962 963 /** formatted lba size */ 964 uint8_t flbas; 965 966 /** metadata capabilities */ 967 uint8_t mc; 968 969 /** end-to-end data protection capabilities */ 970 uint8_t dpc; 971 972 /** end-to-end data protection type settings */ 973 uint8_t dps; 974 975 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 976 uint8_t nmic; 977 978 /** Reservation Capabilities */ 979 uint8_t rescap; 980 981 /** Format Progress Indicator */ 982 uint8_t fpi; 983 984 /** Deallocate Logical Block Features */ 985 uint8_t dlfeat; 986 987 /** Namespace Atomic Write Unit Normal */ 988 uint16_t nawun; 989 990 /** Namespace Atomic Write Unit Power Fail */ 991 uint16_t nawupf; 992 993 /** Namespace Atomic Compare & Write Unit */ 994 uint16_t nacwu; 995 996 /** Namespace Atomic Boundary Size Normal */ 997 uint16_t nabsn; 998 999 /** Namespace Atomic Boundary Offset */ 1000 uint16_t nabo; 1001 1002 /** Namespace Atomic Boundary Size Power Fail */ 1003 uint16_t nabspf; 1004 1005 /** Namespace Optimal IO Boundary */ 1006 uint16_t noiob; 1007 1008 /** NVM Capacity */ 1009 uint8_t nvmcap[16]; 1010 1011 /* bytes 64-103: Reserved */ 1012 uint8_t reserved5[40]; 1013 1014 /** Namespace Globally Unique Identifier */ 1015 uint8_t nguid[16]; 1016 1017 /** IEEE Extended Unique Identifier */ 1018 uint8_t eui64[8]; 1019 1020 /** lba format support */ 1021 uint32_t lbaf[16]; 1022 1023 uint8_t reserved6[192]; 1024 1025 uint8_t vendor_specific[3712]; 1026 } __packed __aligned(4); 1027 1028 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 1029 1030 enum nvme_log_page { 1031 1032 /* 0x00 - reserved */ 1033 NVME_LOG_ERROR = 0x01, 1034 NVME_LOG_HEALTH_INFORMATION = 0x02, 1035 NVME_LOG_FIRMWARE_SLOT = 0x03, 1036 NVME_LOG_CHANGED_NAMESPACE = 0x04, 1037 NVME_LOG_COMMAND_EFFECT = 0x05, 1038 /* 0x06-0x7F - reserved */ 1039 /* 0x80-0xBF - I/O command set specific */ 1040 NVME_LOG_RES_NOTIFICATION = 0x80, 1041 /* 0xC0-0xFF - vendor specific */ 1042 1043 /* 1044 * The following are Intel Specific log pages, but they seem 1045 * to be widely implemented. 1046 */ 1047 INTEL_LOG_READ_LAT_LOG = 0xc1, 1048 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 1049 INTEL_LOG_TEMP_STATS = 0xc5, 1050 INTEL_LOG_ADD_SMART = 0xca, 1051 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 1052 1053 /* 1054 * HGST log page, with lots ofs sub pages. 1055 */ 1056 HGST_INFO_LOG = 0xc1, 1057 }; 1058 1059 struct nvme_error_information_entry { 1060 1061 uint64_t error_count; 1062 uint16_t sqid; 1063 uint16_t cid; 1064 uint16_t status; 1065 uint16_t error_location; 1066 uint64_t lba; 1067 uint32_t nsid; 1068 uint8_t vendor_specific; 1069 uint8_t reserved[35]; 1070 } __packed __aligned(4); 1071 1072 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 1073 1074 struct nvme_health_information_page { 1075 1076 uint8_t critical_warning; 1077 uint16_t temperature; 1078 uint8_t available_spare; 1079 uint8_t available_spare_threshold; 1080 uint8_t percentage_used; 1081 1082 uint8_t reserved[26]; 1083 1084 /* 1085 * Note that the following are 128-bit values, but are 1086 * defined as an array of 2 64-bit values. 1087 */ 1088 /* Data Units Read is always in 512-byte units. */ 1089 uint64_t data_units_read[2]; 1090 /* Data Units Written is always in 512-byte units. */ 1091 uint64_t data_units_written[2]; 1092 /* For NVM command set, this includes Compare commands. */ 1093 uint64_t host_read_commands[2]; 1094 uint64_t host_write_commands[2]; 1095 /* Controller Busy Time is reported in minutes. */ 1096 uint64_t controller_busy_time[2]; 1097 uint64_t power_cycles[2]; 1098 uint64_t power_on_hours[2]; 1099 uint64_t unsafe_shutdowns[2]; 1100 uint64_t media_errors[2]; 1101 uint64_t num_error_info_log_entries[2]; 1102 uint32_t warning_temp_time; 1103 uint32_t error_temp_time; 1104 uint16_t temp_sensor[8]; 1105 1106 uint8_t reserved2[296]; 1107 } __packed __aligned(4); 1108 1109 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 1110 1111 struct nvme_firmware_page { 1112 1113 uint8_t afi; 1114 uint8_t reserved[7]; 1115 uint64_t revision[7]; /* revisions for 7 slots */ 1116 uint8_t reserved2[448]; 1117 } __packed __aligned(4); 1118 1119 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 1120 1121 struct nvme_ns_list { 1122 uint32_t ns[1024]; 1123 } __packed __aligned(4); 1124 1125 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list"); 1126 1127 struct intel_log_temp_stats 1128 { 1129 uint64_t current; 1130 uint64_t overtemp_flag_last; 1131 uint64_t overtemp_flag_life; 1132 uint64_t max_temp; 1133 uint64_t min_temp; 1134 uint64_t _rsvd[5]; 1135 uint64_t max_oper_temp; 1136 uint64_t min_oper_temp; 1137 uint64_t est_offset; 1138 } __packed __aligned(4); 1139 1140 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 1141 1142 #define NVME_TEST_MAX_THREADS 128 1143 1144 struct nvme_io_test { 1145 1146 enum nvme_nvm_opcode opc; 1147 uint32_t size; 1148 uint32_t time; /* in seconds */ 1149 uint32_t num_threads; 1150 uint32_t flags; 1151 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 1152 }; 1153 1154 enum nvme_io_test_flags { 1155 1156 /* 1157 * Specifies whether dev_refthread/dev_relthread should be 1158 * called during NVME_BIO_TEST. Ignored for other test 1159 * types. 1160 */ 1161 NVME_TEST_FLAG_REFTHREAD = 0x1, 1162 }; 1163 1164 struct nvme_pt_command { 1165 1166 /* 1167 * cmd is used to specify a passthrough command to a controller or 1168 * namespace. 1169 * 1170 * The following fields from cmd may be specified by the caller: 1171 * * opc (opcode) 1172 * * nsid (namespace id) - for admin commands only 1173 * * cdw10-cdw15 1174 * 1175 * Remaining fields must be set to 0 by the caller. 1176 */ 1177 struct nvme_command cmd; 1178 1179 /* 1180 * cpl returns completion status for the passthrough command 1181 * specified by cmd. 1182 * 1183 * The following fields will be filled out by the driver, for 1184 * consumption by the caller: 1185 * * cdw0 1186 * * status (except for phase) 1187 * 1188 * Remaining fields will be set to 0 by the driver. 1189 */ 1190 struct nvme_completion cpl; 1191 1192 /* buf is the data buffer associated with this passthrough command. */ 1193 void * buf; 1194 1195 /* 1196 * len is the length of the data buffer associated with this 1197 * passthrough command. 1198 */ 1199 uint32_t len; 1200 1201 /* 1202 * is_read = 1 if the passthrough command will read data into the 1203 * supplied buffer from the controller. 1204 * 1205 * is_read = 0 if the passthrough command will write data from the 1206 * supplied buffer to the controller. 1207 */ 1208 uint32_t is_read; 1209 1210 /* 1211 * driver_lock is used by the driver only. It must be set to 0 1212 * by the caller. 1213 */ 1214 struct mtx * driver_lock; 1215 }; 1216 1217 #define nvme_completion_is_error(cpl) \ 1218 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0) 1219 1220 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1221 1222 #ifdef _KERNEL 1223 1224 struct bio; 1225 1226 struct nvme_namespace; 1227 struct nvme_controller; 1228 struct nvme_consumer; 1229 1230 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1231 1232 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1233 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1234 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1235 uint32_t, void *, uint32_t); 1236 typedef void (*nvme_cons_fail_fn_t)(void *); 1237 1238 enum nvme_namespace_flags { 1239 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1240 NVME_NS_FLUSH_SUPPORTED = 0x2, 1241 }; 1242 1243 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1244 struct nvme_pt_command *pt, 1245 uint32_t nsid, int is_user_buffer, 1246 int is_admin_cmd); 1247 1248 /* Admin functions */ 1249 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1250 uint8_t feature, uint32_t cdw11, 1251 void *payload, uint32_t payload_size, 1252 nvme_cb_fn_t cb_fn, void *cb_arg); 1253 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1254 uint8_t feature, uint32_t cdw11, 1255 void *payload, uint32_t payload_size, 1256 nvme_cb_fn_t cb_fn, void *cb_arg); 1257 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1258 uint8_t log_page, uint32_t nsid, 1259 void *payload, uint32_t payload_size, 1260 nvme_cb_fn_t cb_fn, void *cb_arg); 1261 1262 /* NVM I/O functions */ 1263 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1264 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1265 void *cb_arg); 1266 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1267 nvme_cb_fn_t cb_fn, void *cb_arg); 1268 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1269 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1270 void *cb_arg); 1271 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1272 nvme_cb_fn_t cb_fn, void *cb_arg); 1273 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1274 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1275 void *cb_arg); 1276 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1277 void *cb_arg); 1278 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1279 size_t len); 1280 1281 /* Registration functions */ 1282 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1283 nvme_cons_ctrlr_fn_t ctrlr_fn, 1284 nvme_cons_async_fn_t async_fn, 1285 nvme_cons_fail_fn_t fail_fn); 1286 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1287 1288 /* Controller helper functions */ 1289 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1290 const struct nvme_controller_data * 1291 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1292 static inline bool 1293 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd) 1294 { 1295 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */ 1296 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) & 1297 NVME_CTRLR_DATA_ONCS_DSM_MASK); 1298 } 1299 1300 /* Namespace helper functions */ 1301 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1302 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1303 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1304 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1305 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1306 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1307 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1308 const struct nvme_namespace_data * 1309 nvme_ns_get_data(struct nvme_namespace *ns); 1310 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1311 1312 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1313 nvme_cb_fn_t cb_fn); 1314 1315 /* 1316 * Command building helper functions -- shared with CAM 1317 * These functions assume allocator zeros out cmd structure 1318 * CAM's xpt_get_ccb and the request allocator for nvme both 1319 * do zero'd allocations. 1320 */ 1321 static inline 1322 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1323 { 1324 1325 cmd->opc = NVME_OPC_FLUSH; 1326 cmd->nsid = htole32(nsid); 1327 } 1328 1329 static inline 1330 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1331 uint64_t lba, uint32_t count) 1332 { 1333 cmd->opc = rwcmd; 1334 cmd->nsid = htole32(nsid); 1335 cmd->cdw10 = htole32(lba & 0xffffffffu); 1336 cmd->cdw11 = htole32(lba >> 32); 1337 cmd->cdw12 = htole32(count-1); 1338 } 1339 1340 static inline 1341 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1342 uint64_t lba, uint32_t count) 1343 { 1344 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1345 } 1346 1347 static inline 1348 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1349 uint64_t lba, uint32_t count) 1350 { 1351 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1352 } 1353 1354 static inline 1355 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1356 uint32_t num_ranges) 1357 { 1358 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1359 cmd->nsid = htole32(nsid); 1360 cmd->cdw10 = htole32(num_ranges - 1); 1361 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE); 1362 } 1363 1364 extern int nvme_use_nvd; 1365 1366 #endif /* _KERNEL */ 1367 1368 /* Endianess conversion functions for NVMe structs */ 1369 static inline 1370 void nvme_completion_swapbytes(struct nvme_completion *s) 1371 { 1372 1373 s->cdw0 = le32toh(s->cdw0); 1374 /* omit rsvd1 */ 1375 s->sqhd = le16toh(s->sqhd); 1376 s->sqid = le16toh(s->sqid); 1377 /* omit cid */ 1378 s->status = le16toh(s->status); 1379 } 1380 1381 static inline 1382 void nvme_power_state_swapbytes(struct nvme_power_state *s) 1383 { 1384 1385 s->mp = le16toh(s->mp); 1386 s->enlat = le32toh(s->enlat); 1387 s->exlat = le32toh(s->exlat); 1388 s->idlp = le16toh(s->idlp); 1389 s->actp = le16toh(s->actp); 1390 } 1391 1392 static inline 1393 void nvme_controller_data_swapbytes(struct nvme_controller_data *s) 1394 { 1395 int i; 1396 1397 s->vid = le16toh(s->vid); 1398 s->ssvid = le16toh(s->ssvid); 1399 s->ctrlr_id = le16toh(s->ctrlr_id); 1400 s->ver = le32toh(s->ver); 1401 s->rtd3r = le32toh(s->rtd3r); 1402 s->rtd3e = le32toh(s->rtd3e); 1403 s->oaes = le32toh(s->oaes); 1404 s->ctratt = le32toh(s->ctratt); 1405 s->oacs = le16toh(s->oacs); 1406 s->wctemp = le16toh(s->wctemp); 1407 s->cctemp = le16toh(s->cctemp); 1408 s->mtfa = le16toh(s->mtfa); 1409 s->hmpre = le32toh(s->hmpre); 1410 s->hmmin = le32toh(s->hmmin); 1411 s->rpmbs = le32toh(s->rpmbs); 1412 s->edstt = le16toh(s->edstt); 1413 s->kas = le16toh(s->kas); 1414 s->hctma = le16toh(s->hctma); 1415 s->mntmt = le16toh(s->mntmt); 1416 s->mxtmt = le16toh(s->mxtmt); 1417 s->sanicap = le32toh(s->sanicap); 1418 s->maxcmd = le16toh(s->maxcmd); 1419 s->nn = le32toh(s->nn); 1420 s->oncs = le16toh(s->oncs); 1421 s->fuses = le16toh(s->fuses); 1422 s->awun = le16toh(s->awun); 1423 s->awupf = le16toh(s->awupf); 1424 s->acwu = le16toh(s->acwu); 1425 s->sgls = le32toh(s->sgls); 1426 for (i = 0; i < 32; i++) 1427 nvme_power_state_swapbytes(&s->power_state[i]); 1428 } 1429 1430 static inline 1431 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s) 1432 { 1433 int i; 1434 1435 s->nsze = le64toh(s->nsze); 1436 s->ncap = le64toh(s->ncap); 1437 s->nuse = le64toh(s->nuse); 1438 s->nawun = le16toh(s->nawun); 1439 s->nawupf = le16toh(s->nawupf); 1440 s->nacwu = le16toh(s->nacwu); 1441 s->nabsn = le16toh(s->nabsn); 1442 s->nabo = le16toh(s->nabo); 1443 s->nabspf = le16toh(s->nabspf); 1444 s->noiob = le16toh(s->noiob); 1445 for (i = 0; i < 16; i++) 1446 s->lbaf[i] = le32toh(s->lbaf[i]); 1447 } 1448 1449 static inline 1450 void nvme_error_information_entry_swapbytes(struct nvme_error_information_entry *s) 1451 { 1452 1453 s->error_count = le64toh(s->error_count); 1454 s->sqid = le16toh(s->sqid); 1455 s->cid = le16toh(s->cid); 1456 s->status = le16toh(s->status); 1457 s->error_location = le16toh(s->error_location); 1458 s->lba = le64toh(s->lba); 1459 s->nsid = le32toh(s->nsid); 1460 } 1461 1462 static inline 1463 void nvme_le128toh(void *p) 1464 { 1465 #if _BYTE_ORDER != _LITTLE_ENDIAN 1466 /* Swap 16 bytes in place */ 1467 char *tmp = (char*)p; 1468 char b; 1469 int i; 1470 for (i = 0; i < 8; i++) { 1471 b = tmp[i]; 1472 tmp[i] = tmp[15-i]; 1473 tmp[15-i] = b; 1474 } 1475 #else 1476 (void)p; 1477 #endif 1478 } 1479 1480 static inline 1481 void nvme_health_information_page_swapbytes(struct nvme_health_information_page *s) 1482 { 1483 int i; 1484 1485 s->temperature = le16toh(s->temperature); 1486 nvme_le128toh((void *)s->data_units_read); 1487 nvme_le128toh((void *)s->data_units_written); 1488 nvme_le128toh((void *)s->host_read_commands); 1489 nvme_le128toh((void *)s->host_write_commands); 1490 nvme_le128toh((void *)s->controller_busy_time); 1491 nvme_le128toh((void *)s->power_cycles); 1492 nvme_le128toh((void *)s->power_on_hours); 1493 nvme_le128toh((void *)s->unsafe_shutdowns); 1494 nvme_le128toh((void *)s->media_errors); 1495 nvme_le128toh((void *)s->num_error_info_log_entries); 1496 s->warning_temp_time = le32toh(s->warning_temp_time); 1497 s->error_temp_time = le32toh(s->error_temp_time); 1498 for (i = 0; i < 8; i++) 1499 s->temp_sensor[i] = le16toh(s->temp_sensor[i]); 1500 } 1501 1502 1503 static inline 1504 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s) 1505 { 1506 int i; 1507 1508 for (i = 0; i < 7; i++) 1509 s->revision[i] = le64toh(s->revision[i]); 1510 } 1511 1512 static inline 1513 void nvme_ns_list_swapbytes(struct nvme_ns_list *s) 1514 { 1515 int i; 1516 1517 for (i = 0; i < 1024; i++) 1518 s->ns[i] = le32toh(s->ns[i]); 1519 } 1520 1521 static inline 1522 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s) 1523 { 1524 1525 s->current = le64toh(s->current); 1526 s->overtemp_flag_last = le64toh(s->overtemp_flag_last); 1527 s->overtemp_flag_life = le64toh(s->overtemp_flag_life); 1528 s->max_temp = le64toh(s->max_temp); 1529 s->min_temp = le64toh(s->min_temp); 1530 /* omit _rsvd[] */ 1531 s->max_oper_temp = le64toh(s->max_oper_temp); 1532 s->min_oper_temp = le64toh(s->min_oper_temp); 1533 s->est_offset = le64toh(s->est_offset); 1534 } 1535 1536 #endif /* __NVME_H__ */ 1537