1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_H__ 32 #define __NVME_H__ 33 34 #ifdef _KERNEL 35 #include <sys/types.h> 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/endian.h> 40 41 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 42 #define NVME_RESET_CONTROLLER _IO('n', 1) 43 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid) 44 45 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 46 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 47 48 /* 49 * Macros to deal with NVME revisions, as defined VS register 50 */ 51 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 52 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 53 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 54 55 /* 56 * Use to mark a command to apply to all namespaces, or to retrieve global 57 * log pages. 58 */ 59 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 60 61 /* Cap nvme to 1MB transfers driver explodes with larger sizes */ 62 #define NVME_MAX_XFER_SIZE (MAXPHYS < (1<<20) ? MAXPHYS : (1<<20)) 63 64 /* Register field definitions */ 65 #define NVME_CAP_LO_REG_MQES_SHIFT (0) 66 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 67 #define NVME_CAP_LO_REG_CQR_SHIFT (16) 68 #define NVME_CAP_LO_REG_CQR_MASK (0x1) 69 #define NVME_CAP_LO_REG_AMS_SHIFT (17) 70 #define NVME_CAP_LO_REG_AMS_MASK (0x3) 71 #define NVME_CAP_LO_REG_TO_SHIFT (24) 72 #define NVME_CAP_LO_REG_TO_MASK (0xFF) 73 #define NVME_CAP_LO_MQES(x) \ 74 (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK) 75 #define NVME_CAP_LO_CQR(x) \ 76 (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK) 77 #define NVME_CAP_LO_AMS(x) \ 78 (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK) 79 #define NVME_CAP_LO_TO(x) \ 80 (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK) 81 82 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0) 83 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF) 84 #define NVME_CAP_HI_REG_NSSRS_SHIFT (4) 85 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1) 86 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5) 87 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1) 88 #define NVME_CAP_HI_REG_BPS_SHIFT (13) 89 #define NVME_CAP_HI_REG_BPS_MASK (0x1) 90 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16) 91 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF) 92 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20) 93 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF) 94 #define NVME_CAP_HI_REG_PMRS_SHIFT (24) 95 #define NVME_CAP_HI_REG_PMRS_MASK (0x1) 96 #define NVME_CAP_HI_REG_CMBS_SHIFT (25) 97 #define NVME_CAP_HI_REG_CMBS_MASK (0x1) 98 #define NVME_CAP_HI_DSTRD(x) \ 99 (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK) 100 #define NVME_CAP_HI_CSS_NVM(x) \ 101 (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK) 102 #define NVME_CAP_HI_MPSMIN(x) \ 103 (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK) 104 #define NVME_CAP_HI_MPSMAX(x) \ 105 (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK) 106 107 #define NVME_CC_REG_EN_SHIFT (0) 108 #define NVME_CC_REG_EN_MASK (0x1) 109 #define NVME_CC_REG_CSS_SHIFT (4) 110 #define NVME_CC_REG_CSS_MASK (0x7) 111 #define NVME_CC_REG_MPS_SHIFT (7) 112 #define NVME_CC_REG_MPS_MASK (0xF) 113 #define NVME_CC_REG_AMS_SHIFT (11) 114 #define NVME_CC_REG_AMS_MASK (0x7) 115 #define NVME_CC_REG_SHN_SHIFT (14) 116 #define NVME_CC_REG_SHN_MASK (0x3) 117 #define NVME_CC_REG_IOSQES_SHIFT (16) 118 #define NVME_CC_REG_IOSQES_MASK (0xF) 119 #define NVME_CC_REG_IOCQES_SHIFT (20) 120 #define NVME_CC_REG_IOCQES_MASK (0xF) 121 122 #define NVME_CSTS_REG_RDY_SHIFT (0) 123 #define NVME_CSTS_REG_RDY_MASK (0x1) 124 #define NVME_CSTS_REG_CFS_SHIFT (1) 125 #define NVME_CSTS_REG_CFS_MASK (0x1) 126 #define NVME_CSTS_REG_SHST_SHIFT (2) 127 #define NVME_CSTS_REG_SHST_MASK (0x3) 128 #define NVME_CSTS_REG_NVSRO_SHIFT (4) 129 #define NVME_CSTS_REG_NVSRO_MASK (0x1) 130 #define NVME_CSTS_REG_PP_SHIFT (5) 131 #define NVME_CSTS_REG_PP_MASK (0x1) 132 133 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK) 134 135 #define NVME_AQA_REG_ASQS_SHIFT (0) 136 #define NVME_AQA_REG_ASQS_MASK (0xFFF) 137 #define NVME_AQA_REG_ACQS_SHIFT (16) 138 #define NVME_AQA_REG_ACQS_MASK (0xFFF) 139 140 /* Command field definitions */ 141 142 #define NVME_CMD_FUSE_SHIFT (8) 143 #define NVME_CMD_FUSE_MASK (0x3) 144 145 #define NVME_STATUS_P_SHIFT (0) 146 #define NVME_STATUS_P_MASK (0x1) 147 #define NVME_STATUS_SC_SHIFT (1) 148 #define NVME_STATUS_SC_MASK (0xFF) 149 #define NVME_STATUS_SCT_SHIFT (9) 150 #define NVME_STATUS_SCT_MASK (0x7) 151 #define NVME_STATUS_CRD_SHIFT (12) 152 #define NVME_STATUS_CRD_MASK (0x3) 153 #define NVME_STATUS_M_SHIFT (14) 154 #define NVME_STATUS_M_MASK (0x1) 155 #define NVME_STATUS_DNR_SHIFT (15) 156 #define NVME_STATUS_DNR_MASK (0x1) 157 158 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 159 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 160 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) 161 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 162 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 163 164 #define NVME_PWR_ST_MPS_SHIFT (0) 165 #define NVME_PWR_ST_MPS_MASK (0x1) 166 #define NVME_PWR_ST_NOPS_SHIFT (1) 167 #define NVME_PWR_ST_NOPS_MASK (0x1) 168 #define NVME_PWR_ST_RRT_SHIFT (0) 169 #define NVME_PWR_ST_RRT_MASK (0x1F) 170 #define NVME_PWR_ST_RRL_SHIFT (0) 171 #define NVME_PWR_ST_RRL_MASK (0x1F) 172 #define NVME_PWR_ST_RWT_SHIFT (0) 173 #define NVME_PWR_ST_RWT_MASK (0x1F) 174 #define NVME_PWR_ST_RWL_SHIFT (0) 175 #define NVME_PWR_ST_RWL_MASK (0x1F) 176 #define NVME_PWR_ST_IPS_SHIFT (6) 177 #define NVME_PWR_ST_IPS_MASK (0x3) 178 #define NVME_PWR_ST_APW_SHIFT (0) 179 #define NVME_PWR_ST_APW_MASK (0x7) 180 #define NVME_PWR_ST_APS_SHIFT (6) 181 #define NVME_PWR_ST_APS_MASK (0x3) 182 183 /** Controller Multi-path I/O and Namespace Sharing Capabilities */ 184 /* More then one port */ 185 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0) 186 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1) 187 /* More then one controller */ 188 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1) 189 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1) 190 /* SR-IOV Virtual Function */ 191 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2) 192 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1) 193 /* Asymmetric Namespace Access Reporting */ 194 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3) 195 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1) 196 197 /** OACS - optional admin command support */ 198 /* supports security send/receive commands */ 199 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0) 200 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1) 201 /* supports format nvm command */ 202 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1) 203 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1) 204 /* supports firmware activate/download commands */ 205 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2) 206 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1) 207 /* supports namespace management commands */ 208 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3) 209 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1) 210 /* supports Device Self-test command */ 211 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4) 212 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1) 213 /* supports Directives */ 214 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5) 215 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1) 216 /* supports NVMe-MI Send/Receive */ 217 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6) 218 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1) 219 /* supports Virtualization Management */ 220 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7) 221 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1) 222 /* supports Doorbell Buffer Config */ 223 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8) 224 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1) 225 /* supports Get LBA Status */ 226 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9) 227 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1) 228 229 /** firmware updates */ 230 /* first slot is read-only */ 231 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0) 232 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1) 233 /* number of firmware slots */ 234 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1) 235 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7) 236 /* firmware activation without reset */ 237 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4) 238 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1) 239 240 /** log page attributes */ 241 /* per namespace smart/health log page */ 242 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0) 243 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1) 244 245 /** AVSCC - admin vendor specific command configuration */ 246 /* admin vendor specific commands use spec format */ 247 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0) 248 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1) 249 250 /** Autonomous Power State Transition Attributes */ 251 /* Autonomous Power State Transitions supported */ 252 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0) 253 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1) 254 255 /** Sanitize Capabilities */ 256 /* Crypto Erase Support */ 257 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0) 258 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1) 259 /* Block Erase Support */ 260 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1) 261 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1) 262 /* Overwrite Support */ 263 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2) 264 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1) 265 /* No-Deallocate Inhibited */ 266 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29) 267 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1) 268 /* No-Deallocate Modifies Media After Sanitize */ 269 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30) 270 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3) 271 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0) 272 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1) 273 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2) 274 275 /** submission queue entry size */ 276 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0) 277 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF) 278 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4) 279 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF) 280 281 /** completion queue entry size */ 282 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0) 283 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF) 284 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4) 285 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF) 286 287 /** optional nvm command support */ 288 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0) 289 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1) 290 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1) 291 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1) 292 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2) 293 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1) 294 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3) 295 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1) 296 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4) 297 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1) 298 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5) 299 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1) 300 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6) 301 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1) 302 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7) 303 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1) 304 305 /** Fused Operation Support */ 306 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0) 307 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1) 308 309 /** Format NVM Attributes */ 310 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0) 311 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1) 312 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1) 313 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1) 314 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2) 315 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1) 316 317 /** volatile write cache */ 318 /* volatile write cache present */ 319 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0) 320 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1) 321 /* flush all namespaces supported */ 322 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1) 323 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3) 324 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0) 325 #define NVME_CTRLR_DATA_VWC_ALL_NO (2) 326 #define NVME_CTRLR_DATA_VWC_ALL_YES (3) 327 328 /** namespace features */ 329 /* thin provisioning */ 330 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0) 331 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1) 332 /* NAWUN, NAWUPF, and NACWU fields are valid */ 333 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1) 334 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1) 335 /* Deallocated or Unwritten Logical Block errors supported */ 336 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2) 337 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1) 338 /* NGUID and EUI64 fields are not reusable */ 339 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3) 340 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1) 341 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */ 342 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4) 343 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1) 344 345 /** formatted lba size */ 346 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0) 347 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF) 348 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4) 349 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1) 350 351 /** metadata capabilities */ 352 /* metadata can be transferred as part of data prp list */ 353 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0) 354 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1) 355 /* metadata can be transferred with separate metadata pointer */ 356 #define NVME_NS_DATA_MC_POINTER_SHIFT (1) 357 #define NVME_NS_DATA_MC_POINTER_MASK (0x1) 358 359 /** end-to-end data protection capabilities */ 360 /* protection information type 1 */ 361 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0) 362 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1) 363 /* protection information type 2 */ 364 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1) 365 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1) 366 /* protection information type 3 */ 367 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2) 368 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1) 369 /* first eight bytes of metadata */ 370 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3) 371 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1) 372 /* last eight bytes of metadata */ 373 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4) 374 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1) 375 376 /** end-to-end data protection type settings */ 377 /* protection information type */ 378 #define NVME_NS_DATA_DPS_PIT_SHIFT (0) 379 #define NVME_NS_DATA_DPS_PIT_MASK (0x7) 380 /* 1 == protection info transferred at start of metadata */ 381 /* 0 == protection info transferred at end of metadata */ 382 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3) 383 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1) 384 385 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 386 /* the namespace may be attached to two or more controllers */ 387 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0) 388 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1) 389 390 /** Reservation Capabilities */ 391 /* Persist Through Power Loss */ 392 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0) 393 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1) 394 /* supports the Write Exclusive */ 395 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1) 396 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1) 397 /* supports the Exclusive Access */ 398 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2) 399 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1) 400 /* supports the Write Exclusive – Registrants Only */ 401 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3) 402 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1) 403 /* supports the Exclusive Access - Registrants Only */ 404 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4) 405 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1) 406 /* supports the Write Exclusive – All Registrants */ 407 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5) 408 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1) 409 /* supports the Exclusive Access - All Registrants */ 410 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6) 411 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1) 412 /* Ignore Existing Key is used as defined in revision 1.3 or later */ 413 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7) 414 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1) 415 416 /** Format Progress Indicator */ 417 /* percentage of the Format NVM command that remains to be completed */ 418 #define NVME_NS_DATA_FPI_PERC_SHIFT (0) 419 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f) 420 /* namespace supports the Format Progress Indicator */ 421 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7) 422 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1) 423 424 /** Deallocate Logical Block Features */ 425 /* deallocated logical block read behavior */ 426 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0) 427 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07) 428 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00) 429 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01) 430 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02) 431 /* supports the Deallocate bit in the Write Zeroes */ 432 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3) 433 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01) 434 /* Guard field for deallocated logical blocks is set to the CRC */ 435 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4) 436 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01) 437 438 /** lba format support */ 439 /* metadata size */ 440 #define NVME_NS_DATA_LBAF_MS_SHIFT (0) 441 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF) 442 /* lba data size */ 443 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16) 444 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF) 445 /* relative performance */ 446 #define NVME_NS_DATA_LBAF_RP_SHIFT (24) 447 #define NVME_NS_DATA_LBAF_RP_MASK (0x3) 448 449 enum nvme_critical_warning_state { 450 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1, 451 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2, 452 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4, 453 NVME_CRIT_WARN_ST_READ_ONLY = 0x8, 454 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10, 455 }; 456 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0) 457 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE (0x100) 458 #define NVME_ASYNC_EVENT_FW_ACTIVATE (0x200) 459 460 /* slot for current FW */ 461 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0) 462 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7) 463 464 /* Commands Supported and Effects */ 465 #define NVME_CE_PAGE_CSUP_SHIFT (0) 466 #define NVME_CE_PAGE_CSUP_MASK (0x1) 467 #define NVME_CE_PAGE_LBCC_SHIFT (1) 468 #define NVME_CE_PAGE_LBCC_MASK (0x1) 469 #define NVME_CE_PAGE_NCC_SHIFT (2) 470 #define NVME_CE_PAGE_NCC_MASK (0x1) 471 #define NVME_CE_PAGE_NIC_SHIFT (3) 472 #define NVME_CE_PAGE_NIC_MASK (0x1) 473 #define NVME_CE_PAGE_CCC_SHIFT (4) 474 #define NVME_CE_PAGE_CCC_MASK (0x1) 475 #define NVME_CE_PAGE_CSE_SHIFT (16) 476 #define NVME_CE_PAGE_CSE_MASK (0x7) 477 #define NVME_CE_PAGE_UUID_SHIFT (19) 478 #define NVME_CE_PAGE_UUID_MASK (0x1) 479 480 /* Sanitize Status */ 481 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0) 482 #define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7) 483 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0) 484 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1) 485 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2) 486 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3) 487 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4) 488 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3) 489 #define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f) 490 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8) 491 #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1) 492 493 /* CC register SHN field values */ 494 enum shn_value { 495 NVME_SHN_NORMAL = 0x1, 496 NVME_SHN_ABRUPT = 0x2, 497 }; 498 499 /* CSTS register SHST field values */ 500 enum shst_value { 501 NVME_SHST_NORMAL = 0x0, 502 NVME_SHST_OCCURRING = 0x1, 503 NVME_SHST_COMPLETE = 0x2, 504 }; 505 506 struct nvme_registers 507 { 508 uint32_t cap_lo; /* controller capabilities */ 509 uint32_t cap_hi; 510 uint32_t vs; /* version */ 511 uint32_t intms; /* interrupt mask set */ 512 uint32_t intmc; /* interrupt mask clear */ 513 uint32_t cc; /* controller configuration */ 514 uint32_t reserved1; 515 uint32_t csts; /* controller status */ 516 uint32_t nssr; /* NVM Subsystem Reset */ 517 uint32_t aqa; /* admin queue attributes */ 518 uint64_t asq; /* admin submission queue base addr */ 519 uint64_t acq; /* admin completion queue base addr */ 520 uint32_t cmbloc; /* Controller Memory Buffer Location */ 521 uint32_t cmbsz; /* Controller Memory Buffer Size */ 522 uint32_t bpinfo; /* Boot Partition Information */ 523 uint32_t bprsel; /* Boot Partition Read Select */ 524 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */ 525 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */ 526 uint32_t cmbsts; /* Controller Memory Buffer Status */ 527 uint8_t reserved3[3492]; /* 5Ch - DFFh */ 528 uint32_t pmrcap; /* Persistent Memory Capabilities */ 529 uint32_t pmrctl; /* Persistent Memory Region Control */ 530 uint32_t pmrsts; /* Persistent Memory Region Status */ 531 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */ 532 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */ 533 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */ 534 uint32_t pmrmsc_hi; 535 uint8_t reserved4[484]; /* E1Ch - FFFh */ 536 struct { 537 uint32_t sq_tdbl; /* submission queue tail doorbell */ 538 uint32_t cq_hdbl; /* completion queue head doorbell */ 539 } doorbell[1] __packed; 540 } __packed; 541 542 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 543 544 struct nvme_command 545 { 546 /* dword 0 */ 547 uint8_t opc; /* opcode */ 548 uint8_t fuse; /* fused operation */ 549 uint16_t cid; /* command identifier */ 550 551 /* dword 1 */ 552 uint32_t nsid; /* namespace identifier */ 553 554 /* dword 2-3 */ 555 uint32_t rsvd2; 556 uint32_t rsvd3; 557 558 /* dword 4-5 */ 559 uint64_t mptr; /* metadata pointer */ 560 561 /* dword 6-7 */ 562 uint64_t prp1; /* prp entry 1 */ 563 564 /* dword 8-9 */ 565 uint64_t prp2; /* prp entry 2 */ 566 567 /* dword 10-15 */ 568 uint32_t cdw10; /* command-specific */ 569 uint32_t cdw11; /* command-specific */ 570 uint32_t cdw12; /* command-specific */ 571 uint32_t cdw13; /* command-specific */ 572 uint32_t cdw14; /* command-specific */ 573 uint32_t cdw15; /* command-specific */ 574 } __packed; 575 576 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 577 578 struct nvme_completion { 579 /* dword 0 */ 580 uint32_t cdw0; /* command-specific */ 581 582 /* dword 1 */ 583 uint32_t rsvd1; 584 585 /* dword 2 */ 586 uint16_t sqhd; /* submission queue head pointer */ 587 uint16_t sqid; /* submission queue identifier */ 588 589 /* dword 3 */ 590 uint16_t cid; /* command identifier */ 591 uint16_t status; 592 } __packed; 593 594 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 595 596 struct nvme_dsm_range { 597 uint32_t attributes; 598 uint32_t length; 599 uint64_t starting_lba; 600 } __packed; 601 602 /* Largest DSM Trim that can be done */ 603 #define NVME_MAX_DSM_TRIM 4096 604 605 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 606 607 /* status code types */ 608 enum nvme_status_code_type { 609 NVME_SCT_GENERIC = 0x0, 610 NVME_SCT_COMMAND_SPECIFIC = 0x1, 611 NVME_SCT_MEDIA_ERROR = 0x2, 612 NVME_SCT_PATH_RELATED = 0x3, 613 /* 0x3-0x6 - reserved */ 614 NVME_SCT_VENDOR_SPECIFIC = 0x7, 615 }; 616 617 /* generic command status codes */ 618 enum nvme_generic_command_status_code { 619 NVME_SC_SUCCESS = 0x00, 620 NVME_SC_INVALID_OPCODE = 0x01, 621 NVME_SC_INVALID_FIELD = 0x02, 622 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 623 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 624 NVME_SC_ABORTED_POWER_LOSS = 0x05, 625 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 626 NVME_SC_ABORTED_BY_REQUEST = 0x07, 627 NVME_SC_ABORTED_SQ_DELETION = 0x08, 628 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 629 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 630 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 631 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 632 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 633 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 634 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 635 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 636 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 637 NVME_SC_INVALID_USE_OF_CMB = 0x12, 638 NVME_SC_PRP_OFFET_INVALID = 0x13, 639 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 640 NVME_SC_OPERATION_DENIED = 0x15, 641 NVME_SC_SGL_OFFSET_INVALID = 0x16, 642 /* 0x17 - reserved */ 643 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 644 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 645 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 646 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 647 NVME_SC_SANITIZE_FAILED = 0x1c, 648 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 649 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 650 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 651 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20, 652 NVME_SC_COMMAND_INTERRUPTED = 0x21, 653 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22, 654 655 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 656 NVME_SC_CAPACITY_EXCEEDED = 0x81, 657 NVME_SC_NAMESPACE_NOT_READY = 0x82, 658 NVME_SC_RESERVATION_CONFLICT = 0x83, 659 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 660 }; 661 662 /* command specific status codes */ 663 enum nvme_command_specific_status_code { 664 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 665 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 666 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 667 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 668 /* 0x04 - reserved */ 669 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 670 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 671 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 672 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 673 NVME_SC_INVALID_LOG_PAGE = 0x09, 674 NVME_SC_INVALID_FORMAT = 0x0a, 675 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 676 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 677 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 678 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 679 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 680 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 681 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 682 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 683 NVME_SC_FW_ACT_PROHIBITED = 0x13, 684 NVME_SC_OVERLAPPING_RANGE = 0x14, 685 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 686 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 687 /* 0x17 - reserved */ 688 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 689 NVME_SC_NS_IS_PRIVATE = 0x19, 690 NVME_SC_NS_NOT_ATTACHED = 0x1a, 691 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 692 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 693 NVME_SC_SELT_TEST_IN_PROGRESS = 0x1d, 694 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 695 NVME_SC_INVALID_CTRLR_ID = 0x1f, 696 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 697 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 698 NVME_SC_INVALID_RESOURCE_ID = 0x22, 699 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23, 700 NVME_SC_ANA_GROUP_ID_INVALID = 0x24, 701 NVME_SC_ANA_ATTACH_FAILED = 0x25, 702 703 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 704 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 705 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 706 }; 707 708 /* media error status codes */ 709 enum nvme_media_error_status_code { 710 NVME_SC_WRITE_FAULTS = 0x80, 711 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 712 NVME_SC_GUARD_CHECK_ERROR = 0x82, 713 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 714 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 715 NVME_SC_COMPARE_FAILURE = 0x85, 716 NVME_SC_ACCESS_DENIED = 0x86, 717 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 718 }; 719 720 /* path related status codes */ 721 enum nvme_path_related_status_code { 722 NVME_SC_INTERNAL_PATH_ERROR = 0x00, 723 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01, 724 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02, 725 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03, 726 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60, 727 NVME_SC_HOST_PATHING_ERROR = 0x70, 728 NVME_SC_COMMAND_ABOTHED_BY_HOST = 0x71, 729 }; 730 731 /* admin opcodes */ 732 enum nvme_admin_opcode { 733 NVME_OPC_DELETE_IO_SQ = 0x00, 734 NVME_OPC_CREATE_IO_SQ = 0x01, 735 NVME_OPC_GET_LOG_PAGE = 0x02, 736 /* 0x03 - reserved */ 737 NVME_OPC_DELETE_IO_CQ = 0x04, 738 NVME_OPC_CREATE_IO_CQ = 0x05, 739 NVME_OPC_IDENTIFY = 0x06, 740 /* 0x07 - reserved */ 741 NVME_OPC_ABORT = 0x08, 742 NVME_OPC_SET_FEATURES = 0x09, 743 NVME_OPC_GET_FEATURES = 0x0a, 744 /* 0x0b - reserved */ 745 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 746 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 747 /* 0x0e-0x0f - reserved */ 748 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 749 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 750 /* 0x12-0x13 - reserved */ 751 NVME_OPC_DEVICE_SELF_TEST = 0x14, 752 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 753 /* 0x16-0x17 - reserved */ 754 NVME_OPC_KEEP_ALIVE = 0x18, 755 NVME_OPC_DIRECTIVE_SEND = 0x19, 756 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 757 /* 0x1b - reserved */ 758 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 759 NVME_OPC_NVME_MI_SEND = 0x1d, 760 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 761 /* 0x1f-0x7b - reserved */ 762 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 763 764 NVME_OPC_FORMAT_NVM = 0x80, 765 NVME_OPC_SECURITY_SEND = 0x81, 766 NVME_OPC_SECURITY_RECEIVE = 0x82, 767 /* 0x83 - reserved */ 768 NVME_OPC_SANITIZE = 0x84, 769 /* 0x85 - reserved */ 770 NVME_OPC_GET_LBA_STATUS = 0x86, 771 }; 772 773 /* nvme nvm opcodes */ 774 enum nvme_nvm_opcode { 775 NVME_OPC_FLUSH = 0x00, 776 NVME_OPC_WRITE = 0x01, 777 NVME_OPC_READ = 0x02, 778 /* 0x03 - reserved */ 779 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 780 NVME_OPC_COMPARE = 0x05, 781 /* 0x06-0x07 - reserved */ 782 NVME_OPC_WRITE_ZEROES = 0x08, 783 NVME_OPC_DATASET_MANAGEMENT = 0x09, 784 /* 0x0a-0x0b - reserved */ 785 NVME_OPC_VERIFY = 0x0c, 786 NVME_OPC_RESERVATION_REGISTER = 0x0d, 787 NVME_OPC_RESERVATION_REPORT = 0x0e, 788 /* 0x0f-0x10 - reserved */ 789 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 790 /* 0x12-0x14 - reserved */ 791 NVME_OPC_RESERVATION_RELEASE = 0x15, 792 }; 793 794 enum nvme_feature { 795 /* 0x00 - reserved */ 796 NVME_FEAT_ARBITRATION = 0x01, 797 NVME_FEAT_POWER_MANAGEMENT = 0x02, 798 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 799 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 800 NVME_FEAT_ERROR_RECOVERY = 0x05, 801 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 802 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 803 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 804 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 805 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 806 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 807 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 808 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 809 NVME_FEAT_TIMESTAMP = 0x0E, 810 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 811 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 812 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 813 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12, 814 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13, 815 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14, 816 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15, 817 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16, 818 NVME_FEAT_SANITIZE_CONFIG = 0x17, 819 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18, 820 /* 0x19-0x77 - reserved */ 821 /* 0x78-0x7f - NVMe Management Interface */ 822 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 823 NVME_FEAT_HOST_IDENTIFIER = 0x81, 824 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82, 825 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83, 826 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84, 827 /* 0x85-0xBF - command set specific (reserved) */ 828 /* 0xC0-0xFF - vendor specific */ 829 }; 830 831 enum nvme_dsm_attribute { 832 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 833 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 834 NVME_DSM_ATTR_DEALLOCATE = 0x4, 835 }; 836 837 enum nvme_activate_action { 838 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 839 NVME_AA_REPLACE_ACTIVATE = 0x1, 840 NVME_AA_ACTIVATE = 0x2, 841 }; 842 843 struct nvme_power_state { 844 /** Maximum Power */ 845 uint16_t mp; /* Maximum Power */ 846 uint8_t ps_rsvd1; 847 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */ 848 849 uint32_t enlat; /* Entry Latency */ 850 uint32_t exlat; /* Exit Latency */ 851 852 uint8_t rrt; /* Relative Read Throughput */ 853 uint8_t rrl; /* Relative Read Latency */ 854 uint8_t rwt; /* Relative Write Throughput */ 855 uint8_t rwl; /* Relative Write Latency */ 856 857 uint16_t idlp; /* Idle Power */ 858 uint8_t ips; /* Idle Power Scale */ 859 uint8_t ps_rsvd8; 860 861 uint16_t actp; /* Active Power */ 862 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ 863 uint8_t ps_rsvd10[9]; 864 } __packed; 865 866 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 867 868 #define NVME_SERIAL_NUMBER_LENGTH 20 869 #define NVME_MODEL_NUMBER_LENGTH 40 870 #define NVME_FIRMWARE_REVISION_LENGTH 8 871 872 struct nvme_controller_data { 873 /* bytes 0-255: controller capabilities and features */ 874 875 /** pci vendor id */ 876 uint16_t vid; 877 878 /** pci subsystem vendor id */ 879 uint16_t ssvid; 880 881 /** serial number */ 882 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 883 884 /** model number */ 885 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 886 887 /** firmware revision */ 888 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 889 890 /** recommended arbitration burst */ 891 uint8_t rab; 892 893 /** ieee oui identifier */ 894 uint8_t ieee[3]; 895 896 /** multi-interface capabilities */ 897 uint8_t mic; 898 899 /** maximum data transfer size */ 900 uint8_t mdts; 901 902 /** Controller ID */ 903 uint16_t ctrlr_id; 904 905 /** Version */ 906 uint32_t ver; 907 908 /** RTD3 Resume Latency */ 909 uint32_t rtd3r; 910 911 /** RTD3 Enter Latency */ 912 uint32_t rtd3e; 913 914 /** Optional Asynchronous Events Supported */ 915 uint32_t oaes; /* bitfield really */ 916 917 /** Controller Attributes */ 918 uint32_t ctratt; /* bitfield really */ 919 920 /** Read Recovery Levels Supported */ 921 uint16_t rrls; 922 923 uint8_t reserved1[9]; 924 925 /** Controller Type */ 926 uint8_t cntrltype; 927 928 /** FRU Globally Unique Identifier */ 929 uint8_t fguid[16]; 930 931 /** Command Retry Delay Time 1 */ 932 uint16_t crdt1; 933 934 /** Command Retry Delay Time 2 */ 935 uint16_t crdt2; 936 937 /** Command Retry Delay Time 3 */ 938 uint16_t crdt3; 939 940 uint8_t reserved2[122]; 941 942 /* bytes 256-511: admin command set attributes */ 943 944 /** optional admin command support */ 945 uint16_t oacs; 946 947 /** abort command limit */ 948 uint8_t acl; 949 950 /** asynchronous event request limit */ 951 uint8_t aerl; 952 953 /** firmware updates */ 954 uint8_t frmw; 955 956 /** log page attributes */ 957 uint8_t lpa; 958 959 /** error log page entries */ 960 uint8_t elpe; 961 962 /** number of power states supported */ 963 uint8_t npss; 964 965 /** admin vendor specific command configuration */ 966 uint8_t avscc; 967 968 /** Autonomous Power State Transition Attributes */ 969 uint8_t apsta; 970 971 /** Warning Composite Temperature Threshold */ 972 uint16_t wctemp; 973 974 /** Critical Composite Temperature Threshold */ 975 uint16_t cctemp; 976 977 /** Maximum Time for Firmware Activation */ 978 uint16_t mtfa; 979 980 /** Host Memory Buffer Preferred Size */ 981 uint32_t hmpre; 982 983 /** Host Memory Buffer Minimum Size */ 984 uint32_t hmmin; 985 986 /** Name space capabilities */ 987 struct { 988 /* if nsmgmt, report tnvmcap and unvmcap */ 989 uint8_t tnvmcap[16]; 990 uint8_t unvmcap[16]; 991 } __packed untncap; 992 993 /** Replay Protected Memory Block Support */ 994 uint32_t rpmbs; /* Really a bitfield */ 995 996 /** Extended Device Self-test Time */ 997 uint16_t edstt; 998 999 /** Device Self-test Options */ 1000 uint8_t dsto; /* Really a bitfield */ 1001 1002 /** Firmware Update Granularity */ 1003 uint8_t fwug; 1004 1005 /** Keep Alive Support */ 1006 uint16_t kas; 1007 1008 /** Host Controlled Thermal Management Attributes */ 1009 uint16_t hctma; /* Really a bitfield */ 1010 1011 /** Minimum Thermal Management Temperature */ 1012 uint16_t mntmt; 1013 1014 /** Maximum Thermal Management Temperature */ 1015 uint16_t mxtmt; 1016 1017 /** Sanitize Capabilities */ 1018 uint32_t sanicap; /* Really a bitfield */ 1019 1020 /** Host Memory Buffer Minimum Descriptor Entry Size */ 1021 uint32_t hmminds; 1022 1023 /** Host Memory Maximum Descriptors Entries */ 1024 uint16_t hmmaxd; 1025 1026 /** NVM Set Identifier Maximum */ 1027 uint16_t nsetidmax; 1028 1029 /** Endurance Group Identifier Maximum */ 1030 uint16_t endgidmax; 1031 1032 /** ANA Transition Time */ 1033 uint8_t anatt; 1034 1035 /** Asymmetric Namespace Access Capabilities */ 1036 uint8_t anacap; 1037 1038 /** ANA Group Identifier Maximum */ 1039 uint32_t anagrpmax; 1040 1041 /** Number of ANA Group Identifiers */ 1042 uint32_t nanagrpid; 1043 1044 /** Persistent Event Log Size */ 1045 uint32_t pels; 1046 1047 uint8_t reserved3[156]; 1048 /* bytes 512-703: nvm command set attributes */ 1049 1050 /** submission queue entry size */ 1051 uint8_t sqes; 1052 1053 /** completion queue entry size */ 1054 uint8_t cqes; 1055 1056 /** Maximum Outstanding Commands */ 1057 uint16_t maxcmd; 1058 1059 /** number of namespaces */ 1060 uint32_t nn; 1061 1062 /** optional nvm command support */ 1063 uint16_t oncs; 1064 1065 /** fused operation support */ 1066 uint16_t fuses; 1067 1068 /** format nvm attributes */ 1069 uint8_t fna; 1070 1071 /** volatile write cache */ 1072 uint8_t vwc; 1073 1074 /** Atomic Write Unit Normal */ 1075 uint16_t awun; 1076 1077 /** Atomic Write Unit Power Fail */ 1078 uint16_t awupf; 1079 1080 /** NVM Vendor Specific Command Configuration */ 1081 uint8_t nvscc; 1082 1083 /** Namespace Write Protection Capabilities */ 1084 uint8_t nwpc; 1085 1086 /** Atomic Compare & Write Unit */ 1087 uint16_t acwu; 1088 uint16_t reserved6; 1089 1090 /** SGL Support */ 1091 uint32_t sgls; 1092 1093 /** Maximum Number of Allowed Namespaces */ 1094 uint32_t mnan; 1095 1096 /* bytes 540-767: Reserved */ 1097 uint8_t reserved7[224]; 1098 1099 /** NVM Subsystem NVMe Qualified Name */ 1100 uint8_t subnqn[256]; 1101 1102 /* bytes 1024-1791: Reserved */ 1103 uint8_t reserved8[768]; 1104 1105 /* bytes 1792-2047: NVMe over Fabrics specification */ 1106 uint8_t reserved9[256]; 1107 1108 /* bytes 2048-3071: power state descriptors */ 1109 struct nvme_power_state power_state[32]; 1110 1111 /* bytes 3072-4095: vendor specific */ 1112 uint8_t vs[1024]; 1113 } __packed __aligned(4); 1114 1115 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 1116 1117 struct nvme_namespace_data { 1118 /** namespace size */ 1119 uint64_t nsze; 1120 1121 /** namespace capacity */ 1122 uint64_t ncap; 1123 1124 /** namespace utilization */ 1125 uint64_t nuse; 1126 1127 /** namespace features */ 1128 uint8_t nsfeat; 1129 1130 /** number of lba formats */ 1131 uint8_t nlbaf; 1132 1133 /** formatted lba size */ 1134 uint8_t flbas; 1135 1136 /** metadata capabilities */ 1137 uint8_t mc; 1138 1139 /** end-to-end data protection capabilities */ 1140 uint8_t dpc; 1141 1142 /** end-to-end data protection type settings */ 1143 uint8_t dps; 1144 1145 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 1146 uint8_t nmic; 1147 1148 /** Reservation Capabilities */ 1149 uint8_t rescap; 1150 1151 /** Format Progress Indicator */ 1152 uint8_t fpi; 1153 1154 /** Deallocate Logical Block Features */ 1155 uint8_t dlfeat; 1156 1157 /** Namespace Atomic Write Unit Normal */ 1158 uint16_t nawun; 1159 1160 /** Namespace Atomic Write Unit Power Fail */ 1161 uint16_t nawupf; 1162 1163 /** Namespace Atomic Compare & Write Unit */ 1164 uint16_t nacwu; 1165 1166 /** Namespace Atomic Boundary Size Normal */ 1167 uint16_t nabsn; 1168 1169 /** Namespace Atomic Boundary Offset */ 1170 uint16_t nabo; 1171 1172 /** Namespace Atomic Boundary Size Power Fail */ 1173 uint16_t nabspf; 1174 1175 /** Namespace Optimal IO Boundary */ 1176 uint16_t noiob; 1177 1178 /** NVM Capacity */ 1179 uint8_t nvmcap[16]; 1180 1181 /** Namespace Preferred Write Granularity */ 1182 uint16_t npwg; 1183 1184 /** Namespace Preferred Write Alignment */ 1185 uint16_t npwa; 1186 1187 /** Namespace Preferred Deallocate Granularity */ 1188 uint16_t npdg; 1189 1190 /** Namespace Preferred Deallocate Alignment */ 1191 uint16_t npda; 1192 1193 /** Namespace Optimal Write Size */ 1194 uint16_t nows; 1195 1196 /* bytes 74-91: Reserved */ 1197 uint8_t reserved5[18]; 1198 1199 /** ANA Group Identifier */ 1200 uint32_t anagrpid; 1201 1202 /* bytes 96-98: Reserved */ 1203 uint8_t reserved6[3]; 1204 1205 /** Namespace Attributes */ 1206 uint8_t nsattr; 1207 1208 /** NVM Set Identifier */ 1209 uint16_t nvmsetid; 1210 1211 /** Endurance Group Identifier */ 1212 uint16_t endgid; 1213 1214 /** Namespace Globally Unique Identifier */ 1215 uint8_t nguid[16]; 1216 1217 /** IEEE Extended Unique Identifier */ 1218 uint8_t eui64[8]; 1219 1220 /** lba format support */ 1221 uint32_t lbaf[16]; 1222 1223 uint8_t reserved7[192]; 1224 1225 uint8_t vendor_specific[3712]; 1226 } __packed __aligned(4); 1227 1228 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 1229 1230 enum nvme_log_page { 1231 /* 0x00 - reserved */ 1232 NVME_LOG_ERROR = 0x01, 1233 NVME_LOG_HEALTH_INFORMATION = 0x02, 1234 NVME_LOG_FIRMWARE_SLOT = 0x03, 1235 NVME_LOG_CHANGED_NAMESPACE = 0x04, 1236 NVME_LOG_COMMAND_EFFECT = 0x05, 1237 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1238 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07, 1239 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08, 1240 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09, 1241 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a, 1242 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b, 1243 NVME_LOG_ASYMMETRIC_NAMESPAVE_ACCESS = 0x0c, 1244 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d, 1245 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e, 1246 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f, 1247 /* 0x06-0x7F - reserved */ 1248 /* 0x80-0xBF - I/O command set specific */ 1249 NVME_LOG_RES_NOTIFICATION = 0x80, 1250 NVME_LOG_SANITIZE_STATUS = 0x81, 1251 /* 0x82-0xBF - reserved */ 1252 /* 0xC0-0xFF - vendor specific */ 1253 1254 /* 1255 * The following are Intel Specific log pages, but they seem 1256 * to be widely implemented. 1257 */ 1258 INTEL_LOG_READ_LAT_LOG = 0xc1, 1259 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 1260 INTEL_LOG_TEMP_STATS = 0xc5, 1261 INTEL_LOG_ADD_SMART = 0xca, 1262 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 1263 1264 /* 1265 * HGST log page, with lots ofs sub pages. 1266 */ 1267 HGST_INFO_LOG = 0xc1, 1268 }; 1269 1270 struct nvme_error_information_entry { 1271 uint64_t error_count; 1272 uint16_t sqid; 1273 uint16_t cid; 1274 uint16_t status; 1275 uint16_t error_location; 1276 uint64_t lba; 1277 uint32_t nsid; 1278 uint8_t vendor_specific; 1279 uint8_t trtype; 1280 uint16_t reserved30; 1281 uint64_t csi; 1282 uint16_t ttsi; 1283 uint8_t reserved[22]; 1284 } __packed __aligned(4); 1285 1286 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 1287 1288 struct nvme_health_information_page { 1289 uint8_t critical_warning; 1290 uint16_t temperature; 1291 uint8_t available_spare; 1292 uint8_t available_spare_threshold; 1293 uint8_t percentage_used; 1294 1295 uint8_t reserved[26]; 1296 1297 /* 1298 * Note that the following are 128-bit values, but are 1299 * defined as an array of 2 64-bit values. 1300 */ 1301 /* Data Units Read is always in 512-byte units. */ 1302 uint64_t data_units_read[2]; 1303 /* Data Units Written is always in 512-byte units. */ 1304 uint64_t data_units_written[2]; 1305 /* For NVM command set, this includes Compare commands. */ 1306 uint64_t host_read_commands[2]; 1307 uint64_t host_write_commands[2]; 1308 /* Controller Busy Time is reported in minutes. */ 1309 uint64_t controller_busy_time[2]; 1310 uint64_t power_cycles[2]; 1311 uint64_t power_on_hours[2]; 1312 uint64_t unsafe_shutdowns[2]; 1313 uint64_t media_errors[2]; 1314 uint64_t num_error_info_log_entries[2]; 1315 uint32_t warning_temp_time; 1316 uint32_t error_temp_time; 1317 uint16_t temp_sensor[8]; 1318 /* Thermal Management Temperature 1 Transition Count */ 1319 uint32_t tmt1tc; 1320 /* Thermal Management Temperature 2 Transition Count */ 1321 uint32_t tmt2tc; 1322 /* Total Time For Thermal Management Temperature 1 */ 1323 uint32_t ttftmt1; 1324 /* Total Time For Thermal Management Temperature 2 */ 1325 uint32_t ttftmt2; 1326 1327 uint8_t reserved2[280]; 1328 } __packed __aligned(4); 1329 1330 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 1331 1332 struct nvme_firmware_page { 1333 uint8_t afi; 1334 uint8_t reserved[7]; 1335 uint64_t revision[7]; /* revisions for 7 slots */ 1336 uint8_t reserved2[448]; 1337 } __packed __aligned(4); 1338 1339 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 1340 1341 struct nvme_ns_list { 1342 uint32_t ns[1024]; 1343 } __packed __aligned(4); 1344 1345 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list"); 1346 1347 struct nvme_command_effects_page { 1348 uint32_t acs[256]; 1349 uint32_t iocs[256]; 1350 uint8_t reserved[2048]; 1351 } __packed __aligned(4); 1352 1353 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096, 1354 "bad size for nvme_command_effects_page"); 1355 1356 struct nvme_res_notification_page { 1357 uint64_t log_page_count; 1358 uint8_t log_page_type; 1359 uint8_t available_log_pages; 1360 uint8_t reserved2; 1361 uint32_t nsid; 1362 uint8_t reserved[48]; 1363 } __packed __aligned(4); 1364 1365 _Static_assert(sizeof(struct nvme_res_notification_page) == 64, 1366 "bad size for nvme_res_notification_page"); 1367 1368 struct nvme_sanitize_status_page { 1369 uint16_t sprog; 1370 uint16_t sstat; 1371 uint32_t scdw10; 1372 uint32_t etfo; 1373 uint32_t etfbe; 1374 uint32_t etfce; 1375 uint32_t etfownd; 1376 uint32_t etfbewnd; 1377 uint32_t etfcewnd; 1378 uint8_t reserved[480]; 1379 } __packed __aligned(4); 1380 1381 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512, 1382 "bad size for nvme_sanitize_status_page"); 1383 1384 struct intel_log_temp_stats 1385 { 1386 uint64_t current; 1387 uint64_t overtemp_flag_last; 1388 uint64_t overtemp_flag_life; 1389 uint64_t max_temp; 1390 uint64_t min_temp; 1391 uint64_t _rsvd[5]; 1392 uint64_t max_oper_temp; 1393 uint64_t min_oper_temp; 1394 uint64_t est_offset; 1395 } __packed __aligned(4); 1396 1397 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 1398 1399 struct nvme_resv_reg_ctrlr 1400 { 1401 uint16_t ctrlr_id; /* Controller ID */ 1402 uint8_t rcsts; /* Reservation Status */ 1403 uint8_t reserved3[5]; 1404 uint64_t hostid; /* Host Identifier */ 1405 uint64_t rkey; /* Reservation Key */ 1406 } __packed __aligned(4); 1407 1408 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr"); 1409 1410 struct nvme_resv_reg_ctrlr_ext 1411 { 1412 uint16_t ctrlr_id; /* Controller ID */ 1413 uint8_t rcsts; /* Reservation Status */ 1414 uint8_t reserved3[5]; 1415 uint64_t rkey; /* Reservation Key */ 1416 uint64_t hostid[2]; /* Host Identifier */ 1417 uint8_t reserved32[32]; 1418 } __packed __aligned(4); 1419 1420 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext"); 1421 1422 struct nvme_resv_status 1423 { 1424 uint32_t gen; /* Generation */ 1425 uint8_t rtype; /* Reservation Type */ 1426 uint8_t regctl[2]; /* Number of Registered Controllers */ 1427 uint8_t reserved7[2]; 1428 uint8_t ptpls; /* Persist Through Power Loss State */ 1429 uint8_t reserved10[14]; 1430 struct nvme_resv_reg_ctrlr ctrlr[0]; 1431 } __packed __aligned(4); 1432 1433 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status"); 1434 1435 struct nvme_resv_status_ext 1436 { 1437 uint32_t gen; /* Generation */ 1438 uint8_t rtype; /* Reservation Type */ 1439 uint8_t regctl[2]; /* Number of Registered Controllers */ 1440 uint8_t reserved7[2]; 1441 uint8_t ptpls; /* Persist Through Power Loss State */ 1442 uint8_t reserved10[14]; 1443 uint8_t reserved24[40]; 1444 struct nvme_resv_reg_ctrlr_ext ctrlr[0]; 1445 } __packed __aligned(4); 1446 1447 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext"); 1448 1449 #define NVME_TEST_MAX_THREADS 128 1450 1451 struct nvme_io_test { 1452 enum nvme_nvm_opcode opc; 1453 uint32_t size; 1454 uint32_t time; /* in seconds */ 1455 uint32_t num_threads; 1456 uint32_t flags; 1457 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 1458 }; 1459 1460 enum nvme_io_test_flags { 1461 /* 1462 * Specifies whether dev_refthread/dev_relthread should be 1463 * called during NVME_BIO_TEST. Ignored for other test 1464 * types. 1465 */ 1466 NVME_TEST_FLAG_REFTHREAD = 0x1, 1467 }; 1468 1469 struct nvme_pt_command { 1470 /* 1471 * cmd is used to specify a passthrough command to a controller or 1472 * namespace. 1473 * 1474 * The following fields from cmd may be specified by the caller: 1475 * * opc (opcode) 1476 * * nsid (namespace id) - for admin commands only 1477 * * cdw10-cdw15 1478 * 1479 * Remaining fields must be set to 0 by the caller. 1480 */ 1481 struct nvme_command cmd; 1482 1483 /* 1484 * cpl returns completion status for the passthrough command 1485 * specified by cmd. 1486 * 1487 * The following fields will be filled out by the driver, for 1488 * consumption by the caller: 1489 * * cdw0 1490 * * status (except for phase) 1491 * 1492 * Remaining fields will be set to 0 by the driver. 1493 */ 1494 struct nvme_completion cpl; 1495 1496 /* buf is the data buffer associated with this passthrough command. */ 1497 void * buf; 1498 1499 /* 1500 * len is the length of the data buffer associated with this 1501 * passthrough command. 1502 */ 1503 uint32_t len; 1504 1505 /* 1506 * is_read = 1 if the passthrough command will read data into the 1507 * supplied buffer from the controller. 1508 * 1509 * is_read = 0 if the passthrough command will write data from the 1510 * supplied buffer to the controller. 1511 */ 1512 uint32_t is_read; 1513 1514 /* 1515 * driver_lock is used by the driver only. It must be set to 0 1516 * by the caller. 1517 */ 1518 struct mtx * driver_lock; 1519 }; 1520 1521 struct nvme_get_nsid { 1522 char cdev[SPECNAMELEN + 1]; 1523 uint32_t nsid; 1524 }; 1525 1526 struct nvme_hmb_desc { 1527 uint64_t addr; 1528 uint32_t size; 1529 uint32_t reserved; 1530 }; 1531 1532 #define nvme_completion_is_error(cpl) \ 1533 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0) 1534 1535 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1536 1537 #ifdef _KERNEL 1538 1539 struct bio; 1540 struct thread; 1541 1542 struct nvme_namespace; 1543 struct nvme_controller; 1544 struct nvme_consumer; 1545 1546 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1547 1548 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1549 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1550 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1551 uint32_t, void *, uint32_t); 1552 typedef void (*nvme_cons_fail_fn_t)(void *); 1553 1554 enum nvme_namespace_flags { 1555 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1556 NVME_NS_FLUSH_SUPPORTED = 0x2, 1557 }; 1558 1559 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1560 struct nvme_pt_command *pt, 1561 uint32_t nsid, int is_user_buffer, 1562 int is_admin_cmd); 1563 1564 /* Admin functions */ 1565 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1566 uint8_t feature, uint32_t cdw11, 1567 uint32_t cdw12, uint32_t cdw13, 1568 uint32_t cdw14, uint32_t cdw15, 1569 void *payload, uint32_t payload_size, 1570 nvme_cb_fn_t cb_fn, void *cb_arg); 1571 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1572 uint8_t feature, uint32_t cdw11, 1573 void *payload, uint32_t payload_size, 1574 nvme_cb_fn_t cb_fn, void *cb_arg); 1575 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1576 uint8_t log_page, uint32_t nsid, 1577 void *payload, uint32_t payload_size, 1578 nvme_cb_fn_t cb_fn, void *cb_arg); 1579 1580 /* NVM I/O functions */ 1581 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1582 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1583 void *cb_arg); 1584 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1585 nvme_cb_fn_t cb_fn, void *cb_arg); 1586 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1587 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1588 void *cb_arg); 1589 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1590 nvme_cb_fn_t cb_fn, void *cb_arg); 1591 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1592 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1593 void *cb_arg); 1594 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1595 void *cb_arg); 1596 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1597 size_t len); 1598 1599 /* Registration functions */ 1600 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1601 nvme_cons_ctrlr_fn_t ctrlr_fn, 1602 nvme_cons_async_fn_t async_fn, 1603 nvme_cons_fail_fn_t fail_fn); 1604 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1605 1606 /* Controller helper functions */ 1607 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1608 const struct nvme_controller_data * 1609 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1610 static inline bool 1611 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd) 1612 { 1613 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */ 1614 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) & 1615 NVME_CTRLR_DATA_ONCS_DSM_MASK); 1616 } 1617 1618 /* Namespace helper functions */ 1619 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1620 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1621 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1622 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1623 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1624 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1625 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1626 const struct nvme_namespace_data * 1627 nvme_ns_get_data(struct nvme_namespace *ns); 1628 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1629 1630 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1631 nvme_cb_fn_t cb_fn); 1632 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd, 1633 caddr_t arg, int flag, struct thread *td); 1634 1635 /* 1636 * Command building helper functions -- shared with CAM 1637 * These functions assume allocator zeros out cmd structure 1638 * CAM's xpt_get_ccb and the request allocator for nvme both 1639 * do zero'd allocations. 1640 */ 1641 static inline 1642 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1643 { 1644 1645 cmd->opc = NVME_OPC_FLUSH; 1646 cmd->nsid = htole32(nsid); 1647 } 1648 1649 static inline 1650 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1651 uint64_t lba, uint32_t count) 1652 { 1653 cmd->opc = rwcmd; 1654 cmd->nsid = htole32(nsid); 1655 cmd->cdw10 = htole32(lba & 0xffffffffu); 1656 cmd->cdw11 = htole32(lba >> 32); 1657 cmd->cdw12 = htole32(count-1); 1658 } 1659 1660 static inline 1661 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1662 uint64_t lba, uint32_t count) 1663 { 1664 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1665 } 1666 1667 static inline 1668 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1669 uint64_t lba, uint32_t count) 1670 { 1671 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1672 } 1673 1674 static inline 1675 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1676 uint32_t num_ranges) 1677 { 1678 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1679 cmd->nsid = htole32(nsid); 1680 cmd->cdw10 = htole32(num_ranges - 1); 1681 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE); 1682 } 1683 1684 extern int nvme_use_nvd; 1685 1686 #endif /* _KERNEL */ 1687 1688 /* Endianess conversion functions for NVMe structs */ 1689 static inline 1690 void nvme_completion_swapbytes(struct nvme_completion *s) 1691 { 1692 1693 s->cdw0 = le32toh(s->cdw0); 1694 /* omit rsvd1 */ 1695 s->sqhd = le16toh(s->sqhd); 1696 s->sqid = le16toh(s->sqid); 1697 /* omit cid */ 1698 s->status = le16toh(s->status); 1699 } 1700 1701 static inline 1702 void nvme_power_state_swapbytes(struct nvme_power_state *s) 1703 { 1704 1705 s->mp = le16toh(s->mp); 1706 s->enlat = le32toh(s->enlat); 1707 s->exlat = le32toh(s->exlat); 1708 s->idlp = le16toh(s->idlp); 1709 s->actp = le16toh(s->actp); 1710 } 1711 1712 static inline 1713 void nvme_controller_data_swapbytes(struct nvme_controller_data *s) 1714 { 1715 int i; 1716 1717 s->vid = le16toh(s->vid); 1718 s->ssvid = le16toh(s->ssvid); 1719 s->ctrlr_id = le16toh(s->ctrlr_id); 1720 s->ver = le32toh(s->ver); 1721 s->rtd3r = le32toh(s->rtd3r); 1722 s->rtd3e = le32toh(s->rtd3e); 1723 s->oaes = le32toh(s->oaes); 1724 s->ctratt = le32toh(s->ctratt); 1725 s->rrls = le16toh(s->rrls); 1726 s->crdt1 = le16toh(s->crdt1); 1727 s->crdt2 = le16toh(s->crdt2); 1728 s->crdt3 = le16toh(s->crdt3); 1729 s->oacs = le16toh(s->oacs); 1730 s->wctemp = le16toh(s->wctemp); 1731 s->cctemp = le16toh(s->cctemp); 1732 s->mtfa = le16toh(s->mtfa); 1733 s->hmpre = le32toh(s->hmpre); 1734 s->hmmin = le32toh(s->hmmin); 1735 s->rpmbs = le32toh(s->rpmbs); 1736 s->edstt = le16toh(s->edstt); 1737 s->kas = le16toh(s->kas); 1738 s->hctma = le16toh(s->hctma); 1739 s->mntmt = le16toh(s->mntmt); 1740 s->mxtmt = le16toh(s->mxtmt); 1741 s->sanicap = le32toh(s->sanicap); 1742 s->hmminds = le32toh(s->hmminds); 1743 s->hmmaxd = le16toh(s->hmmaxd); 1744 s->nsetidmax = le16toh(s->nsetidmax); 1745 s->endgidmax = le16toh(s->endgidmax); 1746 s->anagrpmax = le32toh(s->anagrpmax); 1747 s->nanagrpid = le32toh(s->nanagrpid); 1748 s->pels = le32toh(s->pels); 1749 s->maxcmd = le16toh(s->maxcmd); 1750 s->nn = le32toh(s->nn); 1751 s->oncs = le16toh(s->oncs); 1752 s->fuses = le16toh(s->fuses); 1753 s->awun = le16toh(s->awun); 1754 s->awupf = le16toh(s->awupf); 1755 s->acwu = le16toh(s->acwu); 1756 s->sgls = le32toh(s->sgls); 1757 s->mnan = le32toh(s->mnan); 1758 for (i = 0; i < 32; i++) 1759 nvme_power_state_swapbytes(&s->power_state[i]); 1760 } 1761 1762 static inline 1763 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s) 1764 { 1765 int i; 1766 1767 s->nsze = le64toh(s->nsze); 1768 s->ncap = le64toh(s->ncap); 1769 s->nuse = le64toh(s->nuse); 1770 s->nawun = le16toh(s->nawun); 1771 s->nawupf = le16toh(s->nawupf); 1772 s->nacwu = le16toh(s->nacwu); 1773 s->nabsn = le16toh(s->nabsn); 1774 s->nabo = le16toh(s->nabo); 1775 s->nabspf = le16toh(s->nabspf); 1776 s->noiob = le16toh(s->noiob); 1777 s->npwg = le16toh(s->npwg); 1778 s->npwa = le16toh(s->npwa); 1779 s->npdg = le16toh(s->npdg); 1780 s->npda = le16toh(s->npda); 1781 s->nows = le16toh(s->nows); 1782 s->anagrpid = le32toh(s->anagrpid); 1783 s->nvmsetid = le16toh(s->nvmsetid); 1784 s->endgid = le16toh(s->endgid); 1785 for (i = 0; i < 16; i++) 1786 s->lbaf[i] = le32toh(s->lbaf[i]); 1787 } 1788 1789 static inline 1790 void nvme_error_information_entry_swapbytes(struct nvme_error_information_entry *s) 1791 { 1792 1793 s->error_count = le64toh(s->error_count); 1794 s->sqid = le16toh(s->sqid); 1795 s->cid = le16toh(s->cid); 1796 s->status = le16toh(s->status); 1797 s->error_location = le16toh(s->error_location); 1798 s->lba = le64toh(s->lba); 1799 s->nsid = le32toh(s->nsid); 1800 s->csi = le64toh(s->csi); 1801 s->ttsi = le16toh(s->ttsi); 1802 } 1803 1804 static inline 1805 void nvme_le128toh(void *p) 1806 { 1807 #if _BYTE_ORDER != _LITTLE_ENDIAN 1808 /* Swap 16 bytes in place */ 1809 char *tmp = (char*)p; 1810 char b; 1811 int i; 1812 for (i = 0; i < 8; i++) { 1813 b = tmp[i]; 1814 tmp[i] = tmp[15-i]; 1815 tmp[15-i] = b; 1816 } 1817 #else 1818 (void)p; 1819 #endif 1820 } 1821 1822 static inline 1823 void nvme_health_information_page_swapbytes(struct nvme_health_information_page *s) 1824 { 1825 int i; 1826 1827 s->temperature = le16toh(s->temperature); 1828 nvme_le128toh((void *)s->data_units_read); 1829 nvme_le128toh((void *)s->data_units_written); 1830 nvme_le128toh((void *)s->host_read_commands); 1831 nvme_le128toh((void *)s->host_write_commands); 1832 nvme_le128toh((void *)s->controller_busy_time); 1833 nvme_le128toh((void *)s->power_cycles); 1834 nvme_le128toh((void *)s->power_on_hours); 1835 nvme_le128toh((void *)s->unsafe_shutdowns); 1836 nvme_le128toh((void *)s->media_errors); 1837 nvme_le128toh((void *)s->num_error_info_log_entries); 1838 s->warning_temp_time = le32toh(s->warning_temp_time); 1839 s->error_temp_time = le32toh(s->error_temp_time); 1840 for (i = 0; i < 8; i++) 1841 s->temp_sensor[i] = le16toh(s->temp_sensor[i]); 1842 s->tmt1tc = le32toh(s->tmt1tc); 1843 s->tmt2tc = le32toh(s->tmt2tc); 1844 s->ttftmt1 = le32toh(s->ttftmt1); 1845 s->ttftmt2 = le32toh(s->ttftmt2); 1846 } 1847 1848 static inline 1849 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s) 1850 { 1851 int i; 1852 1853 for (i = 0; i < 7; i++) 1854 s->revision[i] = le64toh(s->revision[i]); 1855 } 1856 1857 static inline 1858 void nvme_ns_list_swapbytes(struct nvme_ns_list *s) 1859 { 1860 int i; 1861 1862 for (i = 0; i < 1024; i++) 1863 s->ns[i] = le32toh(s->ns[i]); 1864 } 1865 1866 static inline 1867 void nvme_command_effects_page_swapbytes(struct nvme_command_effects_page *s) 1868 { 1869 int i; 1870 1871 for (i = 0; i < 256; i++) 1872 s->acs[i] = le32toh(s->acs[i]); 1873 for (i = 0; i < 256; i++) 1874 s->iocs[i] = le32toh(s->iocs[i]); 1875 } 1876 1877 static inline 1878 void nvme_res_notification_page_swapbytes(struct nvme_res_notification_page *s) 1879 { 1880 s->log_page_count = le64toh(s->log_page_count); 1881 s->nsid = le32toh(s->nsid); 1882 } 1883 1884 static inline 1885 void nvme_sanitize_status_page_swapbytes(struct nvme_sanitize_status_page *s) 1886 { 1887 s->sprog = le16toh(s->sprog); 1888 s->sstat = le16toh(s->sstat); 1889 s->scdw10 = le32toh(s->scdw10); 1890 s->etfo = le32toh(s->etfo); 1891 s->etfbe = le32toh(s->etfbe); 1892 s->etfce = le32toh(s->etfce); 1893 s->etfownd = le32toh(s->etfownd); 1894 s->etfbewnd = le32toh(s->etfbewnd); 1895 s->etfcewnd = le32toh(s->etfcewnd); 1896 } 1897 1898 static inline 1899 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s) 1900 { 1901 1902 s->current = le64toh(s->current); 1903 s->overtemp_flag_last = le64toh(s->overtemp_flag_last); 1904 s->overtemp_flag_life = le64toh(s->overtemp_flag_life); 1905 s->max_temp = le64toh(s->max_temp); 1906 s->min_temp = le64toh(s->min_temp); 1907 /* omit _rsvd[] */ 1908 s->max_oper_temp = le64toh(s->max_oper_temp); 1909 s->min_oper_temp = le64toh(s->min_oper_temp); 1910 s->est_offset = le64toh(s->est_offset); 1911 } 1912 1913 static inline 1914 void nvme_resv_status_swapbytes(struct nvme_resv_status *s, size_t size) 1915 { 1916 u_int i, n; 1917 1918 s->gen = le32toh(s->gen); 1919 n = (s->regctl[1] << 8) | s->regctl[0]; 1920 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0])); 1921 for (i = 0; i < n; i++) { 1922 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id); 1923 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid); 1924 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey); 1925 } 1926 } 1927 1928 static inline 1929 void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s, size_t size) 1930 { 1931 u_int i, n; 1932 1933 s->gen = le32toh(s->gen); 1934 n = (s->regctl[1] << 8) | s->regctl[0]; 1935 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0])); 1936 for (i = 0; i < n; i++) { 1937 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id); 1938 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey); 1939 nvme_le128toh((void *)s->ctrlr[i].hostid); 1940 } 1941 } 1942 1943 #endif /* __NVME_H__ */ 1944