1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_H__ 32 #define __NVME_H__ 33 34 #ifdef _KERNEL 35 #include <sys/types.h> 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/endian.h> 40 41 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 42 #define NVME_RESET_CONTROLLER _IO('n', 1) 43 #define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid) 44 #define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t) 45 46 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 47 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 48 49 /* 50 * Macros to deal with NVME revisions, as defined VS register 51 */ 52 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 53 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 54 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 55 56 /* 57 * Use to mark a command to apply to all namespaces, or to retrieve global 58 * log pages. 59 */ 60 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 61 62 /* Host memory buffer sizes are always in 4096 byte chunks */ 63 #define NVME_HMB_UNITS 4096 64 65 /* Many items are expressed in terms of power of two times MPS */ 66 #define NVME_MPS_SHIFT 12 67 68 /* Register field definitions */ 69 #define NVME_CAP_LO_REG_MQES_SHIFT (0) 70 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 71 #define NVME_CAP_LO_REG_CQR_SHIFT (16) 72 #define NVME_CAP_LO_REG_CQR_MASK (0x1) 73 #define NVME_CAP_LO_REG_AMS_SHIFT (17) 74 #define NVME_CAP_LO_REG_AMS_MASK (0x3) 75 #define NVME_CAP_LO_REG_TO_SHIFT (24) 76 #define NVME_CAP_LO_REG_TO_MASK (0xFF) 77 #define NVME_CAP_LO_MQES(x) \ 78 (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK) 79 #define NVME_CAP_LO_CQR(x) \ 80 (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK) 81 #define NVME_CAP_LO_AMS(x) \ 82 (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK) 83 #define NVME_CAP_LO_TO(x) \ 84 (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK) 85 86 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0) 87 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF) 88 #define NVME_CAP_HI_REG_NSSRS_SHIFT (4) 89 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1) 90 #define NVME_CAP_HI_REG_CSS_SHIFT (5) 91 #define NVME_CAP_HI_REG_CSS_MASK (0xff) 92 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5) 93 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1) 94 #define NVME_CAP_HI_REG_BPS_SHIFT (13) 95 #define NVME_CAP_HI_REG_BPS_MASK (0x1) 96 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16) 97 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF) 98 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20) 99 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF) 100 #define NVME_CAP_HI_REG_PMRS_SHIFT (24) 101 #define NVME_CAP_HI_REG_PMRS_MASK (0x1) 102 #define NVME_CAP_HI_REG_CMBS_SHIFT (25) 103 #define NVME_CAP_HI_REG_CMBS_MASK (0x1) 104 #define NVME_CAP_HI_DSTRD(x) \ 105 (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK) 106 #define NVME_CAP_HI_NSSRS(x) \ 107 (((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK) 108 #define NVME_CAP_HI_CSS(x) \ 109 (((x) >> NVME_CAP_HI_REG_CSS_SHIFT) & NVME_CAP_HI_REG_CSS_MASK) 110 #define NVME_CAP_HI_CSS_NVM(x) \ 111 (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK) 112 #define NVME_CAP_HI_BPS(x) \ 113 (((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK) 114 #define NVME_CAP_HI_MPSMIN(x) \ 115 (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK) 116 #define NVME_CAP_HI_MPSMAX(x) \ 117 (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK) 118 #define NVME_CAP_HI_PMRS(x) \ 119 (((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK) 120 #define NVME_CAP_HI_CMBS(x) \ 121 (((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK) 122 123 #define NVME_CC_REG_EN_SHIFT (0) 124 #define NVME_CC_REG_EN_MASK (0x1) 125 #define NVME_CC_REG_CSS_SHIFT (4) 126 #define NVME_CC_REG_CSS_MASK (0x7) 127 #define NVME_CC_REG_MPS_SHIFT (7) 128 #define NVME_CC_REG_MPS_MASK (0xF) 129 #define NVME_CC_REG_AMS_SHIFT (11) 130 #define NVME_CC_REG_AMS_MASK (0x7) 131 #define NVME_CC_REG_SHN_SHIFT (14) 132 #define NVME_CC_REG_SHN_MASK (0x3) 133 #define NVME_CC_REG_IOSQES_SHIFT (16) 134 #define NVME_CC_REG_IOSQES_MASK (0xF) 135 #define NVME_CC_REG_IOCQES_SHIFT (20) 136 #define NVME_CC_REG_IOCQES_MASK (0xF) 137 138 #define NVME_CSTS_REG_RDY_SHIFT (0) 139 #define NVME_CSTS_REG_RDY_MASK (0x1) 140 #define NVME_CSTS_REG_CFS_SHIFT (1) 141 #define NVME_CSTS_REG_CFS_MASK (0x1) 142 #define NVME_CSTS_REG_SHST_SHIFT (2) 143 #define NVME_CSTS_REG_SHST_MASK (0x3) 144 #define NVME_CSTS_REG_NVSRO_SHIFT (4) 145 #define NVME_CSTS_REG_NVSRO_MASK (0x1) 146 #define NVME_CSTS_REG_PP_SHIFT (5) 147 #define NVME_CSTS_REG_PP_MASK (0x1) 148 149 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK) 150 151 #define NVME_AQA_REG_ASQS_SHIFT (0) 152 #define NVME_AQA_REG_ASQS_MASK (0xFFF) 153 #define NVME_AQA_REG_ACQS_SHIFT (16) 154 #define NVME_AQA_REG_ACQS_MASK (0xFFF) 155 156 #define NVME_PMRCAP_REG_RDS_SHIFT (3) 157 #define NVME_PMRCAP_REG_RDS_MASK (0x1) 158 #define NVME_PMRCAP_REG_WDS_SHIFT (4) 159 #define NVME_PMRCAP_REG_WDS_MASK (0x1) 160 #define NVME_PMRCAP_REG_BIR_SHIFT (5) 161 #define NVME_PMRCAP_REG_BIR_MASK (0x7) 162 #define NVME_PMRCAP_REG_PMRTU_SHIFT (8) 163 #define NVME_PMRCAP_REG_PMRTU_MASK (0x3) 164 #define NVME_PMRCAP_REG_PMRWBM_SHIFT (10) 165 #define NVME_PMRCAP_REG_PMRWBM_MASK (0xf) 166 #define NVME_PMRCAP_REG_PMRTO_SHIFT (16) 167 #define NVME_PMRCAP_REG_PMRTO_MASK (0xff) 168 #define NVME_PMRCAP_REG_CMSS_SHIFT (24) 169 #define NVME_PMRCAP_REG_CMSS_MASK (0x1) 170 171 #define NVME_PMRCAP_RDS(x) \ 172 (((x) >> NVME_PMRCAP_REG_RDS_SHIFT) & NVME_PMRCAP_REG_RDS_MASK) 173 #define NVME_PMRCAP_WDS(x) \ 174 (((x) >> NVME_PMRCAP_REG_WDS_SHIFT) & NVME_PMRCAP_REG_WDS_MASK) 175 #define NVME_PMRCAP_BIR(x) \ 176 (((x) >> NVME_PMRCAP_REG_BIR_SHIFT) & NVME_PMRCAP_REG_BIR_MASK) 177 #define NVME_PMRCAP_PMRTU(x) \ 178 (((x) >> NVME_PMRCAP_REG_PMRTU_SHIFT) & NVME_PMRCAP_REG_PMRTU_MASK) 179 #define NVME_PMRCAP_PMRWBM(x) \ 180 (((x) >> NVME_PMRCAP_REG_PMRWBM_SHIFT) & NVME_PMRCAP_REG_PMRWBM_MASK) 181 #define NVME_PMRCAP_PMRTO(x) \ 182 (((x) >> NVME_PMRCAP_REG_PMRTO_SHIFT) & NVME_PMRCAP_REG_PMRTO_MASK) 183 #define NVME_PMRCAP_CMSS(x) \ 184 (((x) >> NVME_PMRCAP_REG_CMSS_SHIFT) & NVME_PMRCAP_REG_CMSS_MASK) 185 186 /* Command field definitions */ 187 188 #define NVME_CMD_FUSE_SHIFT (8) 189 #define NVME_CMD_FUSE_MASK (0x3) 190 191 #define NVME_STATUS_P_SHIFT (0) 192 #define NVME_STATUS_P_MASK (0x1) 193 #define NVME_STATUS_SC_SHIFT (1) 194 #define NVME_STATUS_SC_MASK (0xFF) 195 #define NVME_STATUS_SCT_SHIFT (9) 196 #define NVME_STATUS_SCT_MASK (0x7) 197 #define NVME_STATUS_CRD_SHIFT (12) 198 #define NVME_STATUS_CRD_MASK (0x3) 199 #define NVME_STATUS_M_SHIFT (14) 200 #define NVME_STATUS_M_MASK (0x1) 201 #define NVME_STATUS_DNR_SHIFT (15) 202 #define NVME_STATUS_DNR_MASK (0x1) 203 204 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 205 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 206 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) 207 #define NVME_STATUS_GET_CRD(st) (((st) >> NVME_STATUS_CRD_SHIFT) & NVME_STATUS_CRD_MASK) 208 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 209 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 210 211 #define NVME_PWR_ST_MPS_SHIFT (0) 212 #define NVME_PWR_ST_MPS_MASK (0x1) 213 #define NVME_PWR_ST_NOPS_SHIFT (1) 214 #define NVME_PWR_ST_NOPS_MASK (0x1) 215 #define NVME_PWR_ST_RRT_SHIFT (0) 216 #define NVME_PWR_ST_RRT_MASK (0x1F) 217 #define NVME_PWR_ST_RRL_SHIFT (0) 218 #define NVME_PWR_ST_RRL_MASK (0x1F) 219 #define NVME_PWR_ST_RWT_SHIFT (0) 220 #define NVME_PWR_ST_RWT_MASK (0x1F) 221 #define NVME_PWR_ST_RWL_SHIFT (0) 222 #define NVME_PWR_ST_RWL_MASK (0x1F) 223 #define NVME_PWR_ST_IPS_SHIFT (6) 224 #define NVME_PWR_ST_IPS_MASK (0x3) 225 #define NVME_PWR_ST_APW_SHIFT (0) 226 #define NVME_PWR_ST_APW_MASK (0x7) 227 #define NVME_PWR_ST_APS_SHIFT (6) 228 #define NVME_PWR_ST_APS_MASK (0x3) 229 230 /** Controller Multi-path I/O and Namespace Sharing Capabilities */ 231 /* More then one port */ 232 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0) 233 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1) 234 /* More then one controller */ 235 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1) 236 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1) 237 /* SR-IOV Virtual Function */ 238 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2) 239 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1) 240 /* Asymmetric Namespace Access Reporting */ 241 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3) 242 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1) 243 244 /** OAES - Optional Asynchronous Events Supported */ 245 /* supports Namespace Attribute Notices event */ 246 #define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8) 247 #define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1) 248 /* supports Firmware Activation Notices event */ 249 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9) 250 #define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1) 251 /* supports Asymmetric Namespace Access Change Notices event */ 252 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11) 253 #define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1) 254 /* supports Predictable Latency Event Aggregate Log Change Notices event */ 255 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12) 256 #define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1) 257 /* supports LBA Status Information Notices event */ 258 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13) 259 #define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1) 260 /* supports Endurance Group Event Aggregate Log Page Changes Notices event */ 261 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14) 262 #define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1) 263 /* supports Normal NVM Subsystem Shutdown event */ 264 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15) 265 #define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1) 266 /* supports Zone Descriptor Changed Notices event */ 267 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27) 268 #define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1) 269 /* supports Discovery Log Page Change Notification event */ 270 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31) 271 #define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1) 272 273 /** OACS - optional admin command support */ 274 /* supports security send/receive commands */ 275 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0) 276 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1) 277 /* supports format nvm command */ 278 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1) 279 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1) 280 /* supports firmware activate/download commands */ 281 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2) 282 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1) 283 /* supports namespace management commands */ 284 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3) 285 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1) 286 /* supports Device Self-test command */ 287 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4) 288 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1) 289 /* supports Directives */ 290 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5) 291 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1) 292 /* supports NVMe-MI Send/Receive */ 293 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6) 294 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1) 295 /* supports Virtualization Management */ 296 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7) 297 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1) 298 /* supports Doorbell Buffer Config */ 299 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8) 300 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1) 301 /* supports Get LBA Status */ 302 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9) 303 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1) 304 305 /** firmware updates */ 306 /* first slot is read-only */ 307 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0) 308 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1) 309 /* number of firmware slots */ 310 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1) 311 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7) 312 /* firmware activation without reset */ 313 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4) 314 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1) 315 316 /** log page attributes */ 317 /* per namespace smart/health log page */ 318 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0) 319 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1) 320 321 /** AVSCC - admin vendor specific command configuration */ 322 /* admin vendor specific commands use spec format */ 323 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0) 324 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1) 325 326 /** Autonomous Power State Transition Attributes */ 327 /* Autonomous Power State Transitions supported */ 328 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0) 329 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1) 330 331 /** Sanitize Capabilities */ 332 /* Crypto Erase Support */ 333 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0) 334 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1) 335 /* Block Erase Support */ 336 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1) 337 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1) 338 /* Overwrite Support */ 339 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2) 340 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1) 341 /* No-Deallocate Inhibited */ 342 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29) 343 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1) 344 /* No-Deallocate Modifies Media After Sanitize */ 345 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30) 346 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3) 347 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0) 348 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1) 349 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2) 350 351 /** submission queue entry size */ 352 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0) 353 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF) 354 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4) 355 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF) 356 357 /** completion queue entry size */ 358 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0) 359 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF) 360 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4) 361 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF) 362 363 /** optional nvm command support */ 364 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0) 365 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1) 366 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1) 367 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1) 368 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2) 369 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1) 370 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3) 371 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1) 372 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4) 373 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1) 374 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5) 375 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1) 376 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6) 377 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1) 378 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7) 379 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1) 380 381 /** Fused Operation Support */ 382 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0) 383 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1) 384 385 /** Format NVM Attributes */ 386 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0) 387 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1) 388 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1) 389 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1) 390 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2) 391 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1) 392 393 /** volatile write cache */ 394 /* volatile write cache present */ 395 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0) 396 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1) 397 /* flush all namespaces supported */ 398 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1) 399 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3) 400 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0) 401 #define NVME_CTRLR_DATA_VWC_ALL_NO (2) 402 #define NVME_CTRLR_DATA_VWC_ALL_YES (3) 403 404 /** namespace features */ 405 /* thin provisioning */ 406 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0) 407 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1) 408 /* NAWUN, NAWUPF, and NACWU fields are valid */ 409 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1) 410 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1) 411 /* Deallocated or Unwritten Logical Block errors supported */ 412 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2) 413 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1) 414 /* NGUID and EUI64 fields are not reusable */ 415 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3) 416 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1) 417 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */ 418 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4) 419 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1) 420 421 /** formatted lba size */ 422 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0) 423 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF) 424 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4) 425 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1) 426 427 /** metadata capabilities */ 428 /* metadata can be transferred as part of data prp list */ 429 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0) 430 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1) 431 /* metadata can be transferred with separate metadata pointer */ 432 #define NVME_NS_DATA_MC_POINTER_SHIFT (1) 433 #define NVME_NS_DATA_MC_POINTER_MASK (0x1) 434 435 /** end-to-end data protection capabilities */ 436 /* protection information type 1 */ 437 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0) 438 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1) 439 /* protection information type 2 */ 440 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1) 441 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1) 442 /* protection information type 3 */ 443 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2) 444 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1) 445 /* first eight bytes of metadata */ 446 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3) 447 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1) 448 /* last eight bytes of metadata */ 449 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4) 450 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1) 451 452 /** end-to-end data protection type settings */ 453 /* protection information type */ 454 #define NVME_NS_DATA_DPS_PIT_SHIFT (0) 455 #define NVME_NS_DATA_DPS_PIT_MASK (0x7) 456 /* 1 == protection info transferred at start of metadata */ 457 /* 0 == protection info transferred at end of metadata */ 458 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3) 459 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1) 460 461 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 462 /* the namespace may be attached to two or more controllers */ 463 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0) 464 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1) 465 466 /** Reservation Capabilities */ 467 /* Persist Through Power Loss */ 468 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0) 469 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1) 470 /* supports the Write Exclusive */ 471 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1) 472 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1) 473 /* supports the Exclusive Access */ 474 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2) 475 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1) 476 /* supports the Write Exclusive – Registrants Only */ 477 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3) 478 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1) 479 /* supports the Exclusive Access - Registrants Only */ 480 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4) 481 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1) 482 /* supports the Write Exclusive – All Registrants */ 483 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5) 484 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1) 485 /* supports the Exclusive Access - All Registrants */ 486 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6) 487 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1) 488 /* Ignore Existing Key is used as defined in revision 1.3 or later */ 489 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7) 490 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1) 491 492 /** Format Progress Indicator */ 493 /* percentage of the Format NVM command that remains to be completed */ 494 #define NVME_NS_DATA_FPI_PERC_SHIFT (0) 495 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f) 496 /* namespace supports the Format Progress Indicator */ 497 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7) 498 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1) 499 500 /** Deallocate Logical Block Features */ 501 /* deallocated logical block read behavior */ 502 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0) 503 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07) 504 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00) 505 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01) 506 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02) 507 /* supports the Deallocate bit in the Write Zeroes */ 508 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3) 509 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01) 510 /* Guard field for deallocated logical blocks is set to the CRC */ 511 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4) 512 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01) 513 514 /** lba format support */ 515 /* metadata size */ 516 #define NVME_NS_DATA_LBAF_MS_SHIFT (0) 517 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF) 518 /* lba data size */ 519 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16) 520 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF) 521 /* relative performance */ 522 #define NVME_NS_DATA_LBAF_RP_SHIFT (24) 523 #define NVME_NS_DATA_LBAF_RP_MASK (0x3) 524 525 enum nvme_critical_warning_state { 526 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1, 527 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2, 528 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4, 529 NVME_CRIT_WARN_ST_READ_ONLY = 0x8, 530 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10, 531 }; 532 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0) 533 #define NVME_ASYNC_EVENT_NS_ATTRIBUTE (0x100) 534 #define NVME_ASYNC_EVENT_FW_ACTIVATE (0x200) 535 536 /* slot for current FW */ 537 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0) 538 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7) 539 540 /* Commands Supported and Effects */ 541 #define NVME_CE_PAGE_CSUP_SHIFT (0) 542 #define NVME_CE_PAGE_CSUP_MASK (0x1) 543 #define NVME_CE_PAGE_LBCC_SHIFT (1) 544 #define NVME_CE_PAGE_LBCC_MASK (0x1) 545 #define NVME_CE_PAGE_NCC_SHIFT (2) 546 #define NVME_CE_PAGE_NCC_MASK (0x1) 547 #define NVME_CE_PAGE_NIC_SHIFT (3) 548 #define NVME_CE_PAGE_NIC_MASK (0x1) 549 #define NVME_CE_PAGE_CCC_SHIFT (4) 550 #define NVME_CE_PAGE_CCC_MASK (0x1) 551 #define NVME_CE_PAGE_CSE_SHIFT (16) 552 #define NVME_CE_PAGE_CSE_MASK (0x7) 553 #define NVME_CE_PAGE_UUID_SHIFT (19) 554 #define NVME_CE_PAGE_UUID_MASK (0x1) 555 556 /* Sanitize Status */ 557 #define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0) 558 #define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7) 559 #define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0) 560 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1) 561 #define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2) 562 #define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3) 563 #define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4) 564 #define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3) 565 #define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f) 566 #define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8) 567 #define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1) 568 569 /* Helper macro to combine *_MASK and *_SHIFT defines */ 570 #define NVMEB(name) (name##_MASK << name##_SHIFT) 571 572 /* CC register SHN field values */ 573 enum shn_value { 574 NVME_SHN_NORMAL = 0x1, 575 NVME_SHN_ABRUPT = 0x2, 576 }; 577 578 /* CSTS register SHST field values */ 579 enum shst_value { 580 NVME_SHST_NORMAL = 0x0, 581 NVME_SHST_OCCURRING = 0x1, 582 NVME_SHST_COMPLETE = 0x2, 583 }; 584 585 struct nvme_registers { 586 uint32_t cap_lo; /* controller capabilities */ 587 uint32_t cap_hi; 588 uint32_t vs; /* version */ 589 uint32_t intms; /* interrupt mask set */ 590 uint32_t intmc; /* interrupt mask clear */ 591 uint32_t cc; /* controller configuration */ 592 uint32_t reserved1; 593 uint32_t csts; /* controller status */ 594 uint32_t nssr; /* NVM Subsystem Reset */ 595 uint32_t aqa; /* admin queue attributes */ 596 uint64_t asq; /* admin submission queue base addr */ 597 uint64_t acq; /* admin completion queue base addr */ 598 uint32_t cmbloc; /* Controller Memory Buffer Location */ 599 uint32_t cmbsz; /* Controller Memory Buffer Size */ 600 uint32_t bpinfo; /* Boot Partition Information */ 601 uint32_t bprsel; /* Boot Partition Read Select */ 602 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */ 603 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */ 604 uint32_t cmbsts; /* Controller Memory Buffer Status */ 605 uint8_t reserved3[3492]; /* 5Ch - DFFh */ 606 uint32_t pmrcap; /* Persistent Memory Capabilities */ 607 uint32_t pmrctl; /* Persistent Memory Region Control */ 608 uint32_t pmrsts; /* Persistent Memory Region Status */ 609 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */ 610 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */ 611 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */ 612 uint32_t pmrmsc_hi; 613 uint8_t reserved4[484]; /* E1Ch - FFFh */ 614 struct { 615 uint32_t sq_tdbl; /* submission queue tail doorbell */ 616 uint32_t cq_hdbl; /* completion queue head doorbell */ 617 } doorbell[1]; 618 }; 619 620 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 621 622 struct nvme_command { 623 /* dword 0 */ 624 uint8_t opc; /* opcode */ 625 uint8_t fuse; /* fused operation */ 626 uint16_t cid; /* command identifier */ 627 628 /* dword 1 */ 629 uint32_t nsid; /* namespace identifier */ 630 631 /* dword 2-3 */ 632 uint32_t rsvd2; 633 uint32_t rsvd3; 634 635 /* dword 4-5 */ 636 uint64_t mptr; /* metadata pointer */ 637 638 /* dword 6-7 */ 639 uint64_t prp1; /* prp entry 1 */ 640 641 /* dword 8-9 */ 642 uint64_t prp2; /* prp entry 2 */ 643 644 /* dword 10-15 */ 645 uint32_t cdw10; /* command-specific */ 646 uint32_t cdw11; /* command-specific */ 647 uint32_t cdw12; /* command-specific */ 648 uint32_t cdw13; /* command-specific */ 649 uint32_t cdw14; /* command-specific */ 650 uint32_t cdw15; /* command-specific */ 651 }; 652 653 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 654 655 struct nvme_completion { 656 /* dword 0 */ 657 uint32_t cdw0; /* command-specific */ 658 659 /* dword 1 */ 660 uint32_t rsvd1; 661 662 /* dword 2 */ 663 uint16_t sqhd; /* submission queue head pointer */ 664 uint16_t sqid; /* submission queue identifier */ 665 666 /* dword 3 */ 667 uint16_t cid; /* command identifier */ 668 uint16_t status; 669 } __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */ 670 671 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 672 673 struct nvme_dsm_range { 674 uint32_t attributes; 675 uint32_t length; 676 uint64_t starting_lba; 677 }; 678 679 /* Largest DSM Trim that can be done */ 680 #define NVME_MAX_DSM_TRIM 4096 681 682 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 683 684 /* status code types */ 685 enum nvme_status_code_type { 686 NVME_SCT_GENERIC = 0x0, 687 NVME_SCT_COMMAND_SPECIFIC = 0x1, 688 NVME_SCT_MEDIA_ERROR = 0x2, 689 NVME_SCT_PATH_RELATED = 0x3, 690 /* 0x3-0x6 - reserved */ 691 NVME_SCT_VENDOR_SPECIFIC = 0x7, 692 }; 693 694 /* generic command status codes */ 695 enum nvme_generic_command_status_code { 696 NVME_SC_SUCCESS = 0x00, 697 NVME_SC_INVALID_OPCODE = 0x01, 698 NVME_SC_INVALID_FIELD = 0x02, 699 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 700 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 701 NVME_SC_ABORTED_POWER_LOSS = 0x05, 702 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 703 NVME_SC_ABORTED_BY_REQUEST = 0x07, 704 NVME_SC_ABORTED_SQ_DELETION = 0x08, 705 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 706 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 707 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 708 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 709 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 710 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 711 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 712 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 713 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 714 NVME_SC_INVALID_USE_OF_CMB = 0x12, 715 NVME_SC_PRP_OFFET_INVALID = 0x13, 716 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 717 NVME_SC_OPERATION_DENIED = 0x15, 718 NVME_SC_SGL_OFFSET_INVALID = 0x16, 719 /* 0x17 - reserved */ 720 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 721 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 722 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 723 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 724 NVME_SC_SANITIZE_FAILED = 0x1c, 725 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 726 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 727 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 728 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20, 729 NVME_SC_COMMAND_INTERRUPTED = 0x21, 730 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22, 731 732 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 733 NVME_SC_CAPACITY_EXCEEDED = 0x81, 734 NVME_SC_NAMESPACE_NOT_READY = 0x82, 735 NVME_SC_RESERVATION_CONFLICT = 0x83, 736 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 737 }; 738 739 /* command specific status codes */ 740 enum nvme_command_specific_status_code { 741 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 742 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 743 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 744 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 745 /* 0x04 - reserved */ 746 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 747 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 748 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 749 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 750 NVME_SC_INVALID_LOG_PAGE = 0x09, 751 NVME_SC_INVALID_FORMAT = 0x0a, 752 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 753 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 754 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 755 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 756 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 757 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 758 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 759 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 760 NVME_SC_FW_ACT_PROHIBITED = 0x13, 761 NVME_SC_OVERLAPPING_RANGE = 0x14, 762 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 763 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 764 /* 0x17 - reserved */ 765 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 766 NVME_SC_NS_IS_PRIVATE = 0x19, 767 NVME_SC_NS_NOT_ATTACHED = 0x1a, 768 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 769 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 770 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d, 771 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 772 NVME_SC_INVALID_CTRLR_ID = 0x1f, 773 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 774 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 775 NVME_SC_INVALID_RESOURCE_ID = 0x22, 776 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23, 777 NVME_SC_ANA_GROUP_ID_INVALID = 0x24, 778 NVME_SC_ANA_ATTACH_FAILED = 0x25, 779 780 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 781 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 782 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 783 }; 784 785 /* media error status codes */ 786 enum nvme_media_error_status_code { 787 NVME_SC_WRITE_FAULTS = 0x80, 788 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 789 NVME_SC_GUARD_CHECK_ERROR = 0x82, 790 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 791 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 792 NVME_SC_COMPARE_FAILURE = 0x85, 793 NVME_SC_ACCESS_DENIED = 0x86, 794 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 795 }; 796 797 /* path related status codes */ 798 enum nvme_path_related_status_code { 799 NVME_SC_INTERNAL_PATH_ERROR = 0x00, 800 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01, 801 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02, 802 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03, 803 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60, 804 NVME_SC_HOST_PATHING_ERROR = 0x70, 805 NVME_SC_COMMAND_ABOTHED_BY_HOST = 0x71, 806 }; 807 808 /* admin opcodes */ 809 enum nvme_admin_opcode { 810 NVME_OPC_DELETE_IO_SQ = 0x00, 811 NVME_OPC_CREATE_IO_SQ = 0x01, 812 NVME_OPC_GET_LOG_PAGE = 0x02, 813 /* 0x03 - reserved */ 814 NVME_OPC_DELETE_IO_CQ = 0x04, 815 NVME_OPC_CREATE_IO_CQ = 0x05, 816 NVME_OPC_IDENTIFY = 0x06, 817 /* 0x07 - reserved */ 818 NVME_OPC_ABORT = 0x08, 819 NVME_OPC_SET_FEATURES = 0x09, 820 NVME_OPC_GET_FEATURES = 0x0a, 821 /* 0x0b - reserved */ 822 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 823 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 824 /* 0x0e-0x0f - reserved */ 825 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 826 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 827 /* 0x12-0x13 - reserved */ 828 NVME_OPC_DEVICE_SELF_TEST = 0x14, 829 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 830 /* 0x16-0x17 - reserved */ 831 NVME_OPC_KEEP_ALIVE = 0x18, 832 NVME_OPC_DIRECTIVE_SEND = 0x19, 833 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 834 /* 0x1b - reserved */ 835 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 836 NVME_OPC_NVME_MI_SEND = 0x1d, 837 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 838 /* 0x1f-0x7b - reserved */ 839 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 840 841 NVME_OPC_FORMAT_NVM = 0x80, 842 NVME_OPC_SECURITY_SEND = 0x81, 843 NVME_OPC_SECURITY_RECEIVE = 0x82, 844 /* 0x83 - reserved */ 845 NVME_OPC_SANITIZE = 0x84, 846 /* 0x85 - reserved */ 847 NVME_OPC_GET_LBA_STATUS = 0x86, 848 }; 849 850 /* nvme nvm opcodes */ 851 enum nvme_nvm_opcode { 852 NVME_OPC_FLUSH = 0x00, 853 NVME_OPC_WRITE = 0x01, 854 NVME_OPC_READ = 0x02, 855 /* 0x03 - reserved */ 856 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 857 NVME_OPC_COMPARE = 0x05, 858 /* 0x06-0x07 - reserved */ 859 NVME_OPC_WRITE_ZEROES = 0x08, 860 NVME_OPC_DATASET_MANAGEMENT = 0x09, 861 /* 0x0a-0x0b - reserved */ 862 NVME_OPC_VERIFY = 0x0c, 863 NVME_OPC_RESERVATION_REGISTER = 0x0d, 864 NVME_OPC_RESERVATION_REPORT = 0x0e, 865 /* 0x0f-0x10 - reserved */ 866 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 867 /* 0x12-0x14 - reserved */ 868 NVME_OPC_RESERVATION_RELEASE = 0x15, 869 }; 870 871 enum nvme_feature { 872 /* 0x00 - reserved */ 873 NVME_FEAT_ARBITRATION = 0x01, 874 NVME_FEAT_POWER_MANAGEMENT = 0x02, 875 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 876 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 877 NVME_FEAT_ERROR_RECOVERY = 0x05, 878 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 879 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 880 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 881 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 882 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 883 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 884 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 885 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 886 NVME_FEAT_TIMESTAMP = 0x0E, 887 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 888 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 889 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 890 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12, 891 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13, 892 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14, 893 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15, 894 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16, 895 NVME_FEAT_SANITIZE_CONFIG = 0x17, 896 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18, 897 /* 0x19-0x77 - reserved */ 898 /* 0x78-0x7f - NVMe Management Interface */ 899 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 900 NVME_FEAT_HOST_IDENTIFIER = 0x81, 901 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82, 902 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83, 903 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84, 904 /* 0x85-0xBF - command set specific (reserved) */ 905 /* 0xC0-0xFF - vendor specific */ 906 }; 907 908 enum nvme_dsm_attribute { 909 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 910 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 911 NVME_DSM_ATTR_DEALLOCATE = 0x4, 912 }; 913 914 enum nvme_activate_action { 915 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 916 NVME_AA_REPLACE_ACTIVATE = 0x1, 917 NVME_AA_ACTIVATE = 0x2, 918 }; 919 920 struct nvme_power_state { 921 /** Maximum Power */ 922 uint16_t mp; /* Maximum Power */ 923 uint8_t ps_rsvd1; 924 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */ 925 926 uint32_t enlat; /* Entry Latency */ 927 uint32_t exlat; /* Exit Latency */ 928 929 uint8_t rrt; /* Relative Read Throughput */ 930 uint8_t rrl; /* Relative Read Latency */ 931 uint8_t rwt; /* Relative Write Throughput */ 932 uint8_t rwl; /* Relative Write Latency */ 933 934 uint16_t idlp; /* Idle Power */ 935 uint8_t ips; /* Idle Power Scale */ 936 uint8_t ps_rsvd8; 937 938 uint16_t actp; /* Active Power */ 939 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ 940 uint8_t ps_rsvd10[9]; 941 } __packed; 942 943 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 944 945 #define NVME_SERIAL_NUMBER_LENGTH 20 946 #define NVME_MODEL_NUMBER_LENGTH 40 947 #define NVME_FIRMWARE_REVISION_LENGTH 8 948 949 struct nvme_controller_data { 950 /* bytes 0-255: controller capabilities and features */ 951 952 /** pci vendor id */ 953 uint16_t vid; 954 955 /** pci subsystem vendor id */ 956 uint16_t ssvid; 957 958 /** serial number */ 959 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 960 961 /** model number */ 962 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 963 964 /** firmware revision */ 965 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 966 967 /** recommended arbitration burst */ 968 uint8_t rab; 969 970 /** ieee oui identifier */ 971 uint8_t ieee[3]; 972 973 /** multi-interface capabilities */ 974 uint8_t mic; 975 976 /** maximum data transfer size */ 977 uint8_t mdts; 978 979 /** Controller ID */ 980 uint16_t ctrlr_id; 981 982 /** Version */ 983 uint32_t ver; 984 985 /** RTD3 Resume Latency */ 986 uint32_t rtd3r; 987 988 /** RTD3 Enter Latency */ 989 uint32_t rtd3e; 990 991 /** Optional Asynchronous Events Supported */ 992 uint32_t oaes; /* bitfield really */ 993 994 /** Controller Attributes */ 995 uint32_t ctratt; /* bitfield really */ 996 997 /** Read Recovery Levels Supported */ 998 uint16_t rrls; 999 1000 uint8_t reserved1[9]; 1001 1002 /** Controller Type */ 1003 uint8_t cntrltype; 1004 1005 /** FRU Globally Unique Identifier */ 1006 uint8_t fguid[16]; 1007 1008 /** Command Retry Delay Time 1 */ 1009 uint16_t crdt1; 1010 1011 /** Command Retry Delay Time 2 */ 1012 uint16_t crdt2; 1013 1014 /** Command Retry Delay Time 3 */ 1015 uint16_t crdt3; 1016 1017 uint8_t reserved2[122]; 1018 1019 /* bytes 256-511: admin command set attributes */ 1020 1021 /** optional admin command support */ 1022 uint16_t oacs; 1023 1024 /** abort command limit */ 1025 uint8_t acl; 1026 1027 /** asynchronous event request limit */ 1028 uint8_t aerl; 1029 1030 /** firmware updates */ 1031 uint8_t frmw; 1032 1033 /** log page attributes */ 1034 uint8_t lpa; 1035 1036 /** error log page entries */ 1037 uint8_t elpe; 1038 1039 /** number of power states supported */ 1040 uint8_t npss; 1041 1042 /** admin vendor specific command configuration */ 1043 uint8_t avscc; 1044 1045 /** Autonomous Power State Transition Attributes */ 1046 uint8_t apsta; 1047 1048 /** Warning Composite Temperature Threshold */ 1049 uint16_t wctemp; 1050 1051 /** Critical Composite Temperature Threshold */ 1052 uint16_t cctemp; 1053 1054 /** Maximum Time for Firmware Activation */ 1055 uint16_t mtfa; 1056 1057 /** Host Memory Buffer Preferred Size */ 1058 uint32_t hmpre; 1059 1060 /** Host Memory Buffer Minimum Size */ 1061 uint32_t hmmin; 1062 1063 /** Name space capabilities */ 1064 struct { 1065 /* if nsmgmt, report tnvmcap and unvmcap */ 1066 uint8_t tnvmcap[16]; 1067 uint8_t unvmcap[16]; 1068 } __packed untncap; 1069 1070 /** Replay Protected Memory Block Support */ 1071 uint32_t rpmbs; /* Really a bitfield */ 1072 1073 /** Extended Device Self-test Time */ 1074 uint16_t edstt; 1075 1076 /** Device Self-test Options */ 1077 uint8_t dsto; /* Really a bitfield */ 1078 1079 /** Firmware Update Granularity */ 1080 uint8_t fwug; 1081 1082 /** Keep Alive Support */ 1083 uint16_t kas; 1084 1085 /** Host Controlled Thermal Management Attributes */ 1086 uint16_t hctma; /* Really a bitfield */ 1087 1088 /** Minimum Thermal Management Temperature */ 1089 uint16_t mntmt; 1090 1091 /** Maximum Thermal Management Temperature */ 1092 uint16_t mxtmt; 1093 1094 /** Sanitize Capabilities */ 1095 uint32_t sanicap; /* Really a bitfield */ 1096 1097 /** Host Memory Buffer Minimum Descriptor Entry Size */ 1098 uint32_t hmminds; 1099 1100 /** Host Memory Maximum Descriptors Entries */ 1101 uint16_t hmmaxd; 1102 1103 /** NVM Set Identifier Maximum */ 1104 uint16_t nsetidmax; 1105 1106 /** Endurance Group Identifier Maximum */ 1107 uint16_t endgidmax; 1108 1109 /** ANA Transition Time */ 1110 uint8_t anatt; 1111 1112 /** Asymmetric Namespace Access Capabilities */ 1113 uint8_t anacap; 1114 1115 /** ANA Group Identifier Maximum */ 1116 uint32_t anagrpmax; 1117 1118 /** Number of ANA Group Identifiers */ 1119 uint32_t nanagrpid; 1120 1121 /** Persistent Event Log Size */ 1122 uint32_t pels; 1123 1124 uint8_t reserved3[156]; 1125 /* bytes 512-703: nvm command set attributes */ 1126 1127 /** submission queue entry size */ 1128 uint8_t sqes; 1129 1130 /** completion queue entry size */ 1131 uint8_t cqes; 1132 1133 /** Maximum Outstanding Commands */ 1134 uint16_t maxcmd; 1135 1136 /** number of namespaces */ 1137 uint32_t nn; 1138 1139 /** optional nvm command support */ 1140 uint16_t oncs; 1141 1142 /** fused operation support */ 1143 uint16_t fuses; 1144 1145 /** format nvm attributes */ 1146 uint8_t fna; 1147 1148 /** volatile write cache */ 1149 uint8_t vwc; 1150 1151 /** Atomic Write Unit Normal */ 1152 uint16_t awun; 1153 1154 /** Atomic Write Unit Power Fail */ 1155 uint16_t awupf; 1156 1157 /** NVM Vendor Specific Command Configuration */ 1158 uint8_t nvscc; 1159 1160 /** Namespace Write Protection Capabilities */ 1161 uint8_t nwpc; 1162 1163 /** Atomic Compare & Write Unit */ 1164 uint16_t acwu; 1165 uint16_t reserved6; 1166 1167 /** SGL Support */ 1168 uint32_t sgls; 1169 1170 /** Maximum Number of Allowed Namespaces */ 1171 uint32_t mnan; 1172 1173 /* bytes 540-767: Reserved */ 1174 uint8_t reserved7[224]; 1175 1176 /** NVM Subsystem NVMe Qualified Name */ 1177 uint8_t subnqn[256]; 1178 1179 /* bytes 1024-1791: Reserved */ 1180 uint8_t reserved8[768]; 1181 1182 /* bytes 1792-2047: NVMe over Fabrics specification */ 1183 uint8_t reserved9[256]; 1184 1185 /* bytes 2048-3071: power state descriptors */ 1186 struct nvme_power_state power_state[32]; 1187 1188 /* bytes 3072-4095: vendor specific */ 1189 uint8_t vs[1024]; 1190 } __packed __aligned(4); 1191 1192 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 1193 1194 struct nvme_namespace_data { 1195 /** namespace size */ 1196 uint64_t nsze; 1197 1198 /** namespace capacity */ 1199 uint64_t ncap; 1200 1201 /** namespace utilization */ 1202 uint64_t nuse; 1203 1204 /** namespace features */ 1205 uint8_t nsfeat; 1206 1207 /** number of lba formats */ 1208 uint8_t nlbaf; 1209 1210 /** formatted lba size */ 1211 uint8_t flbas; 1212 1213 /** metadata capabilities */ 1214 uint8_t mc; 1215 1216 /** end-to-end data protection capabilities */ 1217 uint8_t dpc; 1218 1219 /** end-to-end data protection type settings */ 1220 uint8_t dps; 1221 1222 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 1223 uint8_t nmic; 1224 1225 /** Reservation Capabilities */ 1226 uint8_t rescap; 1227 1228 /** Format Progress Indicator */ 1229 uint8_t fpi; 1230 1231 /** Deallocate Logical Block Features */ 1232 uint8_t dlfeat; 1233 1234 /** Namespace Atomic Write Unit Normal */ 1235 uint16_t nawun; 1236 1237 /** Namespace Atomic Write Unit Power Fail */ 1238 uint16_t nawupf; 1239 1240 /** Namespace Atomic Compare & Write Unit */ 1241 uint16_t nacwu; 1242 1243 /** Namespace Atomic Boundary Size Normal */ 1244 uint16_t nabsn; 1245 1246 /** Namespace Atomic Boundary Offset */ 1247 uint16_t nabo; 1248 1249 /** Namespace Atomic Boundary Size Power Fail */ 1250 uint16_t nabspf; 1251 1252 /** Namespace Optimal IO Boundary */ 1253 uint16_t noiob; 1254 1255 /** NVM Capacity */ 1256 uint8_t nvmcap[16]; 1257 1258 /** Namespace Preferred Write Granularity */ 1259 uint16_t npwg; 1260 1261 /** Namespace Preferred Write Alignment */ 1262 uint16_t npwa; 1263 1264 /** Namespace Preferred Deallocate Granularity */ 1265 uint16_t npdg; 1266 1267 /** Namespace Preferred Deallocate Alignment */ 1268 uint16_t npda; 1269 1270 /** Namespace Optimal Write Size */ 1271 uint16_t nows; 1272 1273 /* bytes 74-91: Reserved */ 1274 uint8_t reserved5[18]; 1275 1276 /** ANA Group Identifier */ 1277 uint32_t anagrpid; 1278 1279 /* bytes 96-98: Reserved */ 1280 uint8_t reserved6[3]; 1281 1282 /** Namespace Attributes */ 1283 uint8_t nsattr; 1284 1285 /** NVM Set Identifier */ 1286 uint16_t nvmsetid; 1287 1288 /** Endurance Group Identifier */ 1289 uint16_t endgid; 1290 1291 /** Namespace Globally Unique Identifier */ 1292 uint8_t nguid[16]; 1293 1294 /** IEEE Extended Unique Identifier */ 1295 uint8_t eui64[8]; 1296 1297 /** lba format support */ 1298 uint32_t lbaf[16]; 1299 1300 uint8_t reserved7[192]; 1301 1302 uint8_t vendor_specific[3712]; 1303 } __packed __aligned(4); 1304 1305 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 1306 1307 enum nvme_log_page { 1308 /* 0x00 - reserved */ 1309 NVME_LOG_ERROR = 0x01, 1310 NVME_LOG_HEALTH_INFORMATION = 0x02, 1311 NVME_LOG_FIRMWARE_SLOT = 0x03, 1312 NVME_LOG_CHANGED_NAMESPACE = 0x04, 1313 NVME_LOG_COMMAND_EFFECT = 0x05, 1314 NVME_LOG_DEVICE_SELF_TEST = 0x06, 1315 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07, 1316 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08, 1317 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09, 1318 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a, 1319 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b, 1320 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c, 1321 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d, 1322 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e, 1323 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f, 1324 /* 0x06-0x7F - reserved */ 1325 /* 0x80-0xBF - I/O command set specific */ 1326 NVME_LOG_RES_NOTIFICATION = 0x80, 1327 NVME_LOG_SANITIZE_STATUS = 0x81, 1328 /* 0x82-0xBF - reserved */ 1329 /* 0xC0-0xFF - vendor specific */ 1330 1331 /* 1332 * The following are Intel Specific log pages, but they seem 1333 * to be widely implemented. 1334 */ 1335 INTEL_LOG_READ_LAT_LOG = 0xc1, 1336 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 1337 INTEL_LOG_TEMP_STATS = 0xc5, 1338 INTEL_LOG_ADD_SMART = 0xca, 1339 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 1340 1341 /* 1342 * HGST log page, with lots ofs sub pages. 1343 */ 1344 HGST_INFO_LOG = 0xc1, 1345 }; 1346 1347 struct nvme_error_information_entry { 1348 uint64_t error_count; 1349 uint16_t sqid; 1350 uint16_t cid; 1351 uint16_t status; 1352 uint16_t error_location; 1353 uint64_t lba; 1354 uint32_t nsid; 1355 uint8_t vendor_specific; 1356 uint8_t trtype; 1357 uint16_t reserved30; 1358 uint64_t csi; 1359 uint16_t ttsi; 1360 uint8_t reserved[22]; 1361 } __packed __aligned(4); 1362 1363 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 1364 1365 struct nvme_health_information_page { 1366 uint8_t critical_warning; 1367 uint16_t temperature; 1368 uint8_t available_spare; 1369 uint8_t available_spare_threshold; 1370 uint8_t percentage_used; 1371 1372 uint8_t reserved[26]; 1373 1374 /* 1375 * Note that the following are 128-bit values, but are 1376 * defined as an array of 2 64-bit values. 1377 */ 1378 /* Data Units Read is always in 512-byte units. */ 1379 uint64_t data_units_read[2]; 1380 /* Data Units Written is always in 512-byte units. */ 1381 uint64_t data_units_written[2]; 1382 /* For NVM command set, this includes Compare commands. */ 1383 uint64_t host_read_commands[2]; 1384 uint64_t host_write_commands[2]; 1385 /* Controller Busy Time is reported in minutes. */ 1386 uint64_t controller_busy_time[2]; 1387 uint64_t power_cycles[2]; 1388 uint64_t power_on_hours[2]; 1389 uint64_t unsafe_shutdowns[2]; 1390 uint64_t media_errors[2]; 1391 uint64_t num_error_info_log_entries[2]; 1392 uint32_t warning_temp_time; 1393 uint32_t error_temp_time; 1394 uint16_t temp_sensor[8]; 1395 /* Thermal Management Temperature 1 Transition Count */ 1396 uint32_t tmt1tc; 1397 /* Thermal Management Temperature 2 Transition Count */ 1398 uint32_t tmt2tc; 1399 /* Total Time For Thermal Management Temperature 1 */ 1400 uint32_t ttftmt1; 1401 /* Total Time For Thermal Management Temperature 2 */ 1402 uint32_t ttftmt2; 1403 1404 uint8_t reserved2[280]; 1405 } __packed __aligned(4); 1406 1407 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 1408 1409 struct nvme_firmware_page { 1410 uint8_t afi; 1411 uint8_t reserved[7]; 1412 uint64_t revision[7]; /* revisions for 7 slots */ 1413 uint8_t reserved2[448]; 1414 } __packed __aligned(4); 1415 1416 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 1417 1418 struct nvme_ns_list { 1419 uint32_t ns[1024]; 1420 } __packed __aligned(4); 1421 1422 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list"); 1423 1424 struct nvme_command_effects_page { 1425 uint32_t acs[256]; 1426 uint32_t iocs[256]; 1427 uint8_t reserved[2048]; 1428 } __packed __aligned(4); 1429 1430 _Static_assert(sizeof(struct nvme_command_effects_page) == 4096, 1431 "bad size for nvme_command_effects_page"); 1432 1433 struct nvme_device_self_test_page { 1434 uint8_t curr_operation; 1435 uint8_t curr_compl; 1436 uint8_t rsvd2[2]; 1437 struct { 1438 uint8_t status; 1439 uint8_t segment_num; 1440 uint8_t valid_diag_info; 1441 uint8_t rsvd3; 1442 uint64_t poh; 1443 uint32_t nsid; 1444 /* Define as an array to simplify alignment issues */ 1445 uint8_t failing_lba[8]; 1446 uint8_t status_code_type; 1447 uint8_t status_code; 1448 uint8_t vendor_specific[2]; 1449 } __packed result[20]; 1450 } __packed __aligned(4); 1451 1452 _Static_assert(sizeof(struct nvme_device_self_test_page) == 564, 1453 "bad size for nvme_device_self_test_page"); 1454 1455 struct nvme_res_notification_page { 1456 uint64_t log_page_count; 1457 uint8_t log_page_type; 1458 uint8_t available_log_pages; 1459 uint8_t reserved2; 1460 uint32_t nsid; 1461 uint8_t reserved[48]; 1462 } __packed __aligned(4); 1463 1464 _Static_assert(sizeof(struct nvme_res_notification_page) == 64, 1465 "bad size for nvme_res_notification_page"); 1466 1467 struct nvme_sanitize_status_page { 1468 uint16_t sprog; 1469 uint16_t sstat; 1470 uint32_t scdw10; 1471 uint32_t etfo; 1472 uint32_t etfbe; 1473 uint32_t etfce; 1474 uint32_t etfownd; 1475 uint32_t etfbewnd; 1476 uint32_t etfcewnd; 1477 uint8_t reserved[480]; 1478 } __packed __aligned(4); 1479 1480 _Static_assert(sizeof(struct nvme_sanitize_status_page) == 512, 1481 "bad size for nvme_sanitize_status_page"); 1482 1483 struct intel_log_temp_stats { 1484 uint64_t current; 1485 uint64_t overtemp_flag_last; 1486 uint64_t overtemp_flag_life; 1487 uint64_t max_temp; 1488 uint64_t min_temp; 1489 uint64_t _rsvd[5]; 1490 uint64_t max_oper_temp; 1491 uint64_t min_oper_temp; 1492 uint64_t est_offset; 1493 } __packed __aligned(4); 1494 1495 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 1496 1497 struct nvme_resv_reg_ctrlr { 1498 uint16_t ctrlr_id; /* Controller ID */ 1499 uint8_t rcsts; /* Reservation Status */ 1500 uint8_t reserved3[5]; 1501 uint64_t hostid; /* Host Identifier */ 1502 uint64_t rkey; /* Reservation Key */ 1503 } __packed __aligned(4); 1504 1505 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr"); 1506 1507 struct nvme_resv_reg_ctrlr_ext { 1508 uint16_t ctrlr_id; /* Controller ID */ 1509 uint8_t rcsts; /* Reservation Status */ 1510 uint8_t reserved3[5]; 1511 uint64_t rkey; /* Reservation Key */ 1512 uint64_t hostid[2]; /* Host Identifier */ 1513 uint8_t reserved32[32]; 1514 } __packed __aligned(4); 1515 1516 _Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext"); 1517 1518 struct nvme_resv_status { 1519 uint32_t gen; /* Generation */ 1520 uint8_t rtype; /* Reservation Type */ 1521 uint8_t regctl[2]; /* Number of Registered Controllers */ 1522 uint8_t reserved7[2]; 1523 uint8_t ptpls; /* Persist Through Power Loss State */ 1524 uint8_t reserved10[14]; 1525 struct nvme_resv_reg_ctrlr ctrlr[0]; 1526 } __packed __aligned(4); 1527 1528 _Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status"); 1529 1530 struct nvme_resv_status_ext { 1531 uint32_t gen; /* Generation */ 1532 uint8_t rtype; /* Reservation Type */ 1533 uint8_t regctl[2]; /* Number of Registered Controllers */ 1534 uint8_t reserved7[2]; 1535 uint8_t ptpls; /* Persist Through Power Loss State */ 1536 uint8_t reserved10[14]; 1537 uint8_t reserved24[40]; 1538 struct nvme_resv_reg_ctrlr_ext ctrlr[0]; 1539 } __packed __aligned(4); 1540 1541 _Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext"); 1542 1543 #define NVME_TEST_MAX_THREADS 128 1544 1545 struct nvme_io_test { 1546 enum nvme_nvm_opcode opc; 1547 uint32_t size; 1548 uint32_t time; /* in seconds */ 1549 uint32_t num_threads; 1550 uint32_t flags; 1551 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 1552 }; 1553 1554 enum nvme_io_test_flags { 1555 /* 1556 * Specifies whether dev_refthread/dev_relthread should be 1557 * called during NVME_BIO_TEST. Ignored for other test 1558 * types. 1559 */ 1560 NVME_TEST_FLAG_REFTHREAD = 0x1, 1561 }; 1562 1563 struct nvme_pt_command { 1564 /* 1565 * cmd is used to specify a passthrough command to a controller or 1566 * namespace. 1567 * 1568 * The following fields from cmd may be specified by the caller: 1569 * * opc (opcode) 1570 * * nsid (namespace id) - for admin commands only 1571 * * cdw10-cdw15 1572 * 1573 * Remaining fields must be set to 0 by the caller. 1574 */ 1575 struct nvme_command cmd; 1576 1577 /* 1578 * cpl returns completion status for the passthrough command 1579 * specified by cmd. 1580 * 1581 * The following fields will be filled out by the driver, for 1582 * consumption by the caller: 1583 * * cdw0 1584 * * status (except for phase) 1585 * 1586 * Remaining fields will be set to 0 by the driver. 1587 */ 1588 struct nvme_completion cpl; 1589 1590 /* buf is the data buffer associated with this passthrough command. */ 1591 void * buf; 1592 1593 /* 1594 * len is the length of the data buffer associated with this 1595 * passthrough command. 1596 */ 1597 uint32_t len; 1598 1599 /* 1600 * is_read = 1 if the passthrough command will read data into the 1601 * supplied buffer from the controller. 1602 * 1603 * is_read = 0 if the passthrough command will write data from the 1604 * supplied buffer to the controller. 1605 */ 1606 uint32_t is_read; 1607 1608 /* 1609 * driver_lock is used by the driver only. It must be set to 0 1610 * by the caller. 1611 */ 1612 struct mtx * driver_lock; 1613 }; 1614 1615 struct nvme_get_nsid { 1616 char cdev[SPECNAMELEN + 1]; 1617 uint32_t nsid; 1618 }; 1619 1620 struct nvme_hmb_desc { 1621 uint64_t addr; 1622 uint32_t size; 1623 uint32_t reserved; 1624 }; 1625 1626 #define nvme_completion_is_error(cpl) \ 1627 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0) 1628 1629 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1630 1631 #ifdef _KERNEL 1632 1633 struct bio; 1634 struct thread; 1635 1636 struct nvme_namespace; 1637 struct nvme_controller; 1638 struct nvme_consumer; 1639 1640 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1641 1642 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1643 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1644 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1645 uint32_t, void *, uint32_t); 1646 typedef void (*nvme_cons_fail_fn_t)(void *); 1647 1648 enum nvme_namespace_flags { 1649 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1650 NVME_NS_FLUSH_SUPPORTED = 0x2, 1651 }; 1652 1653 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1654 struct nvme_pt_command *pt, 1655 uint32_t nsid, int is_user_buffer, 1656 int is_admin_cmd); 1657 1658 /* Admin functions */ 1659 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1660 uint8_t feature, uint32_t cdw11, 1661 uint32_t cdw12, uint32_t cdw13, 1662 uint32_t cdw14, uint32_t cdw15, 1663 void *payload, uint32_t payload_size, 1664 nvme_cb_fn_t cb_fn, void *cb_arg); 1665 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1666 uint8_t feature, uint32_t cdw11, 1667 void *payload, uint32_t payload_size, 1668 nvme_cb_fn_t cb_fn, void *cb_arg); 1669 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1670 uint8_t log_page, uint32_t nsid, 1671 void *payload, uint32_t payload_size, 1672 nvme_cb_fn_t cb_fn, void *cb_arg); 1673 1674 /* NVM I/O functions */ 1675 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1676 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1677 void *cb_arg); 1678 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1679 nvme_cb_fn_t cb_fn, void *cb_arg); 1680 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1681 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1682 void *cb_arg); 1683 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1684 nvme_cb_fn_t cb_fn, void *cb_arg); 1685 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1686 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1687 void *cb_arg); 1688 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1689 void *cb_arg); 1690 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1691 size_t len); 1692 1693 /* Registration functions */ 1694 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1695 nvme_cons_ctrlr_fn_t ctrlr_fn, 1696 nvme_cons_async_fn_t async_fn, 1697 nvme_cons_fail_fn_t fail_fn); 1698 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1699 1700 /* Controller helper functions */ 1701 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1702 const struct nvme_controller_data * 1703 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1704 static inline bool 1705 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd) 1706 { 1707 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */ 1708 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) & 1709 NVME_CTRLR_DATA_ONCS_DSM_MASK); 1710 } 1711 1712 /* Namespace helper functions */ 1713 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1714 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1715 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1716 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1717 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1718 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1719 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1720 const struct nvme_namespace_data * 1721 nvme_ns_get_data(struct nvme_namespace *ns); 1722 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1723 1724 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1725 nvme_cb_fn_t cb_fn); 1726 int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd, 1727 caddr_t arg, int flag, struct thread *td); 1728 1729 /* 1730 * Command building helper functions -- shared with CAM 1731 * These functions assume allocator zeros out cmd structure 1732 * CAM's xpt_get_ccb and the request allocator for nvme both 1733 * do zero'd allocations. 1734 */ 1735 static inline 1736 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1737 { 1738 1739 cmd->opc = NVME_OPC_FLUSH; 1740 cmd->nsid = htole32(nsid); 1741 } 1742 1743 static inline 1744 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1745 uint64_t lba, uint32_t count) 1746 { 1747 cmd->opc = rwcmd; 1748 cmd->nsid = htole32(nsid); 1749 cmd->cdw10 = htole32(lba & 0xffffffffu); 1750 cmd->cdw11 = htole32(lba >> 32); 1751 cmd->cdw12 = htole32(count-1); 1752 } 1753 1754 static inline 1755 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1756 uint64_t lba, uint32_t count) 1757 { 1758 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1759 } 1760 1761 static inline 1762 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1763 uint64_t lba, uint32_t count) 1764 { 1765 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1766 } 1767 1768 static inline 1769 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1770 uint32_t num_ranges) 1771 { 1772 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1773 cmd->nsid = htole32(nsid); 1774 cmd->cdw10 = htole32(num_ranges - 1); 1775 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE); 1776 } 1777 1778 extern int nvme_use_nvd; 1779 1780 #endif /* _KERNEL */ 1781 1782 /* Endianess conversion functions for NVMe structs */ 1783 static inline 1784 void nvme_completion_swapbytes(struct nvme_completion *s __unused) 1785 { 1786 #if _BYTE_ORDER != _LITTLE_ENDIAN 1787 1788 s->cdw0 = le32toh(s->cdw0); 1789 /* omit rsvd1 */ 1790 s->sqhd = le16toh(s->sqhd); 1791 s->sqid = le16toh(s->sqid); 1792 /* omit cid */ 1793 s->status = le16toh(s->status); 1794 #endif 1795 } 1796 1797 static inline 1798 void nvme_power_state_swapbytes(struct nvme_power_state *s __unused) 1799 { 1800 #if _BYTE_ORDER != _LITTLE_ENDIAN 1801 1802 s->mp = le16toh(s->mp); 1803 s->enlat = le32toh(s->enlat); 1804 s->exlat = le32toh(s->exlat); 1805 s->idlp = le16toh(s->idlp); 1806 s->actp = le16toh(s->actp); 1807 #endif 1808 } 1809 1810 static inline 1811 void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused) 1812 { 1813 #if _BYTE_ORDER != _LITTLE_ENDIAN 1814 int i; 1815 1816 s->vid = le16toh(s->vid); 1817 s->ssvid = le16toh(s->ssvid); 1818 s->ctrlr_id = le16toh(s->ctrlr_id); 1819 s->ver = le32toh(s->ver); 1820 s->rtd3r = le32toh(s->rtd3r); 1821 s->rtd3e = le32toh(s->rtd3e); 1822 s->oaes = le32toh(s->oaes); 1823 s->ctratt = le32toh(s->ctratt); 1824 s->rrls = le16toh(s->rrls); 1825 s->crdt1 = le16toh(s->crdt1); 1826 s->crdt2 = le16toh(s->crdt2); 1827 s->crdt3 = le16toh(s->crdt3); 1828 s->oacs = le16toh(s->oacs); 1829 s->wctemp = le16toh(s->wctemp); 1830 s->cctemp = le16toh(s->cctemp); 1831 s->mtfa = le16toh(s->mtfa); 1832 s->hmpre = le32toh(s->hmpre); 1833 s->hmmin = le32toh(s->hmmin); 1834 s->rpmbs = le32toh(s->rpmbs); 1835 s->edstt = le16toh(s->edstt); 1836 s->kas = le16toh(s->kas); 1837 s->hctma = le16toh(s->hctma); 1838 s->mntmt = le16toh(s->mntmt); 1839 s->mxtmt = le16toh(s->mxtmt); 1840 s->sanicap = le32toh(s->sanicap); 1841 s->hmminds = le32toh(s->hmminds); 1842 s->hmmaxd = le16toh(s->hmmaxd); 1843 s->nsetidmax = le16toh(s->nsetidmax); 1844 s->endgidmax = le16toh(s->endgidmax); 1845 s->anagrpmax = le32toh(s->anagrpmax); 1846 s->nanagrpid = le32toh(s->nanagrpid); 1847 s->pels = le32toh(s->pels); 1848 s->maxcmd = le16toh(s->maxcmd); 1849 s->nn = le32toh(s->nn); 1850 s->oncs = le16toh(s->oncs); 1851 s->fuses = le16toh(s->fuses); 1852 s->awun = le16toh(s->awun); 1853 s->awupf = le16toh(s->awupf); 1854 s->acwu = le16toh(s->acwu); 1855 s->sgls = le32toh(s->sgls); 1856 s->mnan = le32toh(s->mnan); 1857 for (i = 0; i < 32; i++) 1858 nvme_power_state_swapbytes(&s->power_state[i]); 1859 #endif 1860 } 1861 1862 static inline 1863 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused) 1864 { 1865 #if _BYTE_ORDER != _LITTLE_ENDIAN 1866 int i; 1867 1868 s->nsze = le64toh(s->nsze); 1869 s->ncap = le64toh(s->ncap); 1870 s->nuse = le64toh(s->nuse); 1871 s->nawun = le16toh(s->nawun); 1872 s->nawupf = le16toh(s->nawupf); 1873 s->nacwu = le16toh(s->nacwu); 1874 s->nabsn = le16toh(s->nabsn); 1875 s->nabo = le16toh(s->nabo); 1876 s->nabspf = le16toh(s->nabspf); 1877 s->noiob = le16toh(s->noiob); 1878 s->npwg = le16toh(s->npwg); 1879 s->npwa = le16toh(s->npwa); 1880 s->npdg = le16toh(s->npdg); 1881 s->npda = le16toh(s->npda); 1882 s->nows = le16toh(s->nows); 1883 s->anagrpid = le32toh(s->anagrpid); 1884 s->nvmsetid = le16toh(s->nvmsetid); 1885 s->endgid = le16toh(s->endgid); 1886 for (i = 0; i < 16; i++) 1887 s->lbaf[i] = le32toh(s->lbaf[i]); 1888 #endif 1889 } 1890 1891 static inline 1892 void nvme_error_information_entry_swapbytes( 1893 struct nvme_error_information_entry *s __unused) 1894 { 1895 #if _BYTE_ORDER != _LITTLE_ENDIAN 1896 1897 s->error_count = le64toh(s->error_count); 1898 s->sqid = le16toh(s->sqid); 1899 s->cid = le16toh(s->cid); 1900 s->status = le16toh(s->status); 1901 s->error_location = le16toh(s->error_location); 1902 s->lba = le64toh(s->lba); 1903 s->nsid = le32toh(s->nsid); 1904 s->csi = le64toh(s->csi); 1905 s->ttsi = le16toh(s->ttsi); 1906 #endif 1907 } 1908 1909 static inline 1910 void nvme_le128toh(void *p __unused) 1911 { 1912 #if _BYTE_ORDER != _LITTLE_ENDIAN 1913 /* Swap 16 bytes in place */ 1914 char *tmp = (char*)p; 1915 char b; 1916 int i; 1917 for (i = 0; i < 8; i++) { 1918 b = tmp[i]; 1919 tmp[i] = tmp[15-i]; 1920 tmp[15-i] = b; 1921 } 1922 #endif 1923 } 1924 1925 static inline 1926 void nvme_health_information_page_swapbytes( 1927 struct nvme_health_information_page *s __unused) 1928 { 1929 #if _BYTE_ORDER != _LITTLE_ENDIAN 1930 int i; 1931 1932 s->temperature = le16toh(s->temperature); 1933 nvme_le128toh((void *)s->data_units_read); 1934 nvme_le128toh((void *)s->data_units_written); 1935 nvme_le128toh((void *)s->host_read_commands); 1936 nvme_le128toh((void *)s->host_write_commands); 1937 nvme_le128toh((void *)s->controller_busy_time); 1938 nvme_le128toh((void *)s->power_cycles); 1939 nvme_le128toh((void *)s->power_on_hours); 1940 nvme_le128toh((void *)s->unsafe_shutdowns); 1941 nvme_le128toh((void *)s->media_errors); 1942 nvme_le128toh((void *)s->num_error_info_log_entries); 1943 s->warning_temp_time = le32toh(s->warning_temp_time); 1944 s->error_temp_time = le32toh(s->error_temp_time); 1945 for (i = 0; i < 8; i++) 1946 s->temp_sensor[i] = le16toh(s->temp_sensor[i]); 1947 s->tmt1tc = le32toh(s->tmt1tc); 1948 s->tmt2tc = le32toh(s->tmt2tc); 1949 s->ttftmt1 = le32toh(s->ttftmt1); 1950 s->ttftmt2 = le32toh(s->ttftmt2); 1951 #endif 1952 } 1953 1954 static inline 1955 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s __unused) 1956 { 1957 #if _BYTE_ORDER != _LITTLE_ENDIAN 1958 int i; 1959 1960 for (i = 0; i < 7; i++) 1961 s->revision[i] = le64toh(s->revision[i]); 1962 #endif 1963 } 1964 1965 static inline 1966 void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused) 1967 { 1968 #if _BYTE_ORDER != _LITTLE_ENDIAN 1969 int i; 1970 1971 for (i = 0; i < 1024; i++) 1972 s->ns[i] = le32toh(s->ns[i]); 1973 #endif 1974 } 1975 1976 static inline 1977 void nvme_command_effects_page_swapbytes( 1978 struct nvme_command_effects_page *s __unused) 1979 { 1980 #if _BYTE_ORDER != _LITTLE_ENDIAN 1981 int i; 1982 1983 for (i = 0; i < 256; i++) 1984 s->acs[i] = le32toh(s->acs[i]); 1985 for (i = 0; i < 256; i++) 1986 s->iocs[i] = le32toh(s->iocs[i]); 1987 #endif 1988 } 1989 1990 static inline 1991 void nvme_res_notification_page_swapbytes( 1992 struct nvme_res_notification_page *s __unused) 1993 { 1994 #if _BYTE_ORDER != _LITTLE_ENDIAN 1995 s->log_page_count = le64toh(s->log_page_count); 1996 s->nsid = le32toh(s->nsid); 1997 #endif 1998 } 1999 2000 static inline 2001 void nvme_sanitize_status_page_swapbytes( 2002 struct nvme_sanitize_status_page *s __unused) 2003 { 2004 #if _BYTE_ORDER != _LITTLE_ENDIAN 2005 s->sprog = le16toh(s->sprog); 2006 s->sstat = le16toh(s->sstat); 2007 s->scdw10 = le32toh(s->scdw10); 2008 s->etfo = le32toh(s->etfo); 2009 s->etfbe = le32toh(s->etfbe); 2010 s->etfce = le32toh(s->etfce); 2011 s->etfownd = le32toh(s->etfownd); 2012 s->etfbewnd = le32toh(s->etfbewnd); 2013 s->etfcewnd = le32toh(s->etfcewnd); 2014 #endif 2015 } 2016 2017 static inline 2018 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s __unused) 2019 { 2020 #if _BYTE_ORDER != _LITTLE_ENDIAN 2021 2022 s->current = le64toh(s->current); 2023 s->overtemp_flag_last = le64toh(s->overtemp_flag_last); 2024 s->overtemp_flag_life = le64toh(s->overtemp_flag_life); 2025 s->max_temp = le64toh(s->max_temp); 2026 s->min_temp = le64toh(s->min_temp); 2027 /* omit _rsvd[] */ 2028 s->max_oper_temp = le64toh(s->max_oper_temp); 2029 s->min_oper_temp = le64toh(s->min_oper_temp); 2030 s->est_offset = le64toh(s->est_offset); 2031 #endif 2032 } 2033 2034 static inline 2035 void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused, 2036 size_t size __unused) 2037 { 2038 #if _BYTE_ORDER != _LITTLE_ENDIAN 2039 u_int i, n; 2040 2041 s->gen = le32toh(s->gen); 2042 n = (s->regctl[1] << 8) | s->regctl[0]; 2043 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0])); 2044 for (i = 0; i < n; i++) { 2045 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id); 2046 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid); 2047 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey); 2048 } 2049 #endif 2050 } 2051 2052 static inline 2053 void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused, 2054 size_t size __unused) 2055 { 2056 #if _BYTE_ORDER != _LITTLE_ENDIAN 2057 u_int i, n; 2058 2059 s->gen = le32toh(s->gen); 2060 n = (s->regctl[1] << 8) | s->regctl[0]; 2061 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0])); 2062 for (i = 0; i < n; i++) { 2063 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id); 2064 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey); 2065 nvme_le128toh((void *)s->ctrlr[i].hostid); 2066 } 2067 #endif 2068 } 2069 2070 static inline void 2071 nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused) 2072 { 2073 #if _BYTE_ORDER != _LITTLE_ENDIAN 2074 uint8_t *tmp; 2075 uint32_t r, i; 2076 uint8_t b; 2077 2078 for (r = 0; r < 20; r++) { 2079 s->result[r].poh = le64toh(s->result[r].poh); 2080 s->result[r].nsid = le32toh(s->result[r].nsid); 2081 /* Unaligned 64-bit loads fail on some architectures */ 2082 tmp = s->result[r].failing_lba; 2083 for (i = 0; i < 4; i++) { 2084 b = tmp[i]; 2085 tmp[i] = tmp[7-i]; 2086 tmp[7-i] = b; 2087 } 2088 } 2089 #endif 2090 } 2091 #endif /* __NVME_H__ */ 2092