1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_H__ 32 #define __NVME_H__ 33 34 #ifdef _KERNEL 35 #include <sys/types.h> 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/endian.h> 40 41 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 42 #define NVME_RESET_CONTROLLER _IO('n', 1) 43 44 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 45 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 46 47 /* 48 * Macros to deal with NVME revisions, as defined VS register 49 */ 50 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 51 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 52 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 53 54 /* 55 * Use to mark a command to apply to all namespaces, or to retrieve global 56 * log pages. 57 */ 58 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 59 60 /* Cap nvme to 1MB transfers driver explodes with larger sizes */ 61 #define NVME_MAX_XFER_SIZE (MAXPHYS < (1<<20) ? MAXPHYS : (1<<20)) 62 63 /* Register field definitions */ 64 #define NVME_CAP_LO_REG_MQES_SHIFT (0) 65 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 66 #define NVME_CAP_LO_REG_CQR_SHIFT (16) 67 #define NVME_CAP_LO_REG_CQR_MASK (0x1) 68 #define NVME_CAP_LO_REG_AMS_SHIFT (17) 69 #define NVME_CAP_LO_REG_AMS_MASK (0x3) 70 #define NVME_CAP_LO_REG_TO_SHIFT (24) 71 #define NVME_CAP_LO_REG_TO_MASK (0xFF) 72 73 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0) 74 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF) 75 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5) 76 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1) 77 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16) 78 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF) 79 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20) 80 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF) 81 82 #define NVME_CC_REG_EN_SHIFT (0) 83 #define NVME_CC_REG_EN_MASK (0x1) 84 #define NVME_CC_REG_CSS_SHIFT (4) 85 #define NVME_CC_REG_CSS_MASK (0x7) 86 #define NVME_CC_REG_MPS_SHIFT (7) 87 #define NVME_CC_REG_MPS_MASK (0xF) 88 #define NVME_CC_REG_AMS_SHIFT (11) 89 #define NVME_CC_REG_AMS_MASK (0x7) 90 #define NVME_CC_REG_SHN_SHIFT (14) 91 #define NVME_CC_REG_SHN_MASK (0x3) 92 #define NVME_CC_REG_IOSQES_SHIFT (16) 93 #define NVME_CC_REG_IOSQES_MASK (0xF) 94 #define NVME_CC_REG_IOCQES_SHIFT (20) 95 #define NVME_CC_REG_IOCQES_MASK (0xF) 96 97 #define NVME_CSTS_REG_RDY_SHIFT (0) 98 #define NVME_CSTS_REG_RDY_MASK (0x1) 99 #define NVME_CSTS_REG_CFS_SHIFT (1) 100 #define NVME_CSTS_REG_CFS_MASK (0x1) 101 #define NVME_CSTS_REG_SHST_SHIFT (2) 102 #define NVME_CSTS_REG_SHST_MASK (0x3) 103 104 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK) 105 106 #define NVME_AQA_REG_ASQS_SHIFT (0) 107 #define NVME_AQA_REG_ASQS_MASK (0xFFF) 108 #define NVME_AQA_REG_ACQS_SHIFT (16) 109 #define NVME_AQA_REG_ACQS_MASK (0xFFF) 110 111 /* Command field definitions */ 112 113 #define NVME_CMD_FUSE_SHIFT (8) 114 #define NVME_CMD_FUSE_MASK (0x3) 115 116 #define NVME_STATUS_P_SHIFT (0) 117 #define NVME_STATUS_P_MASK (0x1) 118 #define NVME_STATUS_SC_SHIFT (1) 119 #define NVME_STATUS_SC_MASK (0xFF) 120 #define NVME_STATUS_SCT_SHIFT (9) 121 #define NVME_STATUS_SCT_MASK (0x7) 122 #define NVME_STATUS_M_SHIFT (14) 123 #define NVME_STATUS_M_MASK (0x1) 124 #define NVME_STATUS_DNR_SHIFT (15) 125 #define NVME_STATUS_DNR_MASK (0x1) 126 127 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 128 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 129 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) 130 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 131 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 132 133 #define NVME_PWR_ST_MPS_SHIFT (0) 134 #define NVME_PWR_ST_MPS_MASK (0x1) 135 #define NVME_PWR_ST_NOPS_SHIFT (1) 136 #define NVME_PWR_ST_NOPS_MASK (0x1) 137 #define NVME_PWR_ST_RRT_SHIFT (0) 138 #define NVME_PWR_ST_RRT_MASK (0x1F) 139 #define NVME_PWR_ST_RRL_SHIFT (0) 140 #define NVME_PWR_ST_RRL_MASK (0x1F) 141 #define NVME_PWR_ST_RWT_SHIFT (0) 142 #define NVME_PWR_ST_RWT_MASK (0x1F) 143 #define NVME_PWR_ST_RWL_SHIFT (0) 144 #define NVME_PWR_ST_RWL_MASK (0x1F) 145 #define NVME_PWR_ST_IPS_SHIFT (6) 146 #define NVME_PWR_ST_IPS_MASK (0x3) 147 #define NVME_PWR_ST_APW_SHIFT (0) 148 #define NVME_PWR_ST_APW_MASK (0x7) 149 #define NVME_PWR_ST_APS_SHIFT (6) 150 #define NVME_PWR_ST_APS_MASK (0x3) 151 152 /** Controller Multi-path I/O and Namespace Sharing Capabilities */ 153 /* More then one port */ 154 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0) 155 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1) 156 /* More then one controller */ 157 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1) 158 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1) 159 /* SR-IOV Virtual Function */ 160 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2) 161 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1) 162 163 /** OACS - optional admin command support */ 164 /* supports security send/receive commands */ 165 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0) 166 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1) 167 /* supports format nvm command */ 168 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1) 169 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1) 170 /* supports firmware activate/download commands */ 171 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2) 172 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1) 173 /* supports namespace management commands */ 174 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3) 175 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1) 176 /* supports Device Self-test command */ 177 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4) 178 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1) 179 /* supports Directives */ 180 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5) 181 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1) 182 /* supports NVMe-MI Send/Receive */ 183 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6) 184 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1) 185 /* supports Virtualization Management */ 186 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7) 187 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1) 188 /* supports Doorbell Buffer Config */ 189 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8) 190 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1) 191 192 /** firmware updates */ 193 /* first slot is read-only */ 194 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0) 195 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1) 196 /* number of firmware slots */ 197 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1) 198 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7) 199 200 /** log page attributes */ 201 /* per namespace smart/health log page */ 202 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0) 203 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1) 204 205 /** AVSCC - admin vendor specific command configuration */ 206 /* admin vendor specific commands use spec format */ 207 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0) 208 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1) 209 210 /** Autonomous Power State Transition Attributes */ 211 /* Autonomous Power State Transitions supported */ 212 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0) 213 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1) 214 215 /** submission queue entry size */ 216 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0) 217 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF) 218 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4) 219 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF) 220 221 /** completion queue entry size */ 222 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0) 223 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF) 224 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4) 225 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF) 226 227 /** optional nvm command support */ 228 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0) 229 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1) 230 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1) 231 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1) 232 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2) 233 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1) 234 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3) 235 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1) 236 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4) 237 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1) 238 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5) 239 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1) 240 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6) 241 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1) 242 243 /** Fused Operation Support */ 244 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0) 245 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1) 246 247 /** Format NVM Attributes */ 248 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0) 249 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1) 250 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1) 251 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1) 252 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2) 253 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1) 254 255 /** volatile write cache */ 256 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0) 257 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1) 258 259 /** namespace features */ 260 /* thin provisioning */ 261 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0) 262 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1) 263 /* NAWUN, NAWUPF, and NACWU fields are valid */ 264 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1) 265 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1) 266 /* Deallocated or Unwritten Logical Block errors supported */ 267 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2) 268 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1) 269 /* NGUID and EUI64 fields are not reusable */ 270 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3) 271 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1) 272 273 /** formatted lba size */ 274 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0) 275 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF) 276 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4) 277 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1) 278 279 /** metadata capabilities */ 280 /* metadata can be transferred as part of data prp list */ 281 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0) 282 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1) 283 /* metadata can be transferred with separate metadata pointer */ 284 #define NVME_NS_DATA_MC_POINTER_SHIFT (1) 285 #define NVME_NS_DATA_MC_POINTER_MASK (0x1) 286 287 /** end-to-end data protection capabilities */ 288 /* protection information type 1 */ 289 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0) 290 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1) 291 /* protection information type 2 */ 292 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1) 293 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1) 294 /* protection information type 3 */ 295 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2) 296 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1) 297 /* first eight bytes of metadata */ 298 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3) 299 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1) 300 /* last eight bytes of metadata */ 301 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4) 302 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1) 303 304 /** end-to-end data protection type settings */ 305 /* protection information type */ 306 #define NVME_NS_DATA_DPS_PIT_SHIFT (0) 307 #define NVME_NS_DATA_DPS_PIT_MASK (0x7) 308 /* 1 == protection info transferred at start of metadata */ 309 /* 0 == protection info transferred at end of metadata */ 310 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3) 311 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1) 312 313 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 314 /* the namespace may be attached to two or more controllers */ 315 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0) 316 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1) 317 318 /** Reservation Capabilities */ 319 /* Persist Through Power Loss */ 320 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0) 321 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1) 322 /* supports the Write Exclusive */ 323 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1) 324 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1) 325 /* supports the Exclusive Access */ 326 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2) 327 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1) 328 /* supports the Write Exclusive – Registrants Only */ 329 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3) 330 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1) 331 /* supports the Exclusive Access - Registrants Only */ 332 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4) 333 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1) 334 /* supports the Write Exclusive – All Registrants */ 335 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5) 336 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1) 337 /* supports the Exclusive Access - All Registrants */ 338 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6) 339 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1) 340 /* Ignore Existing Key is used as defined in revision 1.3 or later */ 341 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7) 342 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1) 343 344 /** Format Progress Indicator */ 345 /* percentage of the Format NVM command that remains to be completed */ 346 #define NVME_NS_DATA_FPI_PERC_SHIFT (0) 347 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f) 348 /* namespace supports the Format Progress Indicator */ 349 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7) 350 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1) 351 352 /** Deallocate Logical Block Features */ 353 /* deallocated logical block read behavior */ 354 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0) 355 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07) 356 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00) 357 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01) 358 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02) 359 /* supports the Deallocate bit in the Write Zeroes */ 360 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3) 361 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01) 362 /* Guard field for deallocated logical blocks is set to the CRC */ 363 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4) 364 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01) 365 366 /** lba format support */ 367 /* metadata size */ 368 #define NVME_NS_DATA_LBAF_MS_SHIFT (0) 369 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF) 370 /* lba data size */ 371 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16) 372 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF) 373 /* relative performance */ 374 #define NVME_NS_DATA_LBAF_RP_SHIFT (24) 375 #define NVME_NS_DATA_LBAF_RP_MASK (0x3) 376 377 enum nvme_critical_warning_state { 378 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1, 379 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2, 380 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4, 381 NVME_CRIT_WARN_ST_READ_ONLY = 0x8, 382 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10, 383 }; 384 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0) 385 386 /* slot for current FW */ 387 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0) 388 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7) 389 390 /* CC register SHN field values */ 391 enum shn_value { 392 NVME_SHN_NORMAL = 0x1, 393 NVME_SHN_ABRUPT = 0x2, 394 }; 395 396 /* CSTS register SHST field values */ 397 enum shst_value { 398 NVME_SHST_NORMAL = 0x0, 399 NVME_SHST_OCCURRING = 0x1, 400 NVME_SHST_COMPLETE = 0x2, 401 }; 402 403 struct nvme_registers 404 { 405 /** controller capabilities */ 406 uint32_t cap_lo; 407 uint32_t cap_hi; 408 409 uint32_t vs; /* version */ 410 uint32_t intms; /* interrupt mask set */ 411 uint32_t intmc; /* interrupt mask clear */ 412 413 /** controller configuration */ 414 uint32_t cc; 415 416 uint32_t reserved1; 417 418 /** controller status */ 419 uint32_t csts; 420 421 uint32_t reserved2; 422 423 /** admin queue attributes */ 424 uint32_t aqa; 425 426 uint64_t asq; /* admin submission queue base addr */ 427 uint64_t acq; /* admin completion queue base addr */ 428 uint32_t reserved3[0x3f2]; 429 430 struct { 431 uint32_t sq_tdbl; /* submission queue tail doorbell */ 432 uint32_t cq_hdbl; /* completion queue head doorbell */ 433 } doorbell[1] __packed; 434 } __packed; 435 436 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 437 438 struct nvme_command 439 { 440 /* dword 0 */ 441 uint8_t opc; /* opcode */ 442 uint8_t fuse; /* fused operation */ 443 uint16_t cid; /* command identifier */ 444 445 /* dword 1 */ 446 uint32_t nsid; /* namespace identifier */ 447 448 /* dword 2-3 */ 449 uint32_t rsvd2; 450 uint32_t rsvd3; 451 452 /* dword 4-5 */ 453 uint64_t mptr; /* metadata pointer */ 454 455 /* dword 6-7 */ 456 uint64_t prp1; /* prp entry 1 */ 457 458 /* dword 8-9 */ 459 uint64_t prp2; /* prp entry 2 */ 460 461 /* dword 10-15 */ 462 uint32_t cdw10; /* command-specific */ 463 uint32_t cdw11; /* command-specific */ 464 uint32_t cdw12; /* command-specific */ 465 uint32_t cdw13; /* command-specific */ 466 uint32_t cdw14; /* command-specific */ 467 uint32_t cdw15; /* command-specific */ 468 } __packed; 469 470 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 471 472 struct nvme_completion { 473 474 /* dword 0 */ 475 uint32_t cdw0; /* command-specific */ 476 477 /* dword 1 */ 478 uint32_t rsvd1; 479 480 /* dword 2 */ 481 uint16_t sqhd; /* submission queue head pointer */ 482 uint16_t sqid; /* submission queue identifier */ 483 484 /* dword 3 */ 485 uint16_t cid; /* command identifier */ 486 uint16_t status; 487 } __packed; 488 489 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 490 491 struct nvme_dsm_range { 492 uint32_t attributes; 493 uint32_t length; 494 uint64_t starting_lba; 495 } __packed; 496 497 /* Largest DSM Trim that can be done */ 498 #define NVME_MAX_DSM_TRIM 4096 499 500 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 501 502 /* status code types */ 503 enum nvme_status_code_type { 504 NVME_SCT_GENERIC = 0x0, 505 NVME_SCT_COMMAND_SPECIFIC = 0x1, 506 NVME_SCT_MEDIA_ERROR = 0x2, 507 /* 0x3-0x6 - reserved */ 508 NVME_SCT_VENDOR_SPECIFIC = 0x7, 509 }; 510 511 /* generic command status codes */ 512 enum nvme_generic_command_status_code { 513 NVME_SC_SUCCESS = 0x00, 514 NVME_SC_INVALID_OPCODE = 0x01, 515 NVME_SC_INVALID_FIELD = 0x02, 516 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 517 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 518 NVME_SC_ABORTED_POWER_LOSS = 0x05, 519 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 520 NVME_SC_ABORTED_BY_REQUEST = 0x07, 521 NVME_SC_ABORTED_SQ_DELETION = 0x08, 522 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 523 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 524 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 525 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 526 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 527 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 528 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 529 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 530 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 531 NVME_SC_INVALID_USE_OF_CMB = 0x12, 532 NVME_SC_PRP_OFFET_INVALID = 0x13, 533 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 534 NVME_SC_OPERATION_DENIED = 0x15, 535 NVME_SC_SGL_OFFSET_INVALID = 0x16, 536 /* 0x17 - reserved */ 537 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 538 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 539 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 540 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 541 NVME_SC_SANITIZE_FAILED = 0x1c, 542 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 543 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 544 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 545 546 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 547 NVME_SC_CAPACITY_EXCEEDED = 0x81, 548 NVME_SC_NAMESPACE_NOT_READY = 0x82, 549 NVME_SC_RESERVATION_CONFLICT = 0x83, 550 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 551 }; 552 553 /* command specific status codes */ 554 enum nvme_command_specific_status_code { 555 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 556 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 557 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 558 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 559 /* 0x04 - reserved */ 560 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 561 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 562 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 563 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 564 NVME_SC_INVALID_LOG_PAGE = 0x09, 565 NVME_SC_INVALID_FORMAT = 0x0a, 566 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 567 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 568 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 569 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 570 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 571 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 572 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 573 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 574 NVME_SC_FW_ACT_PROHIBITED = 0x13, 575 NVME_SC_OVERLAPPING_RANGE = 0x14, 576 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 577 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 578 /* 0x17 - reserved */ 579 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 580 NVME_SC_NS_IS_PRIVATE = 0x19, 581 NVME_SC_NS_NOT_ATTACHED = 0x1a, 582 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 583 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 584 NVME_SC_SELT_TEST_IN_PROGRESS = 0x1d, 585 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 586 NVME_SC_INVALID_CTRLR_ID = 0x1f, 587 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 588 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 589 NVME_SC_INVALID_RESOURCE_ID = 0x22, 590 591 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 592 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 593 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 594 }; 595 596 /* media error status codes */ 597 enum nvme_media_error_status_code { 598 NVME_SC_WRITE_FAULTS = 0x80, 599 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 600 NVME_SC_GUARD_CHECK_ERROR = 0x82, 601 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 602 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 603 NVME_SC_COMPARE_FAILURE = 0x85, 604 NVME_SC_ACCESS_DENIED = 0x86, 605 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 606 }; 607 608 /* admin opcodes */ 609 enum nvme_admin_opcode { 610 NVME_OPC_DELETE_IO_SQ = 0x00, 611 NVME_OPC_CREATE_IO_SQ = 0x01, 612 NVME_OPC_GET_LOG_PAGE = 0x02, 613 /* 0x03 - reserved */ 614 NVME_OPC_DELETE_IO_CQ = 0x04, 615 NVME_OPC_CREATE_IO_CQ = 0x05, 616 NVME_OPC_IDENTIFY = 0x06, 617 /* 0x07 - reserved */ 618 NVME_OPC_ABORT = 0x08, 619 NVME_OPC_SET_FEATURES = 0x09, 620 NVME_OPC_GET_FEATURES = 0x0a, 621 /* 0x0b - reserved */ 622 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 623 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 624 /* 0x0e-0x0f - reserved */ 625 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 626 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 627 NVME_OPC_DEVICE_SELF_TEST = 0x14, 628 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 629 NVME_OPC_KEEP_ALIVE = 0x18, 630 NVME_OPC_DIRECTIVE_SEND = 0x19, 631 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 632 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 633 NVME_OPC_NVME_MI_SEND = 0x1d, 634 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 635 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 636 637 NVME_OPC_FORMAT_NVM = 0x80, 638 NVME_OPC_SECURITY_SEND = 0x81, 639 NVME_OPC_SECURITY_RECEIVE = 0x82, 640 NVME_OPC_SANITIZE = 0x84, 641 }; 642 643 /* nvme nvm opcodes */ 644 enum nvme_nvm_opcode { 645 NVME_OPC_FLUSH = 0x00, 646 NVME_OPC_WRITE = 0x01, 647 NVME_OPC_READ = 0x02, 648 /* 0x03 - reserved */ 649 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 650 NVME_OPC_COMPARE = 0x05, 651 /* 0x06 - reserved */ 652 NVME_OPC_WRITE_ZEROES = 0x08, 653 /* 0x07 - reserved */ 654 NVME_OPC_DATASET_MANAGEMENT = 0x09, 655 /* 0x0a-0x0c - reserved */ 656 NVME_OPC_RESERVATION_REGISTER = 0x0d, 657 NVME_OPC_RESERVATION_REPORT = 0x0e, 658 /* 0x0f-0x10 - reserved */ 659 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 660 /* 0x12-0x14 - reserved */ 661 NVME_OPC_RESERVATION_RELEASE = 0x15, 662 }; 663 664 enum nvme_feature { 665 /* 0x00 - reserved */ 666 NVME_FEAT_ARBITRATION = 0x01, 667 NVME_FEAT_POWER_MANAGEMENT = 0x02, 668 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 669 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 670 NVME_FEAT_ERROR_RECOVERY = 0x05, 671 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 672 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 673 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 674 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 675 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 676 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 677 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 678 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 679 NVME_FEAT_TIMESTAMP = 0x0E, 680 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 681 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 682 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 683 /* 0x12-0x77 - reserved */ 684 /* 0x78-0x7f - NVMe Management Interface */ 685 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 686 /* 0x81-0xBF - command set specific (reserved) */ 687 /* 0xC0-0xFF - vendor specific */ 688 }; 689 690 enum nvme_dsm_attribute { 691 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 692 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 693 NVME_DSM_ATTR_DEALLOCATE = 0x4, 694 }; 695 696 enum nvme_activate_action { 697 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 698 NVME_AA_REPLACE_ACTIVATE = 0x1, 699 NVME_AA_ACTIVATE = 0x2, 700 }; 701 702 struct nvme_power_state { 703 /** Maximum Power */ 704 uint16_t mp; /* Maximum Power */ 705 uint8_t ps_rsvd1; 706 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */ 707 708 uint32_t enlat; /* Entry Latency */ 709 uint32_t exlat; /* Exit Latency */ 710 711 uint8_t rrt; /* Relative Read Throughput */ 712 uint8_t rrl; /* Relative Read Latency */ 713 uint8_t rwt; /* Relative Write Throughput */ 714 uint8_t rwl; /* Relative Write Latency */ 715 716 uint16_t idlp; /* Idle Power */ 717 uint8_t ips; /* Idle Power Scale */ 718 uint8_t ps_rsvd8; 719 720 uint16_t actp; /* Active Power */ 721 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ 722 uint8_t ps_rsvd10[9]; 723 } __packed; 724 725 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 726 727 #define NVME_SERIAL_NUMBER_LENGTH 20 728 #define NVME_MODEL_NUMBER_LENGTH 40 729 #define NVME_FIRMWARE_REVISION_LENGTH 8 730 731 struct nvme_controller_data { 732 733 /* bytes 0-255: controller capabilities and features */ 734 735 /** pci vendor id */ 736 uint16_t vid; 737 738 /** pci subsystem vendor id */ 739 uint16_t ssvid; 740 741 /** serial number */ 742 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 743 744 /** model number */ 745 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 746 747 /** firmware revision */ 748 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 749 750 /** recommended arbitration burst */ 751 uint8_t rab; 752 753 /** ieee oui identifier */ 754 uint8_t ieee[3]; 755 756 /** multi-interface capabilities */ 757 uint8_t mic; 758 759 /** maximum data transfer size */ 760 uint8_t mdts; 761 762 /** Controller ID */ 763 uint16_t ctrlr_id; 764 765 /** Version */ 766 uint32_t ver; 767 768 /** RTD3 Resume Latency */ 769 uint32_t rtd3r; 770 771 /** RTD3 Enter Latency */ 772 uint32_t rtd3e; 773 774 /** Optional Asynchronous Events Supported */ 775 uint32_t oaes; /* bitfield really */ 776 777 /** Controller Attributes */ 778 uint32_t ctratt; /* bitfield really */ 779 780 uint8_t reserved1[12]; 781 782 /** FRU Globally Unique Identifier */ 783 uint8_t fguid[16]; 784 785 uint8_t reserved2[128]; 786 787 /* bytes 256-511: admin command set attributes */ 788 789 /** optional admin command support */ 790 uint16_t oacs; 791 792 /** abort command limit */ 793 uint8_t acl; 794 795 /** asynchronous event request limit */ 796 uint8_t aerl; 797 798 /** firmware updates */ 799 uint8_t frmw; 800 801 /** log page attributes */ 802 uint8_t lpa; 803 804 /** error log page entries */ 805 uint8_t elpe; 806 807 /** number of power states supported */ 808 uint8_t npss; 809 810 /** admin vendor specific command configuration */ 811 uint8_t avscc; 812 813 /** Autonomous Power State Transition Attributes */ 814 uint8_t apsta; 815 816 /** Warning Composite Temperature Threshold */ 817 uint16_t wctemp; 818 819 /** Critical Composite Temperature Threshold */ 820 uint16_t cctemp; 821 822 /** Maximum Time for Firmware Activation */ 823 uint16_t mtfa; 824 825 /** Host Memory Buffer Preferred Size */ 826 uint32_t hmpre; 827 828 /** Host Memory Buffer Minimum Size */ 829 uint32_t hmmin; 830 831 /** Name space capabilities */ 832 struct { 833 /* if nsmgmt, report tnvmcap and unvmcap */ 834 uint8_t tnvmcap[16]; 835 uint8_t unvmcap[16]; 836 } __packed untncap; 837 838 /** Replay Protected Memory Block Support */ 839 uint32_t rpmbs; /* Really a bitfield */ 840 841 /** Extended Device Self-test Time */ 842 uint16_t edstt; 843 844 /** Device Self-test Options */ 845 uint8_t dsto; /* Really a bitfield */ 846 847 /** Firmware Update Granularity */ 848 uint8_t fwug; 849 850 /** Keep Alive Support */ 851 uint16_t kas; 852 853 /** Host Controlled Thermal Management Attributes */ 854 uint16_t hctma; /* Really a bitfield */ 855 856 /** Minimum Thermal Management Temperature */ 857 uint16_t mntmt; 858 859 /** Maximum Thermal Management Temperature */ 860 uint16_t mxtmt; 861 862 /** Sanitize Capabilities */ 863 uint32_t sanicap; /* Really a bitfield */ 864 865 uint8_t reserved3[180]; 866 /* bytes 512-703: nvm command set attributes */ 867 868 /** submission queue entry size */ 869 uint8_t sqes; 870 871 /** completion queue entry size */ 872 uint8_t cqes; 873 874 /** Maximum Outstanding Commands */ 875 uint16_t maxcmd; 876 877 /** number of namespaces */ 878 uint32_t nn; 879 880 /** optional nvm command support */ 881 uint16_t oncs; 882 883 /** fused operation support */ 884 uint16_t fuses; 885 886 /** format nvm attributes */ 887 uint8_t fna; 888 889 /** volatile write cache */ 890 uint8_t vwc; 891 892 /** Atomic Write Unit Normal */ 893 uint16_t awun; 894 895 /** Atomic Write Unit Power Fail */ 896 uint16_t awupf; 897 898 /** NVM Vendor Specific Command Configuration */ 899 uint8_t nvscc; 900 uint8_t reserved5; 901 902 /** Atomic Compare & Write Unit */ 903 uint16_t acwu; 904 uint16_t reserved6; 905 906 /** SGL Support */ 907 uint32_t sgls; 908 909 /* bytes 540-767: Reserved */ 910 uint8_t reserved7[228]; 911 912 /** NVM Subsystem NVMe Qualified Name */ 913 uint8_t subnqn[256]; 914 915 /* bytes 1024-1791: Reserved */ 916 uint8_t reserved8[768]; 917 918 /* bytes 1792-2047: NVMe over Fabrics specification */ 919 uint8_t reserved9[256]; 920 921 /* bytes 2048-3071: power state descriptors */ 922 struct nvme_power_state power_state[32]; 923 924 /* bytes 3072-4095: vendor specific */ 925 uint8_t vs[1024]; 926 } __packed __aligned(4); 927 928 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 929 930 struct nvme_namespace_data { 931 932 /** namespace size */ 933 uint64_t nsze; 934 935 /** namespace capacity */ 936 uint64_t ncap; 937 938 /** namespace utilization */ 939 uint64_t nuse; 940 941 /** namespace features */ 942 uint8_t nsfeat; 943 944 /** number of lba formats */ 945 uint8_t nlbaf; 946 947 /** formatted lba size */ 948 uint8_t flbas; 949 950 /** metadata capabilities */ 951 uint8_t mc; 952 953 /** end-to-end data protection capabilities */ 954 uint8_t dpc; 955 956 /** end-to-end data protection type settings */ 957 uint8_t dps; 958 959 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 960 uint8_t nmic; 961 962 /** Reservation Capabilities */ 963 uint8_t rescap; 964 965 /** Format Progress Indicator */ 966 uint8_t fpi; 967 968 /** Deallocate Logical Block Features */ 969 uint8_t dlfeat; 970 971 /** Namespace Atomic Write Unit Normal */ 972 uint16_t nawun; 973 974 /** Namespace Atomic Write Unit Power Fail */ 975 uint16_t nawupf; 976 977 /** Namespace Atomic Compare & Write Unit */ 978 uint16_t nacwu; 979 980 /** Namespace Atomic Boundary Size Normal */ 981 uint16_t nabsn; 982 983 /** Namespace Atomic Boundary Offset */ 984 uint16_t nabo; 985 986 /** Namespace Atomic Boundary Size Power Fail */ 987 uint16_t nabspf; 988 989 /** Namespace Optimal IO Boundary */ 990 uint16_t noiob; 991 992 /** NVM Capacity */ 993 uint8_t nvmcap[16]; 994 995 /* bytes 64-103: Reserved */ 996 uint8_t reserved5[40]; 997 998 /** Namespace Globally Unique Identifier */ 999 uint8_t nguid[16]; 1000 1001 /** IEEE Extended Unique Identifier */ 1002 uint8_t eui64[8]; 1003 1004 /** lba format support */ 1005 uint32_t lbaf[16]; 1006 1007 uint8_t reserved6[192]; 1008 1009 uint8_t vendor_specific[3712]; 1010 } __packed __aligned(4); 1011 1012 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 1013 1014 enum nvme_log_page { 1015 1016 /* 0x00 - reserved */ 1017 NVME_LOG_ERROR = 0x01, 1018 NVME_LOG_HEALTH_INFORMATION = 0x02, 1019 NVME_LOG_FIRMWARE_SLOT = 0x03, 1020 NVME_LOG_CHANGED_NAMESPACE = 0x04, 1021 NVME_LOG_COMMAND_EFFECT = 0x05, 1022 /* 0x06-0x7F - reserved */ 1023 /* 0x80-0xBF - I/O command set specific */ 1024 NVME_LOG_RES_NOTIFICATION = 0x80, 1025 /* 0xC0-0xFF - vendor specific */ 1026 1027 /* 1028 * The following are Intel Specific log pages, but they seem 1029 * to be widely implemented. 1030 */ 1031 INTEL_LOG_READ_LAT_LOG = 0xc1, 1032 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 1033 INTEL_LOG_TEMP_STATS = 0xc5, 1034 INTEL_LOG_ADD_SMART = 0xca, 1035 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 1036 1037 /* 1038 * HGST log page, with lots ofs sub pages. 1039 */ 1040 HGST_INFO_LOG = 0xc1, 1041 }; 1042 1043 struct nvme_error_information_entry { 1044 1045 uint64_t error_count; 1046 uint16_t sqid; 1047 uint16_t cid; 1048 uint16_t status; 1049 uint16_t error_location; 1050 uint64_t lba; 1051 uint32_t nsid; 1052 uint8_t vendor_specific; 1053 uint8_t reserved[35]; 1054 } __packed __aligned(4); 1055 1056 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 1057 1058 struct nvme_health_information_page { 1059 1060 uint8_t critical_warning; 1061 uint16_t temperature; 1062 uint8_t available_spare; 1063 uint8_t available_spare_threshold; 1064 uint8_t percentage_used; 1065 1066 uint8_t reserved[26]; 1067 1068 /* 1069 * Note that the following are 128-bit values, but are 1070 * defined as an array of 2 64-bit values. 1071 */ 1072 /* Data Units Read is always in 512-byte units. */ 1073 uint64_t data_units_read[2]; 1074 /* Data Units Written is always in 512-byte units. */ 1075 uint64_t data_units_written[2]; 1076 /* For NVM command set, this includes Compare commands. */ 1077 uint64_t host_read_commands[2]; 1078 uint64_t host_write_commands[2]; 1079 /* Controller Busy Time is reported in minutes. */ 1080 uint64_t controller_busy_time[2]; 1081 uint64_t power_cycles[2]; 1082 uint64_t power_on_hours[2]; 1083 uint64_t unsafe_shutdowns[2]; 1084 uint64_t media_errors[2]; 1085 uint64_t num_error_info_log_entries[2]; 1086 uint32_t warning_temp_time; 1087 uint32_t error_temp_time; 1088 uint16_t temp_sensor[8]; 1089 1090 uint8_t reserved2[296]; 1091 } __packed __aligned(4); 1092 1093 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 1094 1095 struct nvme_firmware_page { 1096 1097 uint8_t afi; 1098 uint8_t reserved[7]; 1099 uint64_t revision[7]; /* revisions for 7 slots */ 1100 uint8_t reserved2[448]; 1101 } __packed __aligned(4); 1102 1103 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 1104 1105 struct nvme_ns_list { 1106 uint32_t ns[1024]; 1107 } __packed __aligned(4); 1108 1109 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list"); 1110 1111 struct intel_log_temp_stats 1112 { 1113 uint64_t current; 1114 uint64_t overtemp_flag_last; 1115 uint64_t overtemp_flag_life; 1116 uint64_t max_temp; 1117 uint64_t min_temp; 1118 uint64_t _rsvd[5]; 1119 uint64_t max_oper_temp; 1120 uint64_t min_oper_temp; 1121 uint64_t est_offset; 1122 } __packed __aligned(4); 1123 1124 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 1125 1126 #define NVME_TEST_MAX_THREADS 128 1127 1128 struct nvme_io_test { 1129 1130 enum nvme_nvm_opcode opc; 1131 uint32_t size; 1132 uint32_t time; /* in seconds */ 1133 uint32_t num_threads; 1134 uint32_t flags; 1135 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 1136 }; 1137 1138 enum nvme_io_test_flags { 1139 1140 /* 1141 * Specifies whether dev_refthread/dev_relthread should be 1142 * called during NVME_BIO_TEST. Ignored for other test 1143 * types. 1144 */ 1145 NVME_TEST_FLAG_REFTHREAD = 0x1, 1146 }; 1147 1148 struct nvme_pt_command { 1149 1150 /* 1151 * cmd is used to specify a passthrough command to a controller or 1152 * namespace. 1153 * 1154 * The following fields from cmd may be specified by the caller: 1155 * * opc (opcode) 1156 * * nsid (namespace id) - for admin commands only 1157 * * cdw10-cdw15 1158 * 1159 * Remaining fields must be set to 0 by the caller. 1160 */ 1161 struct nvme_command cmd; 1162 1163 /* 1164 * cpl returns completion status for the passthrough command 1165 * specified by cmd. 1166 * 1167 * The following fields will be filled out by the driver, for 1168 * consumption by the caller: 1169 * * cdw0 1170 * * status (except for phase) 1171 * 1172 * Remaining fields will be set to 0 by the driver. 1173 */ 1174 struct nvme_completion cpl; 1175 1176 /* buf is the data buffer associated with this passthrough command. */ 1177 void * buf; 1178 1179 /* 1180 * len is the length of the data buffer associated with this 1181 * passthrough command. 1182 */ 1183 uint32_t len; 1184 1185 /* 1186 * is_read = 1 if the passthrough command will read data into the 1187 * supplied buffer from the controller. 1188 * 1189 * is_read = 0 if the passthrough command will write data from the 1190 * supplied buffer to the controller. 1191 */ 1192 uint32_t is_read; 1193 1194 /* 1195 * driver_lock is used by the driver only. It must be set to 0 1196 * by the caller. 1197 */ 1198 struct mtx * driver_lock; 1199 }; 1200 1201 #define nvme_completion_is_error(cpl) \ 1202 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0) 1203 1204 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1205 1206 #ifdef _KERNEL 1207 1208 struct bio; 1209 1210 struct nvme_namespace; 1211 struct nvme_controller; 1212 struct nvme_consumer; 1213 1214 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1215 1216 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1217 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1218 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1219 uint32_t, void *, uint32_t); 1220 typedef void (*nvme_cons_fail_fn_t)(void *); 1221 1222 enum nvme_namespace_flags { 1223 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1224 NVME_NS_FLUSH_SUPPORTED = 0x2, 1225 }; 1226 1227 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1228 struct nvme_pt_command *pt, 1229 uint32_t nsid, int is_user_buffer, 1230 int is_admin_cmd); 1231 1232 /* Admin functions */ 1233 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1234 uint8_t feature, uint32_t cdw11, 1235 void *payload, uint32_t payload_size, 1236 nvme_cb_fn_t cb_fn, void *cb_arg); 1237 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1238 uint8_t feature, uint32_t cdw11, 1239 void *payload, uint32_t payload_size, 1240 nvme_cb_fn_t cb_fn, void *cb_arg); 1241 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1242 uint8_t log_page, uint32_t nsid, 1243 void *payload, uint32_t payload_size, 1244 nvme_cb_fn_t cb_fn, void *cb_arg); 1245 1246 /* NVM I/O functions */ 1247 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1248 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1249 void *cb_arg); 1250 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1251 nvme_cb_fn_t cb_fn, void *cb_arg); 1252 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1253 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1254 void *cb_arg); 1255 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1256 nvme_cb_fn_t cb_fn, void *cb_arg); 1257 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1258 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1259 void *cb_arg); 1260 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1261 void *cb_arg); 1262 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1263 size_t len); 1264 1265 /* Registration functions */ 1266 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1267 nvme_cons_ctrlr_fn_t ctrlr_fn, 1268 nvme_cons_async_fn_t async_fn, 1269 nvme_cons_fail_fn_t fail_fn); 1270 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1271 1272 /* Controller helper functions */ 1273 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1274 const struct nvme_controller_data * 1275 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1276 static inline bool 1277 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd) 1278 { 1279 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */ 1280 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) & 1281 NVME_CTRLR_DATA_ONCS_DSM_MASK); 1282 } 1283 1284 /* Namespace helper functions */ 1285 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1286 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1287 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1288 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1289 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1290 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1291 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1292 const struct nvme_namespace_data * 1293 nvme_ns_get_data(struct nvme_namespace *ns); 1294 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1295 1296 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1297 nvme_cb_fn_t cb_fn); 1298 1299 /* 1300 * Command building helper functions -- shared with CAM 1301 * These functions assume allocator zeros out cmd structure 1302 * CAM's xpt_get_ccb and the request allocator for nvme both 1303 * do zero'd allocations. 1304 */ 1305 static inline 1306 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1307 { 1308 1309 cmd->opc = NVME_OPC_FLUSH; 1310 cmd->nsid = htole32(nsid); 1311 } 1312 1313 static inline 1314 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1315 uint64_t lba, uint32_t count) 1316 { 1317 cmd->opc = rwcmd; 1318 cmd->nsid = htole32(nsid); 1319 cmd->cdw10 = htole32(lba & 0xffffffffu); 1320 cmd->cdw11 = htole32(lba >> 32); 1321 cmd->cdw12 = htole32(count-1); 1322 } 1323 1324 static inline 1325 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1326 uint64_t lba, uint32_t count) 1327 { 1328 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1329 } 1330 1331 static inline 1332 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1333 uint64_t lba, uint32_t count) 1334 { 1335 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1336 } 1337 1338 static inline 1339 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1340 uint32_t num_ranges) 1341 { 1342 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1343 cmd->nsid = htole32(nsid); 1344 cmd->cdw10 = htole32(num_ranges - 1); 1345 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE); 1346 } 1347 1348 extern int nvme_use_nvd; 1349 1350 #endif /* _KERNEL */ 1351 1352 /* Endianess conversion functions for NVMe structs */ 1353 static inline 1354 void nvme_completion_swapbytes(struct nvme_completion *s) 1355 { 1356 1357 s->cdw0 = le32toh(s->cdw0); 1358 /* omit rsvd1 */ 1359 s->sqhd = le16toh(s->sqhd); 1360 s->sqid = le16toh(s->sqid); 1361 /* omit cid */ 1362 s->status = le16toh(s->status); 1363 } 1364 1365 static inline 1366 void nvme_power_state_swapbytes(struct nvme_power_state *s) 1367 { 1368 1369 s->mp = le16toh(s->mp); 1370 s->enlat = le32toh(s->enlat); 1371 s->exlat = le32toh(s->exlat); 1372 s->idlp = le16toh(s->idlp); 1373 s->actp = le16toh(s->actp); 1374 } 1375 1376 static inline 1377 void nvme_controller_data_swapbytes(struct nvme_controller_data *s) 1378 { 1379 int i; 1380 1381 s->vid = le16toh(s->vid); 1382 s->ssvid = le16toh(s->ssvid); 1383 s->ctrlr_id = le16toh(s->ctrlr_id); 1384 s->ver = le32toh(s->ver); 1385 s->rtd3r = le32toh(s->rtd3r); 1386 s->rtd3e = le32toh(s->rtd3e); 1387 s->oaes = le32toh(s->oaes); 1388 s->ctratt = le32toh(s->ctratt); 1389 s->oacs = le16toh(s->oacs); 1390 s->wctemp = le16toh(s->wctemp); 1391 s->cctemp = le16toh(s->cctemp); 1392 s->mtfa = le16toh(s->mtfa); 1393 s->hmpre = le32toh(s->hmpre); 1394 s->hmmin = le32toh(s->hmmin); 1395 s->rpmbs = le32toh(s->rpmbs); 1396 s->edstt = le16toh(s->edstt); 1397 s->kas = le16toh(s->kas); 1398 s->hctma = le16toh(s->hctma); 1399 s->mntmt = le16toh(s->mntmt); 1400 s->mxtmt = le16toh(s->mxtmt); 1401 s->sanicap = le32toh(s->sanicap); 1402 s->maxcmd = le16toh(s->maxcmd); 1403 s->nn = le32toh(s->nn); 1404 s->oncs = le16toh(s->oncs); 1405 s->fuses = le16toh(s->fuses); 1406 s->awun = le16toh(s->awun); 1407 s->awupf = le16toh(s->awupf); 1408 s->acwu = le16toh(s->acwu); 1409 s->sgls = le32toh(s->sgls); 1410 for (i = 0; i < 32; i++) 1411 nvme_power_state_swapbytes(&s->power_state[i]); 1412 } 1413 1414 static inline 1415 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s) 1416 { 1417 int i; 1418 1419 s->nsze = le64toh(s->nsze); 1420 s->ncap = le64toh(s->ncap); 1421 s->nuse = le64toh(s->nuse); 1422 s->nawun = le16toh(s->nawun); 1423 s->nawupf = le16toh(s->nawupf); 1424 s->nacwu = le16toh(s->nacwu); 1425 s->nabsn = le16toh(s->nabsn); 1426 s->nabo = le16toh(s->nabo); 1427 s->nabspf = le16toh(s->nabspf); 1428 s->noiob = le16toh(s->noiob); 1429 for (i = 0; i < 16; i++) 1430 s->lbaf[i] = le32toh(s->lbaf[i]); 1431 } 1432 1433 static inline 1434 void nvme_error_information_entry_swapbytes(struct nvme_error_information_entry *s) 1435 { 1436 1437 s->error_count = le64toh(s->error_count); 1438 s->sqid = le16toh(s->sqid); 1439 s->cid = le16toh(s->cid); 1440 s->status = le16toh(s->status); 1441 s->error_location = le16toh(s->error_location); 1442 s->lba = le64toh(s->lba); 1443 s->nsid = le32toh(s->nsid); 1444 } 1445 1446 static inline 1447 void nvme_le128toh(void *p) 1448 { 1449 #if _BYTE_ORDER != _LITTLE_ENDIAN 1450 /* Swap 16 bytes in place */ 1451 char *tmp = (char*)p; 1452 char b; 1453 int i; 1454 for (i = 0; i < 8; i++) { 1455 b = tmp[i]; 1456 tmp[i] = tmp[15-i]; 1457 tmp[15-i] = b; 1458 } 1459 #else 1460 (void)p; 1461 #endif 1462 } 1463 1464 static inline 1465 void nvme_health_information_page_swapbytes(struct nvme_health_information_page *s) 1466 { 1467 int i; 1468 1469 s->temperature = le16toh(s->temperature); 1470 nvme_le128toh((void *)s->data_units_read); 1471 nvme_le128toh((void *)s->data_units_written); 1472 nvme_le128toh((void *)s->host_read_commands); 1473 nvme_le128toh((void *)s->host_write_commands); 1474 nvme_le128toh((void *)s->controller_busy_time); 1475 nvme_le128toh((void *)s->power_cycles); 1476 nvme_le128toh((void *)s->power_on_hours); 1477 nvme_le128toh((void *)s->unsafe_shutdowns); 1478 nvme_le128toh((void *)s->media_errors); 1479 nvme_le128toh((void *)s->num_error_info_log_entries); 1480 s->warning_temp_time = le32toh(s->warning_temp_time); 1481 s->error_temp_time = le32toh(s->error_temp_time); 1482 for (i = 0; i < 8; i++) 1483 s->temp_sensor[i] = le16toh(s->temp_sensor[i]); 1484 } 1485 1486 1487 static inline 1488 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s) 1489 { 1490 int i; 1491 1492 for (i = 0; i < 7; i++) 1493 s->revision[i] = le64toh(s->revision[i]); 1494 } 1495 1496 static inline 1497 void nvme_ns_list_swapbytes(struct nvme_ns_list *s) 1498 { 1499 int i; 1500 1501 for (i = 0; i < 1024; i++) 1502 s->ns[i] = le32toh(s->ns[i]); 1503 } 1504 1505 static inline 1506 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s) 1507 { 1508 1509 s->current = le64toh(s->current); 1510 s->overtemp_flag_last = le64toh(s->overtemp_flag_last); 1511 s->overtemp_flag_life = le64toh(s->overtemp_flag_life); 1512 s->max_temp = le64toh(s->max_temp); 1513 s->min_temp = le64toh(s->min_temp); 1514 /* omit _rsvd[] */ 1515 s->max_oper_temp = le64toh(s->max_oper_temp); 1516 s->min_oper_temp = le64toh(s->min_oper_temp); 1517 s->est_offset = le64toh(s->est_offset); 1518 } 1519 1520 #endif /* __NVME_H__ */ 1521