1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012-2013 Intel Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef __NVME_H__ 32 #define __NVME_H__ 33 34 #ifdef _KERNEL 35 #include <sys/types.h> 36 #endif 37 38 #include <sys/param.h> 39 #include <sys/endian.h> 40 41 #define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command) 42 #define NVME_RESET_CONTROLLER _IO('n', 1) 43 44 #define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test) 45 #define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test) 46 47 /* 48 * Macros to deal with NVME revisions, as defined VS register 49 */ 50 #define NVME_REV(x, y) (((x) << 16) | ((y) << 8)) 51 #define NVME_MAJOR(r) (((r) >> 16) & 0xffff) 52 #define NVME_MINOR(r) (((r) >> 8) & 0xff) 53 54 /* 55 * Use to mark a command to apply to all namespaces, or to retrieve global 56 * log pages. 57 */ 58 #define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF) 59 60 /* Cap nvme to 1MB transfers driver explodes with larger sizes */ 61 #define NVME_MAX_XFER_SIZE (MAXPHYS < (1<<20) ? MAXPHYS : (1<<20)) 62 63 /* Register field definitions */ 64 #define NVME_CAP_LO_REG_MQES_SHIFT (0) 65 #define NVME_CAP_LO_REG_MQES_MASK (0xFFFF) 66 #define NVME_CAP_LO_REG_CQR_SHIFT (16) 67 #define NVME_CAP_LO_REG_CQR_MASK (0x1) 68 #define NVME_CAP_LO_REG_AMS_SHIFT (17) 69 #define NVME_CAP_LO_REG_AMS_MASK (0x3) 70 #define NVME_CAP_LO_REG_TO_SHIFT (24) 71 #define NVME_CAP_LO_REG_TO_MASK (0xFF) 72 #define NVME_CAP_LO_MQES(x) \ 73 (((x) >> NVME_CAP_LO_REG_MQES_SHIFT) & NVME_CAP_LO_REG_MQES_MASK) 74 #define NVME_CAP_LO_CQR(x) \ 75 (((x) >> NVME_CAP_LO_REG_CQR_SHIFT) & NVME_CAP_LO_REG_CQR_MASK) 76 #define NVME_CAP_LO_AMS(x) \ 77 (((x) >> NVME_CAP_LO_REG_AMS_SHIFT) & NVME_CAP_LO_REG_AMS_MASK) 78 #define NVME_CAP_LO_TO(x) \ 79 (((x) >> NVME_CAP_LO_REG_TO_SHIFT) & NVME_CAP_LO_REG_TO_MASK) 80 81 #define NVME_CAP_HI_REG_DSTRD_SHIFT (0) 82 #define NVME_CAP_HI_REG_DSTRD_MASK (0xF) 83 #define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5) 84 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1) 85 #define NVME_CAP_HI_REG_MPSMIN_SHIFT (16) 86 #define NVME_CAP_HI_REG_MPSMIN_MASK (0xF) 87 #define NVME_CAP_HI_REG_MPSMAX_SHIFT (20) 88 #define NVME_CAP_HI_REG_MPSMAX_MASK (0xF) 89 #define NVME_CAP_HI_DSTRD(x) \ 90 (((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK) 91 #define NVME_CAP_HI_CSS_NVM(x) \ 92 (((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK) 93 #define NVME_CAP_HI_MPSMIN(x) \ 94 (((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK) 95 #define NVME_CAP_HI_MPSMAX(x) \ 96 (((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK) 97 98 #define NVME_CC_REG_EN_SHIFT (0) 99 #define NVME_CC_REG_EN_MASK (0x1) 100 #define NVME_CC_REG_CSS_SHIFT (4) 101 #define NVME_CC_REG_CSS_MASK (0x7) 102 #define NVME_CC_REG_MPS_SHIFT (7) 103 #define NVME_CC_REG_MPS_MASK (0xF) 104 #define NVME_CC_REG_AMS_SHIFT (11) 105 #define NVME_CC_REG_AMS_MASK (0x7) 106 #define NVME_CC_REG_SHN_SHIFT (14) 107 #define NVME_CC_REG_SHN_MASK (0x3) 108 #define NVME_CC_REG_IOSQES_SHIFT (16) 109 #define NVME_CC_REG_IOSQES_MASK (0xF) 110 #define NVME_CC_REG_IOCQES_SHIFT (20) 111 #define NVME_CC_REG_IOCQES_MASK (0xF) 112 113 #define NVME_CSTS_REG_RDY_SHIFT (0) 114 #define NVME_CSTS_REG_RDY_MASK (0x1) 115 #define NVME_CSTS_REG_CFS_SHIFT (1) 116 #define NVME_CSTS_REG_CFS_MASK (0x1) 117 #define NVME_CSTS_REG_SHST_SHIFT (2) 118 #define NVME_CSTS_REG_SHST_MASK (0x3) 119 120 #define NVME_CSTS_GET_SHST(csts) (((csts) >> NVME_CSTS_REG_SHST_SHIFT) & NVME_CSTS_REG_SHST_MASK) 121 122 #define NVME_AQA_REG_ASQS_SHIFT (0) 123 #define NVME_AQA_REG_ASQS_MASK (0xFFF) 124 #define NVME_AQA_REG_ACQS_SHIFT (16) 125 #define NVME_AQA_REG_ACQS_MASK (0xFFF) 126 127 /* Command field definitions */ 128 129 #define NVME_CMD_FUSE_SHIFT (8) 130 #define NVME_CMD_FUSE_MASK (0x3) 131 132 #define NVME_STATUS_P_SHIFT (0) 133 #define NVME_STATUS_P_MASK (0x1) 134 #define NVME_STATUS_SC_SHIFT (1) 135 #define NVME_STATUS_SC_MASK (0xFF) 136 #define NVME_STATUS_SCT_SHIFT (9) 137 #define NVME_STATUS_SCT_MASK (0x7) 138 #define NVME_STATUS_M_SHIFT (14) 139 #define NVME_STATUS_M_MASK (0x1) 140 #define NVME_STATUS_DNR_SHIFT (15) 141 #define NVME_STATUS_DNR_MASK (0x1) 142 143 #define NVME_STATUS_GET_P(st) (((st) >> NVME_STATUS_P_SHIFT) & NVME_STATUS_P_MASK) 144 #define NVME_STATUS_GET_SC(st) (((st) >> NVME_STATUS_SC_SHIFT) & NVME_STATUS_SC_MASK) 145 #define NVME_STATUS_GET_SCT(st) (((st) >> NVME_STATUS_SCT_SHIFT) & NVME_STATUS_SCT_MASK) 146 #define NVME_STATUS_GET_M(st) (((st) >> NVME_STATUS_M_SHIFT) & NVME_STATUS_M_MASK) 147 #define NVME_STATUS_GET_DNR(st) (((st) >> NVME_STATUS_DNR_SHIFT) & NVME_STATUS_DNR_MASK) 148 149 #define NVME_PWR_ST_MPS_SHIFT (0) 150 #define NVME_PWR_ST_MPS_MASK (0x1) 151 #define NVME_PWR_ST_NOPS_SHIFT (1) 152 #define NVME_PWR_ST_NOPS_MASK (0x1) 153 #define NVME_PWR_ST_RRT_SHIFT (0) 154 #define NVME_PWR_ST_RRT_MASK (0x1F) 155 #define NVME_PWR_ST_RRL_SHIFT (0) 156 #define NVME_PWR_ST_RRL_MASK (0x1F) 157 #define NVME_PWR_ST_RWT_SHIFT (0) 158 #define NVME_PWR_ST_RWT_MASK (0x1F) 159 #define NVME_PWR_ST_RWL_SHIFT (0) 160 #define NVME_PWR_ST_RWL_MASK (0x1F) 161 #define NVME_PWR_ST_IPS_SHIFT (6) 162 #define NVME_PWR_ST_IPS_MASK (0x3) 163 #define NVME_PWR_ST_APW_SHIFT (0) 164 #define NVME_PWR_ST_APW_MASK (0x7) 165 #define NVME_PWR_ST_APS_SHIFT (6) 166 #define NVME_PWR_ST_APS_MASK (0x3) 167 168 /** Controller Multi-path I/O and Namespace Sharing Capabilities */ 169 /* More then one port */ 170 #define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0) 171 #define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1) 172 /* More then one controller */ 173 #define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1) 174 #define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1) 175 /* SR-IOV Virtual Function */ 176 #define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2) 177 #define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1) 178 /* Asymmetric Namespace Access Reporting */ 179 #define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3) 180 #define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1) 181 182 /** OACS - optional admin command support */ 183 /* supports security send/receive commands */ 184 #define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0) 185 #define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1) 186 /* supports format nvm command */ 187 #define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1) 188 #define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1) 189 /* supports firmware activate/download commands */ 190 #define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2) 191 #define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1) 192 /* supports namespace management commands */ 193 #define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3) 194 #define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1) 195 /* supports Device Self-test command */ 196 #define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4) 197 #define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1) 198 /* supports Directives */ 199 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5) 200 #define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1) 201 /* supports NVMe-MI Send/Receive */ 202 #define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6) 203 #define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1) 204 /* supports Virtualization Management */ 205 #define NVME_CTRLR_DATA_OACS_VM_SHIFT (7) 206 #define NVME_CTRLR_DATA_OACS_VM_MASK (0x1) 207 /* supports Doorbell Buffer Config */ 208 #define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8) 209 #define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1) 210 /* supports Get LBA Status */ 211 #define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9) 212 #define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1) 213 214 /** firmware updates */ 215 /* first slot is read-only */ 216 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0) 217 #define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1) 218 /* number of firmware slots */ 219 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1) 220 #define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7) 221 /* firmware activation without reset */ 222 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4) 223 #define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1) 224 225 /** log page attributes */ 226 /* per namespace smart/health log page */ 227 #define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0) 228 #define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1) 229 230 /** AVSCC - admin vendor specific command configuration */ 231 /* admin vendor specific commands use spec format */ 232 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0) 233 #define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1) 234 235 /** Autonomous Power State Transition Attributes */ 236 /* Autonomous Power State Transitions supported */ 237 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0) 238 #define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1) 239 240 /** Sanitize Capabilities */ 241 /* Crypto Erase Support */ 242 #define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0) 243 #define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1) 244 /* Block Erase Support */ 245 #define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1) 246 #define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1) 247 /* Overwrite Support */ 248 #define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2) 249 #define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1) 250 /* No-Deallocate Inhibited */ 251 #define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29) 252 #define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1) 253 /* No-Deallocate Modifies Media After Sanitize */ 254 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30) 255 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3) 256 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0) 257 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1) 258 #define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2) 259 260 /** submission queue entry size */ 261 #define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0) 262 #define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF) 263 #define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4) 264 #define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF) 265 266 /** completion queue entry size */ 267 #define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0) 268 #define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF) 269 #define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4) 270 #define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF) 271 272 /** optional nvm command support */ 273 #define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0) 274 #define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1) 275 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1) 276 #define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1) 277 #define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2) 278 #define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1) 279 #define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3) 280 #define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1) 281 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4) 282 #define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1) 283 #define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5) 284 #define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1) 285 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6) 286 #define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1) 287 #define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7) 288 #define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1) 289 290 /** Fused Operation Support */ 291 #define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0) 292 #define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1) 293 294 /** Format NVM Attributes */ 295 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0) 296 #define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1) 297 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1) 298 #define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1) 299 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2) 300 #define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1) 301 302 /** volatile write cache */ 303 /* volatile write cache present */ 304 #define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0) 305 #define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1) 306 /* flush all namespaces supported */ 307 #define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1) 308 #define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3) 309 #define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0) 310 #define NVME_CTRLR_DATA_VWC_ALL_NO (2) 311 #define NVME_CTRLR_DATA_VWC_ALL_YES (3) 312 313 /** namespace features */ 314 /* thin provisioning */ 315 #define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0) 316 #define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1) 317 /* NAWUN, NAWUPF, and NACWU fields are valid */ 318 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1) 319 #define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1) 320 /* Deallocated or Unwritten Logical Block errors supported */ 321 #define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2) 322 #define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1) 323 /* NGUID and EUI64 fields are not reusable */ 324 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3) 325 #define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1) 326 /* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */ 327 #define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4) 328 #define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1) 329 330 /** formatted lba size */ 331 #define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0) 332 #define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF) 333 #define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4) 334 #define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1) 335 336 /** metadata capabilities */ 337 /* metadata can be transferred as part of data prp list */ 338 #define NVME_NS_DATA_MC_EXTENDED_SHIFT (0) 339 #define NVME_NS_DATA_MC_EXTENDED_MASK (0x1) 340 /* metadata can be transferred with separate metadata pointer */ 341 #define NVME_NS_DATA_MC_POINTER_SHIFT (1) 342 #define NVME_NS_DATA_MC_POINTER_MASK (0x1) 343 344 /** end-to-end data protection capabilities */ 345 /* protection information type 1 */ 346 #define NVME_NS_DATA_DPC_PIT1_SHIFT (0) 347 #define NVME_NS_DATA_DPC_PIT1_MASK (0x1) 348 /* protection information type 2 */ 349 #define NVME_NS_DATA_DPC_PIT2_SHIFT (1) 350 #define NVME_NS_DATA_DPC_PIT2_MASK (0x1) 351 /* protection information type 3 */ 352 #define NVME_NS_DATA_DPC_PIT3_SHIFT (2) 353 #define NVME_NS_DATA_DPC_PIT3_MASK (0x1) 354 /* first eight bytes of metadata */ 355 #define NVME_NS_DATA_DPC_MD_START_SHIFT (3) 356 #define NVME_NS_DATA_DPC_MD_START_MASK (0x1) 357 /* last eight bytes of metadata */ 358 #define NVME_NS_DATA_DPC_MD_END_SHIFT (4) 359 #define NVME_NS_DATA_DPC_MD_END_MASK (0x1) 360 361 /** end-to-end data protection type settings */ 362 /* protection information type */ 363 #define NVME_NS_DATA_DPS_PIT_SHIFT (0) 364 #define NVME_NS_DATA_DPS_PIT_MASK (0x7) 365 /* 1 == protection info transferred at start of metadata */ 366 /* 0 == protection info transferred at end of metadata */ 367 #define NVME_NS_DATA_DPS_MD_START_SHIFT (3) 368 #define NVME_NS_DATA_DPS_MD_START_MASK (0x1) 369 370 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 371 /* the namespace may be attached to two or more controllers */ 372 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0) 373 #define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1) 374 375 /** Reservation Capabilities */ 376 /* Persist Through Power Loss */ 377 #define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0) 378 #define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1) 379 /* supports the Write Exclusive */ 380 #define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1) 381 #define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1) 382 /* supports the Exclusive Access */ 383 #define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2) 384 #define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1) 385 /* supports the Write Exclusive – Registrants Only */ 386 #define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3) 387 #define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1) 388 /* supports the Exclusive Access - Registrants Only */ 389 #define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4) 390 #define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1) 391 /* supports the Write Exclusive – All Registrants */ 392 #define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5) 393 #define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1) 394 /* supports the Exclusive Access - All Registrants */ 395 #define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6) 396 #define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1) 397 /* Ignore Existing Key is used as defined in revision 1.3 or later */ 398 #define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7) 399 #define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1) 400 401 /** Format Progress Indicator */ 402 /* percentage of the Format NVM command that remains to be completed */ 403 #define NVME_NS_DATA_FPI_PERC_SHIFT (0) 404 #define NVME_NS_DATA_FPI_PERC_MASK (0x7f) 405 /* namespace supports the Format Progress Indicator */ 406 #define NVME_NS_DATA_FPI_SUPP_SHIFT (7) 407 #define NVME_NS_DATA_FPI_SUPP_MASK (0x1) 408 409 /** Deallocate Logical Block Features */ 410 /* deallocated logical block read behavior */ 411 #define NVME_NS_DATA_DLFEAT_READ_SHIFT (0) 412 #define NVME_NS_DATA_DLFEAT_READ_MASK (0x07) 413 #define NVME_NS_DATA_DLFEAT_READ_NR (0x00) 414 #define NVME_NS_DATA_DLFEAT_READ_00 (0x01) 415 #define NVME_NS_DATA_DLFEAT_READ_FF (0x02) 416 /* supports the Deallocate bit in the Write Zeroes */ 417 #define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3) 418 #define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01) 419 /* Guard field for deallocated logical blocks is set to the CRC */ 420 #define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4) 421 #define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01) 422 423 /** lba format support */ 424 /* metadata size */ 425 #define NVME_NS_DATA_LBAF_MS_SHIFT (0) 426 #define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF) 427 /* lba data size */ 428 #define NVME_NS_DATA_LBAF_LBADS_SHIFT (16) 429 #define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF) 430 /* relative performance */ 431 #define NVME_NS_DATA_LBAF_RP_SHIFT (24) 432 #define NVME_NS_DATA_LBAF_RP_MASK (0x3) 433 434 enum nvme_critical_warning_state { 435 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1, 436 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2, 437 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4, 438 NVME_CRIT_WARN_ST_READ_ONLY = 0x8, 439 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10, 440 }; 441 #define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0) 442 443 /* slot for current FW */ 444 #define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0) 445 #define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7) 446 447 /* CC register SHN field values */ 448 enum shn_value { 449 NVME_SHN_NORMAL = 0x1, 450 NVME_SHN_ABRUPT = 0x2, 451 }; 452 453 /* CSTS register SHST field values */ 454 enum shst_value { 455 NVME_SHST_NORMAL = 0x0, 456 NVME_SHST_OCCURRING = 0x1, 457 NVME_SHST_COMPLETE = 0x2, 458 }; 459 460 struct nvme_registers 461 { 462 /** controller capabilities */ 463 uint32_t cap_lo; 464 uint32_t cap_hi; 465 466 uint32_t vs; /* version */ 467 uint32_t intms; /* interrupt mask set */ 468 uint32_t intmc; /* interrupt mask clear */ 469 470 /** controller configuration */ 471 uint32_t cc; 472 473 uint32_t reserved1; 474 475 /** controller status */ 476 uint32_t csts; 477 478 uint32_t reserved2; 479 480 /** admin queue attributes */ 481 uint32_t aqa; 482 483 uint64_t asq; /* admin submission queue base addr */ 484 uint64_t acq; /* admin completion queue base addr */ 485 uint32_t reserved3[0x3f2]; 486 487 struct { 488 uint32_t sq_tdbl; /* submission queue tail doorbell */ 489 uint32_t cq_hdbl; /* completion queue head doorbell */ 490 } doorbell[1] __packed; 491 } __packed; 492 493 _Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers"); 494 495 struct nvme_command 496 { 497 /* dword 0 */ 498 uint8_t opc; /* opcode */ 499 uint8_t fuse; /* fused operation */ 500 uint16_t cid; /* command identifier */ 501 502 /* dword 1 */ 503 uint32_t nsid; /* namespace identifier */ 504 505 /* dword 2-3 */ 506 uint32_t rsvd2; 507 uint32_t rsvd3; 508 509 /* dword 4-5 */ 510 uint64_t mptr; /* metadata pointer */ 511 512 /* dword 6-7 */ 513 uint64_t prp1; /* prp entry 1 */ 514 515 /* dword 8-9 */ 516 uint64_t prp2; /* prp entry 2 */ 517 518 /* dword 10-15 */ 519 uint32_t cdw10; /* command-specific */ 520 uint32_t cdw11; /* command-specific */ 521 uint32_t cdw12; /* command-specific */ 522 uint32_t cdw13; /* command-specific */ 523 uint32_t cdw14; /* command-specific */ 524 uint32_t cdw15; /* command-specific */ 525 } __packed; 526 527 _Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command"); 528 529 struct nvme_completion { 530 531 /* dword 0 */ 532 uint32_t cdw0; /* command-specific */ 533 534 /* dword 1 */ 535 uint32_t rsvd1; 536 537 /* dword 2 */ 538 uint16_t sqhd; /* submission queue head pointer */ 539 uint16_t sqid; /* submission queue identifier */ 540 541 /* dword 3 */ 542 uint16_t cid; /* command identifier */ 543 uint16_t status; 544 } __packed; 545 546 _Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion"); 547 548 struct nvme_dsm_range { 549 uint32_t attributes; 550 uint32_t length; 551 uint64_t starting_lba; 552 } __packed; 553 554 /* Largest DSM Trim that can be done */ 555 #define NVME_MAX_DSM_TRIM 4096 556 557 _Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage"); 558 559 /* status code types */ 560 enum nvme_status_code_type { 561 NVME_SCT_GENERIC = 0x0, 562 NVME_SCT_COMMAND_SPECIFIC = 0x1, 563 NVME_SCT_MEDIA_ERROR = 0x2, 564 /* 0x3-0x6 - reserved */ 565 NVME_SCT_VENDOR_SPECIFIC = 0x7, 566 }; 567 568 /* generic command status codes */ 569 enum nvme_generic_command_status_code { 570 NVME_SC_SUCCESS = 0x00, 571 NVME_SC_INVALID_OPCODE = 0x01, 572 NVME_SC_INVALID_FIELD = 0x02, 573 NVME_SC_COMMAND_ID_CONFLICT = 0x03, 574 NVME_SC_DATA_TRANSFER_ERROR = 0x04, 575 NVME_SC_ABORTED_POWER_LOSS = 0x05, 576 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06, 577 NVME_SC_ABORTED_BY_REQUEST = 0x07, 578 NVME_SC_ABORTED_SQ_DELETION = 0x08, 579 NVME_SC_ABORTED_FAILED_FUSED = 0x09, 580 NVME_SC_ABORTED_MISSING_FUSED = 0x0a, 581 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b, 582 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c, 583 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d, 584 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e, 585 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f, 586 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10, 587 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11, 588 NVME_SC_INVALID_USE_OF_CMB = 0x12, 589 NVME_SC_PRP_OFFET_INVALID = 0x13, 590 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14, 591 NVME_SC_OPERATION_DENIED = 0x15, 592 NVME_SC_SGL_OFFSET_INVALID = 0x16, 593 /* 0x17 - reserved */ 594 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18, 595 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19, 596 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a, 597 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b, 598 NVME_SC_SANITIZE_FAILED = 0x1c, 599 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d, 600 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e, 601 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f, 602 603 NVME_SC_LBA_OUT_OF_RANGE = 0x80, 604 NVME_SC_CAPACITY_EXCEEDED = 0x81, 605 NVME_SC_NAMESPACE_NOT_READY = 0x82, 606 NVME_SC_RESERVATION_CONFLICT = 0x83, 607 NVME_SC_FORMAT_IN_PROGRESS = 0x84, 608 }; 609 610 /* command specific status codes */ 611 enum nvme_command_specific_status_code { 612 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00, 613 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01, 614 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02, 615 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03, 616 /* 0x04 - reserved */ 617 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05, 618 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06, 619 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07, 620 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08, 621 NVME_SC_INVALID_LOG_PAGE = 0x09, 622 NVME_SC_INVALID_FORMAT = 0x0a, 623 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b, 624 NVME_SC_INVALID_QUEUE_DELETION = 0x0c, 625 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d, 626 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e, 627 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f, 628 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10, 629 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11, 630 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12, 631 NVME_SC_FW_ACT_PROHIBITED = 0x13, 632 NVME_SC_OVERLAPPING_RANGE = 0x14, 633 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15, 634 NVME_SC_NS_ID_UNAVAILABLE = 0x16, 635 /* 0x17 - reserved */ 636 NVME_SC_NS_ALREADY_ATTACHED = 0x18, 637 NVME_SC_NS_IS_PRIVATE = 0x19, 638 NVME_SC_NS_NOT_ATTACHED = 0x1a, 639 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b, 640 NVME_SC_CTRLR_LIST_INVALID = 0x1c, 641 NVME_SC_SELT_TEST_IN_PROGRESS = 0x1d, 642 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e, 643 NVME_SC_INVALID_CTRLR_ID = 0x1f, 644 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20, 645 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21, 646 NVME_SC_INVALID_RESOURCE_ID = 0x22, 647 648 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80, 649 NVME_SC_INVALID_PROTECTION_INFO = 0x81, 650 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82, 651 }; 652 653 /* media error status codes */ 654 enum nvme_media_error_status_code { 655 NVME_SC_WRITE_FAULTS = 0x80, 656 NVME_SC_UNRECOVERED_READ_ERROR = 0x81, 657 NVME_SC_GUARD_CHECK_ERROR = 0x82, 658 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83, 659 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84, 660 NVME_SC_COMPARE_FAILURE = 0x85, 661 NVME_SC_ACCESS_DENIED = 0x86, 662 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87, 663 }; 664 665 /* admin opcodes */ 666 enum nvme_admin_opcode { 667 NVME_OPC_DELETE_IO_SQ = 0x00, 668 NVME_OPC_CREATE_IO_SQ = 0x01, 669 NVME_OPC_GET_LOG_PAGE = 0x02, 670 /* 0x03 - reserved */ 671 NVME_OPC_DELETE_IO_CQ = 0x04, 672 NVME_OPC_CREATE_IO_CQ = 0x05, 673 NVME_OPC_IDENTIFY = 0x06, 674 /* 0x07 - reserved */ 675 NVME_OPC_ABORT = 0x08, 676 NVME_OPC_SET_FEATURES = 0x09, 677 NVME_OPC_GET_FEATURES = 0x0a, 678 /* 0x0b - reserved */ 679 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c, 680 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d, 681 /* 0x0e-0x0f - reserved */ 682 NVME_OPC_FIRMWARE_ACTIVATE = 0x10, 683 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11, 684 NVME_OPC_DEVICE_SELF_TEST = 0x14, 685 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15, 686 NVME_OPC_KEEP_ALIVE = 0x18, 687 NVME_OPC_DIRECTIVE_SEND = 0x19, 688 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a, 689 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c, 690 NVME_OPC_NVME_MI_SEND = 0x1d, 691 NVME_OPC_NVME_MI_RECEIVE = 0x1e, 692 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c, 693 694 NVME_OPC_FORMAT_NVM = 0x80, 695 NVME_OPC_SECURITY_SEND = 0x81, 696 NVME_OPC_SECURITY_RECEIVE = 0x82, 697 NVME_OPC_SANITIZE = 0x84, 698 }; 699 700 /* nvme nvm opcodes */ 701 enum nvme_nvm_opcode { 702 NVME_OPC_FLUSH = 0x00, 703 NVME_OPC_WRITE = 0x01, 704 NVME_OPC_READ = 0x02, 705 /* 0x03 - reserved */ 706 NVME_OPC_WRITE_UNCORRECTABLE = 0x04, 707 NVME_OPC_COMPARE = 0x05, 708 /* 0x06 - reserved */ 709 NVME_OPC_WRITE_ZEROES = 0x08, 710 /* 0x07 - reserved */ 711 NVME_OPC_DATASET_MANAGEMENT = 0x09, 712 /* 0x0a-0x0c - reserved */ 713 NVME_OPC_RESERVATION_REGISTER = 0x0d, 714 NVME_OPC_RESERVATION_REPORT = 0x0e, 715 /* 0x0f-0x10 - reserved */ 716 NVME_OPC_RESERVATION_ACQUIRE = 0x11, 717 /* 0x12-0x14 - reserved */ 718 NVME_OPC_RESERVATION_RELEASE = 0x15, 719 }; 720 721 enum nvme_feature { 722 /* 0x00 - reserved */ 723 NVME_FEAT_ARBITRATION = 0x01, 724 NVME_FEAT_POWER_MANAGEMENT = 0x02, 725 NVME_FEAT_LBA_RANGE_TYPE = 0x03, 726 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04, 727 NVME_FEAT_ERROR_RECOVERY = 0x05, 728 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06, 729 NVME_FEAT_NUMBER_OF_QUEUES = 0x07, 730 NVME_FEAT_INTERRUPT_COALESCING = 0x08, 731 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09, 732 NVME_FEAT_WRITE_ATOMICITY = 0x0A, 733 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B, 734 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C, 735 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D, 736 NVME_FEAT_TIMESTAMP = 0x0E, 737 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F, 738 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10, 739 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11, 740 /* 0x12-0x77 - reserved */ 741 /* 0x78-0x7f - NVMe Management Interface */ 742 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80, 743 /* 0x81-0xBF - command set specific (reserved) */ 744 /* 0xC0-0xFF - vendor specific */ 745 }; 746 747 enum nvme_dsm_attribute { 748 NVME_DSM_ATTR_INTEGRAL_READ = 0x1, 749 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2, 750 NVME_DSM_ATTR_DEALLOCATE = 0x4, 751 }; 752 753 enum nvme_activate_action { 754 NVME_AA_REPLACE_NO_ACTIVATE = 0x0, 755 NVME_AA_REPLACE_ACTIVATE = 0x1, 756 NVME_AA_ACTIVATE = 0x2, 757 }; 758 759 struct nvme_power_state { 760 /** Maximum Power */ 761 uint16_t mp; /* Maximum Power */ 762 uint8_t ps_rsvd1; 763 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */ 764 765 uint32_t enlat; /* Entry Latency */ 766 uint32_t exlat; /* Exit Latency */ 767 768 uint8_t rrt; /* Relative Read Throughput */ 769 uint8_t rrl; /* Relative Read Latency */ 770 uint8_t rwt; /* Relative Write Throughput */ 771 uint8_t rwl; /* Relative Write Latency */ 772 773 uint16_t idlp; /* Idle Power */ 774 uint8_t ips; /* Idle Power Scale */ 775 uint8_t ps_rsvd8; 776 777 uint16_t actp; /* Active Power */ 778 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */ 779 uint8_t ps_rsvd10[9]; 780 } __packed; 781 782 _Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state"); 783 784 #define NVME_SERIAL_NUMBER_LENGTH 20 785 #define NVME_MODEL_NUMBER_LENGTH 40 786 #define NVME_FIRMWARE_REVISION_LENGTH 8 787 788 struct nvme_controller_data { 789 790 /* bytes 0-255: controller capabilities and features */ 791 792 /** pci vendor id */ 793 uint16_t vid; 794 795 /** pci subsystem vendor id */ 796 uint16_t ssvid; 797 798 /** serial number */ 799 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH]; 800 801 /** model number */ 802 uint8_t mn[NVME_MODEL_NUMBER_LENGTH]; 803 804 /** firmware revision */ 805 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH]; 806 807 /** recommended arbitration burst */ 808 uint8_t rab; 809 810 /** ieee oui identifier */ 811 uint8_t ieee[3]; 812 813 /** multi-interface capabilities */ 814 uint8_t mic; 815 816 /** maximum data transfer size */ 817 uint8_t mdts; 818 819 /** Controller ID */ 820 uint16_t ctrlr_id; 821 822 /** Version */ 823 uint32_t ver; 824 825 /** RTD3 Resume Latency */ 826 uint32_t rtd3r; 827 828 /** RTD3 Enter Latency */ 829 uint32_t rtd3e; 830 831 /** Optional Asynchronous Events Supported */ 832 uint32_t oaes; /* bitfield really */ 833 834 /** Controller Attributes */ 835 uint32_t ctratt; /* bitfield really */ 836 837 /** Read Recovery Levels Supported */ 838 uint16_t rrls; 839 840 uint8_t reserved1[9]; 841 842 /** Controller Type */ 843 uint8_t cntrltype; 844 845 /** FRU Globally Unique Identifier */ 846 uint8_t fguid[16]; 847 848 /** Command Retry Delay Time 1 */ 849 uint16_t crdt1; 850 851 /** Command Retry Delay Time 2 */ 852 uint16_t crdt2; 853 854 /** Command Retry Delay Time 3 */ 855 uint16_t crdt3; 856 857 uint8_t reserved2[122]; 858 859 /* bytes 256-511: admin command set attributes */ 860 861 /** optional admin command support */ 862 uint16_t oacs; 863 864 /** abort command limit */ 865 uint8_t acl; 866 867 /** asynchronous event request limit */ 868 uint8_t aerl; 869 870 /** firmware updates */ 871 uint8_t frmw; 872 873 /** log page attributes */ 874 uint8_t lpa; 875 876 /** error log page entries */ 877 uint8_t elpe; 878 879 /** number of power states supported */ 880 uint8_t npss; 881 882 /** admin vendor specific command configuration */ 883 uint8_t avscc; 884 885 /** Autonomous Power State Transition Attributes */ 886 uint8_t apsta; 887 888 /** Warning Composite Temperature Threshold */ 889 uint16_t wctemp; 890 891 /** Critical Composite Temperature Threshold */ 892 uint16_t cctemp; 893 894 /** Maximum Time for Firmware Activation */ 895 uint16_t mtfa; 896 897 /** Host Memory Buffer Preferred Size */ 898 uint32_t hmpre; 899 900 /** Host Memory Buffer Minimum Size */ 901 uint32_t hmmin; 902 903 /** Name space capabilities */ 904 struct { 905 /* if nsmgmt, report tnvmcap and unvmcap */ 906 uint8_t tnvmcap[16]; 907 uint8_t unvmcap[16]; 908 } __packed untncap; 909 910 /** Replay Protected Memory Block Support */ 911 uint32_t rpmbs; /* Really a bitfield */ 912 913 /** Extended Device Self-test Time */ 914 uint16_t edstt; 915 916 /** Device Self-test Options */ 917 uint8_t dsto; /* Really a bitfield */ 918 919 /** Firmware Update Granularity */ 920 uint8_t fwug; 921 922 /** Keep Alive Support */ 923 uint16_t kas; 924 925 /** Host Controlled Thermal Management Attributes */ 926 uint16_t hctma; /* Really a bitfield */ 927 928 /** Minimum Thermal Management Temperature */ 929 uint16_t mntmt; 930 931 /** Maximum Thermal Management Temperature */ 932 uint16_t mxtmt; 933 934 /** Sanitize Capabilities */ 935 uint32_t sanicap; /* Really a bitfield */ 936 937 /** Host Memory Buffer Minimum Descriptor Entry Size */ 938 uint32_t hmminds; 939 940 /** Host Memory Maximum Descriptors Entries */ 941 uint16_t hmmaxd; 942 943 /** NVM Set Identifier Maximum */ 944 uint16_t nsetidmax; 945 946 /** Endurance Group Identifier Maximum */ 947 uint16_t endgidmax; 948 949 /** ANA Transition Time */ 950 uint8_t anatt; 951 952 /** Asymmetric Namespace Access Capabilities */ 953 uint8_t anacap; 954 955 /** ANA Group Identifier Maximum */ 956 uint32_t anagrpmax; 957 958 /** Number of ANA Group Identifiers */ 959 uint32_t nanagrpid; 960 961 /** Persistent Event Log Size */ 962 uint32_t pels; 963 964 uint8_t reserved3[156]; 965 /* bytes 512-703: nvm command set attributes */ 966 967 /** submission queue entry size */ 968 uint8_t sqes; 969 970 /** completion queue entry size */ 971 uint8_t cqes; 972 973 /** Maximum Outstanding Commands */ 974 uint16_t maxcmd; 975 976 /** number of namespaces */ 977 uint32_t nn; 978 979 /** optional nvm command support */ 980 uint16_t oncs; 981 982 /** fused operation support */ 983 uint16_t fuses; 984 985 /** format nvm attributes */ 986 uint8_t fna; 987 988 /** volatile write cache */ 989 uint8_t vwc; 990 991 /** Atomic Write Unit Normal */ 992 uint16_t awun; 993 994 /** Atomic Write Unit Power Fail */ 995 uint16_t awupf; 996 997 /** NVM Vendor Specific Command Configuration */ 998 uint8_t nvscc; 999 1000 /** Namespace Write Protection Capabilities */ 1001 uint8_t nwpc; 1002 1003 /** Atomic Compare & Write Unit */ 1004 uint16_t acwu; 1005 uint16_t reserved6; 1006 1007 /** SGL Support */ 1008 uint32_t sgls; 1009 1010 /** Maximum Number of Allowed Namespaces */ 1011 uint32_t mnan; 1012 1013 /* bytes 540-767: Reserved */ 1014 uint8_t reserved7[224]; 1015 1016 /** NVM Subsystem NVMe Qualified Name */ 1017 uint8_t subnqn[256]; 1018 1019 /* bytes 1024-1791: Reserved */ 1020 uint8_t reserved8[768]; 1021 1022 /* bytes 1792-2047: NVMe over Fabrics specification */ 1023 uint8_t reserved9[256]; 1024 1025 /* bytes 2048-3071: power state descriptors */ 1026 struct nvme_power_state power_state[32]; 1027 1028 /* bytes 3072-4095: vendor specific */ 1029 uint8_t vs[1024]; 1030 } __packed __aligned(4); 1031 1032 _Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data"); 1033 1034 struct nvme_namespace_data { 1035 1036 /** namespace size */ 1037 uint64_t nsze; 1038 1039 /** namespace capacity */ 1040 uint64_t ncap; 1041 1042 /** namespace utilization */ 1043 uint64_t nuse; 1044 1045 /** namespace features */ 1046 uint8_t nsfeat; 1047 1048 /** number of lba formats */ 1049 uint8_t nlbaf; 1050 1051 /** formatted lba size */ 1052 uint8_t flbas; 1053 1054 /** metadata capabilities */ 1055 uint8_t mc; 1056 1057 /** end-to-end data protection capabilities */ 1058 uint8_t dpc; 1059 1060 /** end-to-end data protection type settings */ 1061 uint8_t dps; 1062 1063 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */ 1064 uint8_t nmic; 1065 1066 /** Reservation Capabilities */ 1067 uint8_t rescap; 1068 1069 /** Format Progress Indicator */ 1070 uint8_t fpi; 1071 1072 /** Deallocate Logical Block Features */ 1073 uint8_t dlfeat; 1074 1075 /** Namespace Atomic Write Unit Normal */ 1076 uint16_t nawun; 1077 1078 /** Namespace Atomic Write Unit Power Fail */ 1079 uint16_t nawupf; 1080 1081 /** Namespace Atomic Compare & Write Unit */ 1082 uint16_t nacwu; 1083 1084 /** Namespace Atomic Boundary Size Normal */ 1085 uint16_t nabsn; 1086 1087 /** Namespace Atomic Boundary Offset */ 1088 uint16_t nabo; 1089 1090 /** Namespace Atomic Boundary Size Power Fail */ 1091 uint16_t nabspf; 1092 1093 /** Namespace Optimal IO Boundary */ 1094 uint16_t noiob; 1095 1096 /** NVM Capacity */ 1097 uint8_t nvmcap[16]; 1098 1099 /** Namespace Preferred Write Granularity */ 1100 uint16_t npwg; 1101 1102 /** Namespace Preferred Write Alignment */ 1103 uint16_t npwa; 1104 1105 /** Namespace Preferred Deallocate Granularity */ 1106 uint16_t npdg; 1107 1108 /** Namespace Preferred Deallocate Alignment */ 1109 uint16_t npda; 1110 1111 /** Namespace Optimal Write Size */ 1112 uint16_t nows; 1113 1114 /* bytes 74-91: Reserved */ 1115 uint8_t reserved5[18]; 1116 1117 /** ANA Group Identifier */ 1118 uint32_t anagrpid; 1119 1120 /* bytes 96-98: Reserved */ 1121 uint8_t reserved6[3]; 1122 1123 /** Namespace Attributes */ 1124 uint8_t nsattr; 1125 1126 /** NVM Set Identifier */ 1127 uint16_t nvmsetid; 1128 1129 /** Endurance Group Identifier */ 1130 uint16_t endgid; 1131 1132 /** Namespace Globally Unique Identifier */ 1133 uint8_t nguid[16]; 1134 1135 /** IEEE Extended Unique Identifier */ 1136 uint8_t eui64[8]; 1137 1138 /** lba format support */ 1139 uint32_t lbaf[16]; 1140 1141 uint8_t reserved7[192]; 1142 1143 uint8_t vendor_specific[3712]; 1144 } __packed __aligned(4); 1145 1146 _Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data"); 1147 1148 enum nvme_log_page { 1149 1150 /* 0x00 - reserved */ 1151 NVME_LOG_ERROR = 0x01, 1152 NVME_LOG_HEALTH_INFORMATION = 0x02, 1153 NVME_LOG_FIRMWARE_SLOT = 0x03, 1154 NVME_LOG_CHANGED_NAMESPACE = 0x04, 1155 NVME_LOG_COMMAND_EFFECT = 0x05, 1156 /* 0x06-0x7F - reserved */ 1157 /* 0x80-0xBF - I/O command set specific */ 1158 NVME_LOG_RES_NOTIFICATION = 0x80, 1159 /* 0xC0-0xFF - vendor specific */ 1160 1161 /* 1162 * The following are Intel Specific log pages, but they seem 1163 * to be widely implemented. 1164 */ 1165 INTEL_LOG_READ_LAT_LOG = 0xc1, 1166 INTEL_LOG_WRITE_LAT_LOG = 0xc2, 1167 INTEL_LOG_TEMP_STATS = 0xc5, 1168 INTEL_LOG_ADD_SMART = 0xca, 1169 INTEL_LOG_DRIVE_MKT_NAME = 0xdd, 1170 1171 /* 1172 * HGST log page, with lots ofs sub pages. 1173 */ 1174 HGST_INFO_LOG = 0xc1, 1175 }; 1176 1177 struct nvme_error_information_entry { 1178 1179 uint64_t error_count; 1180 uint16_t sqid; 1181 uint16_t cid; 1182 uint16_t status; 1183 uint16_t error_location; 1184 uint64_t lba; 1185 uint32_t nsid; 1186 uint8_t vendor_specific; 1187 uint8_t reserved[35]; 1188 } __packed __aligned(4); 1189 1190 _Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry"); 1191 1192 struct nvme_health_information_page { 1193 1194 uint8_t critical_warning; 1195 uint16_t temperature; 1196 uint8_t available_spare; 1197 uint8_t available_spare_threshold; 1198 uint8_t percentage_used; 1199 1200 uint8_t reserved[26]; 1201 1202 /* 1203 * Note that the following are 128-bit values, but are 1204 * defined as an array of 2 64-bit values. 1205 */ 1206 /* Data Units Read is always in 512-byte units. */ 1207 uint64_t data_units_read[2]; 1208 /* Data Units Written is always in 512-byte units. */ 1209 uint64_t data_units_written[2]; 1210 /* For NVM command set, this includes Compare commands. */ 1211 uint64_t host_read_commands[2]; 1212 uint64_t host_write_commands[2]; 1213 /* Controller Busy Time is reported in minutes. */ 1214 uint64_t controller_busy_time[2]; 1215 uint64_t power_cycles[2]; 1216 uint64_t power_on_hours[2]; 1217 uint64_t unsafe_shutdowns[2]; 1218 uint64_t media_errors[2]; 1219 uint64_t num_error_info_log_entries[2]; 1220 uint32_t warning_temp_time; 1221 uint32_t error_temp_time; 1222 uint16_t temp_sensor[8]; 1223 1224 uint8_t reserved2[296]; 1225 } __packed __aligned(4); 1226 1227 _Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page"); 1228 1229 struct nvme_firmware_page { 1230 1231 uint8_t afi; 1232 uint8_t reserved[7]; 1233 uint64_t revision[7]; /* revisions for 7 slots */ 1234 uint8_t reserved2[448]; 1235 } __packed __aligned(4); 1236 1237 _Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page"); 1238 1239 struct nvme_ns_list { 1240 uint32_t ns[1024]; 1241 } __packed __aligned(4); 1242 1243 _Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list"); 1244 1245 struct intel_log_temp_stats 1246 { 1247 uint64_t current; 1248 uint64_t overtemp_flag_last; 1249 uint64_t overtemp_flag_life; 1250 uint64_t max_temp; 1251 uint64_t min_temp; 1252 uint64_t _rsvd[5]; 1253 uint64_t max_oper_temp; 1254 uint64_t min_oper_temp; 1255 uint64_t est_offset; 1256 } __packed __aligned(4); 1257 1258 _Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats"); 1259 1260 #define NVME_TEST_MAX_THREADS 128 1261 1262 struct nvme_io_test { 1263 1264 enum nvme_nvm_opcode opc; 1265 uint32_t size; 1266 uint32_t time; /* in seconds */ 1267 uint32_t num_threads; 1268 uint32_t flags; 1269 uint64_t io_completed[NVME_TEST_MAX_THREADS]; 1270 }; 1271 1272 enum nvme_io_test_flags { 1273 1274 /* 1275 * Specifies whether dev_refthread/dev_relthread should be 1276 * called during NVME_BIO_TEST. Ignored for other test 1277 * types. 1278 */ 1279 NVME_TEST_FLAG_REFTHREAD = 0x1, 1280 }; 1281 1282 struct nvme_pt_command { 1283 1284 /* 1285 * cmd is used to specify a passthrough command to a controller or 1286 * namespace. 1287 * 1288 * The following fields from cmd may be specified by the caller: 1289 * * opc (opcode) 1290 * * nsid (namespace id) - for admin commands only 1291 * * cdw10-cdw15 1292 * 1293 * Remaining fields must be set to 0 by the caller. 1294 */ 1295 struct nvme_command cmd; 1296 1297 /* 1298 * cpl returns completion status for the passthrough command 1299 * specified by cmd. 1300 * 1301 * The following fields will be filled out by the driver, for 1302 * consumption by the caller: 1303 * * cdw0 1304 * * status (except for phase) 1305 * 1306 * Remaining fields will be set to 0 by the driver. 1307 */ 1308 struct nvme_completion cpl; 1309 1310 /* buf is the data buffer associated with this passthrough command. */ 1311 void * buf; 1312 1313 /* 1314 * len is the length of the data buffer associated with this 1315 * passthrough command. 1316 */ 1317 uint32_t len; 1318 1319 /* 1320 * is_read = 1 if the passthrough command will read data into the 1321 * supplied buffer from the controller. 1322 * 1323 * is_read = 0 if the passthrough command will write data from the 1324 * supplied buffer to the controller. 1325 */ 1326 uint32_t is_read; 1327 1328 /* 1329 * driver_lock is used by the driver only. It must be set to 0 1330 * by the caller. 1331 */ 1332 struct mtx * driver_lock; 1333 }; 1334 1335 #define nvme_completion_is_error(cpl) \ 1336 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0) 1337 1338 void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen); 1339 1340 #ifdef _KERNEL 1341 1342 struct bio; 1343 1344 struct nvme_namespace; 1345 struct nvme_controller; 1346 struct nvme_consumer; 1347 1348 typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *); 1349 1350 typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *); 1351 typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *); 1352 typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *, 1353 uint32_t, void *, uint32_t); 1354 typedef void (*nvme_cons_fail_fn_t)(void *); 1355 1356 enum nvme_namespace_flags { 1357 NVME_NS_DEALLOCATE_SUPPORTED = 0x1, 1358 NVME_NS_FLUSH_SUPPORTED = 0x2, 1359 }; 1360 1361 int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr, 1362 struct nvme_pt_command *pt, 1363 uint32_t nsid, int is_user_buffer, 1364 int is_admin_cmd); 1365 1366 /* Admin functions */ 1367 void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr, 1368 uint8_t feature, uint32_t cdw11, 1369 void *payload, uint32_t payload_size, 1370 nvme_cb_fn_t cb_fn, void *cb_arg); 1371 void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr, 1372 uint8_t feature, uint32_t cdw11, 1373 void *payload, uint32_t payload_size, 1374 nvme_cb_fn_t cb_fn, void *cb_arg); 1375 void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr, 1376 uint8_t log_page, uint32_t nsid, 1377 void *payload, uint32_t payload_size, 1378 nvme_cb_fn_t cb_fn, void *cb_arg); 1379 1380 /* NVM I/O functions */ 1381 int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload, 1382 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1383 void *cb_arg); 1384 int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp, 1385 nvme_cb_fn_t cb_fn, void *cb_arg); 1386 int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload, 1387 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn, 1388 void *cb_arg); 1389 int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp, 1390 nvme_cb_fn_t cb_fn, void *cb_arg); 1391 int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload, 1392 uint8_t num_ranges, nvme_cb_fn_t cb_fn, 1393 void *cb_arg); 1394 int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn, 1395 void *cb_arg); 1396 int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset, 1397 size_t len); 1398 1399 /* Registration functions */ 1400 struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn, 1401 nvme_cons_ctrlr_fn_t ctrlr_fn, 1402 nvme_cons_async_fn_t async_fn, 1403 nvme_cons_fail_fn_t fail_fn); 1404 void nvme_unregister_consumer(struct nvme_consumer *consumer); 1405 1406 /* Controller helper functions */ 1407 device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr); 1408 const struct nvme_controller_data * 1409 nvme_ctrlr_get_data(struct nvme_controller *ctrlr); 1410 static inline bool 1411 nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd) 1412 { 1413 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */ 1414 return ((cd->oncs >> NVME_CTRLR_DATA_ONCS_DSM_SHIFT) & 1415 NVME_CTRLR_DATA_ONCS_DSM_MASK); 1416 } 1417 1418 /* Namespace helper functions */ 1419 uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns); 1420 uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns); 1421 uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns); 1422 uint64_t nvme_ns_get_size(struct nvme_namespace *ns); 1423 uint32_t nvme_ns_get_flags(struct nvme_namespace *ns); 1424 const char * nvme_ns_get_serial_number(struct nvme_namespace *ns); 1425 const char * nvme_ns_get_model_number(struct nvme_namespace *ns); 1426 const struct nvme_namespace_data * 1427 nvme_ns_get_data(struct nvme_namespace *ns); 1428 uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns); 1429 1430 int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp, 1431 nvme_cb_fn_t cb_fn); 1432 1433 /* 1434 * Command building helper functions -- shared with CAM 1435 * These functions assume allocator zeros out cmd structure 1436 * CAM's xpt_get_ccb and the request allocator for nvme both 1437 * do zero'd allocations. 1438 */ 1439 static inline 1440 void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid) 1441 { 1442 1443 cmd->opc = NVME_OPC_FLUSH; 1444 cmd->nsid = htole32(nsid); 1445 } 1446 1447 static inline 1448 void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid, 1449 uint64_t lba, uint32_t count) 1450 { 1451 cmd->opc = rwcmd; 1452 cmd->nsid = htole32(nsid); 1453 cmd->cdw10 = htole32(lba & 0xffffffffu); 1454 cmd->cdw11 = htole32(lba >> 32); 1455 cmd->cdw12 = htole32(count-1); 1456 } 1457 1458 static inline 1459 void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid, 1460 uint64_t lba, uint32_t count) 1461 { 1462 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count); 1463 } 1464 1465 static inline 1466 void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid, 1467 uint64_t lba, uint32_t count) 1468 { 1469 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count); 1470 } 1471 1472 static inline 1473 void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid, 1474 uint32_t num_ranges) 1475 { 1476 cmd->opc = NVME_OPC_DATASET_MANAGEMENT; 1477 cmd->nsid = htole32(nsid); 1478 cmd->cdw10 = htole32(num_ranges - 1); 1479 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE); 1480 } 1481 1482 extern int nvme_use_nvd; 1483 1484 #endif /* _KERNEL */ 1485 1486 /* Endianess conversion functions for NVMe structs */ 1487 static inline 1488 void nvme_completion_swapbytes(struct nvme_completion *s) 1489 { 1490 1491 s->cdw0 = le32toh(s->cdw0); 1492 /* omit rsvd1 */ 1493 s->sqhd = le16toh(s->sqhd); 1494 s->sqid = le16toh(s->sqid); 1495 /* omit cid */ 1496 s->status = le16toh(s->status); 1497 } 1498 1499 static inline 1500 void nvme_power_state_swapbytes(struct nvme_power_state *s) 1501 { 1502 1503 s->mp = le16toh(s->mp); 1504 s->enlat = le32toh(s->enlat); 1505 s->exlat = le32toh(s->exlat); 1506 s->idlp = le16toh(s->idlp); 1507 s->actp = le16toh(s->actp); 1508 } 1509 1510 static inline 1511 void nvme_controller_data_swapbytes(struct nvme_controller_data *s) 1512 { 1513 int i; 1514 1515 s->vid = le16toh(s->vid); 1516 s->ssvid = le16toh(s->ssvid); 1517 s->ctrlr_id = le16toh(s->ctrlr_id); 1518 s->ver = le32toh(s->ver); 1519 s->rtd3r = le32toh(s->rtd3r); 1520 s->rtd3e = le32toh(s->rtd3e); 1521 s->oaes = le32toh(s->oaes); 1522 s->ctratt = le32toh(s->ctratt); 1523 s->rrls = le16toh(s->rrls); 1524 s->crdt1 = le16toh(s->crdt1); 1525 s->crdt2 = le16toh(s->crdt2); 1526 s->crdt3 = le16toh(s->crdt3); 1527 s->oacs = le16toh(s->oacs); 1528 s->wctemp = le16toh(s->wctemp); 1529 s->cctemp = le16toh(s->cctemp); 1530 s->mtfa = le16toh(s->mtfa); 1531 s->hmpre = le32toh(s->hmpre); 1532 s->hmmin = le32toh(s->hmmin); 1533 s->rpmbs = le32toh(s->rpmbs); 1534 s->edstt = le16toh(s->edstt); 1535 s->kas = le16toh(s->kas); 1536 s->hctma = le16toh(s->hctma); 1537 s->mntmt = le16toh(s->mntmt); 1538 s->mxtmt = le16toh(s->mxtmt); 1539 s->sanicap = le32toh(s->sanicap); 1540 s->hmminds = le32toh(s->hmminds); 1541 s->hmmaxd = le16toh(s->hmmaxd); 1542 s->nsetidmax = le16toh(s->nsetidmax); 1543 s->endgidmax = le16toh(s->endgidmax); 1544 s->anagrpmax = le32toh(s->anagrpmax); 1545 s->nanagrpid = le32toh(s->nanagrpid); 1546 s->pels = le32toh(s->pels); 1547 s->maxcmd = le16toh(s->maxcmd); 1548 s->nn = le32toh(s->nn); 1549 s->oncs = le16toh(s->oncs); 1550 s->fuses = le16toh(s->fuses); 1551 s->awun = le16toh(s->awun); 1552 s->awupf = le16toh(s->awupf); 1553 s->acwu = le16toh(s->acwu); 1554 s->sgls = le32toh(s->sgls); 1555 s->mnan = le32toh(s->mnan); 1556 for (i = 0; i < 32; i++) 1557 nvme_power_state_swapbytes(&s->power_state[i]); 1558 } 1559 1560 static inline 1561 void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s) 1562 { 1563 int i; 1564 1565 s->nsze = le64toh(s->nsze); 1566 s->ncap = le64toh(s->ncap); 1567 s->nuse = le64toh(s->nuse); 1568 s->nawun = le16toh(s->nawun); 1569 s->nawupf = le16toh(s->nawupf); 1570 s->nacwu = le16toh(s->nacwu); 1571 s->nabsn = le16toh(s->nabsn); 1572 s->nabo = le16toh(s->nabo); 1573 s->nabspf = le16toh(s->nabspf); 1574 s->noiob = le16toh(s->noiob); 1575 s->npwg = le16toh(s->npwg); 1576 s->npwa = le16toh(s->npwa); 1577 s->npdg = le16toh(s->npdg); 1578 s->npda = le16toh(s->npda); 1579 s->nows = le16toh(s->nows); 1580 s->anagrpid = le32toh(s->anagrpid); 1581 s->nvmsetid = le16toh(s->nvmsetid); 1582 s->endgid = le16toh(s->endgid); 1583 for (i = 0; i < 16; i++) 1584 s->lbaf[i] = le32toh(s->lbaf[i]); 1585 } 1586 1587 static inline 1588 void nvme_error_information_entry_swapbytes(struct nvme_error_information_entry *s) 1589 { 1590 1591 s->error_count = le64toh(s->error_count); 1592 s->sqid = le16toh(s->sqid); 1593 s->cid = le16toh(s->cid); 1594 s->status = le16toh(s->status); 1595 s->error_location = le16toh(s->error_location); 1596 s->lba = le64toh(s->lba); 1597 s->nsid = le32toh(s->nsid); 1598 } 1599 1600 static inline 1601 void nvme_le128toh(void *p) 1602 { 1603 #if _BYTE_ORDER != _LITTLE_ENDIAN 1604 /* Swap 16 bytes in place */ 1605 char *tmp = (char*)p; 1606 char b; 1607 int i; 1608 for (i = 0; i < 8; i++) { 1609 b = tmp[i]; 1610 tmp[i] = tmp[15-i]; 1611 tmp[15-i] = b; 1612 } 1613 #else 1614 (void)p; 1615 #endif 1616 } 1617 1618 static inline 1619 void nvme_health_information_page_swapbytes(struct nvme_health_information_page *s) 1620 { 1621 int i; 1622 1623 s->temperature = le16toh(s->temperature); 1624 nvme_le128toh((void *)s->data_units_read); 1625 nvme_le128toh((void *)s->data_units_written); 1626 nvme_le128toh((void *)s->host_read_commands); 1627 nvme_le128toh((void *)s->host_write_commands); 1628 nvme_le128toh((void *)s->controller_busy_time); 1629 nvme_le128toh((void *)s->power_cycles); 1630 nvme_le128toh((void *)s->power_on_hours); 1631 nvme_le128toh((void *)s->unsafe_shutdowns); 1632 nvme_le128toh((void *)s->media_errors); 1633 nvme_le128toh((void *)s->num_error_info_log_entries); 1634 s->warning_temp_time = le32toh(s->warning_temp_time); 1635 s->error_temp_time = le32toh(s->error_temp_time); 1636 for (i = 0; i < 8; i++) 1637 s->temp_sensor[i] = le16toh(s->temp_sensor[i]); 1638 } 1639 1640 1641 static inline 1642 void nvme_firmware_page_swapbytes(struct nvme_firmware_page *s) 1643 { 1644 int i; 1645 1646 for (i = 0; i < 7; i++) 1647 s->revision[i] = le64toh(s->revision[i]); 1648 } 1649 1650 static inline 1651 void nvme_ns_list_swapbytes(struct nvme_ns_list *s) 1652 { 1653 int i; 1654 1655 for (i = 0; i < 1024; i++) 1656 s->ns[i] = le32toh(s->ns[i]); 1657 } 1658 1659 static inline 1660 void intel_log_temp_stats_swapbytes(struct intel_log_temp_stats *s) 1661 { 1662 1663 s->current = le64toh(s->current); 1664 s->overtemp_flag_last = le64toh(s->overtemp_flag_last); 1665 s->overtemp_flag_life = le64toh(s->overtemp_flag_life); 1666 s->max_temp = le64toh(s->max_temp); 1667 s->min_temp = le64toh(s->min_temp); 1668 /* omit _rsvd[] */ 1669 s->max_oper_temp = le64toh(s->max_oper_temp); 1670 s->min_oper_temp = le64toh(s->min_oper_temp); 1671 s->est_offset = le64toh(s->est_offset); 1672 } 1673 1674 #endif /* __NVME_H__ */ 1675