1 /*- 2 * Copyright (c) 2016-2017 Alexander Motin <mav@FreeBSD.org> 3 * Copyright (C) 2013 Intel Corporation 4 * Copyright (C) 2015 EMC Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * The Non-Transparent Bridge (NTB) is a device that allows you to connect 31 * two or more systems using a PCI-e links, providing remote memory access. 32 * 33 * This module contains a driver for NTB hardware in Intel Xeon/Atom CPUs. 34 * 35 * NOTE: Much of the code in this module is shared with Linux. Any patches may 36 * be picked up and redistributed in Linux with a dual GPL/BSD license. 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/kernel.h> 44 #include <sys/systm.h> 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/interrupt.h> 48 #include <sys/lock.h> 49 #include <sys/malloc.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/pciio.h> 53 #include <sys/taskqueue.h> 54 #include <sys/tree.h> 55 #include <sys/queue.h> 56 #include <sys/rman.h> 57 #include <sys/sbuf.h> 58 #include <sys/sysctl.h> 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 #include <machine/bus.h> 62 #include <machine/intr_machdep.h> 63 #include <machine/resource.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/iommu/iommu.h> 67 68 #include "ntb_hw_intel.h" 69 #include "../ntb.h" 70 71 #define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT) 72 73 #define NTB_HB_TIMEOUT 1 /* second */ 74 #define ATOM_LINK_RECOVERY_TIME 500 /* ms */ 75 #define BAR_HIGH_MASK (~((1ull << 12) - 1)) 76 77 #define NTB_MSIX_VER_GUARD 0xaabbccdd 78 #define NTB_MSIX_RECEIVED 0xe0f0e0f0 79 80 /* 81 * PCI constants could be somewhere more generic, but aren't defined/used in 82 * pci.c. 83 */ 84 #define PCI_MSIX_ENTRY_SIZE 16 85 #define PCI_MSIX_ENTRY_LOWER_ADDR 0 86 #define PCI_MSIX_ENTRY_UPPER_ADDR 4 87 #define PCI_MSIX_ENTRY_DATA 8 88 89 enum ntb_device_type { 90 NTB_XEON, 91 NTB_ATOM 92 }; 93 94 /* ntb_conn_type are hardware numbers, cannot change. */ 95 enum ntb_conn_type { 96 NTB_CONN_TRANSPARENT = 0, 97 NTB_CONN_B2B = 1, 98 NTB_CONN_RP = 2, 99 }; 100 101 enum ntb_b2b_direction { 102 NTB_DEV_USD = 0, 103 NTB_DEV_DSD = 1, 104 }; 105 106 enum ntb_bar { 107 NTB_CONFIG_BAR = 0, 108 NTB_B2B_BAR_1, 109 NTB_B2B_BAR_2, 110 NTB_B2B_BAR_3, 111 NTB_MAX_BARS 112 }; 113 114 enum { 115 NTB_MSIX_GUARD = 0, 116 NTB_MSIX_DATA0, 117 NTB_MSIX_DATA1, 118 NTB_MSIX_DATA2, 119 NTB_MSIX_OFS0, 120 NTB_MSIX_OFS1, 121 NTB_MSIX_OFS2, 122 NTB_MSIX_DONE, 123 NTB_MAX_MSIX_SPAD 124 }; 125 126 /* Device features and workarounds */ 127 #define HAS_FEATURE(ntb, feature) \ 128 (((ntb)->features & (feature)) != 0) 129 130 struct ntb_hw_info { 131 uint32_t device_id; 132 const char *desc; 133 enum ntb_device_type type; 134 uint32_t features; 135 }; 136 137 struct ntb_pci_bar_info { 138 bus_space_tag_t pci_bus_tag; 139 bus_space_handle_t pci_bus_handle; 140 int pci_resource_id; 141 struct resource *pci_resource; 142 vm_paddr_t pbase; 143 caddr_t vbase; 144 vm_size_t size; 145 vm_memattr_t map_mode; 146 147 /* Configuration register offsets */ 148 uint32_t psz_off; 149 uint32_t ssz_off; 150 uint32_t pbarxlat_off; 151 }; 152 153 struct ntb_int_info { 154 struct resource *res; 155 int rid; 156 void *tag; 157 }; 158 159 struct ntb_vec { 160 struct ntb_softc *ntb; 161 uint32_t num; 162 unsigned masked; 163 }; 164 165 struct ntb_reg { 166 uint32_t ntb_ctl; 167 uint32_t lnk_sta; 168 uint8_t db_size; 169 unsigned mw_bar[NTB_MAX_BARS]; 170 }; 171 172 struct ntb_alt_reg { 173 uint32_t db_bell; 174 uint32_t db_mask; 175 uint32_t spad; 176 }; 177 178 struct ntb_xlat_reg { 179 uint32_t bar0_base; 180 uint32_t bar2_base; 181 uint32_t bar4_base; 182 uint32_t bar5_base; 183 184 uint32_t bar2_xlat; 185 uint32_t bar4_xlat; 186 uint32_t bar5_xlat; 187 188 uint32_t bar2_limit; 189 uint32_t bar4_limit; 190 uint32_t bar5_limit; 191 }; 192 193 struct ntb_b2b_addr { 194 uint64_t bar0_addr; 195 uint64_t bar2_addr64; 196 uint64_t bar4_addr64; 197 uint64_t bar4_addr32; 198 uint64_t bar5_addr32; 199 }; 200 201 struct ntb_msix_data { 202 uint32_t nmd_ofs; 203 uint32_t nmd_data; 204 }; 205 206 struct ntb_softc { 207 /* ntb.c context. Do not move! Must go first! */ 208 void *ntb_store; 209 210 device_t device; 211 enum ntb_device_type type; 212 uint32_t features; 213 214 struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 215 struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 216 uint32_t allocated_interrupts; 217 218 struct ntb_msix_data peer_msix_data[XEON_NONLINK_DB_MSIX_BITS]; 219 struct ntb_msix_data msix_data[XEON_NONLINK_DB_MSIX_BITS]; 220 bool peer_msix_good; 221 bool peer_msix_done; 222 struct ntb_pci_bar_info *peer_lapic_bar; 223 struct callout peer_msix_work; 224 225 bus_dma_tag_t bar0_dma_tag; 226 bus_dmamap_t bar0_dma_map; 227 228 struct callout heartbeat_timer; 229 struct callout lr_timer; 230 231 struct ntb_vec *msix_vec; 232 233 uint32_t ppd; 234 enum ntb_conn_type conn_type; 235 enum ntb_b2b_direction dev_type; 236 237 /* Offset of peer bar0 in B2B BAR */ 238 uint64_t b2b_off; 239 /* Memory window used to access peer bar0 */ 240 #define B2B_MW_DISABLED UINT8_MAX 241 uint8_t b2b_mw_idx; 242 uint32_t msix_xlat; 243 uint8_t msix_mw_idx; 244 245 uint8_t mw_count; 246 uint8_t spad_count; 247 uint8_t db_count; 248 uint8_t db_vec_count; 249 uint8_t db_vec_shift; 250 251 /* Protects local db_mask. */ 252 #define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 253 #define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 254 #define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) 255 struct mtx db_mask_lock; 256 257 volatile uint32_t ntb_ctl; 258 volatile uint32_t lnk_sta; 259 260 uint64_t db_valid_mask; 261 uint64_t db_link_mask; 262 uint64_t db_mask; 263 uint64_t fake_db; /* NTB_SB01BASE_LOCKUP*/ 264 uint64_t force_db; /* NTB_SB01BASE_LOCKUP*/ 265 266 int last_ts; /* ticks @ last irq */ 267 268 const struct ntb_reg *reg; 269 const struct ntb_alt_reg *self_reg; 270 const struct ntb_alt_reg *peer_reg; 271 const struct ntb_xlat_reg *xlat_reg; 272 }; 273 274 #ifdef __i386__ 275 static __inline uint64_t 276 bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 277 bus_size_t offset) 278 { 279 280 return (bus_space_read_4(tag, handle, offset) | 281 ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); 282 } 283 284 static __inline void 285 bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, 286 bus_size_t offset, uint64_t val) 287 { 288 289 bus_space_write_4(tag, handle, offset, val); 290 bus_space_write_4(tag, handle, offset + 4, val >> 32); 291 } 292 #endif 293 294 #define intel_ntb_bar_read(SIZE, bar, offset) \ 295 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 296 ntb->bar_info[(bar)].pci_bus_handle, (offset)) 297 #define intel_ntb_bar_write(SIZE, bar, offset, val) \ 298 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 299 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 300 #define intel_ntb_reg_read(SIZE, offset) \ 301 intel_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 302 #define intel_ntb_reg_write(SIZE, offset, val) \ 303 intel_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 304 #define intel_ntb_mw_read(SIZE, offset) \ 305 intel_ntb_bar_read(SIZE, intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 306 offset) 307 #define intel_ntb_mw_write(SIZE, offset, val) \ 308 intel_ntb_bar_write(SIZE, intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 309 offset, val) 310 311 static int intel_ntb_probe(device_t device); 312 static int intel_ntb_attach(device_t device); 313 static int intel_ntb_detach(device_t device); 314 static uint64_t intel_ntb_db_valid_mask(device_t dev); 315 static void intel_ntb_spad_clear(device_t dev); 316 static uint64_t intel_ntb_db_vector_mask(device_t dev, uint32_t vector); 317 static bool intel_ntb_link_is_up(device_t dev, enum ntb_speed *speed, 318 enum ntb_width *width); 319 static int intel_ntb_link_enable(device_t dev, enum ntb_speed speed, 320 enum ntb_width width); 321 static int intel_ntb_link_disable(device_t dev); 322 static int intel_ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val); 323 static int intel_ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val); 324 325 static unsigned intel_ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx); 326 static inline enum ntb_bar intel_ntb_mw_to_bar(struct ntb_softc *, unsigned mw); 327 static inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); 328 static inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, 329 uint32_t *base, uint32_t *xlat, uint32_t *lmt); 330 static int intel_ntb_map_pci_bars(struct ntb_softc *ntb); 331 static int intel_ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx, 332 vm_memattr_t); 333 static void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, 334 const char *); 335 static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 336 static int map_memory_window_bar(struct ntb_softc *ntb, 337 struct ntb_pci_bar_info *bar); 338 static void intel_ntb_unmap_pci_bar(struct ntb_softc *ntb); 339 static int intel_ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); 340 static int intel_ntb_init_isr(struct ntb_softc *ntb); 341 static int intel_ntb_setup_legacy_interrupt(struct ntb_softc *ntb); 342 static int intel_ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); 343 static void intel_ntb_teardown_interrupts(struct ntb_softc *ntb); 344 static inline uint64_t intel_ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); 345 static void intel_ntb_interrupt(struct ntb_softc *, uint32_t vec); 346 static void ndev_vec_isr(void *arg); 347 static void ndev_irq_isr(void *arg); 348 static inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); 349 static inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); 350 static inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); 351 static int intel_ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); 352 static void intel_ntb_free_msix_vec(struct ntb_softc *ntb); 353 static void intel_ntb_get_msix_info(struct ntb_softc *ntb); 354 static void intel_ntb_exchange_msix(void *); 355 static struct ntb_hw_info *intel_ntb_get_device_info(uint32_t device_id); 356 static void intel_ntb_detect_max_mw(struct ntb_softc *ntb); 357 static int intel_ntb_detect_xeon(struct ntb_softc *ntb); 358 static int intel_ntb_detect_atom(struct ntb_softc *ntb); 359 static int intel_ntb_xeon_init_dev(struct ntb_softc *ntb); 360 static int intel_ntb_atom_init_dev(struct ntb_softc *ntb); 361 static void intel_ntb_teardown_xeon(struct ntb_softc *ntb); 362 static void configure_atom_secondary_side_bars(struct ntb_softc *ntb); 363 static void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, 364 enum ntb_bar regbar); 365 static void xeon_set_sbar_base_and_limit(struct ntb_softc *, 366 uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); 367 static void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, 368 enum ntb_bar idx); 369 static int xeon_setup_b2b_mw(struct ntb_softc *, 370 const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); 371 static inline bool link_is_up(struct ntb_softc *ntb); 372 static inline bool _xeon_link_is_up(struct ntb_softc *ntb); 373 static inline bool atom_link_is_err(struct ntb_softc *ntb); 374 static inline enum ntb_speed intel_ntb_link_sta_speed(struct ntb_softc *); 375 static inline enum ntb_width intel_ntb_link_sta_width(struct ntb_softc *); 376 static void atom_link_hb(void *arg); 377 static void recover_atom_link(void *arg); 378 static bool intel_ntb_poll_link(struct ntb_softc *ntb); 379 static void save_bar_parameters(struct ntb_pci_bar_info *bar); 380 static void intel_ntb_sysctl_init(struct ntb_softc *); 381 static int sysctl_handle_features(SYSCTL_HANDLER_ARGS); 382 static int sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS); 383 static int sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS); 384 static int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); 385 static int sysctl_handle_register(SYSCTL_HANDLER_ARGS); 386 387 static unsigned g_ntb_hw_debug_level; 388 SYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, 389 &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose"); 390 #define intel_ntb_printf(lvl, ...) do { \ 391 if ((lvl) <= g_ntb_hw_debug_level) { \ 392 device_printf(ntb->device, __VA_ARGS__); \ 393 } \ 394 } while (0) 395 396 #define _NTB_PAT_UC 0 397 #define _NTB_PAT_WC 1 398 #define _NTB_PAT_WT 4 399 #define _NTB_PAT_WP 5 400 #define _NTB_PAT_WB 6 401 #define _NTB_PAT_UCM 7 402 static unsigned g_ntb_mw_pat = _NTB_PAT_UC; 403 SYSCTL_UINT(_hw_ntb, OID_AUTO, default_mw_pat, CTLFLAG_RDTUN, 404 &g_ntb_mw_pat, 0, "Configure the default memory window cache flags (PAT): " 405 "UC: " __XSTRING(_NTB_PAT_UC) ", " 406 "WC: " __XSTRING(_NTB_PAT_WC) ", " 407 "WT: " __XSTRING(_NTB_PAT_WT) ", " 408 "WP: " __XSTRING(_NTB_PAT_WP) ", " 409 "WB: " __XSTRING(_NTB_PAT_WB) ", " 410 "UC-: " __XSTRING(_NTB_PAT_UCM)); 411 412 static inline vm_memattr_t 413 intel_ntb_pat_flags(void) 414 { 415 416 switch (g_ntb_mw_pat) { 417 case _NTB_PAT_WC: 418 return (VM_MEMATTR_WRITE_COMBINING); 419 case _NTB_PAT_WT: 420 return (VM_MEMATTR_WRITE_THROUGH); 421 case _NTB_PAT_WP: 422 return (VM_MEMATTR_WRITE_PROTECTED); 423 case _NTB_PAT_WB: 424 return (VM_MEMATTR_WRITE_BACK); 425 case _NTB_PAT_UCM: 426 return (VM_MEMATTR_WEAK_UNCACHEABLE); 427 case _NTB_PAT_UC: 428 /* FALLTHROUGH */ 429 default: 430 return (VM_MEMATTR_UNCACHEABLE); 431 } 432 } 433 434 /* 435 * Well, this obviously doesn't belong here, but it doesn't seem to exist 436 * anywhere better yet. 437 */ 438 static inline const char * 439 intel_ntb_vm_memattr_to_str(vm_memattr_t pat) 440 { 441 442 switch (pat) { 443 case VM_MEMATTR_WRITE_COMBINING: 444 return ("WRITE_COMBINING"); 445 case VM_MEMATTR_WRITE_THROUGH: 446 return ("WRITE_THROUGH"); 447 case VM_MEMATTR_WRITE_PROTECTED: 448 return ("WRITE_PROTECTED"); 449 case VM_MEMATTR_WRITE_BACK: 450 return ("WRITE_BACK"); 451 case VM_MEMATTR_WEAK_UNCACHEABLE: 452 return ("UNCACHED"); 453 case VM_MEMATTR_UNCACHEABLE: 454 return ("UNCACHEABLE"); 455 default: 456 return ("UNKNOWN"); 457 } 458 } 459 460 static int g_ntb_msix_idx = 1; 461 SYSCTL_INT(_hw_ntb, OID_AUTO, msix_mw_idx, CTLFLAG_RDTUN, &g_ntb_msix_idx, 462 0, "Use this memory window to access the peer MSIX message complex on " 463 "certain Xeon-based NTB systems, as a workaround for a hardware errata. " 464 "Like b2b_mw_idx, negative values index from the last available memory " 465 "window. (Applies on Xeon platforms with SB01BASE_LOCKUP errata.)"); 466 467 static int g_ntb_mw_idx = -1; 468 SYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx, 469 0, "Use this memory window to access the peer NTB registers. A " 470 "non-negative value starts from the first MW index; a negative value " 471 "starts from the last MW index. The default is -1, i.e., the last " 472 "available memory window. Both sides of the NTB MUST set the same " 473 "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)"); 474 475 /* Hardware owns the low 16 bits of features. */ 476 #define NTB_BAR_SIZE_4K (1 << 0) 477 #define NTB_SDOORBELL_LOCKUP (1 << 1) 478 #define NTB_SB01BASE_LOCKUP (1 << 2) 479 #define NTB_B2BDOORBELL_BIT14 (1 << 3) 480 /* Software/configuration owns the top 16 bits. */ 481 #define NTB_SPLIT_BAR (1ull << 16) 482 483 #define NTB_FEATURES_STR \ 484 "\20\21SPLIT_BAR4\04B2B_DOORBELL_BIT14\03SB01BASE_LOCKUP" \ 485 "\02SDOORBELL_LOCKUP\01BAR_SIZE_4K" 486 487 static struct ntb_hw_info pci_ids[] = { 488 /* XXX: PS/SS IDs left out until they are supported. */ 489 { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", 490 NTB_ATOM, 0 }, 491 492 { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", 493 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 494 { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", 495 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 496 { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, 497 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 498 NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, 499 { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON, 500 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 501 NTB_SB01BASE_LOCKUP }, 502 { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON, 503 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 504 NTB_SB01BASE_LOCKUP }, 505 }; 506 507 static const struct ntb_reg atom_reg = { 508 .ntb_ctl = ATOM_NTBCNTL_OFFSET, 509 .lnk_sta = ATOM_LINK_STATUS_OFFSET, 510 .db_size = sizeof(uint64_t), 511 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 512 }; 513 514 static const struct ntb_alt_reg atom_pri_reg = { 515 .db_bell = ATOM_PDOORBELL_OFFSET, 516 .db_mask = ATOM_PDBMSK_OFFSET, 517 .spad = ATOM_SPAD_OFFSET, 518 }; 519 520 static const struct ntb_alt_reg atom_b2b_reg = { 521 .db_bell = ATOM_B2B_DOORBELL_OFFSET, 522 .spad = ATOM_B2B_SPAD_OFFSET, 523 }; 524 525 static const struct ntb_xlat_reg atom_sec_xlat = { 526 #if 0 527 /* "FIXME" says the Linux driver. */ 528 .bar0_base = ATOM_SBAR0BASE_OFFSET, 529 .bar2_base = ATOM_SBAR2BASE_OFFSET, 530 .bar4_base = ATOM_SBAR4BASE_OFFSET, 531 532 .bar2_limit = ATOM_SBAR2LMT_OFFSET, 533 .bar4_limit = ATOM_SBAR4LMT_OFFSET, 534 #endif 535 536 .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, 537 .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, 538 }; 539 540 static const struct ntb_reg xeon_reg = { 541 .ntb_ctl = XEON_NTBCNTL_OFFSET, 542 .lnk_sta = XEON_LINK_STATUS_OFFSET, 543 .db_size = sizeof(uint16_t), 544 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, 545 }; 546 547 static const struct ntb_alt_reg xeon_pri_reg = { 548 .db_bell = XEON_PDOORBELL_OFFSET, 549 .db_mask = XEON_PDBMSK_OFFSET, 550 .spad = XEON_SPAD_OFFSET, 551 }; 552 553 static const struct ntb_alt_reg xeon_b2b_reg = { 554 .db_bell = XEON_B2B_DOORBELL_OFFSET, 555 .spad = XEON_B2B_SPAD_OFFSET, 556 }; 557 558 static const struct ntb_xlat_reg xeon_sec_xlat = { 559 .bar0_base = XEON_SBAR0BASE_OFFSET, 560 .bar2_base = XEON_SBAR2BASE_OFFSET, 561 .bar4_base = XEON_SBAR4BASE_OFFSET, 562 .bar5_base = XEON_SBAR5BASE_OFFSET, 563 564 .bar2_limit = XEON_SBAR2LMT_OFFSET, 565 .bar4_limit = XEON_SBAR4LMT_OFFSET, 566 .bar5_limit = XEON_SBAR5LMT_OFFSET, 567 568 .bar2_xlat = XEON_SBAR2XLAT_OFFSET, 569 .bar4_xlat = XEON_SBAR4XLAT_OFFSET, 570 .bar5_xlat = XEON_SBAR5XLAT_OFFSET, 571 }; 572 573 static struct ntb_b2b_addr xeon_b2b_usd_addr = { 574 .bar0_addr = XEON_B2B_BAR0_ADDR, 575 .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 576 .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 577 .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 578 .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 579 }; 580 581 static struct ntb_b2b_addr xeon_b2b_dsd_addr = { 582 .bar0_addr = XEON_B2B_BAR0_ADDR, 583 .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 584 .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 585 .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 586 .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 587 }; 588 589 SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 590 "B2B MW segment overrides -- MUST be the same on both sides"); 591 592 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, 593 &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 594 "hardware, use this 64-bit address on the bus between the NTB devices for " 595 "the window at BAR2, on the upstream side of the link. MUST be the same " 596 "address on both sides."); 597 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, 598 &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); 599 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, 600 &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " 601 "(split-BAR mode)."); 602 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, 603 &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " 604 "(split-BAR mode)."); 605 606 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, 607 &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 608 "hardware, use this 64-bit address on the bus between the NTB devices for " 609 "the window at BAR2, on the downstream side of the link. MUST be the same" 610 " address on both sides."); 611 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, 612 &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); 613 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, 614 &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " 615 "(split-BAR mode)."); 616 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, 617 &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " 618 "(split-BAR mode)."); 619 620 /* 621 * OS <-> Driver interface structures 622 */ 623 MALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 624 625 /* 626 * OS <-> Driver linkage functions 627 */ 628 static int 629 intel_ntb_probe(device_t device) 630 { 631 struct ntb_hw_info *p; 632 633 p = intel_ntb_get_device_info(pci_get_devid(device)); 634 if (p == NULL) 635 return (ENXIO); 636 637 device_set_desc(device, p->desc); 638 return (0); 639 } 640 641 static int 642 intel_ntb_attach(device_t device) 643 { 644 struct ntb_softc *ntb; 645 struct ntb_hw_info *p; 646 int error; 647 648 ntb = device_get_softc(device); 649 p = intel_ntb_get_device_info(pci_get_devid(device)); 650 651 ntb->device = device; 652 ntb->type = p->type; 653 ntb->features = p->features; 654 ntb->b2b_mw_idx = B2B_MW_DISABLED; 655 ntb->msix_mw_idx = B2B_MW_DISABLED; 656 657 /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ 658 callout_init(&ntb->heartbeat_timer, 1); 659 callout_init(&ntb->lr_timer, 1); 660 callout_init(&ntb->peer_msix_work, 1); 661 mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); 662 663 if (ntb->type == NTB_ATOM) 664 error = intel_ntb_detect_atom(ntb); 665 else 666 error = intel_ntb_detect_xeon(ntb); 667 if (error != 0) 668 goto out; 669 670 intel_ntb_detect_max_mw(ntb); 671 672 pci_enable_busmaster(ntb->device); 673 674 error = intel_ntb_map_pci_bars(ntb); 675 if (error != 0) 676 goto out; 677 if (ntb->type == NTB_ATOM) 678 error = intel_ntb_atom_init_dev(ntb); 679 else 680 error = intel_ntb_xeon_init_dev(ntb); 681 if (error != 0) 682 goto out; 683 684 intel_ntb_spad_clear(device); 685 686 intel_ntb_poll_link(ntb); 687 688 intel_ntb_sysctl_init(ntb); 689 690 /* Attach children to this controller */ 691 error = ntb_register_device(device); 692 693 out: 694 if (error != 0) 695 intel_ntb_detach(device); 696 return (error); 697 } 698 699 static int 700 intel_ntb_detach(device_t device) 701 { 702 struct ntb_softc *ntb; 703 704 ntb = device_get_softc(device); 705 706 /* Detach & delete all children */ 707 ntb_unregister_device(device); 708 709 if (ntb->self_reg != NULL) { 710 DB_MASK_LOCK(ntb); 711 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_valid_mask); 712 DB_MASK_UNLOCK(ntb); 713 } 714 callout_drain(&ntb->heartbeat_timer); 715 callout_drain(&ntb->lr_timer); 716 callout_drain(&ntb->peer_msix_work); 717 pci_disable_busmaster(ntb->device); 718 if (ntb->type == NTB_XEON) 719 intel_ntb_teardown_xeon(ntb); 720 intel_ntb_teardown_interrupts(ntb); 721 722 mtx_destroy(&ntb->db_mask_lock); 723 724 intel_ntb_unmap_pci_bar(ntb); 725 726 return (0); 727 } 728 729 /* 730 * Driver internal routines 731 */ 732 static inline enum ntb_bar 733 intel_ntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) 734 { 735 736 KASSERT(mw < ntb->mw_count, 737 ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); 738 KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); 739 740 return (ntb->reg->mw_bar[mw]); 741 } 742 743 static inline bool 744 bar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) 745 { 746 /* XXX This assertion could be stronger. */ 747 KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); 748 return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(ntb, NTB_SPLIT_BAR)); 749 } 750 751 static inline void 752 bar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, 753 uint32_t *xlat, uint32_t *lmt) 754 { 755 uint32_t basev, lmtv, xlatv; 756 757 switch (bar) { 758 case NTB_B2B_BAR_1: 759 basev = ntb->xlat_reg->bar2_base; 760 lmtv = ntb->xlat_reg->bar2_limit; 761 xlatv = ntb->xlat_reg->bar2_xlat; 762 break; 763 case NTB_B2B_BAR_2: 764 basev = ntb->xlat_reg->bar4_base; 765 lmtv = ntb->xlat_reg->bar4_limit; 766 xlatv = ntb->xlat_reg->bar4_xlat; 767 break; 768 case NTB_B2B_BAR_3: 769 basev = ntb->xlat_reg->bar5_base; 770 lmtv = ntb->xlat_reg->bar5_limit; 771 xlatv = ntb->xlat_reg->bar5_xlat; 772 break; 773 default: 774 KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, 775 ("bad bar")); 776 basev = lmtv = xlatv = 0; 777 break; 778 } 779 780 if (base != NULL) 781 *base = basev; 782 if (xlat != NULL) 783 *xlat = xlatv; 784 if (lmt != NULL) 785 *lmt = lmtv; 786 } 787 788 static int 789 intel_ntb_map_pci_bars(struct ntb_softc *ntb) 790 { 791 struct ntb_pci_bar_info *bar; 792 int rc; 793 794 bar = &ntb->bar_info[NTB_CONFIG_BAR]; 795 bar->pci_resource_id = PCIR_BAR(0); 796 rc = map_mmr_bar(ntb, bar); 797 if (rc != 0) 798 goto out; 799 800 /* 801 * At least on Xeon v4 NTB device leaks to host some remote side 802 * BAR0 writes supposed to update scratchpad registers. I am not 803 * sure why it happens, but it may be related to the fact that 804 * on a link side BAR0 is 32KB, while on a host side it is 64KB. 805 * Without this hack DMAR blocks those accesses as not allowed. 806 */ 807 if (bus_dma_tag_create(bus_get_dma_tag(ntb->device), 1, 0, 808 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 809 bar->size, 1, bar->size, 0, NULL, NULL, &ntb->bar0_dma_tag)) { 810 device_printf(ntb->device, "Unable to create BAR0 tag\n"); 811 return (ENOMEM); 812 } 813 if (bus_dmamap_create(ntb->bar0_dma_tag, 0, &ntb->bar0_dma_map)) { 814 device_printf(ntb->device, "Unable to create BAR0 map\n"); 815 return (ENOMEM); 816 } 817 if (bus_dma_iommu_load_ident(ntb->bar0_dma_tag, ntb->bar0_dma_map, 818 bar->pbase, bar->size, 0)) { 819 device_printf(ntb->device, "Unable to load BAR0 map\n"); 820 return (ENOMEM); 821 } 822 823 bar = &ntb->bar_info[NTB_B2B_BAR_1]; 824 bar->pci_resource_id = PCIR_BAR(2); 825 rc = map_memory_window_bar(ntb, bar); 826 if (rc != 0) 827 goto out; 828 bar->psz_off = XEON_PBAR23SZ_OFFSET; 829 bar->ssz_off = XEON_SBAR23SZ_OFFSET; 830 bar->pbarxlat_off = XEON_PBAR2XLAT_OFFSET; 831 832 bar = &ntb->bar_info[NTB_B2B_BAR_2]; 833 bar->pci_resource_id = PCIR_BAR(4); 834 rc = map_memory_window_bar(ntb, bar); 835 if (rc != 0) 836 goto out; 837 bar->psz_off = XEON_PBAR4SZ_OFFSET; 838 bar->ssz_off = XEON_SBAR4SZ_OFFSET; 839 bar->pbarxlat_off = XEON_PBAR4XLAT_OFFSET; 840 841 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 842 goto out; 843 844 bar = &ntb->bar_info[NTB_B2B_BAR_3]; 845 bar->pci_resource_id = PCIR_BAR(5); 846 rc = map_memory_window_bar(ntb, bar); 847 bar->psz_off = XEON_PBAR5SZ_OFFSET; 848 bar->ssz_off = XEON_SBAR5SZ_OFFSET; 849 bar->pbarxlat_off = XEON_PBAR5XLAT_OFFSET; 850 851 out: 852 if (rc != 0) 853 device_printf(ntb->device, 854 "unable to allocate pci resource\n"); 855 return (rc); 856 } 857 858 static void 859 print_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, 860 const char *kind) 861 { 862 863 device_printf(ntb->device, 864 "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", 865 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 866 (char *)bar->vbase + bar->size - 1, 867 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 868 (uintmax_t)bar->size, kind); 869 } 870 871 static int 872 map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 873 { 874 875 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 876 &bar->pci_resource_id, RF_ACTIVE); 877 if (bar->pci_resource == NULL) 878 return (ENXIO); 879 880 save_bar_parameters(bar); 881 bar->map_mode = VM_MEMATTR_UNCACHEABLE; 882 print_map_success(ntb, bar, "mmr"); 883 return (0); 884 } 885 886 static int 887 map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 888 { 889 int rc; 890 vm_memattr_t mapmode; 891 uint8_t bar_size_bits = 0; 892 893 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 894 &bar->pci_resource_id, RF_ACTIVE); 895 896 if (bar->pci_resource == NULL) 897 return (ENXIO); 898 899 save_bar_parameters(bar); 900 /* 901 * Ivytown NTB BAR sizes are misreported by the hardware due to a 902 * hardware issue. To work around this, query the size it should be 903 * configured to by the device and modify the resource to correspond to 904 * this new size. The BIOS on systems with this problem is required to 905 * provide enough address space to allow the driver to make this change 906 * safely. 907 * 908 * Ideally I could have just specified the size when I allocated the 909 * resource like: 910 * bus_alloc_resource(ntb->device, 911 * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 912 * 1ul << bar_size_bits, RF_ACTIVE); 913 * but the PCI driver does not honor the size in this call, so we have 914 * to modify it after the fact. 915 */ 916 if (HAS_FEATURE(ntb, NTB_BAR_SIZE_4K)) { 917 if (bar->pci_resource_id == PCIR_BAR(2)) 918 bar_size_bits = pci_read_config(ntb->device, 919 XEON_PBAR23SZ_OFFSET, 1); 920 else 921 bar_size_bits = pci_read_config(ntb->device, 922 XEON_PBAR45SZ_OFFSET, 1); 923 924 rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 925 bar->pci_resource, bar->pbase, 926 bar->pbase + (1ul << bar_size_bits) - 1); 927 if (rc != 0) { 928 device_printf(ntb->device, 929 "unable to resize bar\n"); 930 return (rc); 931 } 932 933 save_bar_parameters(bar); 934 } 935 936 bar->map_mode = VM_MEMATTR_UNCACHEABLE; 937 print_map_success(ntb, bar, "mw"); 938 939 /* 940 * Optionally, mark MW BARs as anything other than UC to improve 941 * performance. 942 */ 943 mapmode = intel_ntb_pat_flags(); 944 if (mapmode == bar->map_mode) 945 return (0); 946 947 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode); 948 if (rc == 0) { 949 bar->map_mode = mapmode; 950 device_printf(ntb->device, 951 "Marked BAR%d v:[%p-%p] p:[%p-%p] as " 952 "%s.\n", 953 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 954 (char *)bar->vbase + bar->size - 1, 955 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 956 intel_ntb_vm_memattr_to_str(mapmode)); 957 } else 958 device_printf(ntb->device, 959 "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " 960 "%s: %d\n", 961 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 962 (char *)bar->vbase + bar->size - 1, 963 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 964 intel_ntb_vm_memattr_to_str(mapmode), rc); 965 /* Proceed anyway */ 966 return (0); 967 } 968 969 static void 970 intel_ntb_unmap_pci_bar(struct ntb_softc *ntb) 971 { 972 struct ntb_pci_bar_info *bar; 973 int i; 974 975 if (ntb->bar0_dma_map != NULL) { 976 bus_dmamap_unload(ntb->bar0_dma_tag, ntb->bar0_dma_map); 977 bus_dmamap_destroy(ntb->bar0_dma_tag, ntb->bar0_dma_map); 978 } 979 if (ntb->bar0_dma_tag != NULL) 980 bus_dma_tag_destroy(ntb->bar0_dma_tag); 981 for (i = 0; i < NTB_MAX_BARS; i++) { 982 bar = &ntb->bar_info[i]; 983 if (bar->pci_resource != NULL) 984 bus_release_resource(ntb->device, SYS_RES_MEMORY, 985 bar->pci_resource_id, bar->pci_resource); 986 } 987 } 988 989 static int 990 intel_ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) 991 { 992 uint32_t i; 993 int rc; 994 995 for (i = 0; i < num_vectors; i++) { 996 ntb->int_info[i].rid = i + 1; 997 ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, 998 SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); 999 if (ntb->int_info[i].res == NULL) { 1000 device_printf(ntb->device, 1001 "bus_alloc_resource failed\n"); 1002 return (ENOMEM); 1003 } 1004 ntb->int_info[i].tag = NULL; 1005 ntb->allocated_interrupts++; 1006 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, 1007 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, 1008 &ntb->msix_vec[i], &ntb->int_info[i].tag); 1009 if (rc != 0) { 1010 device_printf(ntb->device, "bus_setup_intr failed\n"); 1011 return (ENXIO); 1012 } 1013 } 1014 return (0); 1015 } 1016 1017 /* 1018 * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector 1019 * cannot be allocated for each MSI-X message. JHB seems to think remapping 1020 * should be okay. This tunable should enable us to test that hypothesis 1021 * when someone gets their hands on some Xeon hardware. 1022 */ 1023 static int ntb_force_remap_mode; 1024 SYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, 1025 &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" 1026 " to a smaller number of ithreads, even if the desired number are " 1027 "available"); 1028 1029 /* 1030 * In case it is NOT ok, give consumers an abort button. 1031 */ 1032 static int ntb_prefer_intx; 1033 SYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, 1034 &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " 1035 "than remapping MSI-X messages over available slots (match Linux driver " 1036 "behavior)"); 1037 1038 /* 1039 * Remap the desired number of MSI-X messages to available ithreads in a simple 1040 * round-robin fashion. 1041 */ 1042 static int 1043 intel_ntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) 1044 { 1045 u_int *vectors; 1046 uint32_t i; 1047 int rc; 1048 1049 if (ntb_prefer_intx != 0) 1050 return (ENXIO); 1051 1052 vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); 1053 1054 for (i = 0; i < desired; i++) 1055 vectors[i] = (i % avail) + 1; 1056 1057 rc = pci_remap_msix(dev, desired, vectors); 1058 free(vectors, M_NTB); 1059 return (rc); 1060 } 1061 1062 static int 1063 intel_ntb_init_isr(struct ntb_softc *ntb) 1064 { 1065 uint32_t desired_vectors, num_vectors; 1066 int rc; 1067 1068 ntb->allocated_interrupts = 0; 1069 ntb->last_ts = ticks; 1070 1071 /* 1072 * Mask all doorbell interrupts. (Except link events!) 1073 */ 1074 DB_MASK_LOCK(ntb); 1075 ntb->db_mask = ntb->db_valid_mask; 1076 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1077 DB_MASK_UNLOCK(ntb); 1078 1079 num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 1080 ntb->db_count); 1081 if (desired_vectors >= 1) { 1082 rc = pci_alloc_msix(ntb->device, &num_vectors); 1083 1084 if (ntb_force_remap_mode != 0 && rc == 0 && 1085 num_vectors == desired_vectors) 1086 num_vectors--; 1087 1088 if (rc == 0 && num_vectors < desired_vectors) { 1089 rc = intel_ntb_remap_msix(ntb->device, desired_vectors, 1090 num_vectors); 1091 if (rc == 0) 1092 num_vectors = desired_vectors; 1093 else 1094 pci_release_msi(ntb->device); 1095 } 1096 if (rc != 0) 1097 num_vectors = 1; 1098 } else 1099 num_vectors = 1; 1100 1101 if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) { 1102 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1103 device_printf(ntb->device, 1104 "Errata workaround does not support MSI or INTX\n"); 1105 return (EINVAL); 1106 } 1107 1108 ntb->db_vec_count = 1; 1109 ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; 1110 rc = intel_ntb_setup_legacy_interrupt(ntb); 1111 } else { 1112 if (num_vectors - 1 != XEON_NONLINK_DB_MSIX_BITS && 1113 HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1114 device_printf(ntb->device, 1115 "Errata workaround expects %d doorbell bits\n", 1116 XEON_NONLINK_DB_MSIX_BITS); 1117 return (EINVAL); 1118 } 1119 1120 intel_ntb_create_msix_vec(ntb, num_vectors); 1121 rc = intel_ntb_setup_msix(ntb, num_vectors); 1122 } 1123 if (rc != 0) { 1124 device_printf(ntb->device, 1125 "Error allocating interrupts: %d\n", rc); 1126 intel_ntb_free_msix_vec(ntb); 1127 } 1128 1129 return (rc); 1130 } 1131 1132 static int 1133 intel_ntb_setup_legacy_interrupt(struct ntb_softc *ntb) 1134 { 1135 int rc; 1136 1137 ntb->int_info[0].rid = 0; 1138 ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, 1139 &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 1140 if (ntb->int_info[0].res == NULL) { 1141 device_printf(ntb->device, "bus_alloc_resource failed\n"); 1142 return (ENOMEM); 1143 } 1144 1145 ntb->int_info[0].tag = NULL; 1146 ntb->allocated_interrupts = 1; 1147 1148 rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, 1149 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, 1150 ntb, &ntb->int_info[0].tag); 1151 if (rc != 0) { 1152 device_printf(ntb->device, "bus_setup_intr failed\n"); 1153 return (ENXIO); 1154 } 1155 1156 return (0); 1157 } 1158 1159 static void 1160 intel_ntb_teardown_interrupts(struct ntb_softc *ntb) 1161 { 1162 struct ntb_int_info *current_int; 1163 int i; 1164 1165 for (i = 0; i < ntb->allocated_interrupts; i++) { 1166 current_int = &ntb->int_info[i]; 1167 if (current_int->tag != NULL) 1168 bus_teardown_intr(ntb->device, current_int->res, 1169 current_int->tag); 1170 1171 if (current_int->res != NULL) 1172 bus_release_resource(ntb->device, SYS_RES_IRQ, 1173 rman_get_rid(current_int->res), current_int->res); 1174 } 1175 1176 intel_ntb_free_msix_vec(ntb); 1177 pci_release_msi(ntb->device); 1178 } 1179 1180 /* 1181 * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it 1182 * out to make code clearer. 1183 */ 1184 static inline uint64_t 1185 db_ioread(struct ntb_softc *ntb, uint64_t regoff) 1186 { 1187 1188 if (ntb->type == NTB_ATOM) 1189 return (intel_ntb_reg_read(8, regoff)); 1190 1191 KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1192 1193 return (intel_ntb_reg_read(2, regoff)); 1194 } 1195 1196 static inline void 1197 db_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1198 { 1199 1200 KASSERT((val & ~ntb->db_valid_mask) == 0, 1201 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1202 (uintmax_t)(val & ~ntb->db_valid_mask), 1203 (uintmax_t)ntb->db_valid_mask)); 1204 1205 if (regoff == ntb->self_reg->db_mask) 1206 DB_MASK_ASSERT(ntb, MA_OWNED); 1207 db_iowrite_raw(ntb, regoff, val); 1208 } 1209 1210 static inline void 1211 db_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1212 { 1213 1214 if (ntb->type == NTB_ATOM) { 1215 intel_ntb_reg_write(8, regoff, val); 1216 return; 1217 } 1218 1219 KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1220 intel_ntb_reg_write(2, regoff, (uint16_t)val); 1221 } 1222 1223 static void 1224 intel_ntb_db_set_mask(device_t dev, uint64_t bits) 1225 { 1226 struct ntb_softc *ntb = device_get_softc(dev); 1227 1228 DB_MASK_LOCK(ntb); 1229 ntb->db_mask |= bits; 1230 if (!HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1231 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1232 DB_MASK_UNLOCK(ntb); 1233 } 1234 1235 static void 1236 intel_ntb_db_clear_mask(device_t dev, uint64_t bits) 1237 { 1238 struct ntb_softc *ntb = device_get_softc(dev); 1239 uint64_t ibits; 1240 int i; 1241 1242 KASSERT((bits & ~ntb->db_valid_mask) == 0, 1243 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1244 (uintmax_t)(bits & ~ntb->db_valid_mask), 1245 (uintmax_t)ntb->db_valid_mask)); 1246 1247 DB_MASK_LOCK(ntb); 1248 ibits = ntb->fake_db & ntb->db_mask & bits; 1249 ntb->db_mask &= ~bits; 1250 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1251 /* Simulate fake interrupts if unmasked DB bits are set. */ 1252 ntb->force_db |= ibits; 1253 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 1254 if ((ibits & intel_ntb_db_vector_mask(dev, i)) != 0) 1255 swi_sched(ntb->int_info[i].tag, 0); 1256 } 1257 } else { 1258 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1259 } 1260 DB_MASK_UNLOCK(ntb); 1261 } 1262 1263 static uint64_t 1264 intel_ntb_db_read(device_t dev) 1265 { 1266 struct ntb_softc *ntb = device_get_softc(dev); 1267 1268 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1269 return (ntb->fake_db); 1270 1271 return (db_ioread(ntb, ntb->self_reg->db_bell)); 1272 } 1273 1274 static void 1275 intel_ntb_db_clear(device_t dev, uint64_t bits) 1276 { 1277 struct ntb_softc *ntb = device_get_softc(dev); 1278 1279 KASSERT((bits & ~ntb->db_valid_mask) == 0, 1280 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1281 (uintmax_t)(bits & ~ntb->db_valid_mask), 1282 (uintmax_t)ntb->db_valid_mask)); 1283 1284 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1285 DB_MASK_LOCK(ntb); 1286 ntb->fake_db &= ~bits; 1287 DB_MASK_UNLOCK(ntb); 1288 return; 1289 } 1290 1291 db_iowrite(ntb, ntb->self_reg->db_bell, bits); 1292 } 1293 1294 static inline uint64_t 1295 intel_ntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) 1296 { 1297 uint64_t shift, mask; 1298 1299 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1300 /* 1301 * Remap vectors in custom way to make at least first 1302 * three doorbells to not generate stray events. 1303 * This breaks Linux compatibility (if one existed) 1304 * when more then one DB is used (not by if_ntb). 1305 */ 1306 if (db_vector < XEON_NONLINK_DB_MSIX_BITS - 1) 1307 return (1 << db_vector); 1308 if (db_vector == XEON_NONLINK_DB_MSIX_BITS - 1) 1309 return (0x7ffc); 1310 } 1311 1312 shift = ntb->db_vec_shift; 1313 mask = (1ull << shift) - 1; 1314 return (mask << (shift * db_vector)); 1315 } 1316 1317 static void 1318 intel_ntb_interrupt(struct ntb_softc *ntb, uint32_t vec) 1319 { 1320 uint64_t vec_mask; 1321 1322 ntb->last_ts = ticks; 1323 vec_mask = intel_ntb_vec_mask(ntb, vec); 1324 1325 if ((vec_mask & ntb->db_link_mask) != 0) { 1326 if (intel_ntb_poll_link(ntb)) 1327 ntb_link_event(ntb->device); 1328 } 1329 1330 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) && 1331 (vec_mask & ntb->db_link_mask) == 0) { 1332 DB_MASK_LOCK(ntb); 1333 1334 /* 1335 * Do not report same DB events again if not cleared yet, 1336 * unless the mask was just cleared for them and this 1337 * interrupt handler call can be the consequence of it. 1338 */ 1339 vec_mask &= ~ntb->fake_db | ntb->force_db; 1340 ntb->force_db &= ~vec_mask; 1341 1342 /* Update our internal doorbell register. */ 1343 ntb->fake_db |= vec_mask; 1344 1345 /* Do not report masked DB events. */ 1346 vec_mask &= ~ntb->db_mask; 1347 1348 DB_MASK_UNLOCK(ntb); 1349 } 1350 1351 if ((vec_mask & ntb->db_valid_mask) != 0) 1352 ntb_db_event(ntb->device, vec); 1353 } 1354 1355 static void 1356 ndev_vec_isr(void *arg) 1357 { 1358 struct ntb_vec *nvec = arg; 1359 1360 intel_ntb_interrupt(nvec->ntb, nvec->num); 1361 } 1362 1363 static void 1364 ndev_irq_isr(void *arg) 1365 { 1366 /* If we couldn't set up MSI-X, we only have the one vector. */ 1367 intel_ntb_interrupt(arg, 0); 1368 } 1369 1370 static int 1371 intel_ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) 1372 { 1373 uint32_t i; 1374 1375 ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, 1376 M_ZERO | M_WAITOK); 1377 for (i = 0; i < num_vectors; i++) { 1378 ntb->msix_vec[i].num = i; 1379 ntb->msix_vec[i].ntb = ntb; 1380 } 1381 1382 return (0); 1383 } 1384 1385 static void 1386 intel_ntb_free_msix_vec(struct ntb_softc *ntb) 1387 { 1388 1389 if (ntb->msix_vec == NULL) 1390 return; 1391 1392 free(ntb->msix_vec, M_NTB); 1393 ntb->msix_vec = NULL; 1394 } 1395 1396 static void 1397 intel_ntb_get_msix_info(struct ntb_softc *ntb) 1398 { 1399 struct pci_devinfo *dinfo; 1400 struct pcicfg_msix *msix; 1401 uint32_t laddr, data, i, offset; 1402 1403 dinfo = device_get_ivars(ntb->device); 1404 msix = &dinfo->cfg.msix; 1405 1406 CTASSERT(XEON_NONLINK_DB_MSIX_BITS == nitems(ntb->msix_data)); 1407 1408 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 1409 offset = msix->msix_table_offset + i * PCI_MSIX_ENTRY_SIZE; 1410 1411 laddr = bus_read_4(msix->msix_table_res, offset + 1412 PCI_MSIX_ENTRY_LOWER_ADDR); 1413 intel_ntb_printf(2, "local MSIX addr(%u): 0x%x\n", i, laddr); 1414 1415 KASSERT((laddr & MSI_INTEL_ADDR_BASE) == MSI_INTEL_ADDR_BASE, 1416 ("local MSIX addr 0x%x not in MSI base 0x%x", laddr, 1417 MSI_INTEL_ADDR_BASE)); 1418 ntb->msix_data[i].nmd_ofs = laddr; 1419 1420 data = bus_read_4(msix->msix_table_res, offset + 1421 PCI_MSIX_ENTRY_DATA); 1422 intel_ntb_printf(2, "local MSIX data(%u): 0x%x\n", i, data); 1423 1424 ntb->msix_data[i].nmd_data = data; 1425 } 1426 } 1427 1428 static struct ntb_hw_info * 1429 intel_ntb_get_device_info(uint32_t device_id) 1430 { 1431 struct ntb_hw_info *ep; 1432 1433 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) { 1434 if (ep->device_id == device_id) 1435 return (ep); 1436 } 1437 return (NULL); 1438 } 1439 1440 static void 1441 intel_ntb_teardown_xeon(struct ntb_softc *ntb) 1442 { 1443 1444 if (ntb->reg != NULL) 1445 intel_ntb_link_disable(ntb->device); 1446 } 1447 1448 static void 1449 intel_ntb_detect_max_mw(struct ntb_softc *ntb) 1450 { 1451 1452 if (ntb->type == NTB_ATOM) { 1453 ntb->mw_count = ATOM_MW_COUNT; 1454 return; 1455 } 1456 1457 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1458 ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; 1459 else 1460 ntb->mw_count = XEON_SNB_MW_COUNT; 1461 } 1462 1463 static int 1464 intel_ntb_detect_xeon(struct ntb_softc *ntb) 1465 { 1466 uint8_t ppd, conn_type; 1467 1468 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 1469 ntb->ppd = ppd; 1470 1471 if ((ppd & XEON_PPD_DEV_TYPE) != 0) 1472 ntb->dev_type = NTB_DEV_DSD; 1473 else 1474 ntb->dev_type = NTB_DEV_USD; 1475 1476 if ((ppd & XEON_PPD_SPLIT_BAR) != 0) 1477 ntb->features |= NTB_SPLIT_BAR; 1478 1479 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) && 1480 !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1481 device_printf(ntb->device, 1482 "Can not apply SB01BASE_LOCKUP workaround " 1483 "with split BARs disabled!\n"); 1484 device_printf(ntb->device, 1485 "Expect system hangs under heavy NTB traffic!\n"); 1486 ntb->features &= ~NTB_SB01BASE_LOCKUP; 1487 } 1488 1489 /* 1490 * SDOORBELL errata workaround gets in the way of SB01BASE_LOCKUP 1491 * errata workaround; only do one at a time. 1492 */ 1493 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1494 ntb->features &= ~NTB_SDOORBELL_LOCKUP; 1495 1496 conn_type = ppd & XEON_PPD_CONN_TYPE; 1497 switch (conn_type) { 1498 case NTB_CONN_B2B: 1499 ntb->conn_type = conn_type; 1500 break; 1501 case NTB_CONN_RP: 1502 case NTB_CONN_TRANSPARENT: 1503 default: 1504 device_printf(ntb->device, "Unsupported connection type: %u\n", 1505 (unsigned)conn_type); 1506 return (ENXIO); 1507 } 1508 return (0); 1509 } 1510 1511 static int 1512 intel_ntb_detect_atom(struct ntb_softc *ntb) 1513 { 1514 uint32_t ppd, conn_type; 1515 1516 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 1517 ntb->ppd = ppd; 1518 1519 if ((ppd & ATOM_PPD_DEV_TYPE) != 0) 1520 ntb->dev_type = NTB_DEV_DSD; 1521 else 1522 ntb->dev_type = NTB_DEV_USD; 1523 1524 conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; 1525 switch (conn_type) { 1526 case NTB_CONN_B2B: 1527 ntb->conn_type = conn_type; 1528 break; 1529 default: 1530 device_printf(ntb->device, "Unsupported NTB configuration\n"); 1531 return (ENXIO); 1532 } 1533 return (0); 1534 } 1535 1536 static int 1537 intel_ntb_xeon_init_dev(struct ntb_softc *ntb) 1538 { 1539 int rc; 1540 1541 ntb->spad_count = XEON_SPAD_COUNT; 1542 ntb->db_count = XEON_DB_COUNT; 1543 ntb->db_link_mask = XEON_DB_LINK_BIT; 1544 ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; 1545 ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; 1546 1547 if (ntb->conn_type != NTB_CONN_B2B) { 1548 device_printf(ntb->device, "Connection type %d not supported\n", 1549 ntb->conn_type); 1550 return (ENXIO); 1551 } 1552 1553 ntb->reg = &xeon_reg; 1554 ntb->self_reg = &xeon_pri_reg; 1555 ntb->peer_reg = &xeon_b2b_reg; 1556 ntb->xlat_reg = &xeon_sec_xlat; 1557 1558 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1559 ntb->force_db = ntb->fake_db = 0; 1560 ntb->msix_mw_idx = (ntb->mw_count + g_ntb_msix_idx) % 1561 ntb->mw_count; 1562 intel_ntb_printf(2, "Setting up MSIX mw idx %d means %u\n", 1563 g_ntb_msix_idx, ntb->msix_mw_idx); 1564 rc = intel_ntb_mw_set_wc_internal(ntb, ntb->msix_mw_idx, 1565 VM_MEMATTR_UNCACHEABLE); 1566 KASSERT(rc == 0, ("shouldn't fail")); 1567 } else if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 1568 /* 1569 * There is a Xeon hardware errata related to writes to SDOORBELL or 1570 * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 1571 * which may hang the system. To workaround this, use a memory 1572 * window to access the interrupt and scratch pad registers on the 1573 * remote system. 1574 */ 1575 ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) % 1576 ntb->mw_count; 1577 intel_ntb_printf(2, "Setting up b2b mw idx %d means %u\n", 1578 g_ntb_mw_idx, ntb->b2b_mw_idx); 1579 rc = intel_ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx, 1580 VM_MEMATTR_UNCACHEABLE); 1581 KASSERT(rc == 0, ("shouldn't fail")); 1582 } else if (HAS_FEATURE(ntb, NTB_B2BDOORBELL_BIT14)) 1583 /* 1584 * HW Errata on bit 14 of b2bdoorbell register. Writes will not be 1585 * mirrored to the remote system. Shrink the number of bits by one, 1586 * since bit 14 is the last bit. 1587 * 1588 * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register 1589 * anyway. Nor for non-B2B connection types. 1590 */ 1591 ntb->db_count = XEON_DB_COUNT - 1; 1592 1593 ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1594 1595 if (ntb->dev_type == NTB_DEV_USD) 1596 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, 1597 &xeon_b2b_usd_addr); 1598 else 1599 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, 1600 &xeon_b2b_dsd_addr); 1601 if (rc != 0) 1602 return (rc); 1603 1604 /* Enable Bus Master and Memory Space on the secondary side */ 1605 intel_ntb_reg_write(2, XEON_SPCICMD_OFFSET, 1606 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1607 1608 /* 1609 * Mask all doorbell interrupts. 1610 */ 1611 DB_MASK_LOCK(ntb); 1612 ntb->db_mask = ntb->db_valid_mask; 1613 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1614 DB_MASK_UNLOCK(ntb); 1615 1616 rc = intel_ntb_init_isr(ntb); 1617 return (rc); 1618 } 1619 1620 static int 1621 intel_ntb_atom_init_dev(struct ntb_softc *ntb) 1622 { 1623 int error; 1624 1625 KASSERT(ntb->conn_type == NTB_CONN_B2B, 1626 ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); 1627 1628 ntb->spad_count = ATOM_SPAD_COUNT; 1629 ntb->db_count = ATOM_DB_COUNT; 1630 ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; 1631 ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; 1632 ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1633 1634 ntb->reg = &atom_reg; 1635 ntb->self_reg = &atom_pri_reg; 1636 ntb->peer_reg = &atom_b2b_reg; 1637 ntb->xlat_reg = &atom_sec_xlat; 1638 1639 /* 1640 * FIXME - MSI-X bug on early Atom HW, remove once internal issue is 1641 * resolved. Mask transaction layer internal parity errors. 1642 */ 1643 pci_write_config(ntb->device, 0xFC, 0x4, 4); 1644 1645 configure_atom_secondary_side_bars(ntb); 1646 1647 /* Enable Bus Master and Memory Space on the secondary side */ 1648 intel_ntb_reg_write(2, ATOM_SPCICMD_OFFSET, 1649 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1650 1651 error = intel_ntb_init_isr(ntb); 1652 if (error != 0) 1653 return (error); 1654 1655 /* Initiate PCI-E link training */ 1656 intel_ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 1657 1658 callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); 1659 1660 return (0); 1661 } 1662 1663 /* XXX: Linux driver doesn't seem to do any of this for Atom. */ 1664 static void 1665 configure_atom_secondary_side_bars(struct ntb_softc *ntb) 1666 { 1667 1668 if (ntb->dev_type == NTB_DEV_USD) { 1669 intel_ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1670 XEON_B2B_BAR2_ADDR64); 1671 intel_ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1672 XEON_B2B_BAR4_ADDR64); 1673 intel_ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1674 intel_ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1675 } else { 1676 intel_ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1677 XEON_B2B_BAR2_ADDR64); 1678 intel_ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1679 XEON_B2B_BAR4_ADDR64); 1680 intel_ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1681 intel_ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1682 } 1683 } 1684 1685 /* 1686 * When working around Xeon SDOORBELL errata by remapping remote registers in a 1687 * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW 1688 * remains for use by a higher layer. 1689 * 1690 * Will only be used if working around SDOORBELL errata and the BIOS-configured 1691 * MW size is sufficiently large. 1692 */ 1693 static unsigned int ntb_b2b_mw_share; 1694 SYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, 1695 0, "If enabled (non-zero), prefer to share half of the B2B peer register " 1696 "MW with higher level consumers. Both sides of the NTB MUST set the same " 1697 "value here."); 1698 1699 static void 1700 xeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, 1701 enum ntb_bar regbar) 1702 { 1703 struct ntb_pci_bar_info *bar; 1704 uint8_t bar_sz; 1705 1706 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) 1707 return; 1708 1709 bar = &ntb->bar_info[idx]; 1710 bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); 1711 if (idx == regbar) { 1712 if (ntb->b2b_off != 0) 1713 bar_sz--; 1714 else 1715 bar_sz = 0; 1716 } 1717 pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); 1718 bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); 1719 (void)bar_sz; 1720 } 1721 1722 static void 1723 xeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, 1724 enum ntb_bar idx, enum ntb_bar regbar) 1725 { 1726 uint64_t reg_val; 1727 uint32_t base_reg, lmt_reg; 1728 1729 bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); 1730 if (idx == regbar) { 1731 if (ntb->b2b_off) 1732 bar_addr += ntb->b2b_off; 1733 else 1734 bar_addr = 0; 1735 } 1736 1737 if (!bar_is_64bit(ntb, idx)) { 1738 intel_ntb_reg_write(4, base_reg, bar_addr); 1739 reg_val = intel_ntb_reg_read(4, base_reg); 1740 (void)reg_val; 1741 1742 intel_ntb_reg_write(4, lmt_reg, bar_addr); 1743 reg_val = intel_ntb_reg_read(4, lmt_reg); 1744 (void)reg_val; 1745 } else { 1746 intel_ntb_reg_write(8, base_reg, bar_addr); 1747 reg_val = intel_ntb_reg_read(8, base_reg); 1748 (void)reg_val; 1749 1750 intel_ntb_reg_write(8, lmt_reg, bar_addr); 1751 reg_val = intel_ntb_reg_read(8, lmt_reg); 1752 (void)reg_val; 1753 } 1754 } 1755 1756 static void 1757 xeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) 1758 { 1759 struct ntb_pci_bar_info *bar; 1760 1761 bar = &ntb->bar_info[idx]; 1762 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { 1763 intel_ntb_reg_write(4, bar->pbarxlat_off, base_addr); 1764 base_addr = intel_ntb_reg_read(4, bar->pbarxlat_off); 1765 } else { 1766 intel_ntb_reg_write(8, bar->pbarxlat_off, base_addr); 1767 base_addr = intel_ntb_reg_read(8, bar->pbarxlat_off); 1768 } 1769 (void)base_addr; 1770 } 1771 1772 static int 1773 xeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, 1774 const struct ntb_b2b_addr *peer_addr) 1775 { 1776 struct ntb_pci_bar_info *b2b_bar; 1777 vm_size_t bar_size; 1778 uint64_t bar_addr; 1779 enum ntb_bar b2b_bar_num, i; 1780 1781 if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { 1782 b2b_bar = NULL; 1783 b2b_bar_num = NTB_CONFIG_BAR; 1784 ntb->b2b_off = 0; 1785 } else { 1786 b2b_bar_num = intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); 1787 KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, 1788 ("invalid b2b mw bar")); 1789 1790 b2b_bar = &ntb->bar_info[b2b_bar_num]; 1791 bar_size = b2b_bar->size; 1792 1793 if (ntb_b2b_mw_share != 0 && 1794 (bar_size >> 1) >= XEON_B2B_MIN_SIZE) 1795 ntb->b2b_off = bar_size >> 1; 1796 else if (bar_size >= XEON_B2B_MIN_SIZE) { 1797 ntb->b2b_off = 0; 1798 } else { 1799 device_printf(ntb->device, 1800 "B2B bar size is too small!\n"); 1801 return (EIO); 1802 } 1803 } 1804 1805 /* 1806 * Reset the secondary bar sizes to match the primary bar sizes. 1807 * (Except, disable or halve the size of the B2B secondary bar.) 1808 */ 1809 for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) 1810 xeon_reset_sbar_size(ntb, i, b2b_bar_num); 1811 1812 bar_addr = 0; 1813 if (b2b_bar_num == NTB_CONFIG_BAR) 1814 bar_addr = addr->bar0_addr; 1815 else if (b2b_bar_num == NTB_B2B_BAR_1) 1816 bar_addr = addr->bar2_addr64; 1817 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1818 bar_addr = addr->bar4_addr64; 1819 else if (b2b_bar_num == NTB_B2B_BAR_2) 1820 bar_addr = addr->bar4_addr32; 1821 else if (b2b_bar_num == NTB_B2B_BAR_3) 1822 bar_addr = addr->bar5_addr32; 1823 else 1824 KASSERT(false, ("invalid bar")); 1825 1826 intel_ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); 1827 1828 /* 1829 * Other SBARs are normally hit by the PBAR xlat, except for the b2b 1830 * register BAR. The B2B BAR is either disabled above or configured 1831 * half-size. It starts at PBAR xlat + offset. 1832 * 1833 * Also set up incoming BAR limits == base (zero length window). 1834 */ 1835 xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, 1836 b2b_bar_num); 1837 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1838 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, 1839 NTB_B2B_BAR_2, b2b_bar_num); 1840 xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, 1841 NTB_B2B_BAR_3, b2b_bar_num); 1842 } else 1843 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, 1844 NTB_B2B_BAR_2, b2b_bar_num); 1845 1846 /* Zero incoming translation addrs */ 1847 intel_ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); 1848 intel_ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); 1849 1850 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1851 uint32_t xlat_reg, lmt_reg; 1852 enum ntb_bar bar_num; 1853 1854 /* 1855 * We point the chosen MSIX MW BAR xlat to remote LAPIC for 1856 * workaround 1857 */ 1858 bar_num = intel_ntb_mw_to_bar(ntb, ntb->msix_mw_idx); 1859 bar_get_xlat_params(ntb, bar_num, NULL, &xlat_reg, &lmt_reg); 1860 if (bar_is_64bit(ntb, bar_num)) { 1861 intel_ntb_reg_write(8, xlat_reg, MSI_INTEL_ADDR_BASE); 1862 ntb->msix_xlat = intel_ntb_reg_read(8, xlat_reg); 1863 intel_ntb_reg_write(8, lmt_reg, 0); 1864 } else { 1865 intel_ntb_reg_write(4, xlat_reg, MSI_INTEL_ADDR_BASE); 1866 ntb->msix_xlat = intel_ntb_reg_read(4, xlat_reg); 1867 intel_ntb_reg_write(4, lmt_reg, 0); 1868 } 1869 1870 ntb->peer_lapic_bar = &ntb->bar_info[bar_num]; 1871 } 1872 (void)intel_ntb_reg_read(8, XEON_SBAR2XLAT_OFFSET); 1873 (void)intel_ntb_reg_read(8, XEON_SBAR4XLAT_OFFSET); 1874 1875 /* Zero outgoing translation limits (whole bar size windows) */ 1876 intel_ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); 1877 intel_ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 1878 1879 /* Set outgoing translation offsets */ 1880 xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); 1881 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1882 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); 1883 xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); 1884 } else 1885 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); 1886 1887 /* Set the translation offset for B2B registers */ 1888 bar_addr = 0; 1889 if (b2b_bar_num == NTB_CONFIG_BAR) 1890 bar_addr = peer_addr->bar0_addr; 1891 else if (b2b_bar_num == NTB_B2B_BAR_1) 1892 bar_addr = peer_addr->bar2_addr64; 1893 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1894 bar_addr = peer_addr->bar4_addr64; 1895 else if (b2b_bar_num == NTB_B2B_BAR_2) 1896 bar_addr = peer_addr->bar4_addr32; 1897 else if (b2b_bar_num == NTB_B2B_BAR_3) 1898 bar_addr = peer_addr->bar5_addr32; 1899 else 1900 KASSERT(false, ("invalid bar")); 1901 1902 /* 1903 * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits 1904 * at a time. 1905 */ 1906 intel_ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); 1907 intel_ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); 1908 return (0); 1909 } 1910 1911 static inline bool 1912 _xeon_link_is_up(struct ntb_softc *ntb) 1913 { 1914 1915 if (ntb->conn_type == NTB_CONN_TRANSPARENT) 1916 return (true); 1917 return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); 1918 } 1919 1920 static inline bool 1921 link_is_up(struct ntb_softc *ntb) 1922 { 1923 1924 if (ntb->type == NTB_XEON) 1925 return (_xeon_link_is_up(ntb) && (ntb->peer_msix_good || 1926 !HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))); 1927 1928 KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1929 return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); 1930 } 1931 1932 static inline bool 1933 atom_link_is_err(struct ntb_softc *ntb) 1934 { 1935 uint32_t status; 1936 1937 KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1938 1939 status = intel_ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1940 if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) 1941 return (true); 1942 1943 status = intel_ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1944 return ((status & ATOM_IBIST_ERR_OFLOW) != 0); 1945 } 1946 1947 /* Atom does not have link status interrupt, poll on that platform */ 1948 static void 1949 atom_link_hb(void *arg) 1950 { 1951 struct ntb_softc *ntb = arg; 1952 sbintime_t timo, poll_ts; 1953 1954 timo = NTB_HB_TIMEOUT * hz; 1955 poll_ts = ntb->last_ts + timo; 1956 1957 /* 1958 * Delay polling the link status if an interrupt was received, unless 1959 * the cached link status says the link is down. 1960 */ 1961 if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { 1962 timo = poll_ts - ticks; 1963 goto out; 1964 } 1965 1966 if (intel_ntb_poll_link(ntb)) 1967 ntb_link_event(ntb->device); 1968 1969 if (!link_is_up(ntb) && atom_link_is_err(ntb)) { 1970 /* Link is down with error, proceed with recovery */ 1971 callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); 1972 return; 1973 } 1974 1975 out: 1976 callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); 1977 } 1978 1979 static void 1980 atom_perform_link_restart(struct ntb_softc *ntb) 1981 { 1982 uint32_t status; 1983 1984 /* Driver resets the NTB ModPhy lanes - magic! */ 1985 intel_ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); 1986 intel_ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); 1987 intel_ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); 1988 intel_ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); 1989 1990 /* Driver waits 100ms to allow the NTB ModPhy to settle */ 1991 pause("ModPhy", hz / 10); 1992 1993 /* Clear AER Errors, write to clear */ 1994 status = intel_ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); 1995 status &= PCIM_AER_COR_REPLAY_ROLLOVER; 1996 intel_ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); 1997 1998 /* Clear unexpected electrical idle event in LTSSM, write to clear */ 1999 status = intel_ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); 2000 status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; 2001 intel_ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); 2002 2003 /* Clear DeSkew Buffer error, write to clear */ 2004 status = intel_ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); 2005 status |= ATOM_DESKEWSTS_DBERR; 2006 intel_ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); 2007 2008 status = intel_ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 2009 status &= ATOM_IBIST_ERR_OFLOW; 2010 intel_ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); 2011 2012 /* Releases the NTB state machine to allow the link to retrain */ 2013 status = intel_ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 2014 status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; 2015 intel_ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); 2016 } 2017 2018 static int 2019 intel_ntb_port_number(device_t dev) 2020 { 2021 struct ntb_softc *ntb = device_get_softc(dev); 2022 2023 return (ntb->dev_type == NTB_DEV_USD ? 0 : 1); 2024 } 2025 2026 static int 2027 intel_ntb_peer_port_count(device_t dev) 2028 { 2029 2030 return (1); 2031 } 2032 2033 static int 2034 intel_ntb_peer_port_number(device_t dev, int pidx) 2035 { 2036 struct ntb_softc *ntb = device_get_softc(dev); 2037 2038 if (pidx != 0) 2039 return (-EINVAL); 2040 2041 return (ntb->dev_type == NTB_DEV_USD ? 1 : 0); 2042 } 2043 2044 static int 2045 intel_ntb_peer_port_idx(device_t dev, int port) 2046 { 2047 int peer_port; 2048 2049 peer_port = intel_ntb_peer_port_number(dev, 0); 2050 if (peer_port == -EINVAL || port != peer_port) 2051 return (-EINVAL); 2052 2053 return (0); 2054 } 2055 2056 static int 2057 intel_ntb_link_enable(device_t dev, enum ntb_speed speed __unused, 2058 enum ntb_width width __unused) 2059 { 2060 struct ntb_softc *ntb = device_get_softc(dev); 2061 uint32_t cntl; 2062 2063 intel_ntb_printf(2, "%s\n", __func__); 2064 2065 if (ntb->type == NTB_ATOM) { 2066 pci_write_config(ntb->device, NTB_PPD_OFFSET, 2067 ntb->ppd | ATOM_PPD_INIT_LINK, 4); 2068 return (0); 2069 } 2070 2071 if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 2072 ntb_link_event(dev); 2073 return (0); 2074 } 2075 2076 cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2077 cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); 2078 cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; 2079 cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; 2080 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2081 cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; 2082 intel_ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 2083 return (0); 2084 } 2085 2086 static int 2087 intel_ntb_link_disable(device_t dev) 2088 { 2089 struct ntb_softc *ntb = device_get_softc(dev); 2090 uint32_t cntl; 2091 2092 intel_ntb_printf(2, "%s\n", __func__); 2093 2094 if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 2095 ntb_link_event(dev); 2096 return (0); 2097 } 2098 2099 cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2100 cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); 2101 cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); 2102 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2103 cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); 2104 cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; 2105 intel_ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 2106 return (0); 2107 } 2108 2109 static bool 2110 intel_ntb_link_enabled(device_t dev) 2111 { 2112 struct ntb_softc *ntb = device_get_softc(dev); 2113 uint32_t cntl; 2114 2115 if (ntb->type == NTB_ATOM) { 2116 cntl = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 2117 return ((cntl & ATOM_PPD_INIT_LINK) != 0); 2118 } 2119 2120 if (ntb->conn_type == NTB_CONN_TRANSPARENT) 2121 return (true); 2122 2123 cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2124 return ((cntl & NTB_CNTL_LINK_DISABLE) == 0); 2125 } 2126 2127 static void 2128 recover_atom_link(void *arg) 2129 { 2130 struct ntb_softc *ntb = arg; 2131 unsigned speed, width, oldspeed, oldwidth; 2132 uint32_t status32; 2133 2134 atom_perform_link_restart(ntb); 2135 2136 /* 2137 * There is a potential race between the 2 NTB devices recovering at 2138 * the same time. If the times are the same, the link will not recover 2139 * and the driver will be stuck in this loop forever. Add a random 2140 * interval to the recovery time to prevent this race. 2141 */ 2142 status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; 2143 pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); 2144 2145 if (atom_link_is_err(ntb)) 2146 goto retry; 2147 2148 status32 = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2149 if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) 2150 goto out; 2151 2152 status32 = intel_ntb_reg_read(4, ntb->reg->lnk_sta); 2153 width = NTB_LNK_STA_WIDTH(status32); 2154 speed = status32 & NTB_LINK_SPEED_MASK; 2155 2156 oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); 2157 oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; 2158 if (oldwidth != width || oldspeed != speed) 2159 goto retry; 2160 2161 out: 2162 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, 2163 ntb); 2164 return; 2165 2166 retry: 2167 callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, 2168 ntb); 2169 } 2170 2171 /* 2172 * Polls the HW link status register(s); returns true if something has changed. 2173 */ 2174 static bool 2175 intel_ntb_poll_link(struct ntb_softc *ntb) 2176 { 2177 uint32_t ntb_cntl; 2178 uint16_t reg_val; 2179 2180 if (ntb->type == NTB_ATOM) { 2181 ntb_cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2182 if (ntb_cntl == ntb->ntb_ctl) 2183 return (false); 2184 2185 ntb->ntb_ctl = ntb_cntl; 2186 ntb->lnk_sta = intel_ntb_reg_read(4, ntb->reg->lnk_sta); 2187 } else { 2188 db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask); 2189 2190 reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 2191 if (reg_val == ntb->lnk_sta) 2192 return (false); 2193 2194 ntb->lnk_sta = reg_val; 2195 2196 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 2197 if (_xeon_link_is_up(ntb)) { 2198 if (!ntb->peer_msix_good) { 2199 callout_reset(&ntb->peer_msix_work, 0, 2200 intel_ntb_exchange_msix, ntb); 2201 return (false); 2202 } 2203 } else { 2204 ntb->peer_msix_good = false; 2205 ntb->peer_msix_done = false; 2206 } 2207 } 2208 } 2209 return (true); 2210 } 2211 2212 static inline enum ntb_speed 2213 intel_ntb_link_sta_speed(struct ntb_softc *ntb) 2214 { 2215 2216 if (!link_is_up(ntb)) 2217 return (NTB_SPEED_NONE); 2218 return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); 2219 } 2220 2221 static inline enum ntb_width 2222 intel_ntb_link_sta_width(struct ntb_softc *ntb) 2223 { 2224 2225 if (!link_is_up(ntb)) 2226 return (NTB_WIDTH_NONE); 2227 return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); 2228 } 2229 2230 SYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 2231 "Driver state, statistics, and HW registers"); 2232 2233 #define NTB_REGSZ_MASK (3ul << 30) 2234 #define NTB_REG_64 (1ul << 30) 2235 #define NTB_REG_32 (2ul << 30) 2236 #define NTB_REG_16 (3ul << 30) 2237 #define NTB_REG_8 (0ul << 30) 2238 2239 #define NTB_DB_READ (1ul << 29) 2240 #define NTB_PCI_REG (1ul << 28) 2241 #define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) 2242 2243 static void 2244 intel_ntb_sysctl_init(struct ntb_softc *ntb) 2245 { 2246 struct sysctl_oid_list *globals, *tree_par, *regpar, *statpar, *errpar; 2247 struct sysctl_ctx_list *ctx; 2248 struct sysctl_oid *tree, *tmptree; 2249 2250 ctx = device_get_sysctl_ctx(ntb->device); 2251 globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)); 2252 2253 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "link_status", 2254 CTLFLAG_RD | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, ntb, 0, 2255 sysctl_handle_link_status_human, "A", 2256 "Link status (human readable)"); 2257 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "active", 2258 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, ntb, 0, 2259 sysctl_handle_link_status, "IU", 2260 "Link status (1=active, 0=inactive)"); 2261 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "admin_up", 2262 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, ntb, 0, 2263 sysctl_handle_link_admin, "IU", 2264 "Set/get interface status (1=UP, 0=DOWN)"); 2265 2266 tree = SYSCTL_ADD_NODE(ctx, globals, OID_AUTO, "debug_info", 2267 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 2268 "Driver state, statistics, and HW registers"); 2269 tree_par = SYSCTL_CHILDREN(tree); 2270 2271 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, 2272 &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); 2273 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, 2274 &ntb->dev_type, 0, "0 - USD; 1 - DSD"); 2275 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD, 2276 &ntb->ppd, 0, "Raw PPD register (cached)"); 2277 2278 if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { 2279 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, 2280 &ntb->b2b_mw_idx, 0, 2281 "Index of the MW used for B2B remote register access"); 2282 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", 2283 CTLFLAG_RD, &ntb->b2b_off, 2284 "If non-zero, offset of B2B register region in shared MW"); 2285 } 2286 2287 SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", 2288 CTLFLAG_RD | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, ntb, 0, 2289 sysctl_handle_features, "A", "Features/errata of this NTB device"); 2290 2291 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, 2292 __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0, 2293 "NTB CTL register (cached)"); 2294 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, 2295 __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0, 2296 "LNK STA register (cached)"); 2297 2298 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, 2299 &ntb->mw_count, 0, "MW count"); 2300 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, 2301 &ntb->spad_count, 0, "Scratchpad count"); 2302 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, 2303 &ntb->db_count, 0, "Doorbell count"); 2304 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, 2305 &ntb->db_vec_count, 0, "Doorbell vector count"); 2306 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, 2307 &ntb->db_vec_shift, 0, "Doorbell vector shift"); 2308 2309 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, 2310 &ntb->db_valid_mask, "Doorbell valid mask"); 2311 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, 2312 &ntb->db_link_mask, "Doorbell link mask"); 2313 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, 2314 &ntb->db_mask, "Doorbell mask (cached)"); 2315 2316 tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", 2317 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 2318 "Raw HW registers (big-endian)"); 2319 regpar = SYSCTL_CHILDREN(tmptree); 2320 2321 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", 2322 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2323 NTB_REG_32 | ntb->reg->ntb_ctl, sysctl_handle_register, "IU", 2324 "NTB Control register"); 2325 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", 2326 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2327 NTB_REG_32 | 0x19c, sysctl_handle_register, "IU", 2328 "NTB Link Capabilities"); 2329 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", 2330 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2331 NTB_REG_32 | 0x1a0, sysctl_handle_register, "IU", 2332 "NTB Link Control register"); 2333 2334 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", 2335 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2336 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, 2337 sysctl_handle_register, "QU", "Doorbell mask register"); 2338 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", 2339 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2340 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, 2341 sysctl_handle_register, "QU", "Doorbell register"); 2342 2343 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", 2344 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2345 NTB_REG_64 | ntb->xlat_reg->bar2_xlat, 2346 sysctl_handle_register, "QU", "Incoming XLAT23 register"); 2347 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2348 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", 2349 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2350 NTB_REG_32 | ntb->xlat_reg->bar4_xlat, 2351 sysctl_handle_register, "IU", "Incoming XLAT4 register"); 2352 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", 2353 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2354 NTB_REG_32 | ntb->xlat_reg->bar5_xlat, 2355 sysctl_handle_register, "IU", "Incoming XLAT5 register"); 2356 } else { 2357 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", 2358 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2359 NTB_REG_64 | ntb->xlat_reg->bar4_xlat, 2360 sysctl_handle_register, "QU", "Incoming XLAT45 register"); 2361 } 2362 2363 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", 2364 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2365 NTB_REG_64 | ntb->xlat_reg->bar2_limit, 2366 sysctl_handle_register, "QU", "Incoming LMT23 register"); 2367 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2368 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", 2369 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2370 NTB_REG_32 | ntb->xlat_reg->bar4_limit, 2371 sysctl_handle_register, "IU", "Incoming LMT4 register"); 2372 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", 2373 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2374 NTB_REG_32 | ntb->xlat_reg->bar5_limit, 2375 sysctl_handle_register, "IU", "Incoming LMT5 register"); 2376 } else { 2377 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", 2378 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2379 NTB_REG_64 | ntb->xlat_reg->bar4_limit, 2380 sysctl_handle_register, "QU", "Incoming LMT45 register"); 2381 } 2382 2383 if (ntb->type == NTB_ATOM) 2384 return; 2385 2386 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", 2387 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Xeon HW statistics"); 2388 statpar = SYSCTL_CHILDREN(tmptree); 2389 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", 2390 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2391 NTB_REG_16 | XEON_USMEMMISS_OFFSET, 2392 sysctl_handle_register, "SU", "Upstream Memory Miss"); 2393 2394 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", 2395 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Xeon HW errors"); 2396 errpar = SYSCTL_CHILDREN(tmptree); 2397 2398 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd", 2399 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2400 NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET, 2401 sysctl_handle_register, "CU", "PPD"); 2402 2403 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz", 2404 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2405 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET, 2406 sysctl_handle_register, "CU", "PBAR23 SZ (log2)"); 2407 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz", 2408 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2409 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET, 2410 sysctl_handle_register, "CU", "PBAR4 SZ (log2)"); 2411 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz", 2412 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2413 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET, 2414 sysctl_handle_register, "CU", "PBAR5 SZ (log2)"); 2415 2416 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz", 2417 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2418 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET, 2419 sysctl_handle_register, "CU", "SBAR23 SZ (log2)"); 2420 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz", 2421 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2422 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET, 2423 sysctl_handle_register, "CU", "SBAR4 SZ (log2)"); 2424 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz", 2425 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2426 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET, 2427 sysctl_handle_register, "CU", "SBAR5 SZ (log2)"); 2428 2429 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts", 2430 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2431 NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, 2432 sysctl_handle_register, "SU", "DEVSTS"); 2433 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts", 2434 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2435 NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, 2436 sysctl_handle_register, "SU", "LNKSTS"); 2437 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts", 2438 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2439 NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET, 2440 sysctl_handle_register, "SU", "SLNKSTS"); 2441 2442 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", 2443 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2444 NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, 2445 sysctl_handle_register, "IU", "UNCERRSTS"); 2446 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", 2447 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2448 NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, 2449 sysctl_handle_register, "IU", "CORERRSTS"); 2450 2451 if (ntb->conn_type != NTB_CONN_B2B) 2452 return; 2453 2454 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat01l", 2455 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2456 NTB_REG_32 | XEON_B2B_XLAT_OFFSETL, 2457 sysctl_handle_register, "IU", "Outgoing XLAT0L register"); 2458 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat01u", 2459 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2460 NTB_REG_32 | XEON_B2B_XLAT_OFFSETU, 2461 sysctl_handle_register, "IU", "Outgoing XLAT0U register"); 2462 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", 2463 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2464 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, 2465 sysctl_handle_register, "QU", "Outgoing XLAT23 register"); 2466 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2467 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", 2468 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2469 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2470 sysctl_handle_register, "IU", "Outgoing XLAT4 register"); 2471 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", 2472 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2473 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, 2474 sysctl_handle_register, "IU", "Outgoing XLAT5 register"); 2475 } else { 2476 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", 2477 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2478 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2479 sysctl_handle_register, "QU", "Outgoing XLAT45 register"); 2480 } 2481 2482 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", 2483 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2484 NTB_REG_64 | XEON_PBAR2LMT_OFFSET, 2485 sysctl_handle_register, "QU", "Outgoing LMT23 register"); 2486 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2487 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", 2488 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2489 NTB_REG_32 | XEON_PBAR4LMT_OFFSET, 2490 sysctl_handle_register, "IU", "Outgoing LMT4 register"); 2491 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", 2492 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2493 NTB_REG_32 | XEON_PBAR5LMT_OFFSET, 2494 sysctl_handle_register, "IU", "Outgoing LMT5 register"); 2495 } else { 2496 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", 2497 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2498 NTB_REG_64 | XEON_PBAR4LMT_OFFSET, 2499 sysctl_handle_register, "QU", "Outgoing LMT45 register"); 2500 } 2501 2502 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", 2503 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2504 NTB_REG_64 | ntb->xlat_reg->bar0_base, 2505 sysctl_handle_register, "QU", "Secondary BAR01 base register"); 2506 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", 2507 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2508 NTB_REG_64 | ntb->xlat_reg->bar2_base, 2509 sysctl_handle_register, "QU", "Secondary BAR23 base register"); 2510 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2511 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", 2512 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2513 NTB_REG_32 | ntb->xlat_reg->bar4_base, 2514 sysctl_handle_register, "IU", 2515 "Secondary BAR4 base register"); 2516 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", 2517 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2518 NTB_REG_32 | ntb->xlat_reg->bar5_base, 2519 sysctl_handle_register, "IU", 2520 "Secondary BAR5 base register"); 2521 } else { 2522 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", 2523 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2524 NTB_REG_64 | ntb->xlat_reg->bar4_base, 2525 sysctl_handle_register, "QU", 2526 "Secondary BAR45 base register"); 2527 } 2528 } 2529 2530 static int 2531 sysctl_handle_features(SYSCTL_HANDLER_ARGS) 2532 { 2533 struct ntb_softc *ntb = arg1; 2534 struct sbuf sb; 2535 int error; 2536 2537 sbuf_new_for_sysctl(&sb, NULL, 256, req); 2538 2539 sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); 2540 error = sbuf_finish(&sb); 2541 sbuf_delete(&sb); 2542 2543 if (error || !req->newptr) 2544 return (error); 2545 return (EINVAL); 2546 } 2547 2548 static int 2549 sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS) 2550 { 2551 struct ntb_softc *ntb = arg1; 2552 unsigned old, new; 2553 int error; 2554 2555 old = intel_ntb_link_enabled(ntb->device); 2556 2557 error = SYSCTL_OUT(req, &old, sizeof(old)); 2558 if (error != 0 || req->newptr == NULL) 2559 return (error); 2560 2561 error = SYSCTL_IN(req, &new, sizeof(new)); 2562 if (error != 0) 2563 return (error); 2564 2565 intel_ntb_printf(0, "Admin set interface state to '%sabled'\n", 2566 (new != 0)? "en" : "dis"); 2567 2568 if (new != 0) 2569 error = intel_ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 2570 else 2571 error = intel_ntb_link_disable(ntb->device); 2572 return (error); 2573 } 2574 2575 static int 2576 sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS) 2577 { 2578 struct ntb_softc *ntb = arg1; 2579 struct sbuf sb; 2580 enum ntb_speed speed; 2581 enum ntb_width width; 2582 int error; 2583 2584 sbuf_new_for_sysctl(&sb, NULL, 32, req); 2585 2586 if (intel_ntb_link_is_up(ntb->device, &speed, &width)) 2587 sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", 2588 (unsigned)speed, (unsigned)width); 2589 else 2590 sbuf_printf(&sb, "down"); 2591 2592 error = sbuf_finish(&sb); 2593 sbuf_delete(&sb); 2594 2595 if (error || !req->newptr) 2596 return (error); 2597 return (EINVAL); 2598 } 2599 2600 static int 2601 sysctl_handle_link_status(SYSCTL_HANDLER_ARGS) 2602 { 2603 struct ntb_softc *ntb = arg1; 2604 unsigned res; 2605 int error; 2606 2607 res = intel_ntb_link_is_up(ntb->device, NULL, NULL); 2608 2609 error = SYSCTL_OUT(req, &res, sizeof(res)); 2610 if (error || !req->newptr) 2611 return (error); 2612 return (EINVAL); 2613 } 2614 2615 static int 2616 sysctl_handle_register(SYSCTL_HANDLER_ARGS) 2617 { 2618 struct ntb_softc *ntb; 2619 const void *outp; 2620 uintptr_t sz; 2621 uint64_t umv; 2622 char be[sizeof(umv)]; 2623 size_t outsz; 2624 uint32_t reg; 2625 bool db, pci; 2626 int error; 2627 2628 ntb = arg1; 2629 reg = arg2 & ~NTB_REGFLAGS_MASK; 2630 sz = arg2 & NTB_REGSZ_MASK; 2631 db = (arg2 & NTB_DB_READ) != 0; 2632 pci = (arg2 & NTB_PCI_REG) != 0; 2633 2634 KASSERT(!(db && pci), ("bogus")); 2635 2636 if (db) { 2637 KASSERT(sz == NTB_REG_64, ("bogus")); 2638 umv = db_ioread(ntb, reg); 2639 outsz = sizeof(uint64_t); 2640 } else { 2641 switch (sz) { 2642 case NTB_REG_64: 2643 if (pci) 2644 umv = pci_read_config(ntb->device, reg, 8); 2645 else 2646 umv = intel_ntb_reg_read(8, reg); 2647 outsz = sizeof(uint64_t); 2648 break; 2649 case NTB_REG_32: 2650 if (pci) 2651 umv = pci_read_config(ntb->device, reg, 4); 2652 else 2653 umv = intel_ntb_reg_read(4, reg); 2654 outsz = sizeof(uint32_t); 2655 break; 2656 case NTB_REG_16: 2657 if (pci) 2658 umv = pci_read_config(ntb->device, reg, 2); 2659 else 2660 umv = intel_ntb_reg_read(2, reg); 2661 outsz = sizeof(uint16_t); 2662 break; 2663 case NTB_REG_8: 2664 if (pci) 2665 umv = pci_read_config(ntb->device, reg, 1); 2666 else 2667 umv = intel_ntb_reg_read(1, reg); 2668 outsz = sizeof(uint8_t); 2669 break; 2670 default: 2671 panic("bogus"); 2672 break; 2673 } 2674 } 2675 2676 /* Encode bigendian so that sysctl -x is legible. */ 2677 be64enc(be, umv); 2678 outp = ((char *)be) + sizeof(umv) - outsz; 2679 2680 error = SYSCTL_OUT(req, outp, outsz); 2681 if (error || !req->newptr) 2682 return (error); 2683 return (EINVAL); 2684 } 2685 2686 static unsigned 2687 intel_ntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx) 2688 { 2689 2690 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2691 uidx >= ntb->b2b_mw_idx) || 2692 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx)) 2693 uidx++; 2694 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2695 uidx >= ntb->b2b_mw_idx) && 2696 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx)) 2697 uidx++; 2698 return (uidx); 2699 } 2700 2701 #ifndef EARLY_AP_STARTUP 2702 static int msix_ready; 2703 2704 static void 2705 intel_ntb_msix_ready(void *arg __unused) 2706 { 2707 2708 msix_ready = 1; 2709 } 2710 SYSINIT(intel_ntb_msix_ready, SI_SUB_SMP, SI_ORDER_ANY, 2711 intel_ntb_msix_ready, NULL); 2712 #endif 2713 2714 static void 2715 intel_ntb_exchange_msix(void *ctx) 2716 { 2717 struct ntb_softc *ntb; 2718 uint32_t val; 2719 unsigned i; 2720 2721 ntb = ctx; 2722 2723 if (ntb->peer_msix_good) 2724 goto msix_good; 2725 if (ntb->peer_msix_done) 2726 goto msix_done; 2727 2728 #ifndef EARLY_AP_STARTUP 2729 /* Block MSIX negotiation until SMP started and IRQ reshuffled. */ 2730 if (!msix_ready) 2731 goto reschedule; 2732 #endif 2733 2734 intel_ntb_get_msix_info(ntb); 2735 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 2736 intel_ntb_peer_spad_write(ntb->device, NTB_MSIX_DATA0 + i, 2737 ntb->msix_data[i].nmd_data); 2738 intel_ntb_peer_spad_write(ntb->device, NTB_MSIX_OFS0 + i, 2739 ntb->msix_data[i].nmd_ofs - ntb->msix_xlat); 2740 } 2741 intel_ntb_peer_spad_write(ntb->device, NTB_MSIX_GUARD, NTB_MSIX_VER_GUARD); 2742 2743 intel_ntb_spad_read(ntb->device, NTB_MSIX_GUARD, &val); 2744 if (val != NTB_MSIX_VER_GUARD) 2745 goto reschedule; 2746 2747 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 2748 intel_ntb_spad_read(ntb->device, NTB_MSIX_DATA0 + i, &val); 2749 intel_ntb_printf(2, "remote MSIX data(%u): 0x%x\n", i, val); 2750 ntb->peer_msix_data[i].nmd_data = val; 2751 intel_ntb_spad_read(ntb->device, NTB_MSIX_OFS0 + i, &val); 2752 intel_ntb_printf(2, "remote MSIX addr(%u): 0x%x\n", i, val); 2753 ntb->peer_msix_data[i].nmd_ofs = val; 2754 } 2755 2756 ntb->peer_msix_done = true; 2757 2758 msix_done: 2759 intel_ntb_peer_spad_write(ntb->device, NTB_MSIX_DONE, NTB_MSIX_RECEIVED); 2760 intel_ntb_spad_read(ntb->device, NTB_MSIX_DONE, &val); 2761 if (val != NTB_MSIX_RECEIVED) 2762 goto reschedule; 2763 2764 intel_ntb_spad_clear(ntb->device); 2765 ntb->peer_msix_good = true; 2766 /* Give peer time to see our NTB_MSIX_RECEIVED. */ 2767 goto reschedule; 2768 2769 msix_good: 2770 intel_ntb_poll_link(ntb); 2771 ntb_link_event(ntb->device); 2772 return; 2773 2774 reschedule: 2775 ntb->lnk_sta = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 2776 if (_xeon_link_is_up(ntb)) { 2777 callout_reset(&ntb->peer_msix_work, 2778 hz * (ntb->peer_msix_good ? 2 : 1) / 10, 2779 intel_ntb_exchange_msix, ntb); 2780 } else 2781 intel_ntb_spad_clear(ntb->device); 2782 } 2783 2784 /* 2785 * Public API to the rest of the OS 2786 */ 2787 2788 static uint8_t 2789 intel_ntb_spad_count(device_t dev) 2790 { 2791 struct ntb_softc *ntb = device_get_softc(dev); 2792 2793 return (ntb->spad_count); 2794 } 2795 2796 static uint8_t 2797 intel_ntb_mw_count(device_t dev) 2798 { 2799 struct ntb_softc *ntb = device_get_softc(dev); 2800 uint8_t res; 2801 2802 res = ntb->mw_count; 2803 if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0) 2804 res--; 2805 if (ntb->msix_mw_idx != B2B_MW_DISABLED) 2806 res--; 2807 return (res); 2808 } 2809 2810 static int 2811 intel_ntb_spad_write(device_t dev, unsigned int idx, uint32_t val) 2812 { 2813 struct ntb_softc *ntb = device_get_softc(dev); 2814 2815 if (idx >= ntb->spad_count) 2816 return (EINVAL); 2817 2818 intel_ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); 2819 2820 return (0); 2821 } 2822 2823 /* 2824 * Zeros the local scratchpad. 2825 */ 2826 static void 2827 intel_ntb_spad_clear(device_t dev) 2828 { 2829 struct ntb_softc *ntb = device_get_softc(dev); 2830 unsigned i; 2831 2832 for (i = 0; i < ntb->spad_count; i++) 2833 intel_ntb_spad_write(dev, i, 0); 2834 } 2835 2836 static int 2837 intel_ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val) 2838 { 2839 struct ntb_softc *ntb = device_get_softc(dev); 2840 2841 if (idx >= ntb->spad_count) 2842 return (EINVAL); 2843 2844 *val = intel_ntb_reg_read(4, ntb->self_reg->spad + idx * 4); 2845 2846 return (0); 2847 } 2848 2849 static int 2850 intel_ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val) 2851 { 2852 struct ntb_softc *ntb = device_get_softc(dev); 2853 2854 if (idx >= ntb->spad_count) 2855 return (EINVAL); 2856 2857 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) 2858 intel_ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); 2859 else 2860 intel_ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); 2861 2862 return (0); 2863 } 2864 2865 static int 2866 intel_ntb_peer_spad_read(device_t dev, unsigned int idx, uint32_t *val) 2867 { 2868 struct ntb_softc *ntb = device_get_softc(dev); 2869 2870 if (idx >= ntb->spad_count) 2871 return (EINVAL); 2872 2873 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) 2874 *val = intel_ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); 2875 else 2876 *val = intel_ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); 2877 2878 return (0); 2879 } 2880 2881 static int 2882 intel_ntb_mw_get_range(device_t dev, unsigned mw_idx, vm_paddr_t *base, 2883 caddr_t *vbase, size_t *size, size_t *align, size_t *align_size, 2884 bus_addr_t *plimit) 2885 { 2886 struct ntb_softc *ntb = device_get_softc(dev); 2887 struct ntb_pci_bar_info *bar; 2888 bus_addr_t limit; 2889 size_t bar_b2b_off; 2890 enum ntb_bar bar_num; 2891 2892 if (mw_idx >= intel_ntb_mw_count(dev)) 2893 return (EINVAL); 2894 mw_idx = intel_ntb_user_mw_to_idx(ntb, mw_idx); 2895 2896 bar_num = intel_ntb_mw_to_bar(ntb, mw_idx); 2897 bar = &ntb->bar_info[bar_num]; 2898 bar_b2b_off = 0; 2899 if (mw_idx == ntb->b2b_mw_idx) { 2900 KASSERT(ntb->b2b_off != 0, 2901 ("user shouldn't get non-shared b2b mw")); 2902 bar_b2b_off = ntb->b2b_off; 2903 } 2904 2905 if (bar_is_64bit(ntb, bar_num)) 2906 limit = BUS_SPACE_MAXADDR; 2907 else 2908 limit = BUS_SPACE_MAXADDR_32BIT; 2909 2910 if (base != NULL) 2911 *base = bar->pbase + bar_b2b_off; 2912 if (vbase != NULL) 2913 *vbase = bar->vbase + bar_b2b_off; 2914 if (size != NULL) 2915 *size = bar->size - bar_b2b_off; 2916 if (align != NULL) 2917 *align = bar->size; 2918 if (align_size != NULL) 2919 *align_size = 1; 2920 if (plimit != NULL) 2921 *plimit = limit; 2922 return (0); 2923 } 2924 2925 static int 2926 intel_ntb_mw_set_trans(device_t dev, unsigned idx, bus_addr_t addr, size_t size) 2927 { 2928 struct ntb_softc *ntb = device_get_softc(dev); 2929 struct ntb_pci_bar_info *bar; 2930 uint64_t base, limit, reg_val; 2931 size_t bar_size, mw_size; 2932 uint32_t base_reg, xlat_reg, limit_reg; 2933 enum ntb_bar bar_num; 2934 2935 if (idx >= intel_ntb_mw_count(dev)) 2936 return (EINVAL); 2937 idx = intel_ntb_user_mw_to_idx(ntb, idx); 2938 2939 bar_num = intel_ntb_mw_to_bar(ntb, idx); 2940 bar = &ntb->bar_info[bar_num]; 2941 2942 bar_size = bar->size; 2943 if (idx == ntb->b2b_mw_idx) 2944 mw_size = bar_size - ntb->b2b_off; 2945 else 2946 mw_size = bar_size; 2947 2948 /* Hardware requires that addr is aligned to bar size */ 2949 if ((addr & (bar_size - 1)) != 0) 2950 return (EINVAL); 2951 2952 if (size > mw_size) 2953 return (EINVAL); 2954 2955 bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); 2956 2957 limit = 0; 2958 if (bar_is_64bit(ntb, bar_num)) { 2959 base = intel_ntb_reg_read(8, base_reg) & BAR_HIGH_MASK; 2960 2961 if (limit_reg != 0 && size != mw_size) 2962 limit = base + size; 2963 2964 /* Set and verify translation address */ 2965 intel_ntb_reg_write(8, xlat_reg, addr); 2966 reg_val = intel_ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK; 2967 if (reg_val != addr) { 2968 intel_ntb_reg_write(8, xlat_reg, 0); 2969 return (EIO); 2970 } 2971 2972 /* Set and verify the limit */ 2973 intel_ntb_reg_write(8, limit_reg, limit); 2974 reg_val = intel_ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK; 2975 if (reg_val != limit) { 2976 intel_ntb_reg_write(8, limit_reg, base); 2977 intel_ntb_reg_write(8, xlat_reg, 0); 2978 return (EIO); 2979 } 2980 } else { 2981 /* Configure 32-bit (split) BAR MW */ 2982 2983 if ((addr & UINT32_MAX) != addr) 2984 return (ERANGE); 2985 if (((addr + size) & UINT32_MAX) != (addr + size)) 2986 return (ERANGE); 2987 2988 base = intel_ntb_reg_read(4, base_reg) & BAR_HIGH_MASK; 2989 2990 if (limit_reg != 0 && size != mw_size) 2991 limit = base + size; 2992 2993 /* Set and verify translation address */ 2994 intel_ntb_reg_write(4, xlat_reg, addr); 2995 reg_val = intel_ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK; 2996 if (reg_val != addr) { 2997 intel_ntb_reg_write(4, xlat_reg, 0); 2998 return (EIO); 2999 } 3000 3001 /* Set and verify the limit */ 3002 intel_ntb_reg_write(4, limit_reg, limit); 3003 reg_val = intel_ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK; 3004 if (reg_val != limit) { 3005 intel_ntb_reg_write(4, limit_reg, base); 3006 intel_ntb_reg_write(4, xlat_reg, 0); 3007 return (EIO); 3008 } 3009 } 3010 return (0); 3011 } 3012 3013 static int 3014 intel_ntb_mw_clear_trans(device_t dev, unsigned mw_idx) 3015 { 3016 3017 return (intel_ntb_mw_set_trans(dev, mw_idx, 0, 0)); 3018 } 3019 3020 static int 3021 intel_ntb_mw_get_wc(device_t dev, unsigned idx, vm_memattr_t *mode) 3022 { 3023 struct ntb_softc *ntb = device_get_softc(dev); 3024 struct ntb_pci_bar_info *bar; 3025 3026 if (idx >= intel_ntb_mw_count(dev)) 3027 return (EINVAL); 3028 idx = intel_ntb_user_mw_to_idx(ntb, idx); 3029 3030 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, idx)]; 3031 *mode = bar->map_mode; 3032 return (0); 3033 } 3034 3035 static int 3036 intel_ntb_mw_set_wc(device_t dev, unsigned idx, vm_memattr_t mode) 3037 { 3038 struct ntb_softc *ntb = device_get_softc(dev); 3039 3040 if (idx >= intel_ntb_mw_count(dev)) 3041 return (EINVAL); 3042 3043 idx = intel_ntb_user_mw_to_idx(ntb, idx); 3044 return (intel_ntb_mw_set_wc_internal(ntb, idx, mode)); 3045 } 3046 3047 static int 3048 intel_ntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) 3049 { 3050 struct ntb_pci_bar_info *bar; 3051 int rc; 3052 3053 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, idx)]; 3054 if (bar->map_mode == mode) 3055 return (0); 3056 3057 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode); 3058 if (rc == 0) 3059 bar->map_mode = mode; 3060 3061 return (rc); 3062 } 3063 3064 static void 3065 intel_ntb_peer_db_set(device_t dev, uint64_t bit) 3066 { 3067 struct ntb_softc *ntb = device_get_softc(dev); 3068 3069 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 3070 struct ntb_pci_bar_info *lapic; 3071 unsigned i; 3072 3073 lapic = ntb->peer_lapic_bar; 3074 3075 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 3076 if ((bit & intel_ntb_db_vector_mask(dev, i)) != 0) 3077 bus_space_write_4(lapic->pci_bus_tag, 3078 lapic->pci_bus_handle, 3079 ntb->peer_msix_data[i].nmd_ofs, 3080 ntb->peer_msix_data[i].nmd_data); 3081 } 3082 return; 3083 } 3084 3085 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 3086 intel_ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit); 3087 return; 3088 } 3089 3090 db_iowrite(ntb, ntb->peer_reg->db_bell, bit); 3091 } 3092 3093 static int 3094 intel_ntb_peer_db_addr(device_t dev, bus_addr_t *db_addr, vm_size_t *db_size) 3095 { 3096 struct ntb_softc *ntb = device_get_softc(dev); 3097 struct ntb_pci_bar_info *bar; 3098 uint64_t regoff; 3099 3100 KASSERT((db_addr != NULL && db_size != NULL), ("must be non-NULL")); 3101 3102 if (!HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 3103 bar = &ntb->bar_info[NTB_CONFIG_BAR]; 3104 regoff = ntb->peer_reg->db_bell; 3105 } else { 3106 KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, 3107 ("invalid b2b idx")); 3108 3109 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; 3110 regoff = XEON_PDOORBELL_OFFSET; 3111 } 3112 KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); 3113 3114 /* HACK: Specific to current x86 bus implementation. */ 3115 *db_addr = ((uint64_t)bar->pci_bus_handle + regoff); 3116 *db_size = ntb->reg->db_size; 3117 return (0); 3118 } 3119 3120 static uint64_t 3121 intel_ntb_db_valid_mask(device_t dev) 3122 { 3123 struct ntb_softc *ntb = device_get_softc(dev); 3124 3125 return (ntb->db_valid_mask); 3126 } 3127 3128 static int 3129 intel_ntb_db_vector_count(device_t dev) 3130 { 3131 struct ntb_softc *ntb = device_get_softc(dev); 3132 3133 return (ntb->db_vec_count); 3134 } 3135 3136 static uint64_t 3137 intel_ntb_db_vector_mask(device_t dev, uint32_t vector) 3138 { 3139 struct ntb_softc *ntb = device_get_softc(dev); 3140 3141 if (vector > ntb->db_vec_count) 3142 return (0); 3143 return (ntb->db_valid_mask & intel_ntb_vec_mask(ntb, vector)); 3144 } 3145 3146 static bool 3147 intel_ntb_link_is_up(device_t dev, enum ntb_speed *speed, enum ntb_width *width) 3148 { 3149 struct ntb_softc *ntb = device_get_softc(dev); 3150 3151 if (speed != NULL) 3152 *speed = intel_ntb_link_sta_speed(ntb); 3153 if (width != NULL) 3154 *width = intel_ntb_link_sta_width(ntb); 3155 return (link_is_up(ntb)); 3156 } 3157 3158 static void 3159 save_bar_parameters(struct ntb_pci_bar_info *bar) 3160 { 3161 3162 bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); 3163 bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); 3164 bar->pbase = rman_get_start(bar->pci_resource); 3165 bar->size = rman_get_size(bar->pci_resource); 3166 bar->vbase = rman_get_virtual(bar->pci_resource); 3167 } 3168 3169 static device_method_t ntb_intel_methods[] = { 3170 /* Device interface */ 3171 DEVMETHOD(device_probe, intel_ntb_probe), 3172 DEVMETHOD(device_attach, intel_ntb_attach), 3173 DEVMETHOD(device_detach, intel_ntb_detach), 3174 /* Bus interface */ 3175 DEVMETHOD(bus_child_location_str, ntb_child_location_str), 3176 DEVMETHOD(bus_print_child, ntb_print_child), 3177 DEVMETHOD(bus_get_dma_tag, ntb_get_dma_tag), 3178 /* NTB interface */ 3179 DEVMETHOD(ntb_port_number, intel_ntb_port_number), 3180 DEVMETHOD(ntb_peer_port_count, intel_ntb_peer_port_count), 3181 DEVMETHOD(ntb_peer_port_number, intel_ntb_peer_port_number), 3182 DEVMETHOD(ntb_peer_port_idx, intel_ntb_peer_port_idx), 3183 DEVMETHOD(ntb_link_is_up, intel_ntb_link_is_up), 3184 DEVMETHOD(ntb_link_enable, intel_ntb_link_enable), 3185 DEVMETHOD(ntb_link_disable, intel_ntb_link_disable), 3186 DEVMETHOD(ntb_link_enabled, intel_ntb_link_enabled), 3187 DEVMETHOD(ntb_mw_count, intel_ntb_mw_count), 3188 DEVMETHOD(ntb_mw_get_range, intel_ntb_mw_get_range), 3189 DEVMETHOD(ntb_mw_set_trans, intel_ntb_mw_set_trans), 3190 DEVMETHOD(ntb_mw_clear_trans, intel_ntb_mw_clear_trans), 3191 DEVMETHOD(ntb_mw_get_wc, intel_ntb_mw_get_wc), 3192 DEVMETHOD(ntb_mw_set_wc, intel_ntb_mw_set_wc), 3193 DEVMETHOD(ntb_spad_count, intel_ntb_spad_count), 3194 DEVMETHOD(ntb_spad_clear, intel_ntb_spad_clear), 3195 DEVMETHOD(ntb_spad_write, intel_ntb_spad_write), 3196 DEVMETHOD(ntb_spad_read, intel_ntb_spad_read), 3197 DEVMETHOD(ntb_peer_spad_write, intel_ntb_peer_spad_write), 3198 DEVMETHOD(ntb_peer_spad_read, intel_ntb_peer_spad_read), 3199 DEVMETHOD(ntb_db_valid_mask, intel_ntb_db_valid_mask), 3200 DEVMETHOD(ntb_db_vector_count, intel_ntb_db_vector_count), 3201 DEVMETHOD(ntb_db_vector_mask, intel_ntb_db_vector_mask), 3202 DEVMETHOD(ntb_db_clear, intel_ntb_db_clear), 3203 DEVMETHOD(ntb_db_clear_mask, intel_ntb_db_clear_mask), 3204 DEVMETHOD(ntb_db_read, intel_ntb_db_read), 3205 DEVMETHOD(ntb_db_set_mask, intel_ntb_db_set_mask), 3206 DEVMETHOD(ntb_peer_db_addr, intel_ntb_peer_db_addr), 3207 DEVMETHOD(ntb_peer_db_set, intel_ntb_peer_db_set), 3208 DEVMETHOD_END 3209 }; 3210 3211 static DEFINE_CLASS_0(ntb_hw, ntb_intel_driver, ntb_intel_methods, 3212 sizeof(struct ntb_softc)); 3213 DRIVER_MODULE(ntb_hw_intel, pci, ntb_intel_driver, ntb_hw_devclass, NULL, NULL); 3214 MODULE_DEPEND(ntb_hw_intel, ntb, 1, 1, 1); 3215 MODULE_VERSION(ntb_hw_intel, 1); 3216 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ntb_hw_intel, pci_ids, 3217 nitems(pci_ids)); 3218