1 /*- 2 * Copyright (c) 2016-2017 Alexander Motin <mav@FreeBSD.org> 3 * Copyright (C) 2013 Intel Corporation 4 * Copyright (C) 2015 EMC Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * The Non-Transparent Bridge (NTB) is a device that allows you to connect 31 * two or more systems using a PCI-e links, providing remote memory access. 32 * 33 * This module contains a driver for NTB hardware in Intel Xeon/Atom CPUs. 34 * 35 * NOTE: Much of the code in this module is shared with Linux. Any patches may 36 * be picked up and redistributed in Linux with a dual GPL/BSD license. 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/kernel.h> 44 #include <sys/systm.h> 45 #include <sys/bus.h> 46 #include <sys/endian.h> 47 #include <sys/interrupt.h> 48 #include <sys/lock.h> 49 #include <sys/malloc.h> 50 #include <sys/module.h> 51 #include <sys/mutex.h> 52 #include <sys/pciio.h> 53 #include <sys/taskqueue.h> 54 #include <sys/tree.h> 55 #include <sys/queue.h> 56 #include <sys/rman.h> 57 #include <sys/sbuf.h> 58 #include <sys/sysctl.h> 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 #include <machine/bus.h> 62 #include <machine/intr_machdep.h> 63 #include <machine/resource.h> 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 #include <dev/iommu/iommu.h> 67 68 #include "ntb_hw_intel.h" 69 #include "../ntb.h" 70 71 #define MAX_MSIX_INTERRUPTS \ 72 MAX(MAX(XEON_DB_COUNT, ATOM_DB_COUNT), XEON_GEN3_DB_COUNT) 73 74 #define NTB_HB_TIMEOUT 1 /* second */ 75 #define ATOM_LINK_RECOVERY_TIME 500 /* ms */ 76 #define BAR_HIGH_MASK (~((1ull << 12) - 1)) 77 78 #define NTB_MSIX_VER_GUARD 0xaabbccdd 79 #define NTB_MSIX_RECEIVED 0xe0f0e0f0 80 81 /* 82 * PCI constants could be somewhere more generic, but aren't defined/used in 83 * pci.c. 84 */ 85 #define PCI_MSIX_ENTRY_SIZE 16 86 #define PCI_MSIX_ENTRY_LOWER_ADDR 0 87 #define PCI_MSIX_ENTRY_UPPER_ADDR 4 88 #define PCI_MSIX_ENTRY_DATA 8 89 90 enum ntb_device_type { 91 NTB_XEON_GEN1, 92 NTB_XEON_GEN3, 93 NTB_ATOM 94 }; 95 96 /* ntb_conn_type are hardware numbers, cannot change. */ 97 enum ntb_conn_type { 98 NTB_CONN_TRANSPARENT = 0, 99 NTB_CONN_B2B = 1, 100 NTB_CONN_RP = 2, 101 }; 102 103 enum ntb_b2b_direction { 104 NTB_DEV_USD = 0, 105 NTB_DEV_DSD = 1, 106 }; 107 108 enum ntb_bar { 109 NTB_CONFIG_BAR = 0, 110 NTB_B2B_BAR_1, 111 NTB_B2B_BAR_2, 112 NTB_B2B_BAR_3, 113 NTB_MAX_BARS 114 }; 115 116 enum { 117 NTB_MSIX_GUARD = 0, 118 NTB_MSIX_DATA0, 119 NTB_MSIX_DATA1, 120 NTB_MSIX_DATA2, 121 NTB_MSIX_OFS0, 122 NTB_MSIX_OFS1, 123 NTB_MSIX_OFS2, 124 NTB_MSIX_DONE, 125 NTB_MAX_MSIX_SPAD 126 }; 127 128 /* Device features and workarounds */ 129 #define HAS_FEATURE(ntb, feature) \ 130 (((ntb)->features & (feature)) != 0) 131 132 struct ntb_hw_info { 133 uint32_t device_id; 134 const char *desc; 135 enum ntb_device_type type; 136 uint32_t features; 137 }; 138 139 struct ntb_pci_bar_info { 140 bus_space_tag_t pci_bus_tag; 141 bus_space_handle_t pci_bus_handle; 142 int pci_resource_id; 143 struct resource *pci_resource; 144 vm_paddr_t pbase; 145 caddr_t vbase; 146 vm_size_t size; 147 vm_memattr_t map_mode; 148 149 /* Configuration register offsets */ 150 uint32_t psz_off; 151 uint32_t ssz_off; 152 uint32_t pbarxlat_off; 153 }; 154 155 struct ntb_int_info { 156 struct resource *res; 157 int rid; 158 void *tag; 159 }; 160 161 struct ntb_vec { 162 struct ntb_softc *ntb; 163 uint32_t num; 164 unsigned masked; 165 }; 166 167 struct ntb_reg { 168 uint32_t ntb_ctl; 169 uint32_t lnk_sta; 170 uint8_t db_size; 171 unsigned mw_bar[NTB_MAX_BARS]; 172 }; 173 174 struct ntb_alt_reg { 175 uint32_t db_bell; 176 uint32_t db_mask; 177 uint32_t spad; 178 }; 179 180 struct ntb_xlat_reg { 181 uint32_t bar0_base; 182 uint32_t bar2_base; 183 uint32_t bar4_base; 184 uint32_t bar5_base; 185 186 uint32_t bar2_xlat; 187 uint32_t bar4_xlat; 188 uint32_t bar5_xlat; 189 190 uint32_t bar2_limit; 191 uint32_t bar4_limit; 192 uint32_t bar5_limit; 193 }; 194 195 struct ntb_b2b_addr { 196 uint64_t bar0_addr; 197 uint64_t bar2_addr64; 198 uint64_t bar4_addr64; 199 uint64_t bar4_addr32; 200 uint64_t bar5_addr32; 201 }; 202 203 struct ntb_msix_data { 204 uint32_t nmd_ofs; 205 uint32_t nmd_data; 206 }; 207 208 struct ntb_softc { 209 /* ntb.c context. Do not move! Must go first! */ 210 void *ntb_store; 211 212 device_t device; 213 enum ntb_device_type type; 214 uint32_t features; 215 216 struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 217 struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 218 uint32_t allocated_interrupts; 219 220 struct ntb_msix_data peer_msix_data[XEON_NONLINK_DB_MSIX_BITS]; 221 struct ntb_msix_data msix_data[XEON_NONLINK_DB_MSIX_BITS]; 222 bool peer_msix_good; 223 bool peer_msix_done; 224 struct ntb_pci_bar_info *peer_lapic_bar; 225 struct callout peer_msix_work; 226 227 bus_dma_tag_t bar0_dma_tag; 228 bus_dmamap_t bar0_dma_map; 229 230 struct callout heartbeat_timer; 231 struct callout lr_timer; 232 233 struct ntb_vec *msix_vec; 234 235 uint32_t ppd; 236 enum ntb_conn_type conn_type; 237 enum ntb_b2b_direction dev_type; 238 239 /* Offset of peer bar0 in B2B BAR */ 240 uint64_t b2b_off; 241 /* Memory window used to access peer bar0 */ 242 #define B2B_MW_DISABLED UINT8_MAX 243 uint8_t b2b_mw_idx; 244 uint32_t msix_xlat; 245 uint8_t msix_mw_idx; 246 247 uint8_t mw_count; 248 uint8_t spad_count; 249 uint8_t db_count; 250 uint8_t db_vec_count; 251 uint8_t db_vec_shift; 252 253 /* Protects local db_mask. */ 254 #define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 255 #define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 256 #define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) 257 struct mtx db_mask_lock; 258 259 volatile uint32_t ntb_ctl; 260 volatile uint32_t lnk_sta; 261 262 uint64_t db_valid_mask; 263 uint64_t db_link_mask; 264 uint64_t db_mask; 265 uint64_t fake_db; /* NTB_SB01BASE_LOCKUP*/ 266 uint64_t force_db; /* NTB_SB01BASE_LOCKUP*/ 267 268 int last_ts; /* ticks @ last irq */ 269 270 const struct ntb_reg *reg; 271 const struct ntb_alt_reg *self_reg; 272 const struct ntb_alt_reg *peer_reg; 273 const struct ntb_xlat_reg *xlat_reg; 274 }; 275 276 #ifdef __i386__ 277 static __inline uint64_t 278 bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 279 bus_size_t offset) 280 { 281 282 return (bus_space_read_4(tag, handle, offset) | 283 ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); 284 } 285 286 static __inline void 287 bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, 288 bus_size_t offset, uint64_t val) 289 { 290 291 bus_space_write_4(tag, handle, offset, val); 292 bus_space_write_4(tag, handle, offset + 4, val >> 32); 293 } 294 #endif 295 296 #define intel_ntb_bar_read(SIZE, bar, offset) \ 297 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 298 ntb->bar_info[(bar)].pci_bus_handle, (offset)) 299 #define intel_ntb_bar_write(SIZE, bar, offset, val) \ 300 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 301 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 302 #define intel_ntb_reg_read(SIZE, offset) \ 303 intel_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 304 #define intel_ntb_reg_write(SIZE, offset, val) \ 305 intel_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 306 #define intel_ntb_mw_read(SIZE, offset) \ 307 intel_ntb_bar_read(SIZE, intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 308 offset) 309 #define intel_ntb_mw_write(SIZE, offset, val) \ 310 intel_ntb_bar_write(SIZE, intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 311 offset, val) 312 313 static int intel_ntb_probe(device_t device); 314 static int intel_ntb_attach(device_t device); 315 static int intel_ntb_detach(device_t device); 316 static uint64_t intel_ntb_db_valid_mask(device_t dev); 317 static void intel_ntb_spad_clear(device_t dev); 318 static uint64_t intel_ntb_db_vector_mask(device_t dev, uint32_t vector); 319 static bool intel_ntb_link_is_up(device_t dev, enum ntb_speed *speed, 320 enum ntb_width *width); 321 static int intel_ntb_link_enable(device_t dev, enum ntb_speed speed, 322 enum ntb_width width); 323 static int intel_ntb_link_disable(device_t dev); 324 static int intel_ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val); 325 static int intel_ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val); 326 327 static unsigned intel_ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx); 328 static inline enum ntb_bar intel_ntb_mw_to_bar(struct ntb_softc *, unsigned mw); 329 static inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); 330 static inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, 331 uint32_t *base, uint32_t *xlat, uint32_t *lmt); 332 static int intel_ntb_map_pci_bars(struct ntb_softc *ntb); 333 static int intel_ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx, 334 vm_memattr_t); 335 static void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, 336 const char *); 337 static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 338 static int map_memory_window_bar(struct ntb_softc *ntb, 339 struct ntb_pci_bar_info *bar); 340 static void intel_ntb_unmap_pci_bar(struct ntb_softc *ntb); 341 static int intel_ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); 342 static int intel_ntb_init_isr(struct ntb_softc *ntb); 343 static int intel_ntb_xeon_gen3_init_isr(struct ntb_softc *ntb); 344 static int intel_ntb_setup_legacy_interrupt(struct ntb_softc *ntb); 345 static int intel_ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); 346 static void intel_ntb_teardown_interrupts(struct ntb_softc *ntb); 347 static inline uint64_t intel_ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); 348 static void intel_ntb_interrupt(struct ntb_softc *, uint32_t vec); 349 static void ndev_vec_isr(void *arg); 350 static void ndev_irq_isr(void *arg); 351 static inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); 352 static inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); 353 static inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); 354 static int intel_ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); 355 static void intel_ntb_free_msix_vec(struct ntb_softc *ntb); 356 static void intel_ntb_get_msix_info(struct ntb_softc *ntb); 357 static void intel_ntb_exchange_msix(void *); 358 static struct ntb_hw_info *intel_ntb_get_device_info(uint32_t device_id); 359 static void intel_ntb_detect_max_mw(struct ntb_softc *ntb); 360 static int intel_ntb_detect_xeon(struct ntb_softc *ntb); 361 static int intel_ntb_detect_xeon_gen3(struct ntb_softc *ntb); 362 static int intel_ntb_detect_atom(struct ntb_softc *ntb); 363 static int intel_ntb_xeon_init_dev(struct ntb_softc *ntb); 364 static int intel_ntb_xeon_gen3_init_dev(struct ntb_softc *ntb); 365 static int intel_ntb_atom_init_dev(struct ntb_softc *ntb); 366 static void intel_ntb_teardown_xeon(struct ntb_softc *ntb); 367 static void configure_atom_secondary_side_bars(struct ntb_softc *ntb); 368 static void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, 369 enum ntb_bar regbar); 370 static void xeon_set_sbar_base_and_limit(struct ntb_softc *, 371 uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); 372 static void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, 373 enum ntb_bar idx); 374 static int xeon_setup_b2b_mw(struct ntb_softc *, 375 const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); 376 static int xeon_gen3_setup_b2b_mw(struct ntb_softc *); 377 static int intel_ntb_mw_set_trans(device_t dev, unsigned idx, bus_addr_t addr, 378 size_t size); 379 static inline bool link_is_up(struct ntb_softc *ntb); 380 static inline bool _xeon_link_is_up(struct ntb_softc *ntb); 381 static inline bool atom_link_is_err(struct ntb_softc *ntb); 382 static inline enum ntb_speed intel_ntb_link_sta_speed(struct ntb_softc *); 383 static inline enum ntb_width intel_ntb_link_sta_width(struct ntb_softc *); 384 static void atom_link_hb(void *arg); 385 static void recover_atom_link(void *arg); 386 static bool intel_ntb_poll_link(struct ntb_softc *ntb); 387 static void save_bar_parameters(struct ntb_pci_bar_info *bar); 388 static void intel_ntb_sysctl_init(struct ntb_softc *); 389 static int sysctl_handle_features(SYSCTL_HANDLER_ARGS); 390 static int sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS); 391 static int sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS); 392 static int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); 393 static int sysctl_handle_register(SYSCTL_HANDLER_ARGS); 394 395 static unsigned g_ntb_hw_debug_level; 396 SYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, 397 &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose"); 398 #define intel_ntb_printf(lvl, ...) do { \ 399 if ((lvl) <= g_ntb_hw_debug_level) { \ 400 device_printf(ntb->device, __VA_ARGS__); \ 401 } \ 402 } while (0) 403 404 #define _NTB_PAT_UC 0 405 #define _NTB_PAT_WC 1 406 #define _NTB_PAT_WT 4 407 #define _NTB_PAT_WP 5 408 #define _NTB_PAT_WB 6 409 #define _NTB_PAT_UCM 7 410 static unsigned g_ntb_mw_pat = _NTB_PAT_UC; 411 SYSCTL_UINT(_hw_ntb, OID_AUTO, default_mw_pat, CTLFLAG_RDTUN, 412 &g_ntb_mw_pat, 0, "Configure the default memory window cache flags (PAT): " 413 "UC: " __XSTRING(_NTB_PAT_UC) ", " 414 "WC: " __XSTRING(_NTB_PAT_WC) ", " 415 "WT: " __XSTRING(_NTB_PAT_WT) ", " 416 "WP: " __XSTRING(_NTB_PAT_WP) ", " 417 "WB: " __XSTRING(_NTB_PAT_WB) ", " 418 "UC-: " __XSTRING(_NTB_PAT_UCM)); 419 420 static inline vm_memattr_t 421 intel_ntb_pat_flags(void) 422 { 423 424 switch (g_ntb_mw_pat) { 425 case _NTB_PAT_WC: 426 return (VM_MEMATTR_WRITE_COMBINING); 427 case _NTB_PAT_WT: 428 return (VM_MEMATTR_WRITE_THROUGH); 429 case _NTB_PAT_WP: 430 return (VM_MEMATTR_WRITE_PROTECTED); 431 case _NTB_PAT_WB: 432 return (VM_MEMATTR_WRITE_BACK); 433 case _NTB_PAT_UCM: 434 return (VM_MEMATTR_WEAK_UNCACHEABLE); 435 case _NTB_PAT_UC: 436 /* FALLTHROUGH */ 437 default: 438 return (VM_MEMATTR_UNCACHEABLE); 439 } 440 } 441 442 /* 443 * Well, this obviously doesn't belong here, but it doesn't seem to exist 444 * anywhere better yet. 445 */ 446 static inline const char * 447 intel_ntb_vm_memattr_to_str(vm_memattr_t pat) 448 { 449 450 switch (pat) { 451 case VM_MEMATTR_WRITE_COMBINING: 452 return ("WRITE_COMBINING"); 453 case VM_MEMATTR_WRITE_THROUGH: 454 return ("WRITE_THROUGH"); 455 case VM_MEMATTR_WRITE_PROTECTED: 456 return ("WRITE_PROTECTED"); 457 case VM_MEMATTR_WRITE_BACK: 458 return ("WRITE_BACK"); 459 case VM_MEMATTR_WEAK_UNCACHEABLE: 460 return ("UNCACHED"); 461 case VM_MEMATTR_UNCACHEABLE: 462 return ("UNCACHEABLE"); 463 default: 464 return ("UNKNOWN"); 465 } 466 } 467 468 static int g_ntb_msix_idx = 1; 469 SYSCTL_INT(_hw_ntb, OID_AUTO, msix_mw_idx, CTLFLAG_RDTUN, &g_ntb_msix_idx, 470 0, "Use this memory window to access the peer MSIX message complex on " 471 "certain Xeon-based NTB systems, as a workaround for a hardware errata. " 472 "Like b2b_mw_idx, negative values index from the last available memory " 473 "window. (Applies on Xeon platforms with SB01BASE_LOCKUP errata.)"); 474 475 static int g_ntb_mw_idx = -1; 476 SYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx, 477 0, "Use this memory window to access the peer NTB registers. A " 478 "non-negative value starts from the first MW index; a negative value " 479 "starts from the last MW index. The default is -1, i.e., the last " 480 "available memory window. Both sides of the NTB MUST set the same " 481 "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)"); 482 483 /* Hardware owns the low 16 bits of features. */ 484 #define NTB_BAR_SIZE_4K (1 << 0) 485 #define NTB_SDOORBELL_LOCKUP (1 << 1) 486 #define NTB_SB01BASE_LOCKUP (1 << 2) 487 #define NTB_B2BDOORBELL_BIT14 (1 << 3) 488 /* Software/configuration owns the top 16 bits. */ 489 #define NTB_SPLIT_BAR (1ull << 16) 490 #define NTB_ONE_MSIX (1ull << 17) 491 492 #define NTB_FEATURES_STR \ 493 "\20\21SPLIT_BAR4\04B2B_DOORBELL_BIT14\03SB01BASE_LOCKUP" \ 494 "\02SDOORBELL_LOCKUP\01BAR_SIZE_4K" 495 496 static struct ntb_hw_info pci_ids[] = { 497 /* XXX: PS/SS IDs left out until they are supported. */ 498 { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", 499 NTB_ATOM, 0 }, 500 501 { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", 502 NTB_XEON_GEN1, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 503 { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", 504 NTB_XEON_GEN1, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 505 { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", 506 NTB_XEON_GEN1, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 507 NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, 508 { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", 509 NTB_XEON_GEN1, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 510 NTB_SB01BASE_LOCKUP }, 511 { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", 512 NTB_XEON_GEN1, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 513 NTB_SB01BASE_LOCKUP }, 514 515 { 0x201C8086, "SKL Xeon E5 V5 Non-Transparent Bridge B2B", 516 NTB_XEON_GEN3, 0 }, 517 }; 518 519 static const struct ntb_reg atom_reg = { 520 .ntb_ctl = ATOM_NTBCNTL_OFFSET, 521 .lnk_sta = ATOM_LINK_STATUS_OFFSET, 522 .db_size = sizeof(uint64_t), 523 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 524 }; 525 526 static const struct ntb_alt_reg atom_pri_reg = { 527 .db_bell = ATOM_PDOORBELL_OFFSET, 528 .db_mask = ATOM_PDBMSK_OFFSET, 529 .spad = ATOM_SPAD_OFFSET, 530 }; 531 532 static const struct ntb_alt_reg atom_b2b_reg = { 533 .db_bell = ATOM_B2B_DOORBELL_OFFSET, 534 .spad = ATOM_B2B_SPAD_OFFSET, 535 }; 536 537 static const struct ntb_xlat_reg atom_sec_xlat = { 538 #if 0 539 /* "FIXME" says the Linux driver. */ 540 .bar0_base = ATOM_SBAR0BASE_OFFSET, 541 .bar2_base = ATOM_SBAR2BASE_OFFSET, 542 .bar4_base = ATOM_SBAR4BASE_OFFSET, 543 544 .bar2_limit = ATOM_SBAR2LMT_OFFSET, 545 .bar4_limit = ATOM_SBAR4LMT_OFFSET, 546 #endif 547 548 .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, 549 .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, 550 }; 551 552 static const struct ntb_reg xeon_reg = { 553 .ntb_ctl = XEON_NTBCNTL_OFFSET, 554 .lnk_sta = XEON_LINK_STATUS_OFFSET, 555 .db_size = sizeof(uint16_t), 556 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, 557 }; 558 559 static const struct ntb_alt_reg xeon_pri_reg = { 560 .db_bell = XEON_PDOORBELL_OFFSET, 561 .db_mask = XEON_PDBMSK_OFFSET, 562 .spad = XEON_SPAD_OFFSET, 563 }; 564 565 static const struct ntb_alt_reg xeon_b2b_reg = { 566 .db_bell = XEON_B2B_DOORBELL_OFFSET, 567 .spad = XEON_B2B_SPAD_OFFSET, 568 }; 569 570 static const struct ntb_xlat_reg xeon_sec_xlat = { 571 .bar0_base = XEON_SBAR0BASE_OFFSET, 572 .bar2_base = XEON_SBAR2BASE_OFFSET, 573 .bar4_base = XEON_SBAR4BASE_OFFSET, 574 .bar5_base = XEON_SBAR5BASE_OFFSET, 575 576 .bar2_limit = XEON_SBAR2LMT_OFFSET, 577 .bar4_limit = XEON_SBAR4LMT_OFFSET, 578 .bar5_limit = XEON_SBAR5LMT_OFFSET, 579 580 .bar2_xlat = XEON_SBAR2XLAT_OFFSET, 581 .bar4_xlat = XEON_SBAR4XLAT_OFFSET, 582 .bar5_xlat = XEON_SBAR5XLAT_OFFSET, 583 }; 584 585 static struct ntb_b2b_addr xeon_b2b_usd_addr = { 586 .bar0_addr = XEON_B2B_BAR0_ADDR, 587 .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 588 .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 589 .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 590 .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 591 }; 592 593 static struct ntb_b2b_addr xeon_b2b_dsd_addr = { 594 .bar0_addr = XEON_B2B_BAR0_ADDR, 595 .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 596 .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 597 .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 598 .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 599 }; 600 601 static const struct ntb_reg xeon_gen3_reg = { 602 .ntb_ctl = XEON_GEN3_REG_IMNTB_CTRL, 603 .lnk_sta = XEON_GEN3_INT_LNK_STS_OFFSET, 604 .db_size = sizeof(uint32_t), 605 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 606 }; 607 608 static const struct ntb_alt_reg xeon_gen3_pri_reg = { 609 .db_bell = XEON_GEN3_REG_EMDOORBELL, 610 .db_mask = XEON_GEN3_REG_IMINT_DISABLE, 611 .spad = XEON_GEN3_REG_IMSPAD, 612 }; 613 614 static const struct ntb_alt_reg xeon_gen3_b2b_reg = { 615 .db_bell = XEON_GEN3_REG_IMDOORBELL, 616 .db_mask = XEON_GEN3_REG_EMINT_DISABLE, 617 .spad = XEON_GEN3_REG_IMB2B_SSPAD, 618 }; 619 620 static const struct ntb_xlat_reg xeon_gen3_sec_xlat = { 621 .bar0_base = XEON_GEN3_EXT_REG_BAR0BASE, 622 .bar2_base = XEON_GEN3_EXT_REG_BAR1BASE, 623 .bar4_base = XEON_GEN3_EXT_REG_BAR2BASE, 624 625 .bar2_limit = XEON_GEN3_REG_IMBAR1XLIMIT, 626 .bar4_limit = XEON_GEN3_REG_IMBAR2XLIMIT, 627 628 .bar2_xlat = XEON_GEN3_REG_IMBAR1XBASE, 629 .bar4_xlat = XEON_GEN3_REG_IMBAR2XBASE, 630 }; 631 632 SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 633 "B2B MW segment overrides -- MUST be the same on both sides"); 634 635 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, 636 &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 637 "hardware, use this 64-bit address on the bus between the NTB devices for " 638 "the window at BAR2, on the upstream side of the link. MUST be the same " 639 "address on both sides."); 640 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, 641 &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); 642 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, 643 &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " 644 "(split-BAR mode)."); 645 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, 646 &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " 647 "(split-BAR mode)."); 648 649 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, 650 &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 651 "hardware, use this 64-bit address on the bus between the NTB devices for " 652 "the window at BAR2, on the downstream side of the link. MUST be the same" 653 " address on both sides."); 654 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, 655 &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); 656 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, 657 &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " 658 "(split-BAR mode)."); 659 SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, 660 &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " 661 "(split-BAR mode)."); 662 663 /* 664 * OS <-> Driver interface structures 665 */ 666 MALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 667 668 /* 669 * OS <-> Driver linkage functions 670 */ 671 static int 672 intel_ntb_probe(device_t device) 673 { 674 struct ntb_hw_info *p; 675 676 p = intel_ntb_get_device_info(pci_get_devid(device)); 677 if (p == NULL) 678 return (ENXIO); 679 680 device_set_desc(device, p->desc); 681 return (0); 682 } 683 684 static int 685 intel_ntb_attach(device_t device) 686 { 687 struct ntb_softc *ntb; 688 struct ntb_hw_info *p; 689 int error; 690 691 ntb = device_get_softc(device); 692 p = intel_ntb_get_device_info(pci_get_devid(device)); 693 694 ntb->device = device; 695 ntb->type = p->type; 696 ntb->features = p->features; 697 ntb->b2b_mw_idx = B2B_MW_DISABLED; 698 ntb->msix_mw_idx = B2B_MW_DISABLED; 699 700 /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ 701 callout_init(&ntb->heartbeat_timer, 1); 702 callout_init(&ntb->lr_timer, 1); 703 callout_init(&ntb->peer_msix_work, 1); 704 mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); 705 706 if (ntb->type == NTB_ATOM) 707 error = intel_ntb_detect_atom(ntb); 708 else if (ntb->type == NTB_XEON_GEN3) 709 error = intel_ntb_detect_xeon_gen3(ntb); 710 else 711 error = intel_ntb_detect_xeon(ntb); 712 if (error != 0) 713 goto out; 714 715 intel_ntb_detect_max_mw(ntb); 716 717 pci_enable_busmaster(ntb->device); 718 719 error = intel_ntb_map_pci_bars(ntb); 720 if (error != 0) 721 goto out; 722 if (ntb->type == NTB_ATOM) 723 error = intel_ntb_atom_init_dev(ntb); 724 else if (ntb->type == NTB_XEON_GEN3) 725 error = intel_ntb_xeon_gen3_init_dev(ntb); 726 else 727 error = intel_ntb_xeon_init_dev(ntb); 728 if (error != 0) 729 goto out; 730 731 intel_ntb_spad_clear(device); 732 733 intel_ntb_poll_link(ntb); 734 735 intel_ntb_sysctl_init(ntb); 736 737 /* Attach children to this controller */ 738 error = ntb_register_device(device); 739 740 out: 741 if (error != 0) 742 intel_ntb_detach(device); 743 return (error); 744 } 745 746 static int 747 intel_ntb_detach(device_t device) 748 { 749 struct ntb_softc *ntb; 750 751 ntb = device_get_softc(device); 752 753 /* Detach & delete all children */ 754 ntb_unregister_device(device); 755 756 if (ntb->self_reg != NULL) { 757 DB_MASK_LOCK(ntb); 758 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_valid_mask); 759 DB_MASK_UNLOCK(ntb); 760 } 761 callout_drain(&ntb->heartbeat_timer); 762 callout_drain(&ntb->lr_timer); 763 callout_drain(&ntb->peer_msix_work); 764 pci_disable_busmaster(ntb->device); 765 if (ntb->type == NTB_XEON_GEN1) 766 intel_ntb_teardown_xeon(ntb); 767 intel_ntb_teardown_interrupts(ntb); 768 769 mtx_destroy(&ntb->db_mask_lock); 770 771 intel_ntb_unmap_pci_bar(ntb); 772 773 return (0); 774 } 775 776 /* 777 * Driver internal routines 778 */ 779 static inline enum ntb_bar 780 intel_ntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) 781 { 782 783 KASSERT(mw < ntb->mw_count, 784 ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); 785 KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); 786 787 return (ntb->reg->mw_bar[mw]); 788 } 789 790 static inline bool 791 bar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) 792 { 793 /* XXX This assertion could be stronger. */ 794 KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); 795 return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(ntb, NTB_SPLIT_BAR)); 796 } 797 798 static inline void 799 bar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, 800 uint32_t *xlat, uint32_t *lmt) 801 { 802 uint32_t basev, lmtv, xlatv; 803 804 switch (bar) { 805 case NTB_B2B_BAR_1: 806 basev = ntb->xlat_reg->bar2_base; 807 lmtv = ntb->xlat_reg->bar2_limit; 808 xlatv = ntb->xlat_reg->bar2_xlat; 809 break; 810 case NTB_B2B_BAR_2: 811 basev = ntb->xlat_reg->bar4_base; 812 lmtv = ntb->xlat_reg->bar4_limit; 813 xlatv = ntb->xlat_reg->bar4_xlat; 814 break; 815 case NTB_B2B_BAR_3: 816 basev = ntb->xlat_reg->bar5_base; 817 lmtv = ntb->xlat_reg->bar5_limit; 818 xlatv = ntb->xlat_reg->bar5_xlat; 819 break; 820 default: 821 KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, 822 ("bad bar")); 823 basev = lmtv = xlatv = 0; 824 break; 825 } 826 827 if (base != NULL) 828 *base = basev; 829 if (xlat != NULL) 830 *xlat = xlatv; 831 if (lmt != NULL) 832 *lmt = lmtv; 833 } 834 835 static int 836 intel_ntb_map_pci_bars(struct ntb_softc *ntb) 837 { 838 struct ntb_pci_bar_info *bar; 839 int rc; 840 841 bar = &ntb->bar_info[NTB_CONFIG_BAR]; 842 bar->pci_resource_id = PCIR_BAR(0); 843 rc = map_mmr_bar(ntb, bar); 844 if (rc != 0) 845 goto out; 846 847 /* 848 * At least on Xeon v4 NTB device leaks to host some remote side 849 * BAR0 writes supposed to update scratchpad registers. I am not 850 * sure why it happens, but it may be related to the fact that 851 * on a link side BAR0 is 32KB, while on a host side it is 64KB. 852 * Without this hack DMAR blocks those accesses as not allowed. 853 */ 854 if (bus_dma_tag_create(bus_get_dma_tag(ntb->device), 1, 0, 855 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 856 bar->size, 1, bar->size, 0, NULL, NULL, &ntb->bar0_dma_tag)) { 857 device_printf(ntb->device, "Unable to create BAR0 tag\n"); 858 return (ENOMEM); 859 } 860 if (bus_dmamap_create(ntb->bar0_dma_tag, 0, &ntb->bar0_dma_map)) { 861 device_printf(ntb->device, "Unable to create BAR0 map\n"); 862 return (ENOMEM); 863 } 864 if (bus_dma_iommu_load_ident(ntb->bar0_dma_tag, ntb->bar0_dma_map, 865 bar->pbase, bar->size, 0)) { 866 device_printf(ntb->device, "Unable to load BAR0 map\n"); 867 return (ENOMEM); 868 } 869 870 bar = &ntb->bar_info[NTB_B2B_BAR_1]; 871 bar->pci_resource_id = PCIR_BAR(2); 872 rc = map_memory_window_bar(ntb, bar); 873 if (rc != 0) 874 goto out; 875 if (ntb->type == NTB_XEON_GEN3) { 876 bar->psz_off = XEON_GEN3_INT_REG_IMBAR1SZ; 877 bar->ssz_off = XEON_GEN3_INT_REG_EMBAR1SZ; 878 bar->pbarxlat_off = XEON_GEN3_REG_EMBAR1XBASE; 879 } else { 880 bar->psz_off = XEON_PBAR23SZ_OFFSET; 881 bar->ssz_off = XEON_SBAR23SZ_OFFSET; 882 bar->pbarxlat_off = XEON_PBAR2XLAT_OFFSET; 883 } 884 885 bar = &ntb->bar_info[NTB_B2B_BAR_2]; 886 bar->pci_resource_id = PCIR_BAR(4); 887 rc = map_memory_window_bar(ntb, bar); 888 if (rc != 0) 889 goto out; 890 if (ntb->type == NTB_XEON_GEN3) { 891 bar->psz_off = XEON_GEN3_INT_REG_IMBAR2SZ; 892 bar->ssz_off = XEON_GEN3_INT_REG_EMBAR2SZ; 893 bar->pbarxlat_off = XEON_GEN3_REG_EMBAR2XBASE; 894 } else { 895 bar->psz_off = XEON_PBAR4SZ_OFFSET; 896 bar->ssz_off = XEON_SBAR4SZ_OFFSET; 897 bar->pbarxlat_off = XEON_PBAR4XLAT_OFFSET; 898 } 899 900 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 901 goto out; 902 903 if (ntb->type == NTB_XEON_GEN3) { 904 device_printf(ntb->device, "no split bar support\n"); 905 return (ENXIO); 906 } 907 908 bar = &ntb->bar_info[NTB_B2B_BAR_3]; 909 bar->pci_resource_id = PCIR_BAR(5); 910 rc = map_memory_window_bar(ntb, bar); 911 bar->psz_off = XEON_PBAR5SZ_OFFSET; 912 bar->ssz_off = XEON_SBAR5SZ_OFFSET; 913 bar->pbarxlat_off = XEON_PBAR5XLAT_OFFSET; 914 915 out: 916 if (rc != 0) 917 device_printf(ntb->device, 918 "unable to allocate pci resource\n"); 919 return (rc); 920 } 921 922 static void 923 print_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, 924 const char *kind) 925 { 926 927 device_printf(ntb->device, 928 "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", 929 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 930 (char *)bar->vbase + bar->size - 1, 931 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 932 (uintmax_t)bar->size, kind); 933 } 934 935 static int 936 map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 937 { 938 939 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 940 &bar->pci_resource_id, RF_ACTIVE); 941 if (bar->pci_resource == NULL) 942 return (ENXIO); 943 944 save_bar_parameters(bar); 945 bar->map_mode = VM_MEMATTR_UNCACHEABLE; 946 print_map_success(ntb, bar, "mmr"); 947 return (0); 948 } 949 950 static int 951 map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 952 { 953 int rc; 954 vm_memattr_t mapmode; 955 uint8_t bar_size_bits = 0; 956 957 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 958 &bar->pci_resource_id, RF_ACTIVE); 959 960 if (bar->pci_resource == NULL) 961 return (ENXIO); 962 963 save_bar_parameters(bar); 964 /* 965 * Ivytown NTB BAR sizes are misreported by the hardware due to a 966 * hardware issue. To work around this, query the size it should be 967 * configured to by the device and modify the resource to correspond to 968 * this new size. The BIOS on systems with this problem is required to 969 * provide enough address space to allow the driver to make this change 970 * safely. 971 * 972 * Ideally I could have just specified the size when I allocated the 973 * resource like: 974 * bus_alloc_resource(ntb->device, 975 * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 976 * 1ul << bar_size_bits, RF_ACTIVE); 977 * but the PCI driver does not honor the size in this call, so we have 978 * to modify it after the fact. 979 */ 980 if (HAS_FEATURE(ntb, NTB_BAR_SIZE_4K)) { 981 if (bar->pci_resource_id == PCIR_BAR(2)) 982 bar_size_bits = pci_read_config(ntb->device, 983 XEON_PBAR23SZ_OFFSET, 1); 984 else 985 bar_size_bits = pci_read_config(ntb->device, 986 XEON_PBAR45SZ_OFFSET, 1); 987 988 rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 989 bar->pci_resource, bar->pbase, 990 bar->pbase + (1ul << bar_size_bits) - 1); 991 if (rc != 0) { 992 device_printf(ntb->device, 993 "unable to resize bar\n"); 994 return (rc); 995 } 996 997 save_bar_parameters(bar); 998 } 999 1000 bar->map_mode = VM_MEMATTR_UNCACHEABLE; 1001 print_map_success(ntb, bar, "mw"); 1002 1003 /* 1004 * Optionally, mark MW BARs as anything other than UC to improve 1005 * performance. 1006 */ 1007 mapmode = intel_ntb_pat_flags(); 1008 if (mapmode == bar->map_mode) 1009 return (0); 1010 1011 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode); 1012 if (rc == 0) { 1013 bar->map_mode = mapmode; 1014 device_printf(ntb->device, 1015 "Marked BAR%d v:[%p-%p] p:[%p-%p] as " 1016 "%s.\n", 1017 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 1018 (char *)bar->vbase + bar->size - 1, 1019 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 1020 intel_ntb_vm_memattr_to_str(mapmode)); 1021 } else 1022 device_printf(ntb->device, 1023 "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " 1024 "%s: %d\n", 1025 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 1026 (char *)bar->vbase + bar->size - 1, 1027 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 1028 intel_ntb_vm_memattr_to_str(mapmode), rc); 1029 /* Proceed anyway */ 1030 return (0); 1031 } 1032 1033 static void 1034 intel_ntb_unmap_pci_bar(struct ntb_softc *ntb) 1035 { 1036 struct ntb_pci_bar_info *bar; 1037 int i; 1038 1039 if (ntb->bar0_dma_map != NULL) { 1040 bus_dmamap_unload(ntb->bar0_dma_tag, ntb->bar0_dma_map); 1041 bus_dmamap_destroy(ntb->bar0_dma_tag, ntb->bar0_dma_map); 1042 } 1043 if (ntb->bar0_dma_tag != NULL) 1044 bus_dma_tag_destroy(ntb->bar0_dma_tag); 1045 for (i = 0; i < NTB_MAX_BARS; i++) { 1046 bar = &ntb->bar_info[i]; 1047 if (bar->pci_resource != NULL) 1048 bus_release_resource(ntb->device, SYS_RES_MEMORY, 1049 bar->pci_resource_id, bar->pci_resource); 1050 } 1051 } 1052 1053 static int 1054 intel_ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) 1055 { 1056 uint32_t i; 1057 int rc; 1058 1059 for (i = 0; i < num_vectors; i++) { 1060 ntb->int_info[i].rid = i + 1; 1061 ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, 1062 SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); 1063 if (ntb->int_info[i].res == NULL) { 1064 device_printf(ntb->device, 1065 "bus_alloc_resource failed\n"); 1066 return (ENOMEM); 1067 } 1068 ntb->int_info[i].tag = NULL; 1069 ntb->allocated_interrupts++; 1070 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, 1071 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, 1072 &ntb->msix_vec[i], &ntb->int_info[i].tag); 1073 if (rc != 0) { 1074 device_printf(ntb->device, "bus_setup_intr failed\n"); 1075 return (ENXIO); 1076 } 1077 } 1078 return (0); 1079 } 1080 1081 /* 1082 * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector 1083 * cannot be allocated for each MSI-X message. JHB seems to think remapping 1084 * should be okay. This tunable should enable us to test that hypothesis 1085 * when someone gets their hands on some Xeon hardware. 1086 */ 1087 static int ntb_force_remap_mode; 1088 SYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, 1089 &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" 1090 " to a smaller number of ithreads, even if the desired number are " 1091 "available"); 1092 1093 /* 1094 * In case it is NOT ok, give consumers an abort button. 1095 */ 1096 static int ntb_prefer_intx; 1097 SYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, 1098 &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " 1099 "than remapping MSI-X messages over available slots (match Linux driver " 1100 "behavior)"); 1101 1102 /* 1103 * Remap the desired number of MSI-X messages to available ithreads in a simple 1104 * round-robin fashion. 1105 */ 1106 static int 1107 intel_ntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) 1108 { 1109 u_int *vectors; 1110 uint32_t i; 1111 int rc; 1112 1113 if (ntb_prefer_intx != 0) 1114 return (ENXIO); 1115 1116 vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); 1117 1118 for (i = 0; i < desired; i++) 1119 vectors[i] = (i % avail) + 1; 1120 1121 rc = pci_remap_msix(dev, desired, vectors); 1122 free(vectors, M_NTB); 1123 return (rc); 1124 } 1125 1126 static int 1127 intel_ntb_xeon_gen3_init_isr(struct ntb_softc *ntb) 1128 { 1129 uint64_t i, reg; 1130 uint32_t desired_vectors, num_vectors; 1131 int rc; 1132 1133 ntb->allocated_interrupts = 0; 1134 ntb->last_ts = ticks; 1135 1136 /* Mask all the interrupts, including hardware interrupt */ 1137 intel_ntb_reg_write(8, XEON_GEN3_REG_IMINT_DISABLE, ~0ULL); 1138 1139 /* Clear Interrupt Status */ 1140 reg = intel_ntb_reg_read(8, XEON_GEN3_REG_IMINT_STATUS); 1141 intel_ntb_reg_write(8, XEON_GEN3_REG_IMINT_STATUS, reg); 1142 1143 num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 1144 XEON_GEN3_DB_MSIX_VECTOR_COUNT); 1145 1146 rc = pci_alloc_msix(ntb->device, &num_vectors); 1147 if (rc != 0) { 1148 device_printf(ntb->device, 1149 "Interrupt allocation failed %d\n", rc); 1150 return (rc); 1151 } 1152 if (desired_vectors != num_vectors) { 1153 device_printf(ntb->device, "Couldn't get %d vectors\n", 1154 XEON_GEN3_DB_MSIX_VECTOR_COUNT); 1155 return (ENXIO); 1156 } 1157 /* 32 db + 1 hardware */ 1158 if (num_vectors == XEON_GEN3_DB_MSIX_VECTOR_COUNT) { 1159 /* Program INTVECXX source register */ 1160 for (i = 0; i < XEON_GEN3_DB_MSIX_VECTOR_COUNT; i++) { 1161 /* interrupt source i for vector i */ 1162 intel_ntb_reg_write(1, XEON_GEN3_REG_IMINTVEC00 + i, i); 1163 if (i == (XEON_GEN3_DB_MSIX_VECTOR_COUNT - 1)) { 1164 intel_ntb_reg_write(1, 1165 XEON_GEN3_REG_IMINTVEC00 + i, 1166 XEON_GEN3_LINK_VECTOR_INDEX); 1167 } 1168 } 1169 1170 intel_ntb_create_msix_vec(ntb, num_vectors); 1171 rc = intel_ntb_setup_msix(ntb, num_vectors); 1172 1173 /* enable all interrupts */ 1174 intel_ntb_reg_write(8, XEON_GEN3_REG_IMINT_DISABLE, 0ULL); 1175 } else { 1176 device_printf(ntb->device, "need to remap interrupts, giving up.\n"); 1177 return (ENXIO); 1178 } 1179 1180 return (0); 1181 } 1182 1183 static int 1184 intel_ntb_init_isr(struct ntb_softc *ntb) 1185 { 1186 uint32_t desired_vectors, num_vectors; 1187 int rc; 1188 1189 ntb->allocated_interrupts = 0; 1190 ntb->last_ts = ticks; 1191 1192 /* 1193 * Mask all doorbell interrupts. (Except link events!) 1194 */ 1195 DB_MASK_LOCK(ntb); 1196 ntb->db_mask = ntb->db_valid_mask; 1197 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1198 DB_MASK_UNLOCK(ntb); 1199 1200 num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 1201 ntb->db_count); 1202 if (desired_vectors >= 1) { 1203 rc = pci_alloc_msix(ntb->device, &num_vectors); 1204 1205 if (ntb_force_remap_mode != 0 && rc == 0 && 1206 num_vectors == desired_vectors) 1207 num_vectors--; 1208 1209 if (rc == 0 && num_vectors < desired_vectors) { 1210 rc = intel_ntb_remap_msix(ntb->device, desired_vectors, 1211 num_vectors); 1212 if (rc == 0) 1213 num_vectors = desired_vectors; 1214 else 1215 pci_release_msi(ntb->device); 1216 } 1217 if (rc != 0) 1218 num_vectors = 1; 1219 } else 1220 num_vectors = 1; 1221 1222 if (ntb->type == NTB_XEON_GEN1 && num_vectors < ntb->db_vec_count) { 1223 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1224 device_printf(ntb->device, 1225 "Errata workaround does not support MSI or INTX\n"); 1226 return (EINVAL); 1227 } 1228 1229 ntb->db_vec_count = 1; 1230 ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; 1231 rc = intel_ntb_setup_legacy_interrupt(ntb); 1232 } else { 1233 if (num_vectors - 1 != XEON_NONLINK_DB_MSIX_BITS && 1234 HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1235 device_printf(ntb->device, 1236 "Errata workaround expects %d doorbell bits\n", 1237 XEON_NONLINK_DB_MSIX_BITS); 1238 return (EINVAL); 1239 } 1240 1241 intel_ntb_create_msix_vec(ntb, num_vectors); 1242 rc = intel_ntb_setup_msix(ntb, num_vectors); 1243 } 1244 if (rc != 0) { 1245 device_printf(ntb->device, 1246 "Error allocating interrupts: %d\n", rc); 1247 intel_ntb_free_msix_vec(ntb); 1248 } 1249 1250 return (rc); 1251 } 1252 1253 static int 1254 intel_ntb_setup_legacy_interrupt(struct ntb_softc *ntb) 1255 { 1256 int rc; 1257 1258 ntb->int_info[0].rid = 0; 1259 ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, 1260 &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 1261 if (ntb->int_info[0].res == NULL) { 1262 device_printf(ntb->device, "bus_alloc_resource failed\n"); 1263 return (ENOMEM); 1264 } 1265 1266 ntb->int_info[0].tag = NULL; 1267 ntb->allocated_interrupts = 1; 1268 1269 rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, 1270 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, 1271 ntb, &ntb->int_info[0].tag); 1272 if (rc != 0) { 1273 device_printf(ntb->device, "bus_setup_intr failed\n"); 1274 return (ENXIO); 1275 } 1276 1277 return (0); 1278 } 1279 1280 static void 1281 intel_ntb_teardown_interrupts(struct ntb_softc *ntb) 1282 { 1283 struct ntb_int_info *current_int; 1284 int i; 1285 1286 for (i = 0; i < ntb->allocated_interrupts; i++) { 1287 current_int = &ntb->int_info[i]; 1288 if (current_int->tag != NULL) 1289 bus_teardown_intr(ntb->device, current_int->res, 1290 current_int->tag); 1291 1292 if (current_int->res != NULL) 1293 bus_release_resource(ntb->device, SYS_RES_IRQ, 1294 rman_get_rid(current_int->res), current_int->res); 1295 } 1296 1297 intel_ntb_free_msix_vec(ntb); 1298 pci_release_msi(ntb->device); 1299 } 1300 1301 static inline uint64_t 1302 db_ioread(struct ntb_softc *ntb, uint64_t regoff) 1303 { 1304 1305 switch (ntb->type) { 1306 case NTB_ATOM: 1307 case NTB_XEON_GEN3: 1308 return (intel_ntb_reg_read(8, regoff)); 1309 case NTB_XEON_GEN1: 1310 return (intel_ntb_reg_read(2, regoff)); 1311 } 1312 } 1313 1314 static inline void 1315 db_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1316 { 1317 1318 KASSERT((val & ~ntb->db_valid_mask) == 0, 1319 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1320 (uintmax_t)(val & ~ntb->db_valid_mask), 1321 (uintmax_t)ntb->db_valid_mask)); 1322 1323 if (regoff == ntb->self_reg->db_mask) 1324 DB_MASK_ASSERT(ntb, MA_OWNED); 1325 db_iowrite_raw(ntb, regoff, val); 1326 } 1327 1328 static inline void 1329 db_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1330 { 1331 1332 switch (ntb->type) { 1333 case NTB_ATOM: 1334 case NTB_XEON_GEN3: 1335 intel_ntb_reg_write(8, regoff, val); 1336 break; 1337 case NTB_XEON_GEN1: 1338 intel_ntb_reg_write(2, regoff, (uint16_t)val); 1339 break; 1340 } 1341 } 1342 1343 static void 1344 intel_ntb_db_set_mask(device_t dev, uint64_t bits) 1345 { 1346 struct ntb_softc *ntb = device_get_softc(dev); 1347 1348 DB_MASK_LOCK(ntb); 1349 ntb->db_mask |= bits; 1350 if (!HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1351 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1352 DB_MASK_UNLOCK(ntb); 1353 } 1354 1355 static void 1356 intel_ntb_db_clear_mask(device_t dev, uint64_t bits) 1357 { 1358 struct ntb_softc *ntb = device_get_softc(dev); 1359 uint64_t ibits; 1360 int i; 1361 1362 KASSERT((bits & ~ntb->db_valid_mask) == 0, 1363 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1364 (uintmax_t)(bits & ~ntb->db_valid_mask), 1365 (uintmax_t)ntb->db_valid_mask)); 1366 1367 DB_MASK_LOCK(ntb); 1368 ibits = ntb->fake_db & ntb->db_mask & bits; 1369 ntb->db_mask &= ~bits; 1370 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1371 /* Simulate fake interrupts if unmasked DB bits are set. */ 1372 ntb->force_db |= ibits; 1373 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 1374 if ((ibits & intel_ntb_db_vector_mask(dev, i)) != 0) 1375 swi_sched(ntb->int_info[i].tag, 0); 1376 } 1377 } else { 1378 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1379 } 1380 DB_MASK_UNLOCK(ntb); 1381 } 1382 1383 static uint64_t 1384 intel_ntb_db_read(device_t dev) 1385 { 1386 struct ntb_softc *ntb = device_get_softc(dev); 1387 1388 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1389 return (ntb->fake_db); 1390 if (ntb->type == NTB_XEON_GEN3) 1391 return (intel_ntb_reg_read(8, XEON_GEN3_REG_IMINT_STATUS)); 1392 else 1393 return (db_ioread(ntb, ntb->self_reg->db_bell)); 1394 } 1395 1396 static void 1397 intel_ntb_db_clear(device_t dev, uint64_t bits) 1398 { 1399 struct ntb_softc *ntb = device_get_softc(dev); 1400 1401 KASSERT((bits & ~ntb->db_valid_mask) == 0, 1402 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1403 (uintmax_t)(bits & ~ntb->db_valid_mask), 1404 (uintmax_t)ntb->db_valid_mask)); 1405 1406 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1407 DB_MASK_LOCK(ntb); 1408 ntb->fake_db &= ~bits; 1409 DB_MASK_UNLOCK(ntb); 1410 return; 1411 } 1412 1413 if (ntb->type == NTB_XEON_GEN3) 1414 intel_ntb_reg_write(4, XEON_GEN3_REG_IMINT_STATUS, 1415 (uint32_t)bits); 1416 else 1417 db_iowrite(ntb, ntb->self_reg->db_bell, bits); 1418 } 1419 1420 static inline uint64_t 1421 intel_ntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) 1422 { 1423 uint64_t shift, mask; 1424 1425 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1426 /* 1427 * Remap vectors in custom way to make at least first 1428 * three doorbells to not generate stray events. 1429 * This breaks Linux compatibility (if one existed) 1430 * when more then one DB is used (not by if_ntb). 1431 */ 1432 if (db_vector < XEON_NONLINK_DB_MSIX_BITS - 1) 1433 return (1 << db_vector); 1434 if (db_vector == XEON_NONLINK_DB_MSIX_BITS - 1) 1435 return (0x7ffc); 1436 } 1437 1438 shift = ntb->db_vec_shift; 1439 mask = (1ull << shift) - 1; 1440 return (mask << (shift * db_vector)); 1441 } 1442 1443 static void 1444 intel_ntb_interrupt(struct ntb_softc *ntb, uint32_t vec) 1445 { 1446 uint64_t vec_mask; 1447 1448 ntb->last_ts = ticks; 1449 vec_mask = intel_ntb_vec_mask(ntb, vec); 1450 1451 if (ntb->type == NTB_XEON_GEN3 && vec == XEON_GEN3_LINK_VECTOR_INDEX) 1452 vec_mask |= ntb->db_link_mask; 1453 if ((vec_mask & ntb->db_link_mask) != 0) { 1454 if (intel_ntb_poll_link(ntb)) 1455 ntb_link_event(ntb->device); 1456 if (ntb->type == NTB_XEON_GEN3) 1457 intel_ntb_reg_write(8, XEON_GEN3_REG_IMINT_STATUS, 1458 intel_ntb_reg_read(8, XEON_GEN3_REG_IMINT_STATUS)); 1459 } 1460 1461 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) && 1462 (vec_mask & ntb->db_link_mask) == 0) { 1463 DB_MASK_LOCK(ntb); 1464 1465 /* 1466 * Do not report same DB events again if not cleared yet, 1467 * unless the mask was just cleared for them and this 1468 * interrupt handler call can be the consequence of it. 1469 */ 1470 vec_mask &= ~ntb->fake_db | ntb->force_db; 1471 ntb->force_db &= ~vec_mask; 1472 1473 /* Update our internal doorbell register. */ 1474 ntb->fake_db |= vec_mask; 1475 1476 /* Do not report masked DB events. */ 1477 vec_mask &= ~ntb->db_mask; 1478 1479 DB_MASK_UNLOCK(ntb); 1480 } 1481 1482 if ((vec_mask & ntb->db_valid_mask) != 0) 1483 ntb_db_event(ntb->device, vec); 1484 } 1485 1486 static void 1487 ndev_vec_isr(void *arg) 1488 { 1489 struct ntb_vec *nvec = arg; 1490 1491 intel_ntb_interrupt(nvec->ntb, nvec->num); 1492 } 1493 1494 static void 1495 ndev_irq_isr(void *arg) 1496 { 1497 /* If we couldn't set up MSI-X, we only have the one vector. */ 1498 intel_ntb_interrupt(arg, 0); 1499 } 1500 1501 static int 1502 intel_ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) 1503 { 1504 uint32_t i; 1505 1506 ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, 1507 M_ZERO | M_WAITOK); 1508 for (i = 0; i < num_vectors; i++) { 1509 ntb->msix_vec[i].num = i; 1510 ntb->msix_vec[i].ntb = ntb; 1511 } 1512 1513 return (0); 1514 } 1515 1516 static void 1517 intel_ntb_free_msix_vec(struct ntb_softc *ntb) 1518 { 1519 1520 if (ntb->msix_vec == NULL) 1521 return; 1522 1523 free(ntb->msix_vec, M_NTB); 1524 ntb->msix_vec = NULL; 1525 } 1526 1527 static void 1528 intel_ntb_get_msix_info(struct ntb_softc *ntb) 1529 { 1530 struct pci_devinfo *dinfo; 1531 struct pcicfg_msix *msix; 1532 uint32_t laddr, data, i, offset; 1533 1534 dinfo = device_get_ivars(ntb->device); 1535 msix = &dinfo->cfg.msix; 1536 1537 CTASSERT(XEON_NONLINK_DB_MSIX_BITS == nitems(ntb->msix_data)); 1538 1539 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 1540 offset = msix->msix_table_offset + i * PCI_MSIX_ENTRY_SIZE; 1541 1542 laddr = bus_read_4(msix->msix_table_res, offset + 1543 PCI_MSIX_ENTRY_LOWER_ADDR); 1544 intel_ntb_printf(2, "local MSIX addr(%u): 0x%x\n", i, laddr); 1545 1546 KASSERT((laddr & MSI_INTEL_ADDR_BASE) == MSI_INTEL_ADDR_BASE, 1547 ("local MSIX addr 0x%x not in MSI base 0x%x", laddr, 1548 MSI_INTEL_ADDR_BASE)); 1549 ntb->msix_data[i].nmd_ofs = laddr; 1550 1551 data = bus_read_4(msix->msix_table_res, offset + 1552 PCI_MSIX_ENTRY_DATA); 1553 intel_ntb_printf(2, "local MSIX data(%u): 0x%x\n", i, data); 1554 1555 ntb->msix_data[i].nmd_data = data; 1556 } 1557 } 1558 1559 static struct ntb_hw_info * 1560 intel_ntb_get_device_info(uint32_t device_id) 1561 { 1562 struct ntb_hw_info *ep; 1563 1564 for (ep = pci_ids; ep < &pci_ids[nitems(pci_ids)]; ep++) { 1565 if (ep->device_id == device_id) 1566 return (ep); 1567 } 1568 return (NULL); 1569 } 1570 1571 static void 1572 intel_ntb_teardown_xeon(struct ntb_softc *ntb) 1573 { 1574 1575 if (ntb->reg != NULL) 1576 intel_ntb_link_disable(ntb->device); 1577 } 1578 1579 static void 1580 intel_ntb_detect_max_mw(struct ntb_softc *ntb) 1581 { 1582 1583 switch (ntb->type) { 1584 case NTB_ATOM: 1585 ntb->mw_count = ATOM_MW_COUNT; 1586 break; 1587 case NTB_XEON_GEN1: 1588 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1589 ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; 1590 else 1591 ntb->mw_count = XEON_SNB_MW_COUNT; 1592 break; 1593 case NTB_XEON_GEN3: 1594 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1595 ntb->mw_count = XEON_GEN3_SPLIT_MW_COUNT; 1596 else 1597 ntb->mw_count = XEON_GEN3_MW_COUNT; 1598 break; 1599 } 1600 } 1601 1602 static int 1603 intel_ntb_detect_xeon(struct ntb_softc *ntb) 1604 { 1605 uint8_t ppd, conn_type; 1606 1607 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 1608 ntb->ppd = ppd; 1609 1610 if ((ppd & XEON_PPD_DEV_TYPE) != 0) 1611 ntb->dev_type = NTB_DEV_DSD; 1612 else 1613 ntb->dev_type = NTB_DEV_USD; 1614 1615 if ((ppd & XEON_PPD_SPLIT_BAR) != 0) 1616 ntb->features |= NTB_SPLIT_BAR; 1617 1618 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) && 1619 !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1620 device_printf(ntb->device, 1621 "Can not apply SB01BASE_LOCKUP workaround " 1622 "with split BARs disabled!\n"); 1623 device_printf(ntb->device, 1624 "Expect system hangs under heavy NTB traffic!\n"); 1625 ntb->features &= ~NTB_SB01BASE_LOCKUP; 1626 } 1627 1628 /* 1629 * SDOORBELL errata workaround gets in the way of SB01BASE_LOCKUP 1630 * errata workaround; only do one at a time. 1631 */ 1632 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1633 ntb->features &= ~NTB_SDOORBELL_LOCKUP; 1634 1635 conn_type = ppd & XEON_PPD_CONN_TYPE; 1636 switch (conn_type) { 1637 case NTB_CONN_B2B: 1638 ntb->conn_type = conn_type; 1639 break; 1640 case NTB_CONN_RP: 1641 case NTB_CONN_TRANSPARENT: 1642 default: 1643 device_printf(ntb->device, "Unsupported connection type: %u\n", 1644 (unsigned)conn_type); 1645 return (ENXIO); 1646 } 1647 return (0); 1648 } 1649 1650 static int 1651 intel_ntb_detect_atom(struct ntb_softc *ntb) 1652 { 1653 uint32_t ppd, conn_type; 1654 1655 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 1656 ntb->ppd = ppd; 1657 1658 if ((ppd & ATOM_PPD_DEV_TYPE) != 0) 1659 ntb->dev_type = NTB_DEV_DSD; 1660 else 1661 ntb->dev_type = NTB_DEV_USD; 1662 1663 conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; 1664 switch (conn_type) { 1665 case NTB_CONN_B2B: 1666 ntb->conn_type = conn_type; 1667 break; 1668 default: 1669 device_printf(ntb->device, "Unsupported NTB configuration\n"); 1670 return (ENXIO); 1671 } 1672 return (0); 1673 } 1674 1675 static int 1676 intel_ntb_detect_xeon_gen3(struct ntb_softc *ntb) 1677 { 1678 uint8_t ppd, conn_type; 1679 1680 ppd = pci_read_config(ntb->device, XEON_GEN3_INT_REG_PPD, 1); 1681 ntb->ppd = ppd; 1682 1683 /* check port definition */ 1684 conn_type = XEON_GEN3_REG_PPD_PORT_DEF_F(ppd); 1685 switch (conn_type) { 1686 case NTB_CONN_B2B: 1687 ntb->conn_type = conn_type; 1688 break; 1689 default: 1690 device_printf(ntb->device, "Unsupported connection type: %u\n", 1691 conn_type); 1692 return (ENXIO); 1693 } 1694 1695 /* check cross link configuration status */ 1696 if (XEON_GEN3_REG_PPD_CONF_STS_F(ppd)) { 1697 /* NTB Port is configured as DSD/USP */ 1698 ntb->dev_type = NTB_DEV_DSD; 1699 } else { 1700 /* NTB Port is configured as USD/DSP */ 1701 ntb->dev_type = NTB_DEV_USD; 1702 } 1703 1704 if (XEON_GEN3_REG_PPD_ONE_MSIX_F(ppd)) { 1705 /* 1706 * This bit when set, causes only a single MSI-X message to be 1707 * generated if MSI-X is enabled. 1708 */ 1709 ntb->features |= NTB_ONE_MSIX; 1710 } 1711 1712 if (XEON_GEN3_REG_PPD_BAR45_SPL_F(ppd)) { 1713 /* BARs 4 and 5 are presented as two 32b non-prefetchable BARs */ 1714 ntb->features |= NTB_SPLIT_BAR; 1715 } 1716 1717 device_printf(ntb->device, "conn type 0x%02x, dev type 0x%02x," 1718 "features 0x%02x\n", ntb->conn_type, ntb->dev_type, ntb->features); 1719 1720 return (0); 1721 } 1722 1723 static int 1724 intel_ntb_xeon_init_dev(struct ntb_softc *ntb) 1725 { 1726 int rc; 1727 1728 ntb->spad_count = XEON_SPAD_COUNT; 1729 ntb->db_count = XEON_DB_COUNT; 1730 ntb->db_link_mask = XEON_DB_LINK_BIT; 1731 ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; 1732 ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; 1733 1734 if (ntb->conn_type != NTB_CONN_B2B) { 1735 device_printf(ntb->device, "Connection type %d not supported\n", 1736 ntb->conn_type); 1737 return (ENXIO); 1738 } 1739 1740 ntb->reg = &xeon_reg; 1741 ntb->self_reg = &xeon_pri_reg; 1742 ntb->peer_reg = &xeon_b2b_reg; 1743 ntb->xlat_reg = &xeon_sec_xlat; 1744 1745 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1746 ntb->force_db = ntb->fake_db = 0; 1747 ntb->msix_mw_idx = (ntb->mw_count + g_ntb_msix_idx) % 1748 ntb->mw_count; 1749 intel_ntb_printf(2, "Setting up MSIX mw idx %d means %u\n", 1750 g_ntb_msix_idx, ntb->msix_mw_idx); 1751 rc = intel_ntb_mw_set_wc_internal(ntb, ntb->msix_mw_idx, 1752 VM_MEMATTR_UNCACHEABLE); 1753 KASSERT(rc == 0, ("shouldn't fail")); 1754 } else if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 1755 /* 1756 * There is a Xeon hardware errata related to writes to SDOORBELL or 1757 * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 1758 * which may hang the system. To workaround this, use a memory 1759 * window to access the interrupt and scratch pad registers on the 1760 * remote system. 1761 */ 1762 ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) % 1763 ntb->mw_count; 1764 intel_ntb_printf(2, "Setting up b2b mw idx %d means %u\n", 1765 g_ntb_mw_idx, ntb->b2b_mw_idx); 1766 rc = intel_ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx, 1767 VM_MEMATTR_UNCACHEABLE); 1768 KASSERT(rc == 0, ("shouldn't fail")); 1769 } else if (HAS_FEATURE(ntb, NTB_B2BDOORBELL_BIT14)) 1770 /* 1771 * HW Errata on bit 14 of b2bdoorbell register. Writes will not be 1772 * mirrored to the remote system. Shrink the number of bits by one, 1773 * since bit 14 is the last bit. 1774 * 1775 * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register 1776 * anyway. Nor for non-B2B connection types. 1777 */ 1778 ntb->db_count = XEON_DB_COUNT - 1; 1779 1780 ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1781 1782 if (ntb->dev_type == NTB_DEV_USD) 1783 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, 1784 &xeon_b2b_usd_addr); 1785 else 1786 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, 1787 &xeon_b2b_dsd_addr); 1788 if (rc != 0) 1789 return (rc); 1790 1791 /* Enable Bus Master and Memory Space on the secondary side */ 1792 intel_ntb_reg_write(2, XEON_SPCICMD_OFFSET, 1793 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1794 1795 /* 1796 * Mask all doorbell interrupts. 1797 */ 1798 DB_MASK_LOCK(ntb); 1799 ntb->db_mask = ntb->db_valid_mask; 1800 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1801 DB_MASK_UNLOCK(ntb); 1802 1803 rc = intel_ntb_init_isr(ntb); 1804 return (rc); 1805 } 1806 1807 static int 1808 intel_ntb_xeon_gen3_init_dev(struct ntb_softc *ntb) 1809 { 1810 int rc; 1811 1812 ntb->spad_count = XEON_GEN3_SPAD_COUNT; 1813 ntb->db_count = XEON_GEN3_DB_COUNT; 1814 ntb->db_link_mask = XEON_GEN3_DB_LINK_BIT; 1815 ntb->db_vec_count = XEON_GEN3_DB_MSIX_VECTOR_COUNT; 1816 ntb->db_vec_shift = XEON_GEN3_DB_MSIX_VECTOR_SHIFT; 1817 1818 if (ntb->conn_type != NTB_CONN_B2B) { 1819 device_printf(ntb->device, "Connection type %d not supported\n", 1820 ntb->conn_type); 1821 return (ENXIO); 1822 } 1823 1824 ntb->reg = &xeon_gen3_reg; 1825 ntb->self_reg = &xeon_gen3_pri_reg; 1826 ntb->peer_reg = &xeon_gen3_b2b_reg; 1827 ntb->xlat_reg = &xeon_gen3_sec_xlat; 1828 1829 ntb->db_valid_mask = (1ULL << ntb->db_count) - 1; 1830 1831 xeon_gen3_setup_b2b_mw(ntb); 1832 1833 /* Enable Bus Master and Memory Space on the External Side */ 1834 intel_ntb_reg_write(2, XEON_GEN3_EXT_REG_PCI_CMD, 1835 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1836 1837 /* Setup Interrupt */ 1838 rc = intel_ntb_xeon_gen3_init_isr(ntb); 1839 1840 return (rc); 1841 } 1842 1843 static int 1844 intel_ntb_atom_init_dev(struct ntb_softc *ntb) 1845 { 1846 int error; 1847 1848 KASSERT(ntb->conn_type == NTB_CONN_B2B, 1849 ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); 1850 1851 ntb->spad_count = ATOM_SPAD_COUNT; 1852 ntb->db_count = ATOM_DB_COUNT; 1853 ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; 1854 ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; 1855 ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1856 1857 ntb->reg = &atom_reg; 1858 ntb->self_reg = &atom_pri_reg; 1859 ntb->peer_reg = &atom_b2b_reg; 1860 ntb->xlat_reg = &atom_sec_xlat; 1861 1862 /* 1863 * FIXME - MSI-X bug on early Atom HW, remove once internal issue is 1864 * resolved. Mask transaction layer internal parity errors. 1865 */ 1866 pci_write_config(ntb->device, 0xFC, 0x4, 4); 1867 1868 configure_atom_secondary_side_bars(ntb); 1869 1870 /* Enable Bus Master and Memory Space on the secondary side */ 1871 intel_ntb_reg_write(2, ATOM_SPCICMD_OFFSET, 1872 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1873 1874 error = intel_ntb_init_isr(ntb); 1875 if (error != 0) 1876 return (error); 1877 1878 /* Initiate PCI-E link training */ 1879 intel_ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 1880 1881 callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); 1882 1883 return (0); 1884 } 1885 1886 /* XXX: Linux driver doesn't seem to do any of this for Atom. */ 1887 static void 1888 configure_atom_secondary_side_bars(struct ntb_softc *ntb) 1889 { 1890 1891 if (ntb->dev_type == NTB_DEV_USD) { 1892 intel_ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1893 XEON_B2B_BAR2_ADDR64); 1894 intel_ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1895 XEON_B2B_BAR4_ADDR64); 1896 intel_ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1897 intel_ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1898 } else { 1899 intel_ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1900 XEON_B2B_BAR2_ADDR64); 1901 intel_ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1902 XEON_B2B_BAR4_ADDR64); 1903 intel_ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1904 intel_ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1905 } 1906 } 1907 1908 /* 1909 * When working around Xeon SDOORBELL errata by remapping remote registers in a 1910 * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW 1911 * remains for use by a higher layer. 1912 * 1913 * Will only be used if working around SDOORBELL errata and the BIOS-configured 1914 * MW size is sufficiently large. 1915 */ 1916 static unsigned int ntb_b2b_mw_share; 1917 SYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, 1918 0, "If enabled (non-zero), prefer to share half of the B2B peer register " 1919 "MW with higher level consumers. Both sides of the NTB MUST set the same " 1920 "value here."); 1921 1922 static void 1923 xeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, 1924 enum ntb_bar regbar) 1925 { 1926 struct ntb_pci_bar_info *bar; 1927 uint8_t bar_sz; 1928 1929 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) 1930 return; 1931 1932 bar = &ntb->bar_info[idx]; 1933 bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); 1934 if (idx == regbar) { 1935 if (ntb->b2b_off != 0) 1936 bar_sz--; 1937 else 1938 bar_sz = 0; 1939 } 1940 pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); 1941 bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); 1942 (void)bar_sz; 1943 } 1944 1945 static void 1946 xeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, 1947 enum ntb_bar idx, enum ntb_bar regbar) 1948 { 1949 uint64_t reg_val; 1950 uint32_t base_reg, lmt_reg; 1951 1952 bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); 1953 if (idx == regbar) { 1954 if (ntb->b2b_off) 1955 bar_addr += ntb->b2b_off; 1956 else 1957 bar_addr = 0; 1958 } 1959 1960 if (!bar_is_64bit(ntb, idx)) { 1961 intel_ntb_reg_write(4, base_reg, bar_addr); 1962 reg_val = intel_ntb_reg_read(4, base_reg); 1963 (void)reg_val; 1964 1965 intel_ntb_reg_write(4, lmt_reg, bar_addr); 1966 reg_val = intel_ntb_reg_read(4, lmt_reg); 1967 (void)reg_val; 1968 } else { 1969 intel_ntb_reg_write(8, base_reg, bar_addr); 1970 reg_val = intel_ntb_reg_read(8, base_reg); 1971 (void)reg_val; 1972 1973 intel_ntb_reg_write(8, lmt_reg, bar_addr); 1974 reg_val = intel_ntb_reg_read(8, lmt_reg); 1975 (void)reg_val; 1976 } 1977 } 1978 1979 static void 1980 xeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) 1981 { 1982 struct ntb_pci_bar_info *bar; 1983 1984 bar = &ntb->bar_info[idx]; 1985 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { 1986 intel_ntb_reg_write(4, bar->pbarxlat_off, base_addr); 1987 base_addr = intel_ntb_reg_read(4, bar->pbarxlat_off); 1988 } else { 1989 intel_ntb_reg_write(8, bar->pbarxlat_off, base_addr); 1990 base_addr = intel_ntb_reg_read(8, bar->pbarxlat_off); 1991 } 1992 (void)base_addr; 1993 } 1994 1995 static int 1996 xeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, 1997 const struct ntb_b2b_addr *peer_addr) 1998 { 1999 struct ntb_pci_bar_info *b2b_bar; 2000 vm_size_t bar_size; 2001 uint64_t bar_addr; 2002 enum ntb_bar b2b_bar_num, i; 2003 2004 if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { 2005 b2b_bar = NULL; 2006 b2b_bar_num = NTB_CONFIG_BAR; 2007 ntb->b2b_off = 0; 2008 } else { 2009 b2b_bar_num = intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); 2010 KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, 2011 ("invalid b2b mw bar")); 2012 2013 b2b_bar = &ntb->bar_info[b2b_bar_num]; 2014 bar_size = b2b_bar->size; 2015 2016 if (ntb_b2b_mw_share != 0 && 2017 (bar_size >> 1) >= XEON_B2B_MIN_SIZE) 2018 ntb->b2b_off = bar_size >> 1; 2019 else if (bar_size >= XEON_B2B_MIN_SIZE) { 2020 ntb->b2b_off = 0; 2021 } else { 2022 device_printf(ntb->device, 2023 "B2B bar size is too small!\n"); 2024 return (EIO); 2025 } 2026 } 2027 2028 /* 2029 * Reset the secondary bar sizes to match the primary bar sizes. 2030 * (Except, disable or halve the size of the B2B secondary bar.) 2031 */ 2032 for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) 2033 xeon_reset_sbar_size(ntb, i, b2b_bar_num); 2034 2035 bar_addr = 0; 2036 if (b2b_bar_num == NTB_CONFIG_BAR) 2037 bar_addr = addr->bar0_addr; 2038 else if (b2b_bar_num == NTB_B2B_BAR_1) 2039 bar_addr = addr->bar2_addr64; 2040 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2041 bar_addr = addr->bar4_addr64; 2042 else if (b2b_bar_num == NTB_B2B_BAR_2) 2043 bar_addr = addr->bar4_addr32; 2044 else if (b2b_bar_num == NTB_B2B_BAR_3) 2045 bar_addr = addr->bar5_addr32; 2046 else 2047 KASSERT(false, ("invalid bar")); 2048 2049 intel_ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); 2050 2051 /* 2052 * Other SBARs are normally hit by the PBAR xlat, except for the b2b 2053 * register BAR. The B2B BAR is either disabled above or configured 2054 * half-size. It starts at PBAR xlat + offset. 2055 * 2056 * Also set up incoming BAR limits == base (zero length window). 2057 */ 2058 xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, 2059 b2b_bar_num); 2060 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2061 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, 2062 NTB_B2B_BAR_2, b2b_bar_num); 2063 xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, 2064 NTB_B2B_BAR_3, b2b_bar_num); 2065 } else 2066 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, 2067 NTB_B2B_BAR_2, b2b_bar_num); 2068 2069 /* Zero incoming translation addrs */ 2070 intel_ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); 2071 intel_ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); 2072 2073 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 2074 uint32_t xlat_reg, lmt_reg; 2075 enum ntb_bar bar_num; 2076 2077 /* 2078 * We point the chosen MSIX MW BAR xlat to remote LAPIC for 2079 * workaround 2080 */ 2081 bar_num = intel_ntb_mw_to_bar(ntb, ntb->msix_mw_idx); 2082 bar_get_xlat_params(ntb, bar_num, NULL, &xlat_reg, &lmt_reg); 2083 if (bar_is_64bit(ntb, bar_num)) { 2084 intel_ntb_reg_write(8, xlat_reg, MSI_INTEL_ADDR_BASE); 2085 ntb->msix_xlat = intel_ntb_reg_read(8, xlat_reg); 2086 intel_ntb_reg_write(8, lmt_reg, 0); 2087 } else { 2088 intel_ntb_reg_write(4, xlat_reg, MSI_INTEL_ADDR_BASE); 2089 ntb->msix_xlat = intel_ntb_reg_read(4, xlat_reg); 2090 intel_ntb_reg_write(4, lmt_reg, 0); 2091 } 2092 2093 ntb->peer_lapic_bar = &ntb->bar_info[bar_num]; 2094 } 2095 (void)intel_ntb_reg_read(8, XEON_SBAR2XLAT_OFFSET); 2096 (void)intel_ntb_reg_read(8, XEON_SBAR4XLAT_OFFSET); 2097 2098 /* Zero outgoing translation limits (whole bar size windows) */ 2099 intel_ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); 2100 intel_ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 2101 2102 /* Set outgoing translation offsets */ 2103 xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); 2104 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2105 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); 2106 xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); 2107 } else 2108 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); 2109 2110 /* Set the translation offset for B2B registers */ 2111 bar_addr = 0; 2112 if (b2b_bar_num == NTB_CONFIG_BAR) 2113 bar_addr = peer_addr->bar0_addr; 2114 else if (b2b_bar_num == NTB_B2B_BAR_1) 2115 bar_addr = peer_addr->bar2_addr64; 2116 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2117 bar_addr = peer_addr->bar4_addr64; 2118 else if (b2b_bar_num == NTB_B2B_BAR_2) 2119 bar_addr = peer_addr->bar4_addr32; 2120 else if (b2b_bar_num == NTB_B2B_BAR_3) 2121 bar_addr = peer_addr->bar5_addr32; 2122 else 2123 KASSERT(false, ("invalid bar")); 2124 2125 /* 2126 * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits 2127 * at a time. 2128 */ 2129 intel_ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); 2130 intel_ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); 2131 return (0); 2132 } 2133 2134 static int 2135 xeon_gen3_setup_b2b_mw(struct ntb_softc *ntb) 2136 { 2137 uint64_t reg; 2138 uint32_t embarsz, imbarsz; 2139 2140 /* IMBAR1SZ should be equal to EMBAR1SZ */ 2141 embarsz = pci_read_config(ntb->device, XEON_GEN3_INT_REG_EMBAR1SZ, 1); 2142 imbarsz = pci_read_config(ntb->device, XEON_GEN3_INT_REG_IMBAR1SZ, 1); 2143 if (embarsz != imbarsz) { 2144 device_printf(ntb->device, 2145 "IMBAR1SZ (%u) should be equal to EMBAR1SZ (%u)\n", 2146 imbarsz, embarsz); 2147 return (EIO); 2148 } 2149 2150 /* IMBAR2SZ should be equal to EMBAR2SZ */ 2151 embarsz = pci_read_config(ntb->device, XEON_GEN3_INT_REG_EMBAR2SZ, 1); 2152 imbarsz = pci_read_config(ntb->device, XEON_GEN3_INT_REG_IMBAR2SZ, 1); 2153 if (embarsz != imbarsz) { 2154 device_printf(ntb->device, 2155 "IMBAR2SZ (%u) should be equal to EMBAR2SZ (%u)\n", 2156 imbarsz, embarsz); 2157 return (EIO); 2158 } 2159 2160 /* Client will provide the incoming IMBAR1/2XBASE, zero it for now */ 2161 intel_ntb_reg_write(8, XEON_GEN3_REG_IMBAR1XBASE, 0); 2162 intel_ntb_reg_write(8, XEON_GEN3_REG_IMBAR2XBASE, 0); 2163 2164 /* 2165 * If the value in EMBAR1LIMIT is set equal to the value in EMBAR1, 2166 * the memory window for EMBAR1 is disabled. 2167 * Note: It is needed to avoid malacious access. 2168 */ 2169 reg = pci_read_config(ntb->device, XEON_GEN3_EXT_REG_BAR1BASE, 8); 2170 intel_ntb_reg_write(8, XEON_GEN3_REG_IMBAR1XLIMIT, reg); 2171 2172 reg = pci_read_config(ntb->device, XEON_GEN3_EXT_REG_BAR2BASE, 8); 2173 intel_ntb_reg_write(8, XEON_GEN3_REG_IMBAR2XLIMIT, reg); 2174 2175 return (0); 2176 } 2177 2178 static inline bool 2179 _xeon_link_is_up(struct ntb_softc *ntb) 2180 { 2181 2182 if (ntb->conn_type == NTB_CONN_TRANSPARENT) 2183 return (true); 2184 return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); 2185 } 2186 2187 static inline bool 2188 link_is_up(struct ntb_softc *ntb) 2189 { 2190 2191 if (ntb->type == NTB_XEON_GEN1 || ntb->type == NTB_XEON_GEN3) 2192 return (_xeon_link_is_up(ntb) && (ntb->peer_msix_good || 2193 !HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))); 2194 2195 KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 2196 return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); 2197 } 2198 2199 static inline bool 2200 atom_link_is_err(struct ntb_softc *ntb) 2201 { 2202 uint32_t status; 2203 2204 KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 2205 2206 status = intel_ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 2207 if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) 2208 return (true); 2209 2210 status = intel_ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 2211 return ((status & ATOM_IBIST_ERR_OFLOW) != 0); 2212 } 2213 2214 /* Atom does not have link status interrupt, poll on that platform */ 2215 static void 2216 atom_link_hb(void *arg) 2217 { 2218 struct ntb_softc *ntb = arg; 2219 sbintime_t timo, poll_ts; 2220 2221 timo = NTB_HB_TIMEOUT * hz; 2222 poll_ts = ntb->last_ts + timo; 2223 2224 /* 2225 * Delay polling the link status if an interrupt was received, unless 2226 * the cached link status says the link is down. 2227 */ 2228 if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { 2229 timo = poll_ts - ticks; 2230 goto out; 2231 } 2232 2233 if (intel_ntb_poll_link(ntb)) 2234 ntb_link_event(ntb->device); 2235 2236 if (!link_is_up(ntb) && atom_link_is_err(ntb)) { 2237 /* Link is down with error, proceed with recovery */ 2238 callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); 2239 return; 2240 } 2241 2242 out: 2243 callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); 2244 } 2245 2246 static void 2247 atom_perform_link_restart(struct ntb_softc *ntb) 2248 { 2249 uint32_t status; 2250 2251 /* Driver resets the NTB ModPhy lanes - magic! */ 2252 intel_ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); 2253 intel_ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); 2254 intel_ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); 2255 intel_ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); 2256 2257 /* Driver waits 100ms to allow the NTB ModPhy to settle */ 2258 pause("ModPhy", hz / 10); 2259 2260 /* Clear AER Errors, write to clear */ 2261 status = intel_ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); 2262 status &= PCIM_AER_COR_REPLAY_ROLLOVER; 2263 intel_ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); 2264 2265 /* Clear unexpected electrical idle event in LTSSM, write to clear */ 2266 status = intel_ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); 2267 status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; 2268 intel_ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); 2269 2270 /* Clear DeSkew Buffer error, write to clear */ 2271 status = intel_ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); 2272 status |= ATOM_DESKEWSTS_DBERR; 2273 intel_ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); 2274 2275 status = intel_ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 2276 status &= ATOM_IBIST_ERR_OFLOW; 2277 intel_ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); 2278 2279 /* Releases the NTB state machine to allow the link to retrain */ 2280 status = intel_ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 2281 status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; 2282 intel_ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); 2283 } 2284 2285 static int 2286 intel_ntb_port_number(device_t dev) 2287 { 2288 struct ntb_softc *ntb = device_get_softc(dev); 2289 2290 return (ntb->dev_type == NTB_DEV_USD ? 0 : 1); 2291 } 2292 2293 static int 2294 intel_ntb_peer_port_count(device_t dev) 2295 { 2296 2297 return (1); 2298 } 2299 2300 static int 2301 intel_ntb_peer_port_number(device_t dev, int pidx) 2302 { 2303 struct ntb_softc *ntb = device_get_softc(dev); 2304 2305 if (pidx != 0) 2306 return (-EINVAL); 2307 2308 return (ntb->dev_type == NTB_DEV_USD ? 1 : 0); 2309 } 2310 2311 static int 2312 intel_ntb_peer_port_idx(device_t dev, int port) 2313 { 2314 int peer_port; 2315 2316 peer_port = intel_ntb_peer_port_number(dev, 0); 2317 if (peer_port == -EINVAL || port != peer_port) 2318 return (-EINVAL); 2319 2320 return (0); 2321 } 2322 2323 static int 2324 intel_ntb_link_enable(device_t dev, enum ntb_speed speed __unused, 2325 enum ntb_width width __unused) 2326 { 2327 struct ntb_softc *ntb = device_get_softc(dev); 2328 uint32_t cntl; 2329 2330 intel_ntb_printf(2, "%s\n", __func__); 2331 2332 if (ntb->type == NTB_ATOM) { 2333 pci_write_config(ntb->device, NTB_PPD_OFFSET, 2334 ntb->ppd | ATOM_PPD_INIT_LINK, 4); 2335 return (0); 2336 } 2337 2338 if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 2339 ntb_link_event(dev); 2340 return (0); 2341 } 2342 2343 cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2344 cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); 2345 cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; 2346 cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; 2347 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2348 cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; 2349 intel_ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 2350 return (0); 2351 } 2352 2353 static int 2354 intel_ntb_link_disable(device_t dev) 2355 { 2356 struct ntb_softc *ntb = device_get_softc(dev); 2357 uint32_t cntl; 2358 2359 intel_ntb_printf(2, "%s\n", __func__); 2360 2361 if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 2362 ntb_link_event(dev); 2363 return (0); 2364 } 2365 2366 cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2367 cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); 2368 cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); 2369 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2370 cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); 2371 cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; 2372 intel_ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 2373 return (0); 2374 } 2375 2376 static bool 2377 intel_ntb_link_enabled(device_t dev) 2378 { 2379 struct ntb_softc *ntb = device_get_softc(dev); 2380 uint32_t cntl; 2381 2382 if (ntb->type == NTB_ATOM) { 2383 cntl = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 2384 return ((cntl & ATOM_PPD_INIT_LINK) != 0); 2385 } 2386 2387 if (ntb->conn_type == NTB_CONN_TRANSPARENT) 2388 return (true); 2389 2390 cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2391 return ((cntl & NTB_CNTL_LINK_DISABLE) == 0); 2392 } 2393 2394 static void 2395 recover_atom_link(void *arg) 2396 { 2397 struct ntb_softc *ntb = arg; 2398 unsigned speed, width, oldspeed, oldwidth; 2399 uint32_t status32; 2400 2401 atom_perform_link_restart(ntb); 2402 2403 /* 2404 * There is a potential race between the 2 NTB devices recovering at 2405 * the same time. If the times are the same, the link will not recover 2406 * and the driver will be stuck in this loop forever. Add a random 2407 * interval to the recovery time to prevent this race. 2408 */ 2409 status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; 2410 pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); 2411 2412 if (atom_link_is_err(ntb)) 2413 goto retry; 2414 2415 status32 = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2416 if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) 2417 goto out; 2418 2419 status32 = intel_ntb_reg_read(4, ntb->reg->lnk_sta); 2420 width = NTB_LNK_STA_WIDTH(status32); 2421 speed = status32 & NTB_LINK_SPEED_MASK; 2422 2423 oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); 2424 oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; 2425 if (oldwidth != width || oldspeed != speed) 2426 goto retry; 2427 2428 out: 2429 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, 2430 ntb); 2431 return; 2432 2433 retry: 2434 callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, 2435 ntb); 2436 } 2437 2438 /* 2439 * Polls the HW link status register(s); returns true if something has changed. 2440 */ 2441 static bool 2442 intel_ntb_poll_link(struct ntb_softc *ntb) 2443 { 2444 uint32_t ntb_cntl; 2445 uint16_t reg_val; 2446 2447 if (ntb->type == NTB_ATOM) { 2448 ntb_cntl = intel_ntb_reg_read(4, ntb->reg->ntb_ctl); 2449 if (ntb_cntl == ntb->ntb_ctl) 2450 return (false); 2451 2452 ntb->ntb_ctl = ntb_cntl; 2453 ntb->lnk_sta = intel_ntb_reg_read(4, ntb->reg->lnk_sta); 2454 } else { 2455 if (ntb->type == NTB_XEON_GEN1) 2456 db_iowrite_raw(ntb, ntb->self_reg->db_bell, 2457 ntb->db_link_mask); 2458 2459 reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 2460 if (reg_val == ntb->lnk_sta) 2461 return (false); 2462 2463 ntb->lnk_sta = reg_val; 2464 2465 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 2466 if (_xeon_link_is_up(ntb)) { 2467 if (!ntb->peer_msix_good) { 2468 callout_reset(&ntb->peer_msix_work, 0, 2469 intel_ntb_exchange_msix, ntb); 2470 return (false); 2471 } 2472 } else { 2473 ntb->peer_msix_good = false; 2474 ntb->peer_msix_done = false; 2475 } 2476 } 2477 } 2478 return (true); 2479 } 2480 2481 static inline enum ntb_speed 2482 intel_ntb_link_sta_speed(struct ntb_softc *ntb) 2483 { 2484 2485 if (!link_is_up(ntb)) 2486 return (NTB_SPEED_NONE); 2487 return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); 2488 } 2489 2490 static inline enum ntb_width 2491 intel_ntb_link_sta_width(struct ntb_softc *ntb) 2492 { 2493 2494 if (!link_is_up(ntb)) 2495 return (NTB_WIDTH_NONE); 2496 return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); 2497 } 2498 2499 SYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 2500 "Driver state, statistics, and HW registers"); 2501 2502 #define NTB_REGSZ_MASK (3ul << 30) 2503 #define NTB_REG_64 (1ul << 30) 2504 #define NTB_REG_32 (2ul << 30) 2505 #define NTB_REG_16 (3ul << 30) 2506 #define NTB_REG_8 (0ul << 30) 2507 2508 #define NTB_DB_READ (1ul << 29) 2509 #define NTB_PCI_REG (1ul << 28) 2510 #define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) 2511 2512 static void 2513 intel_ntb_sysctl_init(struct ntb_softc *ntb) 2514 { 2515 struct sysctl_oid_list *globals, *tree_par, *regpar, *statpar, *errpar; 2516 struct sysctl_ctx_list *ctx; 2517 struct sysctl_oid *tree, *tmptree; 2518 2519 ctx = device_get_sysctl_ctx(ntb->device); 2520 globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)); 2521 2522 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "link_status", 2523 CTLFLAG_RD | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, ntb, 0, 2524 sysctl_handle_link_status_human, "A", 2525 "Link status (human readable)"); 2526 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "active", 2527 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, ntb, 0, 2528 sysctl_handle_link_status, "IU", 2529 "Link status (1=active, 0=inactive)"); 2530 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "admin_up", 2531 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, ntb, 0, 2532 sysctl_handle_link_admin, "IU", 2533 "Set/get interface status (1=UP, 0=DOWN)"); 2534 2535 tree = SYSCTL_ADD_NODE(ctx, globals, OID_AUTO, "debug_info", 2536 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 2537 "Driver state, statistics, and HW registers"); 2538 tree_par = SYSCTL_CHILDREN(tree); 2539 2540 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, 2541 &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); 2542 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, 2543 &ntb->dev_type, 0, "0 - USD; 1 - DSD"); 2544 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD, 2545 &ntb->ppd, 0, "Raw PPD register (cached)"); 2546 2547 if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { 2548 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, 2549 &ntb->b2b_mw_idx, 0, 2550 "Index of the MW used for B2B remote register access"); 2551 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", 2552 CTLFLAG_RD, &ntb->b2b_off, 2553 "If non-zero, offset of B2B register region in shared MW"); 2554 } 2555 2556 SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", 2557 CTLFLAG_RD | CTLTYPE_STRING | CTLFLAG_NEEDGIANT, ntb, 0, 2558 sysctl_handle_features, "A", "Features/errata of this NTB device"); 2559 2560 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, 2561 __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0, 2562 "NTB CTL register (cached)"); 2563 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, 2564 __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0, 2565 "LNK STA register (cached)"); 2566 2567 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, 2568 &ntb->mw_count, 0, "MW count"); 2569 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, 2570 &ntb->spad_count, 0, "Scratchpad count"); 2571 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, 2572 &ntb->db_count, 0, "Doorbell count"); 2573 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, 2574 &ntb->db_vec_count, 0, "Doorbell vector count"); 2575 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, 2576 &ntb->db_vec_shift, 0, "Doorbell vector shift"); 2577 2578 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, 2579 &ntb->db_valid_mask, "Doorbell valid mask"); 2580 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, 2581 &ntb->db_link_mask, "Doorbell link mask"); 2582 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, 2583 &ntb->db_mask, "Doorbell mask (cached)"); 2584 2585 tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", 2586 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 2587 "Raw HW registers (big-endian)"); 2588 regpar = SYSCTL_CHILDREN(tmptree); 2589 2590 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", 2591 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2592 NTB_REG_32 | ntb->reg->ntb_ctl, sysctl_handle_register, "IU", 2593 "NTB Control register"); 2594 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", 2595 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2596 NTB_REG_32 | 0x19c, sysctl_handle_register, "IU", 2597 "NTB Link Capabilities"); 2598 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", 2599 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2600 NTB_REG_32 | 0x1a0, sysctl_handle_register, "IU", 2601 "NTB Link Control register"); 2602 2603 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", 2604 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2605 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, 2606 sysctl_handle_register, "QU", "Doorbell mask register"); 2607 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", 2608 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2609 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, 2610 sysctl_handle_register, "QU", "Doorbell register"); 2611 2612 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", 2613 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2614 NTB_REG_64 | ntb->xlat_reg->bar2_xlat, 2615 sysctl_handle_register, "QU", "Incoming XLAT23 register"); 2616 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2617 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", 2618 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2619 NTB_REG_32 | ntb->xlat_reg->bar4_xlat, 2620 sysctl_handle_register, "IU", "Incoming XLAT4 register"); 2621 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", 2622 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2623 NTB_REG_32 | ntb->xlat_reg->bar5_xlat, 2624 sysctl_handle_register, "IU", "Incoming XLAT5 register"); 2625 } else { 2626 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", 2627 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2628 NTB_REG_64 | ntb->xlat_reg->bar4_xlat, 2629 sysctl_handle_register, "QU", "Incoming XLAT45 register"); 2630 } 2631 2632 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", 2633 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2634 NTB_REG_64 | ntb->xlat_reg->bar2_limit, 2635 sysctl_handle_register, "QU", "Incoming LMT23 register"); 2636 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2637 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", 2638 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2639 NTB_REG_32 | ntb->xlat_reg->bar4_limit, 2640 sysctl_handle_register, "IU", "Incoming LMT4 register"); 2641 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", 2642 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2643 NTB_REG_32 | ntb->xlat_reg->bar5_limit, 2644 sysctl_handle_register, "IU", "Incoming LMT5 register"); 2645 } else { 2646 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", 2647 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2648 NTB_REG_64 | ntb->xlat_reg->bar4_limit, 2649 sysctl_handle_register, "QU", "Incoming LMT45 register"); 2650 } 2651 2652 if (ntb->type == NTB_ATOM) 2653 return; 2654 2655 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", 2656 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Xeon HW statistics"); 2657 statpar = SYSCTL_CHILDREN(tmptree); 2658 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", 2659 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2660 NTB_REG_16 | XEON_USMEMMISS_OFFSET, 2661 sysctl_handle_register, "SU", "Upstream Memory Miss"); 2662 2663 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", 2664 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Xeon HW errors"); 2665 errpar = SYSCTL_CHILDREN(tmptree); 2666 2667 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd", 2668 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2669 NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET, 2670 sysctl_handle_register, "CU", "PPD"); 2671 2672 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz", 2673 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2674 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET, 2675 sysctl_handle_register, "CU", "PBAR23 SZ (log2)"); 2676 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz", 2677 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2678 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET, 2679 sysctl_handle_register, "CU", "PBAR4 SZ (log2)"); 2680 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz", 2681 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2682 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET, 2683 sysctl_handle_register, "CU", "PBAR5 SZ (log2)"); 2684 2685 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz", 2686 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2687 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET, 2688 sysctl_handle_register, "CU", "SBAR23 SZ (log2)"); 2689 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz", 2690 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2691 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET, 2692 sysctl_handle_register, "CU", "SBAR4 SZ (log2)"); 2693 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz", 2694 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2695 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET, 2696 sysctl_handle_register, "CU", "SBAR5 SZ (log2)"); 2697 2698 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts", 2699 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2700 NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, 2701 sysctl_handle_register, "SU", "DEVSTS"); 2702 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts", 2703 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2704 NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, 2705 sysctl_handle_register, "SU", "LNKSTS"); 2706 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts", 2707 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2708 NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET, 2709 sysctl_handle_register, "SU", "SLNKSTS"); 2710 2711 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", 2712 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2713 NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, 2714 sysctl_handle_register, "IU", "UNCERRSTS"); 2715 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", 2716 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2717 NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, 2718 sysctl_handle_register, "IU", "CORERRSTS"); 2719 2720 if (ntb->conn_type != NTB_CONN_B2B) 2721 return; 2722 2723 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat01l", 2724 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2725 NTB_REG_32 | XEON_B2B_XLAT_OFFSETL, 2726 sysctl_handle_register, "IU", "Outgoing XLAT0L register"); 2727 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat01u", 2728 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2729 NTB_REG_32 | XEON_B2B_XLAT_OFFSETU, 2730 sysctl_handle_register, "IU", "Outgoing XLAT0U register"); 2731 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", 2732 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2733 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, 2734 sysctl_handle_register, "QU", "Outgoing XLAT23 register"); 2735 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2736 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", 2737 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2738 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2739 sysctl_handle_register, "IU", "Outgoing XLAT4 register"); 2740 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", 2741 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2742 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, 2743 sysctl_handle_register, "IU", "Outgoing XLAT5 register"); 2744 } else { 2745 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", 2746 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2747 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2748 sysctl_handle_register, "QU", "Outgoing XLAT45 register"); 2749 } 2750 2751 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", 2752 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2753 NTB_REG_64 | XEON_PBAR2LMT_OFFSET, 2754 sysctl_handle_register, "QU", "Outgoing LMT23 register"); 2755 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2756 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", 2757 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2758 NTB_REG_32 | XEON_PBAR4LMT_OFFSET, 2759 sysctl_handle_register, "IU", "Outgoing LMT4 register"); 2760 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", 2761 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2762 NTB_REG_32 | XEON_PBAR5LMT_OFFSET, 2763 sysctl_handle_register, "IU", "Outgoing LMT5 register"); 2764 } else { 2765 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", 2766 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2767 NTB_REG_64 | XEON_PBAR4LMT_OFFSET, 2768 sysctl_handle_register, "QU", "Outgoing LMT45 register"); 2769 } 2770 2771 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", 2772 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2773 NTB_REG_64 | ntb->xlat_reg->bar0_base, 2774 sysctl_handle_register, "QU", "Secondary BAR01 base register"); 2775 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", 2776 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2777 NTB_REG_64 | ntb->xlat_reg->bar2_base, 2778 sysctl_handle_register, "QU", "Secondary BAR23 base register"); 2779 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2780 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", 2781 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2782 NTB_REG_32 | ntb->xlat_reg->bar4_base, 2783 sysctl_handle_register, "IU", 2784 "Secondary BAR4 base register"); 2785 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", 2786 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2787 NTB_REG_32 | ntb->xlat_reg->bar5_base, 2788 sysctl_handle_register, "IU", 2789 "Secondary BAR5 base register"); 2790 } else { 2791 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", 2792 CTLFLAG_RD | CTLTYPE_OPAQUE | CTLFLAG_NEEDGIANT, ntb, 2793 NTB_REG_64 | ntb->xlat_reg->bar4_base, 2794 sysctl_handle_register, "QU", 2795 "Secondary BAR45 base register"); 2796 } 2797 } 2798 2799 static int 2800 sysctl_handle_features(SYSCTL_HANDLER_ARGS) 2801 { 2802 struct ntb_softc *ntb = arg1; 2803 struct sbuf sb; 2804 int error; 2805 2806 sbuf_new_for_sysctl(&sb, NULL, 256, req); 2807 2808 sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); 2809 error = sbuf_finish(&sb); 2810 sbuf_delete(&sb); 2811 2812 if (error || !req->newptr) 2813 return (error); 2814 return (EINVAL); 2815 } 2816 2817 static int 2818 sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS) 2819 { 2820 struct ntb_softc *ntb = arg1; 2821 unsigned old, new; 2822 int error; 2823 2824 old = intel_ntb_link_enabled(ntb->device); 2825 2826 error = SYSCTL_OUT(req, &old, sizeof(old)); 2827 if (error != 0 || req->newptr == NULL) 2828 return (error); 2829 2830 error = SYSCTL_IN(req, &new, sizeof(new)); 2831 if (error != 0) 2832 return (error); 2833 2834 intel_ntb_printf(0, "Admin set interface state to '%sabled'\n", 2835 (new != 0)? "en" : "dis"); 2836 2837 if (new != 0) 2838 error = intel_ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 2839 else 2840 error = intel_ntb_link_disable(ntb->device); 2841 return (error); 2842 } 2843 2844 static int 2845 sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS) 2846 { 2847 struct ntb_softc *ntb = arg1; 2848 struct sbuf sb; 2849 enum ntb_speed speed; 2850 enum ntb_width width; 2851 int error; 2852 2853 sbuf_new_for_sysctl(&sb, NULL, 32, req); 2854 2855 if (intel_ntb_link_is_up(ntb->device, &speed, &width)) 2856 sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", 2857 (unsigned)speed, (unsigned)width); 2858 else 2859 sbuf_printf(&sb, "down"); 2860 2861 error = sbuf_finish(&sb); 2862 sbuf_delete(&sb); 2863 2864 if (error || !req->newptr) 2865 return (error); 2866 return (EINVAL); 2867 } 2868 2869 static int 2870 sysctl_handle_link_status(SYSCTL_HANDLER_ARGS) 2871 { 2872 struct ntb_softc *ntb = arg1; 2873 unsigned res; 2874 int error; 2875 2876 res = intel_ntb_link_is_up(ntb->device, NULL, NULL); 2877 2878 error = SYSCTL_OUT(req, &res, sizeof(res)); 2879 if (error || !req->newptr) 2880 return (error); 2881 return (EINVAL); 2882 } 2883 2884 static int 2885 sysctl_handle_register(SYSCTL_HANDLER_ARGS) 2886 { 2887 struct ntb_softc *ntb; 2888 const void *outp; 2889 uintptr_t sz; 2890 uint64_t umv; 2891 char be[sizeof(umv)]; 2892 size_t outsz; 2893 uint32_t reg; 2894 bool db, pci; 2895 int error; 2896 2897 ntb = arg1; 2898 reg = arg2 & ~NTB_REGFLAGS_MASK; 2899 sz = arg2 & NTB_REGSZ_MASK; 2900 db = (arg2 & NTB_DB_READ) != 0; 2901 pci = (arg2 & NTB_PCI_REG) != 0; 2902 2903 KASSERT(!(db && pci), ("bogus")); 2904 2905 if (db) { 2906 KASSERT(sz == NTB_REG_64, ("bogus")); 2907 umv = db_ioread(ntb, reg); 2908 outsz = sizeof(uint64_t); 2909 } else { 2910 switch (sz) { 2911 case NTB_REG_64: 2912 if (pci) 2913 umv = pci_read_config(ntb->device, reg, 8); 2914 else 2915 umv = intel_ntb_reg_read(8, reg); 2916 outsz = sizeof(uint64_t); 2917 break; 2918 case NTB_REG_32: 2919 if (pci) 2920 umv = pci_read_config(ntb->device, reg, 4); 2921 else 2922 umv = intel_ntb_reg_read(4, reg); 2923 outsz = sizeof(uint32_t); 2924 break; 2925 case NTB_REG_16: 2926 if (pci) 2927 umv = pci_read_config(ntb->device, reg, 2); 2928 else 2929 umv = intel_ntb_reg_read(2, reg); 2930 outsz = sizeof(uint16_t); 2931 break; 2932 case NTB_REG_8: 2933 if (pci) 2934 umv = pci_read_config(ntb->device, reg, 1); 2935 else 2936 umv = intel_ntb_reg_read(1, reg); 2937 outsz = sizeof(uint8_t); 2938 break; 2939 default: 2940 panic("bogus"); 2941 break; 2942 } 2943 } 2944 2945 /* Encode bigendian so that sysctl -x is legible. */ 2946 be64enc(be, umv); 2947 outp = ((char *)be) + sizeof(umv) - outsz; 2948 2949 error = SYSCTL_OUT(req, outp, outsz); 2950 if (error || !req->newptr) 2951 return (error); 2952 return (EINVAL); 2953 } 2954 2955 static unsigned 2956 intel_ntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx) 2957 { 2958 2959 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2960 uidx >= ntb->b2b_mw_idx) || 2961 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx)) 2962 uidx++; 2963 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2964 uidx >= ntb->b2b_mw_idx) && 2965 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx)) 2966 uidx++; 2967 return (uidx); 2968 } 2969 2970 #ifndef EARLY_AP_STARTUP 2971 static int msix_ready; 2972 2973 static void 2974 intel_ntb_msix_ready(void *arg __unused) 2975 { 2976 2977 msix_ready = 1; 2978 } 2979 SYSINIT(intel_ntb_msix_ready, SI_SUB_SMP, SI_ORDER_ANY, 2980 intel_ntb_msix_ready, NULL); 2981 #endif 2982 2983 static void 2984 intel_ntb_exchange_msix(void *ctx) 2985 { 2986 struct ntb_softc *ntb; 2987 uint32_t val; 2988 unsigned i; 2989 2990 ntb = ctx; 2991 2992 if (ntb->peer_msix_good) 2993 goto msix_good; 2994 if (ntb->peer_msix_done) 2995 goto msix_done; 2996 2997 #ifndef EARLY_AP_STARTUP 2998 /* Block MSIX negotiation until SMP started and IRQ reshuffled. */ 2999 if (!msix_ready) 3000 goto reschedule; 3001 #endif 3002 3003 intel_ntb_get_msix_info(ntb); 3004 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 3005 intel_ntb_peer_spad_write(ntb->device, NTB_MSIX_DATA0 + i, 3006 ntb->msix_data[i].nmd_data); 3007 intel_ntb_peer_spad_write(ntb->device, NTB_MSIX_OFS0 + i, 3008 ntb->msix_data[i].nmd_ofs - ntb->msix_xlat); 3009 } 3010 intel_ntb_peer_spad_write(ntb->device, NTB_MSIX_GUARD, NTB_MSIX_VER_GUARD); 3011 3012 intel_ntb_spad_read(ntb->device, NTB_MSIX_GUARD, &val); 3013 if (val != NTB_MSIX_VER_GUARD) 3014 goto reschedule; 3015 3016 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 3017 intel_ntb_spad_read(ntb->device, NTB_MSIX_DATA0 + i, &val); 3018 intel_ntb_printf(2, "remote MSIX data(%u): 0x%x\n", i, val); 3019 ntb->peer_msix_data[i].nmd_data = val; 3020 intel_ntb_spad_read(ntb->device, NTB_MSIX_OFS0 + i, &val); 3021 intel_ntb_printf(2, "remote MSIX addr(%u): 0x%x\n", i, val); 3022 ntb->peer_msix_data[i].nmd_ofs = val; 3023 } 3024 3025 ntb->peer_msix_done = true; 3026 3027 msix_done: 3028 intel_ntb_peer_spad_write(ntb->device, NTB_MSIX_DONE, NTB_MSIX_RECEIVED); 3029 intel_ntb_spad_read(ntb->device, NTB_MSIX_DONE, &val); 3030 if (val != NTB_MSIX_RECEIVED) 3031 goto reschedule; 3032 3033 intel_ntb_spad_clear(ntb->device); 3034 ntb->peer_msix_good = true; 3035 /* Give peer time to see our NTB_MSIX_RECEIVED. */ 3036 goto reschedule; 3037 3038 msix_good: 3039 intel_ntb_poll_link(ntb); 3040 ntb_link_event(ntb->device); 3041 return; 3042 3043 reschedule: 3044 ntb->lnk_sta = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 3045 if (_xeon_link_is_up(ntb)) { 3046 callout_reset(&ntb->peer_msix_work, 3047 hz * (ntb->peer_msix_good ? 2 : 1) / 10, 3048 intel_ntb_exchange_msix, ntb); 3049 } else 3050 intel_ntb_spad_clear(ntb->device); 3051 } 3052 3053 /* 3054 * Public API to the rest of the OS 3055 */ 3056 3057 static uint8_t 3058 intel_ntb_spad_count(device_t dev) 3059 { 3060 struct ntb_softc *ntb = device_get_softc(dev); 3061 3062 return (ntb->spad_count); 3063 } 3064 3065 static uint8_t 3066 intel_ntb_mw_count(device_t dev) 3067 { 3068 struct ntb_softc *ntb = device_get_softc(dev); 3069 uint8_t res; 3070 3071 res = ntb->mw_count; 3072 if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0) 3073 res--; 3074 if (ntb->msix_mw_idx != B2B_MW_DISABLED) 3075 res--; 3076 return (res); 3077 } 3078 3079 static int 3080 intel_ntb_spad_write(device_t dev, unsigned int idx, uint32_t val) 3081 { 3082 struct ntb_softc *ntb = device_get_softc(dev); 3083 3084 if (idx >= ntb->spad_count) 3085 return (EINVAL); 3086 3087 intel_ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); 3088 3089 return (0); 3090 } 3091 3092 /* 3093 * Zeros the local scratchpad. 3094 */ 3095 static void 3096 intel_ntb_spad_clear(device_t dev) 3097 { 3098 struct ntb_softc *ntb = device_get_softc(dev); 3099 unsigned i; 3100 3101 for (i = 0; i < ntb->spad_count; i++) 3102 intel_ntb_spad_write(dev, i, 0); 3103 } 3104 3105 static int 3106 intel_ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val) 3107 { 3108 struct ntb_softc *ntb = device_get_softc(dev); 3109 3110 if (idx >= ntb->spad_count) 3111 return (EINVAL); 3112 3113 *val = intel_ntb_reg_read(4, ntb->self_reg->spad + idx * 4); 3114 3115 return (0); 3116 } 3117 3118 static int 3119 intel_ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val) 3120 { 3121 struct ntb_softc *ntb = device_get_softc(dev); 3122 3123 if (idx >= ntb->spad_count) 3124 return (EINVAL); 3125 3126 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) 3127 intel_ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); 3128 else 3129 intel_ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); 3130 3131 return (0); 3132 } 3133 3134 static int 3135 intel_ntb_peer_spad_read(device_t dev, unsigned int idx, uint32_t *val) 3136 { 3137 struct ntb_softc *ntb = device_get_softc(dev); 3138 3139 if (idx >= ntb->spad_count) 3140 return (EINVAL); 3141 3142 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) 3143 *val = intel_ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); 3144 else 3145 *val = intel_ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); 3146 3147 return (0); 3148 } 3149 3150 static int 3151 intel_ntb_mw_get_range(device_t dev, unsigned mw_idx, vm_paddr_t *base, 3152 caddr_t *vbase, size_t *size, size_t *align, size_t *align_size, 3153 bus_addr_t *plimit) 3154 { 3155 struct ntb_softc *ntb = device_get_softc(dev); 3156 struct ntb_pci_bar_info *bar; 3157 bus_addr_t limit; 3158 size_t bar_b2b_off; 3159 enum ntb_bar bar_num; 3160 3161 if (mw_idx >= intel_ntb_mw_count(dev)) 3162 return (EINVAL); 3163 mw_idx = intel_ntb_user_mw_to_idx(ntb, mw_idx); 3164 3165 bar_num = intel_ntb_mw_to_bar(ntb, mw_idx); 3166 bar = &ntb->bar_info[bar_num]; 3167 bar_b2b_off = 0; 3168 if (mw_idx == ntb->b2b_mw_idx) { 3169 KASSERT(ntb->b2b_off != 0, 3170 ("user shouldn't get non-shared b2b mw")); 3171 bar_b2b_off = ntb->b2b_off; 3172 } 3173 3174 if (bar_is_64bit(ntb, bar_num)) 3175 limit = BUS_SPACE_MAXADDR; 3176 else 3177 limit = BUS_SPACE_MAXADDR_32BIT; 3178 3179 if (base != NULL) 3180 *base = bar->pbase + bar_b2b_off; 3181 if (vbase != NULL) 3182 *vbase = bar->vbase + bar_b2b_off; 3183 if (size != NULL) 3184 *size = bar->size - bar_b2b_off; 3185 if (align != NULL) 3186 *align = bar->size; 3187 if (align_size != NULL) 3188 *align_size = 1; 3189 if (plimit != NULL) 3190 *plimit = limit; 3191 return (0); 3192 } 3193 3194 static int 3195 intel_ntb_mw_set_trans(device_t dev, unsigned idx, bus_addr_t addr, size_t size) 3196 { 3197 struct ntb_softc *ntb = device_get_softc(dev); 3198 struct ntb_pci_bar_info *bar; 3199 uint64_t base, limit, reg_val; 3200 size_t bar_size, mw_size; 3201 uint32_t base_reg, xlat_reg, limit_reg; 3202 enum ntb_bar bar_num; 3203 3204 if (idx >= intel_ntb_mw_count(dev)) 3205 return (EINVAL); 3206 idx = intel_ntb_user_mw_to_idx(ntb, idx); 3207 3208 bar_num = intel_ntb_mw_to_bar(ntb, idx); 3209 bar = &ntb->bar_info[bar_num]; 3210 3211 bar_size = bar->size; 3212 if (idx == ntb->b2b_mw_idx) 3213 mw_size = bar_size - ntb->b2b_off; 3214 else 3215 mw_size = bar_size; 3216 3217 /* Hardware requires that addr is aligned to bar size */ 3218 if ((addr & (bar_size - 1)) != 0) 3219 return (EINVAL); 3220 3221 if (size > mw_size) 3222 return (EINVAL); 3223 3224 bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); 3225 3226 limit = 0; 3227 if (bar_is_64bit(ntb, bar_num)) { 3228 base = intel_ntb_reg_read(8, base_reg) & BAR_HIGH_MASK; 3229 3230 if (limit_reg != 0 && size != mw_size) 3231 limit = base + size; 3232 else 3233 limit = base + mw_size; 3234 3235 /* Set and verify translation address */ 3236 intel_ntb_reg_write(8, xlat_reg, addr); 3237 reg_val = intel_ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK; 3238 if (reg_val != addr) { 3239 intel_ntb_reg_write(8, xlat_reg, 0); 3240 return (EIO); 3241 } 3242 3243 /* Set and verify the limit */ 3244 intel_ntb_reg_write(8, limit_reg, limit); 3245 reg_val = intel_ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK; 3246 if (reg_val != limit) { 3247 intel_ntb_reg_write(8, limit_reg, base); 3248 intel_ntb_reg_write(8, xlat_reg, 0); 3249 return (EIO); 3250 } 3251 3252 if (ntb->type == NTB_XEON_GEN3) { 3253 limit = base + size; 3254 3255 /* set EMBAR1/2XLIMIT */ 3256 if (!idx) 3257 intel_ntb_reg_write(8, 3258 XEON_GEN3_REG_EMBAR1XLIMIT, limit); 3259 else 3260 intel_ntb_reg_write(8, 3261 XEON_GEN3_REG_EMBAR2XLIMIT, limit); 3262 } 3263 } else { 3264 /* Configure 32-bit (split) BAR MW */ 3265 if (ntb->type == NTB_XEON_GEN3) 3266 return (EIO); 3267 3268 if ((addr & UINT32_MAX) != addr) 3269 return (ERANGE); 3270 if (((addr + size) & UINT32_MAX) != (addr + size)) 3271 return (ERANGE); 3272 3273 base = intel_ntb_reg_read(4, base_reg) & BAR_HIGH_MASK; 3274 3275 if (limit_reg != 0 && size != mw_size) 3276 limit = base + size; 3277 3278 /* Set and verify translation address */ 3279 intel_ntb_reg_write(4, xlat_reg, addr); 3280 reg_val = intel_ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK; 3281 if (reg_val != addr) { 3282 intel_ntb_reg_write(4, xlat_reg, 0); 3283 return (EIO); 3284 } 3285 3286 /* Set and verify the limit */ 3287 intel_ntb_reg_write(4, limit_reg, limit); 3288 reg_val = intel_ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK; 3289 if (reg_val != limit) { 3290 intel_ntb_reg_write(4, limit_reg, base); 3291 intel_ntb_reg_write(4, xlat_reg, 0); 3292 return (EIO); 3293 } 3294 } 3295 return (0); 3296 } 3297 3298 static int 3299 intel_ntb_mw_clear_trans(device_t dev, unsigned mw_idx) 3300 { 3301 3302 return (intel_ntb_mw_set_trans(dev, mw_idx, 0, 0)); 3303 } 3304 3305 static int 3306 intel_ntb_mw_get_wc(device_t dev, unsigned idx, vm_memattr_t *mode) 3307 { 3308 struct ntb_softc *ntb = device_get_softc(dev); 3309 struct ntb_pci_bar_info *bar; 3310 3311 if (idx >= intel_ntb_mw_count(dev)) 3312 return (EINVAL); 3313 idx = intel_ntb_user_mw_to_idx(ntb, idx); 3314 3315 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, idx)]; 3316 *mode = bar->map_mode; 3317 return (0); 3318 } 3319 3320 static int 3321 intel_ntb_mw_set_wc(device_t dev, unsigned idx, vm_memattr_t mode) 3322 { 3323 struct ntb_softc *ntb = device_get_softc(dev); 3324 3325 if (idx >= intel_ntb_mw_count(dev)) 3326 return (EINVAL); 3327 3328 idx = intel_ntb_user_mw_to_idx(ntb, idx); 3329 return (intel_ntb_mw_set_wc_internal(ntb, idx, mode)); 3330 } 3331 3332 static int 3333 intel_ntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) 3334 { 3335 struct ntb_pci_bar_info *bar; 3336 int rc; 3337 3338 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, idx)]; 3339 if (bar->map_mode == mode) 3340 return (0); 3341 3342 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode); 3343 if (rc == 0) 3344 bar->map_mode = mode; 3345 3346 return (rc); 3347 } 3348 3349 static void 3350 intel_ntb_peer_db_set(device_t dev, uint64_t bits) 3351 { 3352 struct ntb_softc *ntb = device_get_softc(dev); 3353 uint64_t db; 3354 3355 if ((bits & ~ntb->db_valid_mask) != 0) { 3356 device_printf(ntb->device, "Invalid doorbell bits %#jx\n", 3357 (uintmax_t)bits); 3358 return; 3359 } 3360 3361 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 3362 struct ntb_pci_bar_info *lapic; 3363 unsigned i; 3364 3365 lapic = ntb->peer_lapic_bar; 3366 3367 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 3368 if ((bits & intel_ntb_db_vector_mask(dev, i)) != 0) 3369 bus_space_write_4(lapic->pci_bus_tag, 3370 lapic->pci_bus_handle, 3371 ntb->peer_msix_data[i].nmd_ofs, 3372 ntb->peer_msix_data[i].nmd_data); 3373 } 3374 return; 3375 } 3376 3377 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 3378 intel_ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bits); 3379 return; 3380 } 3381 3382 if (ntb->type == NTB_XEON_GEN3) { 3383 while (bits != 0) { 3384 db = ffsll(bits); 3385 3386 intel_ntb_reg_write(1, 3387 ntb->peer_reg->db_bell + (db - 1) * 4, 0x1); 3388 3389 bits = bits & (bits - 1); 3390 } 3391 } else { 3392 db_iowrite(ntb, ntb->peer_reg->db_bell, bits); 3393 } 3394 } 3395 3396 static int 3397 intel_ntb_peer_db_addr(device_t dev, bus_addr_t *db_addr, vm_size_t *db_size) 3398 { 3399 struct ntb_softc *ntb = device_get_softc(dev); 3400 struct ntb_pci_bar_info *bar; 3401 uint64_t regoff; 3402 3403 KASSERT((db_addr != NULL && db_size != NULL), ("must be non-NULL")); 3404 3405 if (!HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 3406 bar = &ntb->bar_info[NTB_CONFIG_BAR]; 3407 regoff = ntb->peer_reg->db_bell; 3408 } else { 3409 KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, 3410 ("invalid b2b idx")); 3411 3412 bar = &ntb->bar_info[intel_ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; 3413 regoff = XEON_PDOORBELL_OFFSET; 3414 } 3415 KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); 3416 3417 /* HACK: Specific to current x86 bus implementation. */ 3418 *db_addr = ((uint64_t)bar->pci_bus_handle + regoff); 3419 *db_size = ntb->reg->db_size; 3420 return (0); 3421 } 3422 3423 static uint64_t 3424 intel_ntb_db_valid_mask(device_t dev) 3425 { 3426 struct ntb_softc *ntb = device_get_softc(dev); 3427 3428 return (ntb->db_valid_mask); 3429 } 3430 3431 static int 3432 intel_ntb_db_vector_count(device_t dev) 3433 { 3434 struct ntb_softc *ntb = device_get_softc(dev); 3435 3436 return (ntb->db_vec_count); 3437 } 3438 3439 static uint64_t 3440 intel_ntb_db_vector_mask(device_t dev, uint32_t vector) 3441 { 3442 struct ntb_softc *ntb = device_get_softc(dev); 3443 3444 if (vector > ntb->db_vec_count) 3445 return (0); 3446 return (ntb->db_valid_mask & intel_ntb_vec_mask(ntb, vector)); 3447 } 3448 3449 static bool 3450 intel_ntb_link_is_up(device_t dev, enum ntb_speed *speed, enum ntb_width *width) 3451 { 3452 struct ntb_softc *ntb = device_get_softc(dev); 3453 3454 if (speed != NULL) 3455 *speed = intel_ntb_link_sta_speed(ntb); 3456 if (width != NULL) 3457 *width = intel_ntb_link_sta_width(ntb); 3458 return (link_is_up(ntb)); 3459 } 3460 3461 static void 3462 save_bar_parameters(struct ntb_pci_bar_info *bar) 3463 { 3464 3465 bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); 3466 bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); 3467 bar->pbase = rman_get_start(bar->pci_resource); 3468 bar->size = rman_get_size(bar->pci_resource); 3469 bar->vbase = rman_get_virtual(bar->pci_resource); 3470 } 3471 3472 static device_method_t ntb_intel_methods[] = { 3473 /* Device interface */ 3474 DEVMETHOD(device_probe, intel_ntb_probe), 3475 DEVMETHOD(device_attach, intel_ntb_attach), 3476 DEVMETHOD(device_detach, intel_ntb_detach), 3477 /* Bus interface */ 3478 DEVMETHOD(bus_child_location_str, ntb_child_location_str), 3479 DEVMETHOD(bus_print_child, ntb_print_child), 3480 DEVMETHOD(bus_get_dma_tag, ntb_get_dma_tag), 3481 /* NTB interface */ 3482 DEVMETHOD(ntb_port_number, intel_ntb_port_number), 3483 DEVMETHOD(ntb_peer_port_count, intel_ntb_peer_port_count), 3484 DEVMETHOD(ntb_peer_port_number, intel_ntb_peer_port_number), 3485 DEVMETHOD(ntb_peer_port_idx, intel_ntb_peer_port_idx), 3486 DEVMETHOD(ntb_link_is_up, intel_ntb_link_is_up), 3487 DEVMETHOD(ntb_link_enable, intel_ntb_link_enable), 3488 DEVMETHOD(ntb_link_disable, intel_ntb_link_disable), 3489 DEVMETHOD(ntb_link_enabled, intel_ntb_link_enabled), 3490 DEVMETHOD(ntb_mw_count, intel_ntb_mw_count), 3491 DEVMETHOD(ntb_mw_get_range, intel_ntb_mw_get_range), 3492 DEVMETHOD(ntb_mw_set_trans, intel_ntb_mw_set_trans), 3493 DEVMETHOD(ntb_mw_clear_trans, intel_ntb_mw_clear_trans), 3494 DEVMETHOD(ntb_mw_get_wc, intel_ntb_mw_get_wc), 3495 DEVMETHOD(ntb_mw_set_wc, intel_ntb_mw_set_wc), 3496 DEVMETHOD(ntb_spad_count, intel_ntb_spad_count), 3497 DEVMETHOD(ntb_spad_clear, intel_ntb_spad_clear), 3498 DEVMETHOD(ntb_spad_write, intel_ntb_spad_write), 3499 DEVMETHOD(ntb_spad_read, intel_ntb_spad_read), 3500 DEVMETHOD(ntb_peer_spad_write, intel_ntb_peer_spad_write), 3501 DEVMETHOD(ntb_peer_spad_read, intel_ntb_peer_spad_read), 3502 DEVMETHOD(ntb_db_valid_mask, intel_ntb_db_valid_mask), 3503 DEVMETHOD(ntb_db_vector_count, intel_ntb_db_vector_count), 3504 DEVMETHOD(ntb_db_vector_mask, intel_ntb_db_vector_mask), 3505 DEVMETHOD(ntb_db_clear, intel_ntb_db_clear), 3506 DEVMETHOD(ntb_db_clear_mask, intel_ntb_db_clear_mask), 3507 DEVMETHOD(ntb_db_read, intel_ntb_db_read), 3508 DEVMETHOD(ntb_db_set_mask, intel_ntb_db_set_mask), 3509 DEVMETHOD(ntb_peer_db_addr, intel_ntb_peer_db_addr), 3510 DEVMETHOD(ntb_peer_db_set, intel_ntb_peer_db_set), 3511 DEVMETHOD_END 3512 }; 3513 3514 static DEFINE_CLASS_0(ntb_hw, ntb_intel_driver, ntb_intel_methods, 3515 sizeof(struct ntb_softc)); 3516 DRIVER_MODULE(ntb_hw_intel, pci, ntb_intel_driver, ntb_hw_devclass, NULL, NULL); 3517 MODULE_DEPEND(ntb_hw_intel, ntb, 1, 1, 1); 3518 MODULE_VERSION(ntb_hw_intel, 1); 3519 MODULE_PNP_INFO("W32:vendor/device;D:#", pci, ntb_hw_intel, pci_ids, 3520 nitems(pci_ids)); 3521