1 /*- 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright (C) 2019 Advanced Micro Devices, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * BSD LICENSE 14 * 15 * Copyright (C) 2019 Advanced Micro Devices, Inc. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copy 23 * notice, this list of conditions and the following disclaimer in 24 * the documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of AMD corporation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Contact Information : 42 * Rajesh Kumar <rajesh1.kumar@amd.com> 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifndef NTB_HW_AMD_H 48 #define NTB_HW_AMD_H 49 50 #define NTB_HW_AMD_VENDOR_ID 0x1022 51 #define NTB_HW_AMD_DEVICE_ID1 0x145B 52 #define NTB_HW_AMD_DEVICE_ID2 0x148B 53 54 #define NTB_DEF_PEER_CNT 1 55 #define NTB_DEF_PEER_IDX 0 56 57 #define BIT(n) (1 << n) 58 #define AMD_LINK_HB_TIMEOUT (1 * hz) 59 60 #define NTB_LIN_STA_ACTIVE_BIT 0x00000002 61 #define NTB_LNK_STA_SPEED_MASK 0x000F0000 62 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000 63 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LIN_STA_ACTIVE_BIT)) 64 #define NTB_LNK_STA_SPEED(x) (((x) & NTB_LNK_STA_SPEED_MASK) >> 16) 65 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 20) 66 67 #define amd_ntb_bar_read(SIZE, bar, offset) \ 68 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 69 ntb->bar_info[(bar)].pci_bus_handle, (offset)) 70 #define amd_ntb_bar_write(SIZE, bar, offset, val) \ 71 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 72 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 73 #define amd_ntb_reg_read(SIZE, offset) \ 74 amd_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 75 #define amd_ntb_reg_write(SIZE, offset, val) \ 76 amd_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 77 #define amd_ntb_peer_reg_read(SIZE, offset) \ 78 amd_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset + AMD_PEER_OFFSET) 79 #define amd_ntb_peer_reg_write(SIZE, offset, val) \ 80 amd_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset + AMD_PEER_OFFSET, val) 81 82 #define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 83 #define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 84 #define DB_MASK_ASSERT(sc, f) mtx_assert(&(sc)->db_mask_lock, (f)) 85 86 #define QUIRK_MW0_32BIT 0x01 87 88 /* amd_ntb_conn_type are hardware numbers, cannot change. */ 89 enum amd_ntb_conn_type { 90 NTB_CONN_NONE = -1, 91 NTB_CONN_PRI, 92 NTB_CONN_SEC, 93 }; 94 95 enum ntb_default_port { 96 NTB_PORT_PRI_USD, 97 NTB_PORT_SEC_DSD 98 }; 99 100 enum amd_ntb_bar { 101 NTB_CONFIG_BAR = 0, 102 NTB_BAR_1, 103 NTB_BAR_2, 104 NTB_BAR_3, 105 NTB_MAX_BARS 106 }; 107 108 struct amd_ntb_hw_info { 109 uint16_t vendor_id; 110 uint16_t device_id; 111 uint8_t mw_count; 112 uint8_t bar_start_idx; 113 uint8_t spad_count; 114 uint8_t db_count; 115 uint8_t msix_vector_count; 116 uint8_t quirks; 117 char *desc; 118 }; 119 120 struct amd_ntb_pci_bar_info { 121 bus_space_tag_t pci_bus_tag; 122 bus_space_handle_t pci_bus_handle; 123 struct resource *pci_resource; 124 vm_paddr_t pbase; 125 caddr_t vbase; 126 vm_size_t size; 127 vm_memattr_t map_mode; 128 int pci_resource_id; 129 130 /* Configuration register offsets */ 131 uint32_t xlat_off; 132 uint32_t limit_off; 133 }; 134 135 struct amd_ntb_int_info { 136 struct resource *res; 137 void *tag; 138 int rid; 139 }; 140 141 struct amd_ntb_vec { 142 struct amd_ntb_softc *ntb; 143 uint32_t num; 144 unsigned masked; 145 }; 146 147 enum { 148 /* AMD NTB Link Status Offset */ 149 AMD_LINK_STATUS_OFFSET = 0x68, 150 151 /* AMD NTB register offset */ 152 AMD_CNTL_OFFSET = 0x200, 153 154 /* NTB control register bits */ 155 PMM_REG_CTL = BIT(21), 156 SMM_REG_CTL = BIT(20), 157 SMM_REG_ACC_PATH = BIT(18), 158 PMM_REG_ACC_PATH = BIT(17), 159 NTB_CLK_EN = BIT(16), 160 161 AMD_STA_OFFSET = 0x204, 162 AMD_PGSLV_OFFSET = 0x208, 163 AMD_SPAD_MUX_OFFSET = 0x20C, 164 AMD_SPAD_OFFSET = 0x210, 165 AMD_RSMU_HCID = 0x250, 166 AMD_RSMU_SIID = 0x254, 167 AMD_PSION_OFFSET = 0x300, 168 AMD_SSION_OFFSET = 0x330, 169 AMD_MMINDEX_OFFSET = 0x400, 170 AMD_MMDATA_OFFSET = 0x404, 171 AMD_SIDEINFO_OFFSET = 0x408, 172 173 AMD_SIDE_MASK = BIT(0), 174 AMD_SIDE_READY = BIT(1), 175 176 /* limit register */ 177 AMD_ROMBARLMT_OFFSET = 0x410, 178 AMD_BAR1LMT_OFFSET = 0x414, 179 AMD_BAR23LMT_OFFSET = 0x418, 180 AMD_BAR45LMT_OFFSET = 0x420, 181 182 /* xlat address */ 183 AMD_ROMBARXLAT_OFFSET = 0x428, 184 AMD_BAR1XLAT_OFFSET = 0x430, 185 AMD_BAR23XLAT_OFFSET = 0x438, 186 AMD_BAR45XLAT_OFFSET = 0x440, 187 188 /* doorbell and interrupt */ 189 AMD_DBFM_OFFSET = 0x450, 190 AMD_DBREQ_OFFSET = 0x454, 191 AMD_MIRRDBSTAT_OFFSET = 0x458, 192 AMD_DBMASK_OFFSET = 0x45C, 193 AMD_DBSTAT_OFFSET = 0x460, 194 AMD_INTMASK_OFFSET = 0x470, 195 AMD_INTSTAT_OFFSET = 0x474, 196 197 /* event type */ 198 AMD_PEER_FLUSH_EVENT = BIT(0), 199 AMD_PEER_RESET_EVENT = BIT(1), 200 AMD_PEER_D3_EVENT = BIT(2), 201 AMD_PEER_PMETO_EVENT = BIT(3), 202 AMD_PEER_D0_EVENT = BIT(4), 203 AMD_LINK_UP_EVENT = BIT(5), 204 AMD_LINK_DOWN_EVENT = BIT(6), 205 AMD_EVENT_INTMASK = (AMD_PEER_FLUSH_EVENT | 206 AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT | 207 AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT | 208 AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT), 209 210 AMD_PMESTAT_OFFSET = 0x480, 211 AMD_PMSGTRIG_OFFSET = 0x490, 212 AMD_LTRLATENCY_OFFSET = 0x494, 213 AMD_FLUSHTRIG_OFFSET = 0x498, 214 215 /* SMU register*/ 216 AMD_SMUACK_OFFSET = 0x4A0, 217 AMD_SINRST_OFFSET = 0x4A4, 218 AMD_RSPNUM_OFFSET = 0x4A8, 219 AMD_SMU_SPADMUTEX = 0x4B0, 220 AMD_SMU_SPADOFFSET = 0x4B4, 221 222 AMD_PEER_OFFSET = 0x400, 223 }; 224 225 struct amd_ntb_softc { 226 /* ntb.c context. Do not move! Must go first! */ 227 void *ntb_store; 228 229 device_t device; 230 enum amd_ntb_conn_type conn_type; 231 232 struct amd_ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 233 struct amd_ntb_int_info int_info[16]; 234 struct amd_ntb_vec *msix_vec; 235 uint16_t allocated_interrupts; 236 237 struct callout hb_timer; 238 239 struct amd_ntb_hw_info *hw_info; 240 uint8_t spad_count; 241 uint8_t msix_vec_count; 242 243 struct mtx db_mask_lock; 244 245 volatile uint32_t ntb_ctl; 246 volatile uint32_t lnk_sta; 247 volatile uint32_t peer_sta; 248 volatile uint32_t cntl_sta; 249 250 uint16_t db_valid_mask; 251 uint16_t db_mask; 252 uint32_t int_mask; 253 254 unsigned int self_spad; 255 unsigned int peer_spad; 256 }; 257 258 static void amd_init_side_info(struct amd_ntb_softc *ntb); 259 static void amd_deinit_side_info(struct amd_ntb_softc *ntb); 260 static int amd_ntb_detach(device_t device); 261 262 #endif 263