1 /*- 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright (C) 2019 Advanced Micro Devices, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * BSD LICENSE 14 * 15 * Copyright (C) 2019 Advanced Micro Devices, Inc. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copy 23 * notice, this list of conditions and the following disclaimer in 24 * the documentation and/or other materials provided with the distribution. 25 * 3. Neither the name of AMD corporation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Contact Information : 42 * Rajesh Kumar <rajesh1.kumar@amd.com> 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifndef NTB_HW_AMD_H 48 #define NTB_HW_AMD_H 49 50 #define NTB_HW_AMD_VENDOR_ID 0x1022 51 #define NTB_HW_AMD_DEVICE_ID 0x145B 52 53 #define NTB_DEF_PEER_CNT 1 54 #define NTB_DEF_PEER_IDX 0 55 56 #define BIT(n) (1 << n) 57 #define AMD_LINK_HB_TIMEOUT (1 * hz) 58 59 #define NTB_LIN_STA_ACTIVE_BIT 0x00000002 60 #define NTB_LNK_STA_SPEED_MASK 0x000F0000 61 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000 62 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LIN_STA_ACTIVE_BIT)) 63 #define NTB_LNK_STA_SPEED(x) (((x) & NTB_LNK_STA_SPEED_MASK) >> 16) 64 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 20) 65 66 #define amd_ntb_bar_read(SIZE, bar, offset) \ 67 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 68 ntb->bar_info[(bar)].pci_bus_handle, (offset)) 69 #define amd_ntb_bar_write(SIZE, bar, offset, val) \ 70 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 71 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 72 #define amd_ntb_reg_read(SIZE, offset) \ 73 amd_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 74 #define amd_ntb_reg_write(SIZE, offset, val) \ 75 amd_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 76 #define amd_ntb_peer_reg_read(SIZE, offset) \ 77 amd_ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset + AMD_PEER_OFFSET) 78 #define amd_ntb_peer_reg_write(SIZE, offset, val) \ 79 amd_ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset + AMD_PEER_OFFSET, val) 80 81 #define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 82 #define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 83 #define DB_MASK_ASSERT(sc, f) mtx_assert(&(sc)->db_mask_lock, (f)) 84 85 /* amd_ntb_conn_type are hardware numbers, cannot change. */ 86 enum amd_ntb_conn_type { 87 NTB_CONN_NONE = -1, 88 NTB_CONN_PRI, 89 NTB_CONN_SEC, 90 }; 91 92 enum ntb_default_port { 93 NTB_PORT_PRI_USD, 94 NTB_PORT_SEC_DSD 95 }; 96 97 enum amd_ntb_bar { 98 NTB_CONFIG_BAR = 0, 99 NTB_BAR_1, 100 NTB_BAR_2, 101 NTB_BAR_3, 102 NTB_MAX_BARS 103 }; 104 105 struct amd_ntb_hw_info { 106 uint32_t device_id; 107 const char *desc; 108 }; 109 110 struct amd_ntb_pci_bar_info { 111 bus_space_tag_t pci_bus_tag; 112 bus_space_handle_t pci_bus_handle; 113 struct resource *pci_resource; 114 vm_paddr_t pbase; 115 caddr_t vbase; 116 vm_size_t size; 117 vm_memattr_t map_mode; 118 int pci_resource_id; 119 120 /* Configuration register offsets */ 121 uint32_t xlat_off; 122 uint32_t limit_off; 123 }; 124 125 struct amd_ntb_int_info { 126 struct resource *res; 127 void *tag; 128 int rid; 129 }; 130 131 struct amd_ntb_vec { 132 struct amd_ntb_softc *ntb; 133 uint32_t num; 134 unsigned masked; 135 }; 136 137 enum { 138 /* AMD NTB Capability */ 139 AMD_MW_CNT = 3, 140 AMD_DB_CNT = 16, 141 AMD_MSIX_VECTOR_CNT = 24, 142 AMD_SPADS_CNT = 16, 143 144 /* AMD NTB Link Status Offset */ 145 AMD_LINK_STATUS_OFFSET = 0x68, 146 147 /* AMD NTB register offset */ 148 AMD_CNTL_OFFSET = 0x200, 149 150 /* NTB control register bits */ 151 PMM_REG_CTL = BIT(21), 152 SMM_REG_CTL = BIT(20), 153 SMM_REG_ACC_PATH = BIT(18), 154 PMM_REG_ACC_PATH = BIT(17), 155 NTB_CLK_EN = BIT(16), 156 157 AMD_STA_OFFSET = 0x204, 158 AMD_PGSLV_OFFSET = 0x208, 159 AMD_SPAD_MUX_OFFSET = 0x20C, 160 AMD_SPAD_OFFSET = 0x210, 161 AMD_RSMU_HCID = 0x250, 162 AMD_RSMU_SIID = 0x254, 163 AMD_PSION_OFFSET = 0x300, 164 AMD_SSION_OFFSET = 0x330, 165 AMD_MMINDEX_OFFSET = 0x400, 166 AMD_MMDATA_OFFSET = 0x404, 167 AMD_SIDEINFO_OFFSET = 0x408, 168 169 AMD_SIDE_MASK = BIT(0), 170 AMD_SIDE_READY = BIT(1), 171 172 /* limit register */ 173 AMD_ROMBARLMT_OFFSET = 0x410, 174 AMD_BAR1LMT_OFFSET = 0x414, 175 AMD_BAR23LMT_OFFSET = 0x418, 176 AMD_BAR45LMT_OFFSET = 0x420, 177 178 /* xlat address */ 179 AMD_ROMBARXLAT_OFFSET = 0x428, 180 AMD_BAR1XLAT_OFFSET = 0x430, 181 AMD_BAR23XLAT_OFFSET = 0x438, 182 AMD_BAR45XLAT_OFFSET = 0x440, 183 184 /* doorbell and interrupt */ 185 AMD_DBFM_OFFSET = 0x450, 186 AMD_DBREQ_OFFSET = 0x454, 187 AMD_MIRRDBSTAT_OFFSET = 0x458, 188 AMD_DBMASK_OFFSET = 0x45C, 189 AMD_DBSTAT_OFFSET = 0x460, 190 AMD_INTMASK_OFFSET = 0x470, 191 AMD_INTSTAT_OFFSET = 0x474, 192 193 /* event type */ 194 AMD_PEER_FLUSH_EVENT = BIT(0), 195 AMD_PEER_RESET_EVENT = BIT(1), 196 AMD_PEER_D3_EVENT = BIT(2), 197 AMD_PEER_PMETO_EVENT = BIT(3), 198 AMD_PEER_D0_EVENT = BIT(4), 199 AMD_LINK_UP_EVENT = BIT(5), 200 AMD_LINK_DOWN_EVENT = BIT(6), 201 AMD_EVENT_INTMASK = (AMD_PEER_FLUSH_EVENT | 202 AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT | 203 AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT | 204 AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT), 205 206 AMD_PMESTAT_OFFSET = 0x480, 207 AMD_PMSGTRIG_OFFSET = 0x490, 208 AMD_LTRLATENCY_OFFSET = 0x494, 209 AMD_FLUSHTRIG_OFFSET = 0x498, 210 211 /* SMU register*/ 212 AMD_SMUACK_OFFSET = 0x4A0, 213 AMD_SINRST_OFFSET = 0x4A4, 214 AMD_RSPNUM_OFFSET = 0x4A8, 215 AMD_SMU_SPADMUTEX = 0x4B0, 216 AMD_SMU_SPADOFFSET = 0x4B4, 217 218 AMD_PEER_OFFSET = 0x400, 219 }; 220 221 struct amd_ntb_softc { 222 /* ntb.c context. Do not move! Must go first! */ 223 void *ntb_store; 224 225 device_t device; 226 enum amd_ntb_conn_type conn_type; 227 228 struct amd_ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 229 struct amd_ntb_int_info int_info[AMD_MSIX_VECTOR_CNT]; 230 struct amd_ntb_vec *msix_vec; 231 uint16_t allocated_interrupts; 232 233 struct callout hb_timer; 234 235 uint8_t mw_count; 236 uint8_t spad_count; 237 uint8_t db_count; 238 uint8_t msix_vec_count; 239 240 struct mtx db_mask_lock; 241 242 volatile uint32_t ntb_ctl; 243 volatile uint32_t lnk_sta; 244 volatile uint32_t peer_sta; 245 volatile uint32_t cntl_sta; 246 247 uint16_t db_valid_mask; 248 uint16_t db_mask; 249 uint32_t int_mask; 250 251 unsigned int self_spad; 252 unsigned int peer_spad; 253 }; 254 255 static void amd_init_side_info(struct amd_ntb_softc *ntb); 256 static void amd_deinit_side_info(struct amd_ntb_softc *ntb); 257 static int amd_ntb_detach(device_t device); 258 259 #endif 260