1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #ifdef HAVE_KERNEL_OPTION_HEADERS 92 #include "opt_device_polling.h" 93 #endif 94 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/bus.h> 98 #include <sys/endian.h> 99 #include <sys/kernel.h> 100 #include <sys/lock.h> 101 #include <sys/malloc.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/rman.h> 106 #include <sys/socket.h> 107 #include <sys/sockio.h> 108 #include <sys/sysctl.h> 109 110 #include <net/bpf.h> 111 #include <net/if.h> 112 #include <net/if_arp.h> 113 #include <net/ethernet.h> 114 #include <net/if_dl.h> 115 #include <net/if_media.h> 116 #include <net/if_types.h> 117 #include <net/if_vlan_var.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/mii_bitbang.h> 121 #include <dev/mii/miivar.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #include <machine/bus.h> 127 128 #include <dev/nge/if_ngereg.h> 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 MODULE_DEPEND(nge, pci, 1, 1, 1); 134 MODULE_DEPEND(nge, ether, 1, 1, 1); 135 MODULE_DEPEND(nge, miibus, 1, 1, 1); 136 137 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static const struct nge_type nge_devs[] = { 143 { NGE_VENDORID, NGE_DEVICEID, 144 "National Semiconductor Gigabit Ethernet" }, 145 { 0, 0, NULL } 146 }; 147 148 static int nge_probe(device_t); 149 static int nge_attach(device_t); 150 static int nge_detach(device_t); 151 static int nge_shutdown(device_t); 152 static int nge_suspend(device_t); 153 static int nge_resume(device_t); 154 155 static __inline void nge_discard_rxbuf(struct nge_softc *, int); 156 static int nge_newbuf(struct nge_softc *, int); 157 static int nge_encap(struct nge_softc *, struct mbuf **); 158 #ifndef __NO_STRICT_ALIGNMENT 159 static __inline void nge_fixup_rx(struct mbuf *); 160 #endif 161 static int nge_rxeof(struct nge_softc *); 162 static void nge_txeof(struct nge_softc *); 163 static void nge_intr(void *); 164 static void nge_tick(void *); 165 static void nge_stats_update(struct nge_softc *); 166 static void nge_start(struct ifnet *); 167 static void nge_start_locked(struct ifnet *); 168 static int nge_ioctl(struct ifnet *, u_long, caddr_t); 169 static void nge_init(void *); 170 static void nge_init_locked(struct nge_softc *); 171 static int nge_stop_mac(struct nge_softc *); 172 static void nge_stop(struct nge_softc *); 173 static void nge_wol(struct nge_softc *); 174 static void nge_watchdog(struct nge_softc *); 175 static int nge_mediachange(struct ifnet *); 176 static void nge_mediastatus(struct ifnet *, struct ifmediareq *); 177 178 static void nge_delay(struct nge_softc *); 179 static void nge_eeprom_idle(struct nge_softc *); 180 static void nge_eeprom_putbyte(struct nge_softc *, int); 181 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 182 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int); 183 184 static int nge_miibus_readreg(device_t, int, int); 185 static int nge_miibus_writereg(device_t, int, int, int); 186 static void nge_miibus_statchg(device_t); 187 188 static void nge_rxfilter(struct nge_softc *); 189 static void nge_reset(struct nge_softc *); 190 static void nge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 191 static int nge_dma_alloc(struct nge_softc *); 192 static void nge_dma_free(struct nge_softc *); 193 static int nge_list_rx_init(struct nge_softc *); 194 static int nge_list_tx_init(struct nge_softc *); 195 static void nge_sysctl_node(struct nge_softc *); 196 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 197 static int sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS); 198 199 /* 200 * MII bit-bang glue 201 */ 202 static uint32_t nge_mii_bitbang_read(device_t); 203 static void nge_mii_bitbang_write(device_t, uint32_t); 204 205 static const struct mii_bitbang_ops nge_mii_bitbang_ops = { 206 nge_mii_bitbang_read, 207 nge_mii_bitbang_write, 208 { 209 NGE_MEAR_MII_DATA, /* MII_BIT_MDO */ 210 NGE_MEAR_MII_DATA, /* MII_BIT_MDI */ 211 NGE_MEAR_MII_CLK, /* MII_BIT_MDC */ 212 NGE_MEAR_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 213 0, /* MII_BIT_DIR_PHY_HOST */ 214 } 215 }; 216 217 static device_method_t nge_methods[] = { 218 /* Device interface */ 219 DEVMETHOD(device_probe, nge_probe), 220 DEVMETHOD(device_attach, nge_attach), 221 DEVMETHOD(device_detach, nge_detach), 222 DEVMETHOD(device_shutdown, nge_shutdown), 223 DEVMETHOD(device_suspend, nge_suspend), 224 DEVMETHOD(device_resume, nge_resume), 225 226 /* MII interface */ 227 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 228 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 229 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 230 231 DEVMETHOD_END 232 }; 233 234 static driver_t nge_driver = { 235 "nge", 236 nge_methods, 237 sizeof(struct nge_softc) 238 }; 239 240 static devclass_t nge_devclass; 241 242 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 243 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 244 245 #define NGE_SETBIT(sc, reg, x) \ 246 CSR_WRITE_4(sc, reg, \ 247 CSR_READ_4(sc, reg) | (x)) 248 249 #define NGE_CLRBIT(sc, reg, x) \ 250 CSR_WRITE_4(sc, reg, \ 251 CSR_READ_4(sc, reg) & ~(x)) 252 253 #define SIO_SET(x) \ 254 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 255 256 #define SIO_CLR(x) \ 257 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 258 259 static void 260 nge_delay(struct nge_softc *sc) 261 { 262 int idx; 263 264 for (idx = (300 / 33) + 1; idx > 0; idx--) 265 CSR_READ_4(sc, NGE_CSR); 266 } 267 268 static void 269 nge_eeprom_idle(struct nge_softc *sc) 270 { 271 int i; 272 273 SIO_SET(NGE_MEAR_EE_CSEL); 274 nge_delay(sc); 275 SIO_SET(NGE_MEAR_EE_CLK); 276 nge_delay(sc); 277 278 for (i = 0; i < 25; i++) { 279 SIO_CLR(NGE_MEAR_EE_CLK); 280 nge_delay(sc); 281 SIO_SET(NGE_MEAR_EE_CLK); 282 nge_delay(sc); 283 } 284 285 SIO_CLR(NGE_MEAR_EE_CLK); 286 nge_delay(sc); 287 SIO_CLR(NGE_MEAR_EE_CSEL); 288 nge_delay(sc); 289 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 290 } 291 292 /* 293 * Send a read command and address to the EEPROM, check for ACK. 294 */ 295 static void 296 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 297 { 298 int d, i; 299 300 d = addr | NGE_EECMD_READ; 301 302 /* 303 * Feed in each bit and stobe the clock. 304 */ 305 for (i = 0x400; i; i >>= 1) { 306 if (d & i) { 307 SIO_SET(NGE_MEAR_EE_DIN); 308 } else { 309 SIO_CLR(NGE_MEAR_EE_DIN); 310 } 311 nge_delay(sc); 312 SIO_SET(NGE_MEAR_EE_CLK); 313 nge_delay(sc); 314 SIO_CLR(NGE_MEAR_EE_CLK); 315 nge_delay(sc); 316 } 317 } 318 319 /* 320 * Read a word of data stored in the EEPROM at address 'addr.' 321 */ 322 static void 323 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 324 { 325 int i; 326 uint16_t word = 0; 327 328 /* Force EEPROM to idle state. */ 329 nge_eeprom_idle(sc); 330 331 /* Enter EEPROM access mode. */ 332 nge_delay(sc); 333 SIO_CLR(NGE_MEAR_EE_CLK); 334 nge_delay(sc); 335 SIO_SET(NGE_MEAR_EE_CSEL); 336 nge_delay(sc); 337 338 /* 339 * Send address of word we want to read. 340 */ 341 nge_eeprom_putbyte(sc, addr); 342 343 /* 344 * Start reading bits from EEPROM. 345 */ 346 for (i = 0x8000; i; i >>= 1) { 347 SIO_SET(NGE_MEAR_EE_CLK); 348 nge_delay(sc); 349 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 350 word |= i; 351 nge_delay(sc); 352 SIO_CLR(NGE_MEAR_EE_CLK); 353 nge_delay(sc); 354 } 355 356 /* Turn off EEPROM access mode. */ 357 nge_eeprom_idle(sc); 358 359 *dest = word; 360 } 361 362 /* 363 * Read a sequence of words from the EEPROM. 364 */ 365 static void 366 nge_read_eeprom(struct nge_softc *sc, caddr_t dest, int off, int cnt) 367 { 368 int i; 369 uint16_t word = 0, *ptr; 370 371 for (i = 0; i < cnt; i++) { 372 nge_eeprom_getword(sc, off + i, &word); 373 ptr = (uint16_t *)(dest + (i * 2)); 374 *ptr = word; 375 } 376 } 377 378 /* 379 * Read the MII serial port for the MII bit-bang module. 380 */ 381 static uint32_t 382 nge_mii_bitbang_read(device_t dev) 383 { 384 struct nge_softc *sc; 385 uint32_t val; 386 387 sc = device_get_softc(dev); 388 389 val = CSR_READ_4(sc, NGE_MEAR); 390 CSR_BARRIER_4(sc, NGE_MEAR, 391 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 392 393 return (val); 394 } 395 396 /* 397 * Write the MII serial port for the MII bit-bang module. 398 */ 399 static void 400 nge_mii_bitbang_write(device_t dev, uint32_t val) 401 { 402 struct nge_softc *sc; 403 404 sc = device_get_softc(dev); 405 406 CSR_WRITE_4(sc, NGE_MEAR, val); 407 CSR_BARRIER_4(sc, NGE_MEAR, 408 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 409 } 410 411 static int 412 nge_miibus_readreg(device_t dev, int phy, int reg) 413 { 414 struct nge_softc *sc; 415 int rv; 416 417 sc = device_get_softc(dev); 418 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 419 /* Pretend PHY is at address 0. */ 420 if (phy != 0) 421 return (0); 422 switch (reg) { 423 case MII_BMCR: 424 reg = NGE_TBI_BMCR; 425 break; 426 case MII_BMSR: 427 /* 83820/83821 has different bit layout for BMSR. */ 428 rv = BMSR_ANEG | BMSR_EXTCAP | BMSR_EXTSTAT; 429 reg = CSR_READ_4(sc, NGE_TBI_BMSR); 430 if ((reg & NGE_TBIBMSR_ANEG_DONE) != 0) 431 rv |= BMSR_ACOMP; 432 if ((reg & NGE_TBIBMSR_LINKSTAT) != 0) 433 rv |= BMSR_LINK; 434 return (rv); 435 case MII_ANAR: 436 reg = NGE_TBI_ANAR; 437 break; 438 case MII_ANLPAR: 439 reg = NGE_TBI_ANLPAR; 440 break; 441 case MII_ANER: 442 reg = NGE_TBI_ANER; 443 break; 444 case MII_EXTSR: 445 reg = NGE_TBI_ESR; 446 break; 447 case MII_PHYIDR1: 448 case MII_PHYIDR2: 449 return (0); 450 default: 451 device_printf(sc->nge_dev, 452 "bad phy register read : %d\n", reg); 453 return (0); 454 } 455 return (CSR_READ_4(sc, reg)); 456 } 457 458 return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg)); 459 } 460 461 static int 462 nge_miibus_writereg(device_t dev, int phy, int reg, int data) 463 { 464 struct nge_softc *sc; 465 466 sc = device_get_softc(dev); 467 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 468 /* Pretend PHY is at address 0. */ 469 if (phy != 0) 470 return (0); 471 switch (reg) { 472 case MII_BMCR: 473 reg = NGE_TBI_BMCR; 474 break; 475 case MII_BMSR: 476 return (0); 477 case MII_ANAR: 478 reg = NGE_TBI_ANAR; 479 break; 480 case MII_ANLPAR: 481 reg = NGE_TBI_ANLPAR; 482 break; 483 case MII_ANER: 484 reg = NGE_TBI_ANER; 485 break; 486 case MII_EXTSR: 487 reg = NGE_TBI_ESR; 488 break; 489 case MII_PHYIDR1: 490 case MII_PHYIDR2: 491 return (0); 492 default: 493 device_printf(sc->nge_dev, 494 "bad phy register write : %d\n", reg); 495 return (0); 496 } 497 CSR_WRITE_4(sc, reg, data); 498 return (0); 499 } 500 501 mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data); 502 503 return (0); 504 } 505 506 /* 507 * media status/link state change handler. 508 */ 509 static void 510 nge_miibus_statchg(device_t dev) 511 { 512 struct nge_softc *sc; 513 struct mii_data *mii; 514 struct ifnet *ifp; 515 struct nge_txdesc *txd; 516 uint32_t done, reg, status; 517 int i; 518 519 sc = device_get_softc(dev); 520 NGE_LOCK_ASSERT(sc); 521 522 mii = device_get_softc(sc->nge_miibus); 523 ifp = sc->nge_ifp; 524 if (mii == NULL || ifp == NULL || 525 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 526 return; 527 528 sc->nge_flags &= ~NGE_FLAG_LINK; 529 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 530 (IFM_AVALID | IFM_ACTIVE)) { 531 switch (IFM_SUBTYPE(mii->mii_media_active)) { 532 case IFM_10_T: 533 case IFM_100_TX: 534 case IFM_1000_T: 535 case IFM_1000_SX: 536 case IFM_1000_LX: 537 case IFM_1000_CX: 538 sc->nge_flags |= NGE_FLAG_LINK; 539 break; 540 default: 541 break; 542 } 543 } 544 545 /* Stop Tx/Rx MACs. */ 546 if (nge_stop_mac(sc) == ETIMEDOUT) 547 device_printf(sc->nge_dev, 548 "%s: unable to stop Tx/Rx MAC\n", __func__); 549 nge_txeof(sc); 550 nge_rxeof(sc); 551 if (sc->nge_head != NULL) { 552 m_freem(sc->nge_head); 553 sc->nge_head = sc->nge_tail = NULL; 554 } 555 556 /* Release queued frames. */ 557 for (i = 0; i < NGE_TX_RING_CNT; i++) { 558 txd = &sc->nge_cdata.nge_txdesc[i]; 559 if (txd->tx_m != NULL) { 560 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 561 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 562 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 563 txd->tx_dmamap); 564 m_freem(txd->tx_m); 565 txd->tx_m = NULL; 566 } 567 } 568 569 /* Program MAC with resolved speed/duplex. */ 570 if ((sc->nge_flags & NGE_FLAG_LINK) != 0) { 571 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 572 NGE_SETBIT(sc, NGE_TX_CFG, 573 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 574 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 575 #ifdef notyet 576 /* Enable flow-control. */ 577 if ((IFM_OPTIONS(mii->mii_media_active) & 578 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) != 0) 579 NGE_SETBIT(sc, NGE_PAUSECSR, 580 NGE_PAUSECSR_PAUSE_ENB); 581 #endif 582 } else { 583 NGE_CLRBIT(sc, NGE_TX_CFG, 584 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 585 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 586 NGE_CLRBIT(sc, NGE_PAUSECSR, NGE_PAUSECSR_PAUSE_ENB); 587 } 588 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 589 reg = CSR_READ_4(sc, NGE_CFG); 590 switch (IFM_SUBTYPE(mii->mii_media_active)) { 591 case IFM_1000_SX: 592 case IFM_1000_LX: 593 case IFM_1000_CX: 594 case IFM_1000_T: 595 reg |= NGE_CFG_MODE_1000; 596 break; 597 default: 598 reg &= ~NGE_CFG_MODE_1000; 599 break; 600 } 601 CSR_WRITE_4(sc, NGE_CFG, reg); 602 603 /* Reset Tx/Rx MAC. */ 604 reg = CSR_READ_4(sc, NGE_CSR); 605 reg |= NGE_CSR_TX_RESET | NGE_CSR_RX_RESET; 606 CSR_WRITE_4(sc, NGE_CSR, reg); 607 /* Check the completion of reset. */ 608 done = 0; 609 for (i = 0; i < NGE_TIMEOUT; i++) { 610 DELAY(1); 611 status = CSR_READ_4(sc, NGE_ISR); 612 if ((status & NGE_ISR_RX_RESET_DONE) != 0) 613 done |= NGE_ISR_RX_RESET_DONE; 614 if ((status & NGE_ISR_TX_RESET_DONE) != 0) 615 done |= NGE_ISR_TX_RESET_DONE; 616 if (done == 617 (NGE_ISR_TX_RESET_DONE | NGE_ISR_RX_RESET_DONE)) 618 break; 619 } 620 if (i == NGE_TIMEOUT) 621 device_printf(sc->nge_dev, 622 "%s: unable to reset Tx/Rx MAC\n", __func__); 623 /* Reuse Rx buffer and reset consumer pointer. */ 624 sc->nge_cdata.nge_rx_cons = 0; 625 /* 626 * It seems that resetting Rx/Tx MAC results in 627 * resetting Tx/Rx descriptor pointer registers such 628 * that reloading Tx/Rx lists address are needed. 629 */ 630 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 631 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 632 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 633 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 634 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 635 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 636 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 637 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 638 /* Reinitialize Tx buffers. */ 639 nge_list_tx_init(sc); 640 641 /* Restart Rx MAC. */ 642 reg = CSR_READ_4(sc, NGE_CSR); 643 reg |= NGE_CSR_RX_ENABLE; 644 CSR_WRITE_4(sc, NGE_CSR, reg); 645 for (i = 0; i < NGE_TIMEOUT; i++) { 646 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0) 647 break; 648 DELAY(1); 649 } 650 if (i == NGE_TIMEOUT) 651 device_printf(sc->nge_dev, 652 "%s: unable to restart Rx MAC\n", __func__); 653 } 654 655 /* Data LED off for TBI mode */ 656 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 657 CSR_WRITE_4(sc, NGE_GPIO, 658 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 659 } 660 661 static void 662 nge_rxfilter(struct nge_softc *sc) 663 { 664 struct ifnet *ifp; 665 struct ifmultiaddr *ifma; 666 uint32_t h, i, rxfilt; 667 int bit, index; 668 669 NGE_LOCK_ASSERT(sc); 670 ifp = sc->nge_ifp; 671 672 /* Make sure to stop Rx filtering. */ 673 rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL); 674 rxfilt &= ~NGE_RXFILTCTL_ENABLE; 675 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 676 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 677 678 rxfilt &= ~(NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_ALLPHYS); 679 rxfilt &= ~NGE_RXFILTCTL_BROAD; 680 /* 681 * We don't want to use the hash table for matching unicast 682 * addresses. 683 */ 684 rxfilt &= ~(NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 685 686 /* 687 * For the NatSemi chip, we have to explicitly enable the 688 * reception of ARP frames, as well as turn on the 'perfect 689 * match' filter where we store the station address, otherwise 690 * we won't receive unicasts meant for this host. 691 */ 692 rxfilt |= NGE_RXFILTCTL_ARP | NGE_RXFILTCTL_PERFECT; 693 694 /* 695 * Set the capture broadcast bit to capture broadcast frames. 696 */ 697 if ((ifp->if_flags & IFF_BROADCAST) != 0) 698 rxfilt |= NGE_RXFILTCTL_BROAD; 699 700 if ((ifp->if_flags & IFF_PROMISC) != 0 || 701 (ifp->if_flags & IFF_ALLMULTI) != 0) { 702 rxfilt |= NGE_RXFILTCTL_ALLMULTI; 703 if ((ifp->if_flags & IFF_PROMISC) != 0) 704 rxfilt |= NGE_RXFILTCTL_ALLPHYS; 705 goto done; 706 } 707 708 /* 709 * We have to explicitly enable the multicast hash table 710 * on the NatSemi chip if we want to use it, which we do. 711 */ 712 rxfilt |= NGE_RXFILTCTL_MCHASH; 713 714 /* first, zot all the existing hash bits */ 715 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 716 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 717 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 718 } 719 720 /* 721 * From the 11 bits returned by the crc routine, the top 7 722 * bits represent the 16-bit word in the mcast hash table 723 * that needs to be updated, and the lower 4 bits represent 724 * which bit within that byte needs to be set. 725 */ 726 if_maddr_rlock(ifp); 727 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 728 if (ifma->ifma_addr->sa_family != AF_LINK) 729 continue; 730 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 731 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 732 index = (h >> 4) & 0x7F; 733 bit = h & 0xF; 734 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 735 NGE_FILTADDR_MCAST_LO + (index * 2)); 736 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 737 } 738 if_maddr_runlock(ifp); 739 740 done: 741 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 742 /* Turn the receive filter on. */ 743 rxfilt |= NGE_RXFILTCTL_ENABLE; 744 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 745 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 746 } 747 748 static void 749 nge_reset(struct nge_softc *sc) 750 { 751 uint32_t v; 752 int i; 753 754 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 755 756 for (i = 0; i < NGE_TIMEOUT; i++) { 757 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 758 break; 759 DELAY(1); 760 } 761 762 if (i == NGE_TIMEOUT) 763 device_printf(sc->nge_dev, "reset never completed\n"); 764 765 /* Wait a little while for the chip to get its brains in order. */ 766 DELAY(1000); 767 768 /* 769 * If this is a NetSemi chip, make sure to clear 770 * PME mode. 771 */ 772 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 773 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 774 775 /* Clear WOL events which may interfere normal Rx filter opertaion. */ 776 CSR_WRITE_4(sc, NGE_WOLCSR, 0); 777 778 /* 779 * Only DP83820 supports 64bits addressing/data transfers and 780 * 64bit addressing requires different descriptor structures. 781 * To make it simple, disable 64bit addressing/data transfers. 782 */ 783 v = CSR_READ_4(sc, NGE_CFG); 784 v &= ~(NGE_CFG_64BIT_ADDR_ENB | NGE_CFG_64BIT_DATA_ENB); 785 CSR_WRITE_4(sc, NGE_CFG, v); 786 } 787 788 /* 789 * Probe for a NatSemi chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792 static int 793 nge_probe(device_t dev) 794 { 795 const struct nge_type *t; 796 797 t = nge_devs; 798 799 while (t->nge_name != NULL) { 800 if ((pci_get_vendor(dev) == t->nge_vid) && 801 (pci_get_device(dev) == t->nge_did)) { 802 device_set_desc(dev, t->nge_name); 803 return (BUS_PROBE_DEFAULT); 804 } 805 t++; 806 } 807 808 return (ENXIO); 809 } 810 811 /* 812 * Attach the interface. Allocate softc structures, do ifmedia 813 * setup and ethernet/BPF attach. 814 */ 815 static int 816 nge_attach(device_t dev) 817 { 818 uint8_t eaddr[ETHER_ADDR_LEN]; 819 uint16_t ea[ETHER_ADDR_LEN/2], ea_temp, reg; 820 struct nge_softc *sc; 821 struct ifnet *ifp; 822 int error, i, rid; 823 824 error = 0; 825 sc = device_get_softc(dev); 826 sc->nge_dev = dev; 827 828 NGE_LOCK_INIT(sc, device_get_nameunit(dev)); 829 callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0); 830 831 /* 832 * Map control/status registers. 833 */ 834 pci_enable_busmaster(dev); 835 836 #ifdef NGE_USEIOSPACE 837 sc->nge_res_type = SYS_RES_IOPORT; 838 sc->nge_res_id = PCIR_BAR(0); 839 #else 840 sc->nge_res_type = SYS_RES_MEMORY; 841 sc->nge_res_id = PCIR_BAR(1); 842 #endif 843 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 844 &sc->nge_res_id, RF_ACTIVE); 845 846 if (sc->nge_res == NULL) { 847 if (sc->nge_res_type == SYS_RES_MEMORY) { 848 sc->nge_res_type = SYS_RES_IOPORT; 849 sc->nge_res_id = PCIR_BAR(0); 850 } else { 851 sc->nge_res_type = SYS_RES_MEMORY; 852 sc->nge_res_id = PCIR_BAR(1); 853 } 854 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 855 &sc->nge_res_id, RF_ACTIVE); 856 if (sc->nge_res == NULL) { 857 device_printf(dev, "couldn't allocate %s resources\n", 858 sc->nge_res_type == SYS_RES_MEMORY ? "memory" : 859 "I/O"); 860 NGE_LOCK_DESTROY(sc); 861 return (ENXIO); 862 } 863 } 864 865 /* Allocate interrupt */ 866 rid = 0; 867 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 868 RF_SHAREABLE | RF_ACTIVE); 869 870 if (sc->nge_irq == NULL) { 871 device_printf(dev, "couldn't map interrupt\n"); 872 error = ENXIO; 873 goto fail; 874 } 875 876 /* Enable MWI. */ 877 reg = pci_read_config(dev, PCIR_COMMAND, 2); 878 reg |= PCIM_CMD_MWRICEN; 879 pci_write_config(dev, PCIR_COMMAND, reg, 2); 880 881 /* Reset the adapter. */ 882 nge_reset(sc); 883 884 /* 885 * Get station address from the EEPROM. 886 */ 887 nge_read_eeprom(sc, (caddr_t)ea, NGE_EE_NODEADDR, 3); 888 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 889 ea[i] = le16toh(ea[i]); 890 ea_temp = ea[0]; 891 ea[0] = ea[2]; 892 ea[2] = ea_temp; 893 bcopy(ea, eaddr, sizeof(eaddr)); 894 895 if (nge_dma_alloc(sc) != 0) { 896 error = ENXIO; 897 goto fail; 898 } 899 900 nge_sysctl_node(sc); 901 902 ifp = sc->nge_ifp = if_alloc(IFT_ETHER); 903 if (ifp == NULL) { 904 device_printf(dev, "can not allocate ifnet structure\n"); 905 error = ENOSPC; 906 goto fail; 907 } 908 ifp->if_softc = sc; 909 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 910 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 911 ifp->if_ioctl = nge_ioctl; 912 ifp->if_start = nge_start; 913 ifp->if_init = nge_init; 914 ifp->if_snd.ifq_drv_maxlen = NGE_TX_RING_CNT - 1; 915 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 916 IFQ_SET_READY(&ifp->if_snd); 917 ifp->if_hwassist = NGE_CSUM_FEATURES; 918 ifp->if_capabilities = IFCAP_HWCSUM; 919 /* 920 * It seems that some hardwares doesn't provide 3.3V auxiliary 921 * supply(3VAUX) to drive PME such that checking PCI power 922 * management capability is necessary. 923 */ 924 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &i) == 0) 925 ifp->if_capabilities |= IFCAP_WOL; 926 ifp->if_capenable = ifp->if_capabilities; 927 928 if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) { 929 sc->nge_flags |= NGE_FLAG_TBI; 930 device_printf(dev, "Using TBI\n"); 931 /* Configure GPIO. */ 932 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 933 | NGE_GPIO_GP4_OUT 934 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 935 | NGE_GPIO_GP3_OUTENB 936 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 937 } 938 939 /* 940 * Do MII setup. 941 */ 942 error = mii_attach(dev, &sc->nge_miibus, ifp, nge_mediachange, 943 nge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 944 if (error != 0) { 945 device_printf(dev, "attaching PHYs failed\n"); 946 goto fail; 947 } 948 949 /* 950 * Call MI attach routine. 951 */ 952 ether_ifattach(ifp, eaddr); 953 954 /* VLAN capability setup. */ 955 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 956 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 957 ifp->if_capenable = ifp->if_capabilities; 958 #ifdef DEVICE_POLLING 959 ifp->if_capabilities |= IFCAP_POLLING; 960 #endif 961 /* 962 * Tell the upper layer(s) we support long frames. 963 * Must appear after the call to ether_ifattach() because 964 * ether_ifattach() sets ifi_hdrlen to the default value. 965 */ 966 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 967 968 /* 969 * Hookup IRQ last. 970 */ 971 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE, 972 NULL, nge_intr, sc, &sc->nge_intrhand); 973 if (error) { 974 device_printf(dev, "couldn't set up irq\n"); 975 goto fail; 976 } 977 978 fail: 979 if (error != 0) 980 nge_detach(dev); 981 return (error); 982 } 983 984 static int 985 nge_detach(device_t dev) 986 { 987 struct nge_softc *sc; 988 struct ifnet *ifp; 989 990 sc = device_get_softc(dev); 991 ifp = sc->nge_ifp; 992 993 #ifdef DEVICE_POLLING 994 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 995 ether_poll_deregister(ifp); 996 #endif 997 998 if (device_is_attached(dev)) { 999 NGE_LOCK(sc); 1000 sc->nge_flags |= NGE_FLAG_DETACH; 1001 nge_stop(sc); 1002 NGE_UNLOCK(sc); 1003 callout_drain(&sc->nge_stat_ch); 1004 if (ifp != NULL) 1005 ether_ifdetach(ifp); 1006 } 1007 1008 if (sc->nge_miibus != NULL) { 1009 device_delete_child(dev, sc->nge_miibus); 1010 sc->nge_miibus = NULL; 1011 } 1012 bus_generic_detach(dev); 1013 if (sc->nge_intrhand != NULL) 1014 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1015 if (sc->nge_irq != NULL) 1016 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1017 if (sc->nge_res != NULL) 1018 bus_release_resource(dev, sc->nge_res_type, sc->nge_res_id, 1019 sc->nge_res); 1020 1021 nge_dma_free(sc); 1022 if (ifp != NULL) 1023 if_free(ifp); 1024 1025 NGE_LOCK_DESTROY(sc); 1026 1027 return (0); 1028 } 1029 1030 struct nge_dmamap_arg { 1031 bus_addr_t nge_busaddr; 1032 }; 1033 1034 static void 1035 nge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1036 { 1037 struct nge_dmamap_arg *ctx; 1038 1039 if (error != 0) 1040 return; 1041 ctx = arg; 1042 ctx->nge_busaddr = segs[0].ds_addr; 1043 } 1044 1045 static int 1046 nge_dma_alloc(struct nge_softc *sc) 1047 { 1048 struct nge_dmamap_arg ctx; 1049 struct nge_txdesc *txd; 1050 struct nge_rxdesc *rxd; 1051 int error, i; 1052 1053 /* Create parent DMA tag. */ 1054 error = bus_dma_tag_create( 1055 bus_get_dma_tag(sc->nge_dev), /* parent */ 1056 1, 0, /* alignment, boundary */ 1057 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1058 BUS_SPACE_MAXADDR, /* highaddr */ 1059 NULL, NULL, /* filter, filterarg */ 1060 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1061 0, /* nsegments */ 1062 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1063 0, /* flags */ 1064 NULL, NULL, /* lockfunc, lockarg */ 1065 &sc->nge_cdata.nge_parent_tag); 1066 if (error != 0) { 1067 device_printf(sc->nge_dev, "failed to create parent DMA tag\n"); 1068 goto fail; 1069 } 1070 /* Create tag for Tx ring. */ 1071 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1072 NGE_RING_ALIGN, 0, /* alignment, boundary */ 1073 BUS_SPACE_MAXADDR, /* lowaddr */ 1074 BUS_SPACE_MAXADDR, /* highaddr */ 1075 NULL, NULL, /* filter, filterarg */ 1076 NGE_TX_RING_SIZE, /* maxsize */ 1077 1, /* nsegments */ 1078 NGE_TX_RING_SIZE, /* maxsegsize */ 1079 0, /* flags */ 1080 NULL, NULL, /* lockfunc, lockarg */ 1081 &sc->nge_cdata.nge_tx_ring_tag); 1082 if (error != 0) { 1083 device_printf(sc->nge_dev, "failed to create Tx ring DMA tag\n"); 1084 goto fail; 1085 } 1086 1087 /* Create tag for Rx ring. */ 1088 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1089 NGE_RING_ALIGN, 0, /* alignment, boundary */ 1090 BUS_SPACE_MAXADDR, /* lowaddr */ 1091 BUS_SPACE_MAXADDR, /* highaddr */ 1092 NULL, NULL, /* filter, filterarg */ 1093 NGE_RX_RING_SIZE, /* maxsize */ 1094 1, /* nsegments */ 1095 NGE_RX_RING_SIZE, /* maxsegsize */ 1096 0, /* flags */ 1097 NULL, NULL, /* lockfunc, lockarg */ 1098 &sc->nge_cdata.nge_rx_ring_tag); 1099 if (error != 0) { 1100 device_printf(sc->nge_dev, 1101 "failed to create Rx ring DMA tag\n"); 1102 goto fail; 1103 } 1104 1105 /* Create tag for Tx buffers. */ 1106 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1107 1, 0, /* alignment, boundary */ 1108 BUS_SPACE_MAXADDR, /* lowaddr */ 1109 BUS_SPACE_MAXADDR, /* highaddr */ 1110 NULL, NULL, /* filter, filterarg */ 1111 MCLBYTES * NGE_MAXTXSEGS, /* maxsize */ 1112 NGE_MAXTXSEGS, /* nsegments */ 1113 MCLBYTES, /* maxsegsize */ 1114 0, /* flags */ 1115 NULL, NULL, /* lockfunc, lockarg */ 1116 &sc->nge_cdata.nge_tx_tag); 1117 if (error != 0) { 1118 device_printf(sc->nge_dev, "failed to create Tx DMA tag\n"); 1119 goto fail; 1120 } 1121 1122 /* Create tag for Rx buffers. */ 1123 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1124 NGE_RX_ALIGN, 0, /* alignment, boundary */ 1125 BUS_SPACE_MAXADDR, /* lowaddr */ 1126 BUS_SPACE_MAXADDR, /* highaddr */ 1127 NULL, NULL, /* filter, filterarg */ 1128 MCLBYTES, /* maxsize */ 1129 1, /* nsegments */ 1130 MCLBYTES, /* maxsegsize */ 1131 0, /* flags */ 1132 NULL, NULL, /* lockfunc, lockarg */ 1133 &sc->nge_cdata.nge_rx_tag); 1134 if (error != 0) { 1135 device_printf(sc->nge_dev, "failed to create Rx DMA tag\n"); 1136 goto fail; 1137 } 1138 1139 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1140 error = bus_dmamem_alloc(sc->nge_cdata.nge_tx_ring_tag, 1141 (void **)&sc->nge_rdata.nge_tx_ring, BUS_DMA_WAITOK | 1142 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_tx_ring_map); 1143 if (error != 0) { 1144 device_printf(sc->nge_dev, 1145 "failed to allocate DMA'able memory for Tx ring\n"); 1146 goto fail; 1147 } 1148 1149 ctx.nge_busaddr = 0; 1150 error = bus_dmamap_load(sc->nge_cdata.nge_tx_ring_tag, 1151 sc->nge_cdata.nge_tx_ring_map, sc->nge_rdata.nge_tx_ring, 1152 NGE_TX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1153 if (error != 0 || ctx.nge_busaddr == 0) { 1154 device_printf(sc->nge_dev, 1155 "failed to load DMA'able memory for Tx ring\n"); 1156 goto fail; 1157 } 1158 sc->nge_rdata.nge_tx_ring_paddr = ctx.nge_busaddr; 1159 1160 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1161 error = bus_dmamem_alloc(sc->nge_cdata.nge_rx_ring_tag, 1162 (void **)&sc->nge_rdata.nge_rx_ring, BUS_DMA_WAITOK | 1163 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_rx_ring_map); 1164 if (error != 0) { 1165 device_printf(sc->nge_dev, 1166 "failed to allocate DMA'able memory for Rx ring\n"); 1167 goto fail; 1168 } 1169 1170 ctx.nge_busaddr = 0; 1171 error = bus_dmamap_load(sc->nge_cdata.nge_rx_ring_tag, 1172 sc->nge_cdata.nge_rx_ring_map, sc->nge_rdata.nge_rx_ring, 1173 NGE_RX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1174 if (error != 0 || ctx.nge_busaddr == 0) { 1175 device_printf(sc->nge_dev, 1176 "failed to load DMA'able memory for Rx ring\n"); 1177 goto fail; 1178 } 1179 sc->nge_rdata.nge_rx_ring_paddr = ctx.nge_busaddr; 1180 1181 /* Create DMA maps for Tx buffers. */ 1182 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1183 txd = &sc->nge_cdata.nge_txdesc[i]; 1184 txd->tx_m = NULL; 1185 txd->tx_dmamap = NULL; 1186 error = bus_dmamap_create(sc->nge_cdata.nge_tx_tag, 0, 1187 &txd->tx_dmamap); 1188 if (error != 0) { 1189 device_printf(sc->nge_dev, 1190 "failed to create Tx dmamap\n"); 1191 goto fail; 1192 } 1193 } 1194 /* Create DMA maps for Rx buffers. */ 1195 if ((error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1196 &sc->nge_cdata.nge_rx_sparemap)) != 0) { 1197 device_printf(sc->nge_dev, 1198 "failed to create spare Rx dmamap\n"); 1199 goto fail; 1200 } 1201 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1202 rxd = &sc->nge_cdata.nge_rxdesc[i]; 1203 rxd->rx_m = NULL; 1204 rxd->rx_dmamap = NULL; 1205 error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1206 &rxd->rx_dmamap); 1207 if (error != 0) { 1208 device_printf(sc->nge_dev, 1209 "failed to create Rx dmamap\n"); 1210 goto fail; 1211 } 1212 } 1213 1214 fail: 1215 return (error); 1216 } 1217 1218 static void 1219 nge_dma_free(struct nge_softc *sc) 1220 { 1221 struct nge_txdesc *txd; 1222 struct nge_rxdesc *rxd; 1223 int i; 1224 1225 /* Tx ring. */ 1226 if (sc->nge_cdata.nge_tx_ring_tag) { 1227 if (sc->nge_cdata.nge_tx_ring_map) 1228 bus_dmamap_unload(sc->nge_cdata.nge_tx_ring_tag, 1229 sc->nge_cdata.nge_tx_ring_map); 1230 if (sc->nge_cdata.nge_tx_ring_map && 1231 sc->nge_rdata.nge_tx_ring) 1232 bus_dmamem_free(sc->nge_cdata.nge_tx_ring_tag, 1233 sc->nge_rdata.nge_tx_ring, 1234 sc->nge_cdata.nge_tx_ring_map); 1235 sc->nge_rdata.nge_tx_ring = NULL; 1236 sc->nge_cdata.nge_tx_ring_map = NULL; 1237 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_ring_tag); 1238 sc->nge_cdata.nge_tx_ring_tag = NULL; 1239 } 1240 /* Rx ring. */ 1241 if (sc->nge_cdata.nge_rx_ring_tag) { 1242 if (sc->nge_cdata.nge_rx_ring_map) 1243 bus_dmamap_unload(sc->nge_cdata.nge_rx_ring_tag, 1244 sc->nge_cdata.nge_rx_ring_map); 1245 if (sc->nge_cdata.nge_rx_ring_map && 1246 sc->nge_rdata.nge_rx_ring) 1247 bus_dmamem_free(sc->nge_cdata.nge_rx_ring_tag, 1248 sc->nge_rdata.nge_rx_ring, 1249 sc->nge_cdata.nge_rx_ring_map); 1250 sc->nge_rdata.nge_rx_ring = NULL; 1251 sc->nge_cdata.nge_rx_ring_map = NULL; 1252 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_ring_tag); 1253 sc->nge_cdata.nge_rx_ring_tag = NULL; 1254 } 1255 /* Tx buffers. */ 1256 if (sc->nge_cdata.nge_tx_tag) { 1257 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1258 txd = &sc->nge_cdata.nge_txdesc[i]; 1259 if (txd->tx_dmamap) { 1260 bus_dmamap_destroy(sc->nge_cdata.nge_tx_tag, 1261 txd->tx_dmamap); 1262 txd->tx_dmamap = NULL; 1263 } 1264 } 1265 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_tag); 1266 sc->nge_cdata.nge_tx_tag = NULL; 1267 } 1268 /* Rx buffers. */ 1269 if (sc->nge_cdata.nge_rx_tag) { 1270 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1271 rxd = &sc->nge_cdata.nge_rxdesc[i]; 1272 if (rxd->rx_dmamap) { 1273 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1274 rxd->rx_dmamap); 1275 rxd->rx_dmamap = NULL; 1276 } 1277 } 1278 if (sc->nge_cdata.nge_rx_sparemap) { 1279 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1280 sc->nge_cdata.nge_rx_sparemap); 1281 sc->nge_cdata.nge_rx_sparemap = 0; 1282 } 1283 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_tag); 1284 sc->nge_cdata.nge_rx_tag = NULL; 1285 } 1286 1287 if (sc->nge_cdata.nge_parent_tag) { 1288 bus_dma_tag_destroy(sc->nge_cdata.nge_parent_tag); 1289 sc->nge_cdata.nge_parent_tag = NULL; 1290 } 1291 } 1292 1293 /* 1294 * Initialize the transmit descriptors. 1295 */ 1296 static int 1297 nge_list_tx_init(struct nge_softc *sc) 1298 { 1299 struct nge_ring_data *rd; 1300 struct nge_txdesc *txd; 1301 bus_addr_t addr; 1302 int i; 1303 1304 sc->nge_cdata.nge_tx_prod = 0; 1305 sc->nge_cdata.nge_tx_cons = 0; 1306 sc->nge_cdata.nge_tx_cnt = 0; 1307 1308 rd = &sc->nge_rdata; 1309 bzero(rd->nge_tx_ring, sizeof(struct nge_desc) * NGE_TX_RING_CNT); 1310 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1311 if (i == NGE_TX_RING_CNT - 1) 1312 addr = NGE_TX_RING_ADDR(sc, 0); 1313 else 1314 addr = NGE_TX_RING_ADDR(sc, i + 1); 1315 rd->nge_tx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 1316 txd = &sc->nge_cdata.nge_txdesc[i]; 1317 txd->tx_m = NULL; 1318 } 1319 1320 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1321 sc->nge_cdata.nge_tx_ring_map, 1322 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1323 1324 return (0); 1325 } 1326 1327 /* 1328 * Initialize the RX descriptors and allocate mbufs for them. Note that 1329 * we arrange the descriptors in a closed ring, so that the last descriptor 1330 * points back to the first. 1331 */ 1332 static int 1333 nge_list_rx_init(struct nge_softc *sc) 1334 { 1335 struct nge_ring_data *rd; 1336 bus_addr_t addr; 1337 int i; 1338 1339 sc->nge_cdata.nge_rx_cons = 0; 1340 sc->nge_head = sc->nge_tail = NULL; 1341 1342 rd = &sc->nge_rdata; 1343 bzero(rd->nge_rx_ring, sizeof(struct nge_desc) * NGE_RX_RING_CNT); 1344 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1345 if (nge_newbuf(sc, i) != 0) 1346 return (ENOBUFS); 1347 if (i == NGE_RX_RING_CNT - 1) 1348 addr = NGE_RX_RING_ADDR(sc, 0); 1349 else 1350 addr = NGE_RX_RING_ADDR(sc, i + 1); 1351 rd->nge_rx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 1352 } 1353 1354 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1355 sc->nge_cdata.nge_rx_ring_map, 1356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1357 1358 return (0); 1359 } 1360 1361 static __inline void 1362 nge_discard_rxbuf(struct nge_softc *sc, int idx) 1363 { 1364 struct nge_desc *desc; 1365 1366 desc = &sc->nge_rdata.nge_rx_ring[idx]; 1367 desc->nge_cmdsts = htole32(MCLBYTES - sizeof(uint64_t)); 1368 desc->nge_extsts = 0; 1369 } 1370 1371 /* 1372 * Initialize an RX descriptor and attach an MBUF cluster. 1373 */ 1374 static int 1375 nge_newbuf(struct nge_softc *sc, int idx) 1376 { 1377 struct nge_desc *desc; 1378 struct nge_rxdesc *rxd; 1379 struct mbuf *m; 1380 bus_dma_segment_t segs[1]; 1381 bus_dmamap_t map; 1382 int nsegs; 1383 1384 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1385 if (m == NULL) 1386 return (ENOBUFS); 1387 m->m_len = m->m_pkthdr.len = MCLBYTES; 1388 m_adj(m, sizeof(uint64_t)); 1389 1390 if (bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_rx_tag, 1391 sc->nge_cdata.nge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1392 m_freem(m); 1393 return (ENOBUFS); 1394 } 1395 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1396 1397 rxd = &sc->nge_cdata.nge_rxdesc[idx]; 1398 if (rxd->rx_m != NULL) { 1399 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1400 BUS_DMASYNC_POSTREAD); 1401 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap); 1402 } 1403 map = rxd->rx_dmamap; 1404 rxd->rx_dmamap = sc->nge_cdata.nge_rx_sparemap; 1405 sc->nge_cdata.nge_rx_sparemap = map; 1406 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1407 BUS_DMASYNC_PREREAD); 1408 rxd->rx_m = m; 1409 desc = &sc->nge_rdata.nge_rx_ring[idx]; 1410 desc->nge_ptr = htole32(NGE_ADDR_LO(segs[0].ds_addr)); 1411 desc->nge_cmdsts = htole32(segs[0].ds_len); 1412 desc->nge_extsts = 0; 1413 1414 return (0); 1415 } 1416 1417 #ifndef __NO_STRICT_ALIGNMENT 1418 static __inline void 1419 nge_fixup_rx(struct mbuf *m) 1420 { 1421 int i; 1422 uint16_t *src, *dst; 1423 1424 src = mtod(m, uint16_t *); 1425 dst = src - 1; 1426 1427 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1428 *dst++ = *src++; 1429 1430 m->m_data -= ETHER_ALIGN; 1431 } 1432 #endif 1433 1434 /* 1435 * A frame has been uploaded: pass the resulting mbuf chain up to 1436 * the higher level protocols. 1437 */ 1438 static int 1439 nge_rxeof(struct nge_softc *sc) 1440 { 1441 struct mbuf *m; 1442 struct ifnet *ifp; 1443 struct nge_desc *cur_rx; 1444 struct nge_rxdesc *rxd; 1445 int cons, prog, rx_npkts, total_len; 1446 uint32_t cmdsts, extsts; 1447 1448 NGE_LOCK_ASSERT(sc); 1449 1450 ifp = sc->nge_ifp; 1451 cons = sc->nge_cdata.nge_rx_cons; 1452 rx_npkts = 0; 1453 1454 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1455 sc->nge_cdata.nge_rx_ring_map, 1456 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1457 1458 for (prog = 0; prog < NGE_RX_RING_CNT && 1459 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1460 NGE_INC(cons, NGE_RX_RING_CNT)) { 1461 #ifdef DEVICE_POLLING 1462 if (ifp->if_capenable & IFCAP_POLLING) { 1463 if (sc->rxcycles <= 0) 1464 break; 1465 sc->rxcycles--; 1466 } 1467 #endif 1468 cur_rx = &sc->nge_rdata.nge_rx_ring[cons]; 1469 cmdsts = le32toh(cur_rx->nge_cmdsts); 1470 extsts = le32toh(cur_rx->nge_extsts); 1471 if ((cmdsts & NGE_CMDSTS_OWN) == 0) 1472 break; 1473 prog++; 1474 rxd = &sc->nge_cdata.nge_rxdesc[cons]; 1475 m = rxd->rx_m; 1476 total_len = cmdsts & NGE_CMDSTS_BUFLEN; 1477 1478 if ((cmdsts & NGE_CMDSTS_MORE) != 0) { 1479 if (nge_newbuf(sc, cons) != 0) { 1480 ifp->if_iqdrops++; 1481 if (sc->nge_head != NULL) { 1482 m_freem(sc->nge_head); 1483 sc->nge_head = sc->nge_tail = NULL; 1484 } 1485 nge_discard_rxbuf(sc, cons); 1486 continue; 1487 } 1488 m->m_len = total_len; 1489 if (sc->nge_head == NULL) { 1490 m->m_pkthdr.len = total_len; 1491 sc->nge_head = sc->nge_tail = m; 1492 } else { 1493 m->m_flags &= ~M_PKTHDR; 1494 sc->nge_head->m_pkthdr.len += total_len; 1495 sc->nge_tail->m_next = m; 1496 sc->nge_tail = m; 1497 } 1498 continue; 1499 } 1500 1501 /* 1502 * If an error occurs, update stats, clear the 1503 * status word and leave the mbuf cluster in place: 1504 * it should simply get re-used next time this descriptor 1505 * comes up in the ring. 1506 */ 1507 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1508 if ((cmdsts & NGE_RXSTAT_RUNT) && 1509 total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 4)) { 1510 /* 1511 * Work-around hardware bug, accept runt frames 1512 * if its length is larger than or equal to 56. 1513 */ 1514 } else { 1515 /* 1516 * Input error counters are updated by hardware. 1517 */ 1518 if (sc->nge_head != NULL) { 1519 m_freem(sc->nge_head); 1520 sc->nge_head = sc->nge_tail = NULL; 1521 } 1522 nge_discard_rxbuf(sc, cons); 1523 continue; 1524 } 1525 } 1526 1527 /* Try conjure up a replacement mbuf. */ 1528 1529 if (nge_newbuf(sc, cons) != 0) { 1530 ifp->if_iqdrops++; 1531 if (sc->nge_head != NULL) { 1532 m_freem(sc->nge_head); 1533 sc->nge_head = sc->nge_tail = NULL; 1534 } 1535 nge_discard_rxbuf(sc, cons); 1536 continue; 1537 } 1538 1539 /* Chain received mbufs. */ 1540 if (sc->nge_head != NULL) { 1541 m->m_len = total_len; 1542 m->m_flags &= ~M_PKTHDR; 1543 sc->nge_tail->m_next = m; 1544 m = sc->nge_head; 1545 m->m_pkthdr.len += total_len; 1546 sc->nge_head = sc->nge_tail = NULL; 1547 } else 1548 m->m_pkthdr.len = m->m_len = total_len; 1549 1550 /* 1551 * Ok. NatSemi really screwed up here. This is the 1552 * only gigE chip I know of with alignment constraints 1553 * on receive buffers. RX buffers must be 64-bit aligned. 1554 */ 1555 /* 1556 * By popular demand, ignore the alignment problems 1557 * on the non-strict alignment platform. The performance hit 1558 * incurred due to unaligned accesses is much smaller 1559 * than the hit produced by forcing buffer copies all 1560 * the time, especially with jumbo frames. We still 1561 * need to fix up the alignment everywhere else though. 1562 */ 1563 #ifndef __NO_STRICT_ALIGNMENT 1564 nge_fixup_rx(m); 1565 #endif 1566 m->m_pkthdr.rcvif = ifp; 1567 ifp->if_ipackets++; 1568 1569 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1570 /* Do IP checksum checking. */ 1571 if ((extsts & NGE_RXEXTSTS_IPPKT) != 0) 1572 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1573 if ((extsts & NGE_RXEXTSTS_IPCSUMERR) == 0) 1574 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1575 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1576 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1577 (extsts & NGE_RXEXTSTS_UDPPKT && 1578 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1579 m->m_pkthdr.csum_flags |= 1580 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1581 m->m_pkthdr.csum_data = 0xffff; 1582 } 1583 } 1584 1585 /* 1586 * If we received a packet with a vlan tag, pass it 1587 * to vlan_input() instead of ether_input(). 1588 */ 1589 if ((extsts & NGE_RXEXTSTS_VLANPKT) != 0 && 1590 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 1591 m->m_pkthdr.ether_vtag = 1592 bswap16(extsts & NGE_RXEXTSTS_VTCI); 1593 m->m_flags |= M_VLANTAG; 1594 } 1595 NGE_UNLOCK(sc); 1596 (*ifp->if_input)(ifp, m); 1597 NGE_LOCK(sc); 1598 rx_npkts++; 1599 } 1600 1601 if (prog > 0) { 1602 sc->nge_cdata.nge_rx_cons = cons; 1603 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1604 sc->nge_cdata.nge_rx_ring_map, 1605 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1606 } 1607 return (rx_npkts); 1608 } 1609 1610 /* 1611 * A frame was downloaded to the chip. It's safe for us to clean up 1612 * the list buffers. 1613 */ 1614 static void 1615 nge_txeof(struct nge_softc *sc) 1616 { 1617 struct nge_desc *cur_tx; 1618 struct nge_txdesc *txd; 1619 struct ifnet *ifp; 1620 uint32_t cmdsts; 1621 int cons, prod; 1622 1623 NGE_LOCK_ASSERT(sc); 1624 ifp = sc->nge_ifp; 1625 1626 cons = sc->nge_cdata.nge_tx_cons; 1627 prod = sc->nge_cdata.nge_tx_prod; 1628 if (cons == prod) 1629 return; 1630 1631 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1632 sc->nge_cdata.nge_tx_ring_map, 1633 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1634 1635 /* 1636 * Go through our tx list and free mbufs for those 1637 * frames that have been transmitted. 1638 */ 1639 for (; cons != prod; NGE_INC(cons, NGE_TX_RING_CNT)) { 1640 cur_tx = &sc->nge_rdata.nge_tx_ring[cons]; 1641 cmdsts = le32toh(cur_tx->nge_cmdsts); 1642 if ((cmdsts & NGE_CMDSTS_OWN) != 0) 1643 break; 1644 sc->nge_cdata.nge_tx_cnt--; 1645 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1646 if ((cmdsts & NGE_CMDSTS_MORE) != 0) 1647 continue; 1648 1649 txd = &sc->nge_cdata.nge_txdesc[cons]; 1650 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap, 1651 BUS_DMASYNC_POSTWRITE); 1652 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap); 1653 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1654 ifp->if_oerrors++; 1655 if ((cmdsts & NGE_TXSTAT_EXCESSCOLLS) != 0) 1656 ifp->if_collisions++; 1657 if ((cmdsts & NGE_TXSTAT_OUTOFWINCOLL) != 0) 1658 ifp->if_collisions++; 1659 } else 1660 ifp->if_opackets++; 1661 1662 ifp->if_collisions += (cmdsts & NGE_TXSTAT_COLLCNT) >> 16; 1663 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1664 __func__)); 1665 m_freem(txd->tx_m); 1666 txd->tx_m = NULL; 1667 } 1668 1669 sc->nge_cdata.nge_tx_cons = cons; 1670 if (sc->nge_cdata.nge_tx_cnt == 0) 1671 sc->nge_watchdog_timer = 0; 1672 } 1673 1674 static void 1675 nge_tick(void *xsc) 1676 { 1677 struct nge_softc *sc; 1678 struct mii_data *mii; 1679 1680 sc = xsc; 1681 NGE_LOCK_ASSERT(sc); 1682 mii = device_get_softc(sc->nge_miibus); 1683 mii_tick(mii); 1684 /* 1685 * For PHYs that does not reset established link, it is 1686 * necessary to check whether driver still have a valid 1687 * link(e.g link state change callback is not called). 1688 * Otherwise, driver think it lost link because driver 1689 * initialization routine clears link state flag. 1690 */ 1691 if ((sc->nge_flags & NGE_FLAG_LINK) == 0) 1692 nge_miibus_statchg(sc->nge_dev); 1693 nge_stats_update(sc); 1694 nge_watchdog(sc); 1695 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 1696 } 1697 1698 static void 1699 nge_stats_update(struct nge_softc *sc) 1700 { 1701 struct ifnet *ifp; 1702 struct nge_stats now, *stats, *nstats; 1703 1704 NGE_LOCK_ASSERT(sc); 1705 1706 ifp = sc->nge_ifp; 1707 stats = &now; 1708 stats->rx_pkts_errs = 1709 CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF; 1710 stats->rx_crc_errs = 1711 CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF; 1712 stats->rx_fifo_oflows = 1713 CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF; 1714 stats->rx_align_errs = 1715 CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF; 1716 stats->rx_sym_errs = 1717 CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF; 1718 stats->rx_pkts_jumbos = 1719 CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF; 1720 stats->rx_len_errs = 1721 CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF; 1722 stats->rx_unctl_frames = 1723 CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF; 1724 stats->rx_pause = 1725 CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF; 1726 stats->tx_pause = 1727 CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF; 1728 stats->tx_seq_errs = 1729 CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF; 1730 1731 /* 1732 * Since we've accept errored frames exclude Rx length errors. 1733 */ 1734 ifp->if_ierrors += stats->rx_pkts_errs + stats->rx_crc_errs + 1735 stats->rx_fifo_oflows + stats->rx_sym_errs; 1736 1737 nstats = &sc->nge_stats; 1738 nstats->rx_pkts_errs += stats->rx_pkts_errs; 1739 nstats->rx_crc_errs += stats->rx_crc_errs; 1740 nstats->rx_fifo_oflows += stats->rx_fifo_oflows; 1741 nstats->rx_align_errs += stats->rx_align_errs; 1742 nstats->rx_sym_errs += stats->rx_sym_errs; 1743 nstats->rx_pkts_jumbos += stats->rx_pkts_jumbos; 1744 nstats->rx_len_errs += stats->rx_len_errs; 1745 nstats->rx_unctl_frames += stats->rx_unctl_frames; 1746 nstats->rx_pause += stats->rx_pause; 1747 nstats->tx_pause += stats->tx_pause; 1748 nstats->tx_seq_errs += stats->tx_seq_errs; 1749 } 1750 1751 #ifdef DEVICE_POLLING 1752 static poll_handler_t nge_poll; 1753 1754 static int 1755 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1756 { 1757 struct nge_softc *sc; 1758 int rx_npkts = 0; 1759 1760 sc = ifp->if_softc; 1761 1762 NGE_LOCK(sc); 1763 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1764 NGE_UNLOCK(sc); 1765 return (rx_npkts); 1766 } 1767 1768 /* 1769 * On the nge, reading the status register also clears it. 1770 * So before returning to intr mode we must make sure that all 1771 * possible pending sources of interrupts have been served. 1772 * In practice this means run to completion the *eof routines, 1773 * and then call the interrupt routine. 1774 */ 1775 sc->rxcycles = count; 1776 rx_npkts = nge_rxeof(sc); 1777 nge_txeof(sc); 1778 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1779 nge_start_locked(ifp); 1780 1781 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1782 uint32_t status; 1783 1784 /* Reading the ISR register clears all interrupts. */ 1785 status = CSR_READ_4(sc, NGE_ISR); 1786 1787 if ((status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) != 0) 1788 rx_npkts += nge_rxeof(sc); 1789 1790 if ((status & NGE_ISR_RX_IDLE) != 0) 1791 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1792 1793 if ((status & NGE_ISR_SYSERR) != 0) { 1794 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1795 nge_init_locked(sc); 1796 } 1797 } 1798 NGE_UNLOCK(sc); 1799 return (rx_npkts); 1800 } 1801 #endif /* DEVICE_POLLING */ 1802 1803 static void 1804 nge_intr(void *arg) 1805 { 1806 struct nge_softc *sc; 1807 struct ifnet *ifp; 1808 uint32_t status; 1809 1810 sc = (struct nge_softc *)arg; 1811 ifp = sc->nge_ifp; 1812 1813 NGE_LOCK(sc); 1814 1815 if ((sc->nge_flags & NGE_FLAG_SUSPENDED) != 0) 1816 goto done_locked; 1817 1818 /* Reading the ISR register clears all interrupts. */ 1819 status = CSR_READ_4(sc, NGE_ISR); 1820 if (status == 0xffffffff || (status & NGE_INTRS) == 0) 1821 goto done_locked; 1822 #ifdef DEVICE_POLLING 1823 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1824 goto done_locked; 1825 #endif 1826 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1827 goto done_locked; 1828 1829 /* Disable interrupts. */ 1830 CSR_WRITE_4(sc, NGE_IER, 0); 1831 1832 /* Data LED on for TBI mode */ 1833 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1834 CSR_WRITE_4(sc, NGE_GPIO, 1835 CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT); 1836 1837 for (; (status & NGE_INTRS) != 0;) { 1838 if ((status & (NGE_ISR_TX_DESC_OK | NGE_ISR_TX_ERR | 1839 NGE_ISR_TX_OK | NGE_ISR_TX_IDLE)) != 0) 1840 nge_txeof(sc); 1841 1842 if ((status & (NGE_ISR_RX_DESC_OK | NGE_ISR_RX_ERR | 1843 NGE_ISR_RX_OFLOW | NGE_ISR_RX_FIFO_OFLOW | 1844 NGE_ISR_RX_IDLE | NGE_ISR_RX_OK)) != 0) 1845 nge_rxeof(sc); 1846 1847 if ((status & NGE_ISR_RX_IDLE) != 0) 1848 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1849 1850 if ((status & NGE_ISR_SYSERR) != 0) { 1851 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1852 nge_init_locked(sc); 1853 } 1854 /* Reading the ISR register clears all interrupts. */ 1855 status = CSR_READ_4(sc, NGE_ISR); 1856 } 1857 1858 /* Re-enable interrupts. */ 1859 CSR_WRITE_4(sc, NGE_IER, 1); 1860 1861 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1862 nge_start_locked(ifp); 1863 1864 /* Data LED off for TBI mode */ 1865 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1866 CSR_WRITE_4(sc, NGE_GPIO, 1867 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 1868 1869 done_locked: 1870 NGE_UNLOCK(sc); 1871 } 1872 1873 /* 1874 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1875 * pointers to the fragment pointers. 1876 */ 1877 static int 1878 nge_encap(struct nge_softc *sc, struct mbuf **m_head) 1879 { 1880 struct nge_txdesc *txd, *txd_last; 1881 struct nge_desc *desc; 1882 struct mbuf *m; 1883 bus_dmamap_t map; 1884 bus_dma_segment_t txsegs[NGE_MAXTXSEGS]; 1885 int error, i, nsegs, prod, si; 1886 1887 NGE_LOCK_ASSERT(sc); 1888 1889 m = *m_head; 1890 prod = sc->nge_cdata.nge_tx_prod; 1891 txd = &sc->nge_cdata.nge_txdesc[prod]; 1892 txd_last = txd; 1893 map = txd->tx_dmamap; 1894 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, map, 1895 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1896 if (error == EFBIG) { 1897 m = m_collapse(*m_head, M_NOWAIT, NGE_MAXTXSEGS); 1898 if (m == NULL) { 1899 m_freem(*m_head); 1900 *m_head = NULL; 1901 return (ENOBUFS); 1902 } 1903 *m_head = m; 1904 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, 1905 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1906 if (error != 0) { 1907 m_freem(*m_head); 1908 *m_head = NULL; 1909 return (error); 1910 } 1911 } else if (error != 0) 1912 return (error); 1913 if (nsegs == 0) { 1914 m_freem(*m_head); 1915 *m_head = NULL; 1916 return (EIO); 1917 } 1918 1919 /* Check number of available descriptors. */ 1920 if (sc->nge_cdata.nge_tx_cnt + nsegs >= (NGE_TX_RING_CNT - 1)) { 1921 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, map); 1922 return (ENOBUFS); 1923 } 1924 1925 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, map, BUS_DMASYNC_PREWRITE); 1926 1927 si = prod; 1928 for (i = 0; i < nsegs; i++) { 1929 desc = &sc->nge_rdata.nge_tx_ring[prod]; 1930 desc->nge_ptr = htole32(NGE_ADDR_LO(txsegs[i].ds_addr)); 1931 if (i == 0) 1932 desc->nge_cmdsts = htole32(txsegs[i].ds_len | 1933 NGE_CMDSTS_MORE); 1934 else 1935 desc->nge_cmdsts = htole32(txsegs[i].ds_len | 1936 NGE_CMDSTS_MORE | NGE_CMDSTS_OWN); 1937 desc->nge_extsts = 0; 1938 sc->nge_cdata.nge_tx_cnt++; 1939 NGE_INC(prod, NGE_TX_RING_CNT); 1940 } 1941 /* Update producer index. */ 1942 sc->nge_cdata.nge_tx_prod = prod; 1943 1944 prod = (prod + NGE_TX_RING_CNT - 1) % NGE_TX_RING_CNT; 1945 desc = &sc->nge_rdata.nge_tx_ring[prod]; 1946 /* Check if we have a VLAN tag to insert. */ 1947 if ((m->m_flags & M_VLANTAG) != 0) 1948 desc->nge_extsts |= htole32(NGE_TXEXTSTS_VLANPKT | 1949 bswap16(m->m_pkthdr.ether_vtag)); 1950 /* Set EOP on the last desciptor. */ 1951 desc->nge_cmdsts &= htole32(~NGE_CMDSTS_MORE); 1952 1953 /* Set checksum offload in the first descriptor. */ 1954 desc = &sc->nge_rdata.nge_tx_ring[si]; 1955 if ((m->m_pkthdr.csum_flags & NGE_CSUM_FEATURES) != 0) { 1956 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1957 desc->nge_extsts |= htole32(NGE_TXEXTSTS_IPCSUM); 1958 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1959 desc->nge_extsts |= htole32(NGE_TXEXTSTS_TCPCSUM); 1960 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1961 desc->nge_extsts |= htole32(NGE_TXEXTSTS_UDPCSUM); 1962 } 1963 /* Lastly, turn the first descriptor ownership to hardware. */ 1964 desc->nge_cmdsts |= htole32(NGE_CMDSTS_OWN); 1965 1966 txd = &sc->nge_cdata.nge_txdesc[prod]; 1967 map = txd_last->tx_dmamap; 1968 txd_last->tx_dmamap = txd->tx_dmamap; 1969 txd->tx_dmamap = map; 1970 txd->tx_m = m; 1971 1972 return (0); 1973 } 1974 1975 /* 1976 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1977 * to the mbuf data regions directly in the transmit lists. We also save a 1978 * copy of the pointers since the transmit list fragment pointers are 1979 * physical addresses. 1980 */ 1981 1982 static void 1983 nge_start(struct ifnet *ifp) 1984 { 1985 struct nge_softc *sc; 1986 1987 sc = ifp->if_softc; 1988 NGE_LOCK(sc); 1989 nge_start_locked(ifp); 1990 NGE_UNLOCK(sc); 1991 } 1992 1993 static void 1994 nge_start_locked(struct ifnet *ifp) 1995 { 1996 struct nge_softc *sc; 1997 struct mbuf *m_head; 1998 int enq; 1999 2000 sc = ifp->if_softc; 2001 2002 NGE_LOCK_ASSERT(sc); 2003 2004 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2005 IFF_DRV_RUNNING || (sc->nge_flags & NGE_FLAG_LINK) == 0) 2006 return; 2007 2008 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2009 sc->nge_cdata.nge_tx_cnt < NGE_TX_RING_CNT - 2; ) { 2010 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2011 if (m_head == NULL) 2012 break; 2013 /* 2014 * Pack the data into the transmit ring. If we 2015 * don't have room, set the OACTIVE flag and wait 2016 * for the NIC to drain the ring. 2017 */ 2018 if (nge_encap(sc, &m_head)) { 2019 if (m_head == NULL) 2020 break; 2021 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2022 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2023 break; 2024 } 2025 2026 enq++; 2027 /* 2028 * If there's a BPF listener, bounce a copy of this frame 2029 * to him. 2030 */ 2031 ETHER_BPF_MTAP(ifp, m_head); 2032 } 2033 2034 if (enq > 0) { 2035 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 2036 sc->nge_cdata.nge_tx_ring_map, 2037 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2038 /* Transmit */ 2039 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 2040 2041 /* Set a timeout in case the chip goes out to lunch. */ 2042 sc->nge_watchdog_timer = 5; 2043 } 2044 } 2045 2046 static void 2047 nge_init(void *xsc) 2048 { 2049 struct nge_softc *sc = xsc; 2050 2051 NGE_LOCK(sc); 2052 nge_init_locked(sc); 2053 NGE_UNLOCK(sc); 2054 } 2055 2056 static void 2057 nge_init_locked(struct nge_softc *sc) 2058 { 2059 struct ifnet *ifp = sc->nge_ifp; 2060 struct mii_data *mii; 2061 uint8_t *eaddr; 2062 uint32_t reg; 2063 2064 NGE_LOCK_ASSERT(sc); 2065 2066 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2067 return; 2068 2069 /* 2070 * Cancel pending I/O and free all RX/TX buffers. 2071 */ 2072 nge_stop(sc); 2073 2074 /* Reset the adapter. */ 2075 nge_reset(sc); 2076 2077 /* Disable Rx filter prior to programming Rx filter. */ 2078 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 0); 2079 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 2080 2081 mii = device_get_softc(sc->nge_miibus); 2082 2083 /* Set MAC address. */ 2084 eaddr = IF_LLADDR(sc->nge_ifp); 2085 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 2086 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[1] << 8) | eaddr[0]); 2087 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 2088 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[3] << 8) | eaddr[2]); 2089 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 2090 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[5] << 8) | eaddr[4]); 2091 2092 /* Init circular RX list. */ 2093 if (nge_list_rx_init(sc) == ENOBUFS) { 2094 device_printf(sc->nge_dev, "initialization failed: no " 2095 "memory for rx buffers\n"); 2096 nge_stop(sc); 2097 return; 2098 } 2099 2100 /* 2101 * Init tx descriptors. 2102 */ 2103 nge_list_tx_init(sc); 2104 2105 /* 2106 * For the NatSemi chip, we have to explicitly enable the 2107 * reception of ARP frames, as well as turn on the 'perfect 2108 * match' filter where we store the station address, otherwise 2109 * we won't receive unicasts meant for this host. 2110 */ 2111 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 2112 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 2113 2114 /* 2115 * Set the capture broadcast bit to capture broadcast frames. 2116 */ 2117 if (ifp->if_flags & IFF_BROADCAST) { 2118 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 2119 } else { 2120 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 2121 } 2122 2123 /* Turn the receive filter on. */ 2124 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 2125 2126 /* Set Rx filter. */ 2127 nge_rxfilter(sc); 2128 2129 /* Disable PRIQ ctl. */ 2130 CSR_WRITE_4(sc, NGE_PRIOQCTL, 0); 2131 2132 /* 2133 * Set pause frames paramters. 2134 * Rx stat FIFO hi-threshold : 2 or more packets 2135 * Rx stat FIFO lo-threshold : less than 2 packets 2136 * Rx data FIFO hi-threshold : 2K or more bytes 2137 * Rx data FIFO lo-threshold : less than 2K bytes 2138 * pause time : (512ns * 0xffff) -> 33.55ms 2139 */ 2140 CSR_WRITE_4(sc, NGE_PAUSECSR, 2141 NGE_PAUSECSR_PAUSE_ON_MCAST | 2142 NGE_PAUSECSR_PAUSE_ON_DA | 2143 ((1 << 24) & NGE_PAUSECSR_RX_STATFIFO_THR_HI) | 2144 ((1 << 22) & NGE_PAUSECSR_RX_STATFIFO_THR_LO) | 2145 ((1 << 20) & NGE_PAUSECSR_RX_DATAFIFO_THR_HI) | 2146 ((1 << 18) & NGE_PAUSECSR_RX_DATAFIFO_THR_LO) | 2147 NGE_PAUSECSR_CNT); 2148 2149 /* 2150 * Load the address of the RX and TX lists. 2151 */ 2152 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 2153 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 2154 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 2155 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 2156 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 2157 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 2158 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 2159 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 2160 2161 /* Set RX configuration. */ 2162 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 2163 2164 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, 0); 2165 /* 2166 * Enable hardware checksum validation for all IPv4 2167 * packets, do not reject packets with bad checksums. 2168 */ 2169 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2170 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 2171 2172 /* 2173 * Tell the chip to detect and strip VLAN tag info from 2174 * received frames. The tag will be provided in the extsts 2175 * field in the RX descriptors. 2176 */ 2177 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_DETECT_ENB); 2178 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2179 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_STRIP_ENB); 2180 2181 /* Set TX configuration. */ 2182 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 2183 2184 /* 2185 * Enable TX IPv4 checksumming on a per-packet basis. 2186 */ 2187 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 2188 2189 /* 2190 * Tell the chip to insert VLAN tags on a per-packet basis as 2191 * dictated by the code in the frame encapsulation routine. 2192 */ 2193 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 2194 2195 /* 2196 * Enable the delivery of PHY interrupts based on 2197 * link/speed/duplex status changes. Also enable the 2198 * extsts field in the DMA descriptors (needed for 2199 * TCP/IP checksum offload on transmit). 2200 */ 2201 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 2202 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 2203 2204 /* 2205 * Configure interrupt holdoff (moderation). We can 2206 * have the chip delay interrupt delivery for a certain 2207 * period. Units are in 100us, and the max setting 2208 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 2209 */ 2210 CSR_WRITE_4(sc, NGE_IHR, sc->nge_int_holdoff); 2211 2212 /* 2213 * Enable MAC statistics counters and clear. 2214 */ 2215 reg = CSR_READ_4(sc, NGE_MIBCTL); 2216 reg &= ~NGE_MIBCTL_FREEZE_CNT; 2217 reg |= NGE_MIBCTL_CLEAR_CNT; 2218 CSR_WRITE_4(sc, NGE_MIBCTL, reg); 2219 2220 /* 2221 * Enable interrupts. 2222 */ 2223 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2224 #ifdef DEVICE_POLLING 2225 /* 2226 * ... only enable interrupts if we are not polling, make sure 2227 * they are off otherwise. 2228 */ 2229 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 2230 CSR_WRITE_4(sc, NGE_IER, 0); 2231 else 2232 #endif 2233 CSR_WRITE_4(sc, NGE_IER, 1); 2234 2235 sc->nge_flags &= ~NGE_FLAG_LINK; 2236 mii_mediachg(mii); 2237 2238 sc->nge_watchdog_timer = 0; 2239 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 2240 2241 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2242 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2243 } 2244 2245 /* 2246 * Set media options. 2247 */ 2248 static int 2249 nge_mediachange(struct ifnet *ifp) 2250 { 2251 struct nge_softc *sc; 2252 struct mii_data *mii; 2253 struct mii_softc *miisc; 2254 int error; 2255 2256 sc = ifp->if_softc; 2257 NGE_LOCK(sc); 2258 mii = device_get_softc(sc->nge_miibus); 2259 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2260 PHY_RESET(miisc); 2261 error = mii_mediachg(mii); 2262 NGE_UNLOCK(sc); 2263 2264 return (error); 2265 } 2266 2267 /* 2268 * Report current media status. 2269 */ 2270 static void 2271 nge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2272 { 2273 struct nge_softc *sc; 2274 struct mii_data *mii; 2275 2276 sc = ifp->if_softc; 2277 NGE_LOCK(sc); 2278 mii = device_get_softc(sc->nge_miibus); 2279 mii_pollstat(mii); 2280 ifmr->ifm_active = mii->mii_media_active; 2281 ifmr->ifm_status = mii->mii_media_status; 2282 NGE_UNLOCK(sc); 2283 } 2284 2285 static int 2286 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2287 { 2288 struct nge_softc *sc = ifp->if_softc; 2289 struct ifreq *ifr = (struct ifreq *) data; 2290 struct mii_data *mii; 2291 int error = 0, mask; 2292 2293 switch (command) { 2294 case SIOCSIFMTU: 2295 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NGE_JUMBO_MTU) 2296 error = EINVAL; 2297 else { 2298 NGE_LOCK(sc); 2299 ifp->if_mtu = ifr->ifr_mtu; 2300 /* 2301 * Workaround: if the MTU is larger than 2302 * 8152 (TX FIFO size minus 64 minus 18), turn off 2303 * TX checksum offloading. 2304 */ 2305 if (ifr->ifr_mtu >= 8152) { 2306 ifp->if_capenable &= ~IFCAP_TXCSUM; 2307 ifp->if_hwassist &= ~NGE_CSUM_FEATURES; 2308 } else { 2309 ifp->if_capenable |= IFCAP_TXCSUM; 2310 ifp->if_hwassist |= NGE_CSUM_FEATURES; 2311 } 2312 NGE_UNLOCK(sc); 2313 VLAN_CAPABILITIES(ifp); 2314 } 2315 break; 2316 case SIOCSIFFLAGS: 2317 NGE_LOCK(sc); 2318 if ((ifp->if_flags & IFF_UP) != 0) { 2319 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2320 if ((ifp->if_flags ^ sc->nge_if_flags) & 2321 (IFF_PROMISC | IFF_ALLMULTI)) 2322 nge_rxfilter(sc); 2323 } else { 2324 if ((sc->nge_flags & NGE_FLAG_DETACH) == 0) 2325 nge_init_locked(sc); 2326 } 2327 } else { 2328 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2329 nge_stop(sc); 2330 } 2331 sc->nge_if_flags = ifp->if_flags; 2332 NGE_UNLOCK(sc); 2333 error = 0; 2334 break; 2335 case SIOCADDMULTI: 2336 case SIOCDELMULTI: 2337 NGE_LOCK(sc); 2338 nge_rxfilter(sc); 2339 NGE_UNLOCK(sc); 2340 error = 0; 2341 break; 2342 case SIOCGIFMEDIA: 2343 case SIOCSIFMEDIA: 2344 mii = device_get_softc(sc->nge_miibus); 2345 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2346 break; 2347 case SIOCSIFCAP: 2348 NGE_LOCK(sc); 2349 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2350 #ifdef DEVICE_POLLING 2351 if ((mask & IFCAP_POLLING) != 0 && 2352 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 2353 ifp->if_capenable ^= IFCAP_POLLING; 2354 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 2355 error = ether_poll_register(nge_poll, ifp); 2356 if (error != 0) { 2357 NGE_UNLOCK(sc); 2358 break; 2359 } 2360 /* Disable interrupts. */ 2361 CSR_WRITE_4(sc, NGE_IER, 0); 2362 } else { 2363 error = ether_poll_deregister(ifp); 2364 /* Enable interrupts. */ 2365 CSR_WRITE_4(sc, NGE_IER, 1); 2366 } 2367 } 2368 #endif /* DEVICE_POLLING */ 2369 if ((mask & IFCAP_TXCSUM) != 0 && 2370 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2371 ifp->if_capenable ^= IFCAP_TXCSUM; 2372 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2373 ifp->if_hwassist |= NGE_CSUM_FEATURES; 2374 else 2375 ifp->if_hwassist &= ~NGE_CSUM_FEATURES; 2376 } 2377 if ((mask & IFCAP_RXCSUM) != 0 && 2378 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2379 ifp->if_capenable ^= IFCAP_RXCSUM; 2380 2381 if ((mask & IFCAP_WOL) != 0 && 2382 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2383 if ((mask & IFCAP_WOL_UCAST) != 0) 2384 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2385 if ((mask & IFCAP_WOL_MCAST) != 0) 2386 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2387 if ((mask & IFCAP_WOL_MAGIC) != 0) 2388 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2389 } 2390 2391 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2392 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2393 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2394 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2395 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2396 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2397 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2398 if ((ifp->if_capenable & 2399 IFCAP_VLAN_HWTAGGING) != 0) 2400 NGE_SETBIT(sc, 2401 NGE_VLAN_IP_RXCTL, 2402 NGE_VIPRXCTL_TAG_STRIP_ENB); 2403 else 2404 NGE_CLRBIT(sc, 2405 NGE_VLAN_IP_RXCTL, 2406 NGE_VIPRXCTL_TAG_STRIP_ENB); 2407 } 2408 } 2409 /* 2410 * Both VLAN hardware tagging and checksum offload is 2411 * required to do checksum offload on VLAN interface. 2412 */ 2413 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2414 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2415 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2416 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2417 NGE_UNLOCK(sc); 2418 VLAN_CAPABILITIES(ifp); 2419 break; 2420 default: 2421 error = ether_ioctl(ifp, command, data); 2422 break; 2423 } 2424 2425 return (error); 2426 } 2427 2428 static void 2429 nge_watchdog(struct nge_softc *sc) 2430 { 2431 struct ifnet *ifp; 2432 2433 NGE_LOCK_ASSERT(sc); 2434 2435 if (sc->nge_watchdog_timer == 0 || --sc->nge_watchdog_timer) 2436 return; 2437 2438 ifp = sc->nge_ifp; 2439 ifp->if_oerrors++; 2440 if_printf(ifp, "watchdog timeout\n"); 2441 2442 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2443 nge_init_locked(sc); 2444 2445 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2446 nge_start_locked(ifp); 2447 } 2448 2449 static int 2450 nge_stop_mac(struct nge_softc *sc) 2451 { 2452 uint32_t reg; 2453 int i; 2454 2455 NGE_LOCK_ASSERT(sc); 2456 2457 reg = CSR_READ_4(sc, NGE_CSR); 2458 if ((reg & (NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE)) != 0) { 2459 reg &= ~(NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE); 2460 reg |= NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE; 2461 CSR_WRITE_4(sc, NGE_CSR, reg); 2462 for (i = 0; i < NGE_TIMEOUT; i++) { 2463 DELAY(1); 2464 if ((CSR_READ_4(sc, NGE_CSR) & 2465 (NGE_CSR_RX_ENABLE | NGE_CSR_TX_ENABLE)) == 0) 2466 break; 2467 } 2468 if (i == NGE_TIMEOUT) 2469 return (ETIMEDOUT); 2470 } 2471 2472 return (0); 2473 } 2474 2475 /* 2476 * Stop the adapter and free any mbufs allocated to the 2477 * RX and TX lists. 2478 */ 2479 static void 2480 nge_stop(struct nge_softc *sc) 2481 { 2482 struct nge_txdesc *txd; 2483 struct nge_rxdesc *rxd; 2484 int i; 2485 struct ifnet *ifp; 2486 2487 NGE_LOCK_ASSERT(sc); 2488 ifp = sc->nge_ifp; 2489 2490 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2491 sc->nge_flags &= ~NGE_FLAG_LINK; 2492 callout_stop(&sc->nge_stat_ch); 2493 sc->nge_watchdog_timer = 0; 2494 2495 CSR_WRITE_4(sc, NGE_IER, 0); 2496 CSR_WRITE_4(sc, NGE_IMR, 0); 2497 if (nge_stop_mac(sc) == ETIMEDOUT) 2498 device_printf(sc->nge_dev, 2499 "%s: unable to stop Tx/Rx MAC\n", __func__); 2500 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 0); 2501 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 0); 2502 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2503 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2504 nge_stats_update(sc); 2505 if (sc->nge_head != NULL) { 2506 m_freem(sc->nge_head); 2507 sc->nge_head = sc->nge_tail = NULL; 2508 } 2509 2510 /* 2511 * Free RX and TX mbufs still in the queues. 2512 */ 2513 for (i = 0; i < NGE_RX_RING_CNT; i++) { 2514 rxd = &sc->nge_cdata.nge_rxdesc[i]; 2515 if (rxd->rx_m != NULL) { 2516 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, 2517 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2518 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, 2519 rxd->rx_dmamap); 2520 m_freem(rxd->rx_m); 2521 rxd->rx_m = NULL; 2522 } 2523 } 2524 for (i = 0; i < NGE_TX_RING_CNT; i++) { 2525 txd = &sc->nge_cdata.nge_txdesc[i]; 2526 if (txd->tx_m != NULL) { 2527 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 2528 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2529 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 2530 txd->tx_dmamap); 2531 m_freem(txd->tx_m); 2532 txd->tx_m = NULL; 2533 } 2534 } 2535 } 2536 2537 /* 2538 * Before setting WOL bits, caller should have stopped Receiver. 2539 */ 2540 static void 2541 nge_wol(struct nge_softc *sc) 2542 { 2543 struct ifnet *ifp; 2544 uint32_t reg; 2545 uint16_t pmstat; 2546 int pmc; 2547 2548 NGE_LOCK_ASSERT(sc); 2549 2550 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) != 0) 2551 return; 2552 2553 ifp = sc->nge_ifp; 2554 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2555 /* Disable WOL & disconnect CLKRUN to save power. */ 2556 CSR_WRITE_4(sc, NGE_WOLCSR, 0); 2557 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 2558 } else { 2559 if (nge_stop_mac(sc) == ETIMEDOUT) 2560 device_printf(sc->nge_dev, 2561 "%s: unable to stop Tx/Rx MAC\n", __func__); 2562 /* 2563 * Make sure wake frames will be buffered in the Rx FIFO. 2564 * (i.e. Silent Rx mode.) 2565 */ 2566 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2567 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_HI, BUS_SPACE_BARRIER_WRITE); 2568 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2569 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_LO, BUS_SPACE_BARRIER_WRITE); 2570 /* Enable Rx again. */ 2571 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2572 CSR_BARRIER_4(sc, NGE_CSR, BUS_SPACE_BARRIER_WRITE); 2573 2574 /* Configure WOL events. */ 2575 reg = 0; 2576 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2577 reg |= NGE_WOLCSR_WAKE_ON_UNICAST; 2578 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2579 reg |= NGE_WOLCSR_WAKE_ON_MULTICAST; 2580 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2581 reg |= NGE_WOLCSR_WAKE_ON_MAGICPKT; 2582 CSR_WRITE_4(sc, NGE_WOLCSR, reg); 2583 2584 /* Activate CLKRUN. */ 2585 reg = CSR_READ_4(sc, NGE_CLKRUN); 2586 reg |= NGE_CLKRUN_PMEENB | NGE_CLNRUN_CLKRUN_ENB; 2587 CSR_WRITE_4(sc, NGE_CLKRUN, reg); 2588 } 2589 2590 /* Request PME. */ 2591 pmstat = pci_read_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, 2); 2592 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2593 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2594 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2595 pci_write_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2596 } 2597 2598 /* 2599 * Stop all chip I/O so that the kernel's probe routines don't 2600 * get confused by errant DMAs when rebooting. 2601 */ 2602 static int 2603 nge_shutdown(device_t dev) 2604 { 2605 2606 return (nge_suspend(dev)); 2607 } 2608 2609 static int 2610 nge_suspend(device_t dev) 2611 { 2612 struct nge_softc *sc; 2613 2614 sc = device_get_softc(dev); 2615 2616 NGE_LOCK(sc); 2617 nge_stop(sc); 2618 nge_wol(sc); 2619 sc->nge_flags |= NGE_FLAG_SUSPENDED; 2620 NGE_UNLOCK(sc); 2621 2622 return (0); 2623 } 2624 2625 static int 2626 nge_resume(device_t dev) 2627 { 2628 struct nge_softc *sc; 2629 struct ifnet *ifp; 2630 uint16_t pmstat; 2631 int pmc; 2632 2633 sc = device_get_softc(dev); 2634 2635 NGE_LOCK(sc); 2636 ifp = sc->nge_ifp; 2637 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) == 0) { 2638 /* Disable PME and clear PME status. */ 2639 pmstat = pci_read_config(sc->nge_dev, 2640 pmc + PCIR_POWER_STATUS, 2); 2641 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2642 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2643 pci_write_config(sc->nge_dev, 2644 pmc + PCIR_POWER_STATUS, pmstat, 2); 2645 } 2646 } 2647 if (ifp->if_flags & IFF_UP) { 2648 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2649 nge_init_locked(sc); 2650 } 2651 2652 sc->nge_flags &= ~NGE_FLAG_SUSPENDED; 2653 NGE_UNLOCK(sc); 2654 2655 return (0); 2656 } 2657 2658 #define NGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2659 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2660 2661 static void 2662 nge_sysctl_node(struct nge_softc *sc) 2663 { 2664 struct sysctl_ctx_list *ctx; 2665 struct sysctl_oid_list *child, *parent; 2666 struct sysctl_oid *tree; 2667 struct nge_stats *stats; 2668 int error; 2669 2670 ctx = device_get_sysctl_ctx(sc->nge_dev); 2671 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nge_dev)); 2672 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_holdoff", 2673 CTLTYPE_INT | CTLFLAG_RW, &sc->nge_int_holdoff, 0, 2674 sysctl_hw_nge_int_holdoff, "I", "NGE interrupt moderation"); 2675 /* Pull in device tunables. */ 2676 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2677 error = resource_int_value(device_get_name(sc->nge_dev), 2678 device_get_unit(sc->nge_dev), "int_holdoff", &sc->nge_int_holdoff); 2679 if (error == 0) { 2680 if (sc->nge_int_holdoff < NGE_INT_HOLDOFF_MIN || 2681 sc->nge_int_holdoff > NGE_INT_HOLDOFF_MAX ) { 2682 device_printf(sc->nge_dev, 2683 "int_holdoff value out of range; " 2684 "using default: %d(%d us)\n", 2685 NGE_INT_HOLDOFF_DEFAULT, 2686 NGE_INT_HOLDOFF_DEFAULT * 100); 2687 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2688 } 2689 } 2690 2691 stats = &sc->nge_stats; 2692 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2693 NULL, "NGE statistics"); 2694 parent = SYSCTL_CHILDREN(tree); 2695 2696 /* Rx statistics. */ 2697 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 2698 NULL, "Rx MAC statistics"); 2699 child = SYSCTL_CHILDREN(tree); 2700 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_errs", 2701 &stats->rx_pkts_errs, 2702 "Packet errors including both wire errors and FIFO overruns"); 2703 NGE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 2704 &stats->rx_crc_errs, "CRC errors"); 2705 NGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2706 &stats->rx_fifo_oflows, "FIFO overflows"); 2707 NGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2708 &stats->rx_align_errs, "Frame alignment errors"); 2709 NGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2710 &stats->rx_sym_errs, "One or more symbol errors"); 2711 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_jumbos", 2712 &stats->rx_pkts_jumbos, 2713 "Packets received with length greater than 1518 bytes"); 2714 NGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2715 &stats->rx_len_errs, "In Range Length errors"); 2716 NGE_SYSCTL_STAT_ADD32(ctx, child, "unctl_frames", 2717 &stats->rx_unctl_frames, "Control frames with unsupported opcode"); 2718 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2719 &stats->rx_pause, "Pause frames"); 2720 2721 /* Tx statistics. */ 2722 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 2723 NULL, "Tx MAC statistics"); 2724 child = SYSCTL_CHILDREN(tree); 2725 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2726 &stats->tx_pause, "Pause frames"); 2727 NGE_SYSCTL_STAT_ADD32(ctx, child, "seq_errs", 2728 &stats->tx_seq_errs, 2729 "Loss of collision heartbeat during transmission"); 2730 } 2731 2732 #undef NGE_SYSCTL_STAT_ADD32 2733 2734 static int 2735 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2736 { 2737 int error, value; 2738 2739 if (arg1 == NULL) 2740 return (EINVAL); 2741 value = *(int *)arg1; 2742 error = sysctl_handle_int(oidp, &value, 0, req); 2743 if (error != 0 || req->newptr == NULL) 2744 return (error); 2745 if (value < low || value > high) 2746 return (EINVAL); 2747 *(int *)arg1 = value; 2748 2749 return (0); 2750 } 2751 2752 static int 2753 sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS) 2754 { 2755 2756 return (sysctl_int_range(oidp, arg1, arg2, req, NGE_INT_HOLDOFF_MIN, 2757 NGE_INT_HOLDOFF_MAX)); 2758 } 2759