1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 6 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #ifdef HAVE_KERNEL_OPTION_HEADERS 92 #include "opt_device_polling.h" 93 #endif 94 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/bus.h> 98 #include <sys/endian.h> 99 #include <sys/kernel.h> 100 #include <sys/lock.h> 101 #include <sys/malloc.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/rman.h> 106 #include <sys/socket.h> 107 #include <sys/sockio.h> 108 #include <sys/sysctl.h> 109 110 #include <net/bpf.h> 111 #include <net/if.h> 112 #include <net/if_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/if_types.h> 118 #include <net/if_vlan_var.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/mii_bitbang.h> 122 #include <dev/mii/miivar.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 127 #include <machine/bus.h> 128 129 #include <dev/nge/if_ngereg.h> 130 131 /* "device miibus" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 MODULE_DEPEND(nge, pci, 1, 1, 1); 135 MODULE_DEPEND(nge, ether, 1, 1, 1); 136 MODULE_DEPEND(nge, miibus, 1, 1, 1); 137 138 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static const struct nge_type nge_devs[] = { 144 { NGE_VENDORID, NGE_DEVICEID, 145 "National Semiconductor Gigabit Ethernet" }, 146 { 0, 0, NULL } 147 }; 148 149 static int nge_probe(device_t); 150 static int nge_attach(device_t); 151 static int nge_detach(device_t); 152 static int nge_shutdown(device_t); 153 static int nge_suspend(device_t); 154 static int nge_resume(device_t); 155 156 static __inline void nge_discard_rxbuf(struct nge_softc *, int); 157 static int nge_newbuf(struct nge_softc *, int); 158 static int nge_encap(struct nge_softc *, struct mbuf **); 159 #ifndef __NO_STRICT_ALIGNMENT 160 static __inline void nge_fixup_rx(struct mbuf *); 161 #endif 162 static int nge_rxeof(struct nge_softc *); 163 static void nge_txeof(struct nge_softc *); 164 static void nge_intr(void *); 165 static void nge_tick(void *); 166 static void nge_stats_update(struct nge_softc *); 167 static void nge_start(if_t); 168 static void nge_start_locked(if_t); 169 static int nge_ioctl(if_t, u_long, caddr_t); 170 static void nge_init(void *); 171 static void nge_init_locked(struct nge_softc *); 172 static int nge_stop_mac(struct nge_softc *); 173 static void nge_stop(struct nge_softc *); 174 static void nge_wol(struct nge_softc *); 175 static void nge_watchdog(struct nge_softc *); 176 static int nge_mediachange(if_t); 177 static void nge_mediastatus(if_t, struct ifmediareq *); 178 179 static void nge_delay(struct nge_softc *); 180 static void nge_eeprom_idle(struct nge_softc *); 181 static void nge_eeprom_putbyte(struct nge_softc *, int); 182 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 183 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int); 184 185 static int nge_miibus_readreg(device_t, int, int); 186 static int nge_miibus_writereg(device_t, int, int, int); 187 static void nge_miibus_statchg(device_t); 188 189 static void nge_rxfilter(struct nge_softc *); 190 static void nge_reset(struct nge_softc *); 191 static void nge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 192 static int nge_dma_alloc(struct nge_softc *); 193 static void nge_dma_free(struct nge_softc *); 194 static int nge_list_rx_init(struct nge_softc *); 195 static int nge_list_tx_init(struct nge_softc *); 196 static void nge_sysctl_node(struct nge_softc *); 197 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 198 static int sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS); 199 200 /* 201 * MII bit-bang glue 202 */ 203 static uint32_t nge_mii_bitbang_read(device_t); 204 static void nge_mii_bitbang_write(device_t, uint32_t); 205 206 static const struct mii_bitbang_ops nge_mii_bitbang_ops = { 207 nge_mii_bitbang_read, 208 nge_mii_bitbang_write, 209 { 210 NGE_MEAR_MII_DATA, /* MII_BIT_MDO */ 211 NGE_MEAR_MII_DATA, /* MII_BIT_MDI */ 212 NGE_MEAR_MII_CLK, /* MII_BIT_MDC */ 213 NGE_MEAR_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 214 0, /* MII_BIT_DIR_PHY_HOST */ 215 } 216 }; 217 218 static device_method_t nge_methods[] = { 219 /* Device interface */ 220 DEVMETHOD(device_probe, nge_probe), 221 DEVMETHOD(device_attach, nge_attach), 222 DEVMETHOD(device_detach, nge_detach), 223 DEVMETHOD(device_shutdown, nge_shutdown), 224 DEVMETHOD(device_suspend, nge_suspend), 225 DEVMETHOD(device_resume, nge_resume), 226 227 /* MII interface */ 228 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 229 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 230 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 231 232 DEVMETHOD_END 233 }; 234 235 static driver_t nge_driver = { 236 "nge", 237 nge_methods, 238 sizeof(struct nge_softc) 239 }; 240 241 DRIVER_MODULE(nge, pci, nge_driver, 0, 0); 242 DRIVER_MODULE(miibus, nge, miibus_driver, 0, 0); 243 244 #define NGE_SETBIT(sc, reg, x) \ 245 CSR_WRITE_4(sc, reg, \ 246 CSR_READ_4(sc, reg) | (x)) 247 248 #define NGE_CLRBIT(sc, reg, x) \ 249 CSR_WRITE_4(sc, reg, \ 250 CSR_READ_4(sc, reg) & ~(x)) 251 252 #define SIO_SET(x) \ 253 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 254 255 #define SIO_CLR(x) \ 256 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 257 258 static void 259 nge_delay(struct nge_softc *sc) 260 { 261 int idx; 262 263 for (idx = (300 / 33) + 1; idx > 0; idx--) 264 CSR_READ_4(sc, NGE_CSR); 265 } 266 267 static void 268 nge_eeprom_idle(struct nge_softc *sc) 269 { 270 int i; 271 272 SIO_SET(NGE_MEAR_EE_CSEL); 273 nge_delay(sc); 274 SIO_SET(NGE_MEAR_EE_CLK); 275 nge_delay(sc); 276 277 for (i = 0; i < 25; i++) { 278 SIO_CLR(NGE_MEAR_EE_CLK); 279 nge_delay(sc); 280 SIO_SET(NGE_MEAR_EE_CLK); 281 nge_delay(sc); 282 } 283 284 SIO_CLR(NGE_MEAR_EE_CLK); 285 nge_delay(sc); 286 SIO_CLR(NGE_MEAR_EE_CSEL); 287 nge_delay(sc); 288 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 289 } 290 291 /* 292 * Send a read command and address to the EEPROM, check for ACK. 293 */ 294 static void 295 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 296 { 297 int d, i; 298 299 d = addr | NGE_EECMD_READ; 300 301 /* 302 * Feed in each bit and stobe the clock. 303 */ 304 for (i = 0x400; i; i >>= 1) { 305 if (d & i) { 306 SIO_SET(NGE_MEAR_EE_DIN); 307 } else { 308 SIO_CLR(NGE_MEAR_EE_DIN); 309 } 310 nge_delay(sc); 311 SIO_SET(NGE_MEAR_EE_CLK); 312 nge_delay(sc); 313 SIO_CLR(NGE_MEAR_EE_CLK); 314 nge_delay(sc); 315 } 316 } 317 318 /* 319 * Read a word of data stored in the EEPROM at address 'addr.' 320 */ 321 static void 322 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 323 { 324 int i; 325 uint16_t word = 0; 326 327 /* Force EEPROM to idle state. */ 328 nge_eeprom_idle(sc); 329 330 /* Enter EEPROM access mode. */ 331 nge_delay(sc); 332 SIO_CLR(NGE_MEAR_EE_CLK); 333 nge_delay(sc); 334 SIO_SET(NGE_MEAR_EE_CSEL); 335 nge_delay(sc); 336 337 /* 338 * Send address of word we want to read. 339 */ 340 nge_eeprom_putbyte(sc, addr); 341 342 /* 343 * Start reading bits from EEPROM. 344 */ 345 for (i = 0x8000; i; i >>= 1) { 346 SIO_SET(NGE_MEAR_EE_CLK); 347 nge_delay(sc); 348 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 349 word |= i; 350 nge_delay(sc); 351 SIO_CLR(NGE_MEAR_EE_CLK); 352 nge_delay(sc); 353 } 354 355 /* Turn off EEPROM access mode. */ 356 nge_eeprom_idle(sc); 357 358 *dest = word; 359 } 360 361 /* 362 * Read a sequence of words from the EEPROM. 363 */ 364 static void 365 nge_read_eeprom(struct nge_softc *sc, caddr_t dest, int off, int cnt) 366 { 367 int i; 368 uint16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 nge_eeprom_getword(sc, off + i, &word); 372 ptr = (uint16_t *)(dest + (i * 2)); 373 *ptr = word; 374 } 375 } 376 377 /* 378 * Read the MII serial port for the MII bit-bang module. 379 */ 380 static uint32_t 381 nge_mii_bitbang_read(device_t dev) 382 { 383 struct nge_softc *sc; 384 uint32_t val; 385 386 sc = device_get_softc(dev); 387 388 val = CSR_READ_4(sc, NGE_MEAR); 389 CSR_BARRIER_4(sc, NGE_MEAR, 390 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 391 392 return (val); 393 } 394 395 /* 396 * Write the MII serial port for the MII bit-bang module. 397 */ 398 static void 399 nge_mii_bitbang_write(device_t dev, uint32_t val) 400 { 401 struct nge_softc *sc; 402 403 sc = device_get_softc(dev); 404 405 CSR_WRITE_4(sc, NGE_MEAR, val); 406 CSR_BARRIER_4(sc, NGE_MEAR, 407 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 408 } 409 410 static int 411 nge_miibus_readreg(device_t dev, int phy, int reg) 412 { 413 struct nge_softc *sc; 414 int rv; 415 416 sc = device_get_softc(dev); 417 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 418 /* Pretend PHY is at address 0. */ 419 if (phy != 0) 420 return (0); 421 switch (reg) { 422 case MII_BMCR: 423 reg = NGE_TBI_BMCR; 424 break; 425 case MII_BMSR: 426 /* 83820/83821 has different bit layout for BMSR. */ 427 rv = BMSR_ANEG | BMSR_EXTCAP | BMSR_EXTSTAT; 428 reg = CSR_READ_4(sc, NGE_TBI_BMSR); 429 if ((reg & NGE_TBIBMSR_ANEG_DONE) != 0) 430 rv |= BMSR_ACOMP; 431 if ((reg & NGE_TBIBMSR_LINKSTAT) != 0) 432 rv |= BMSR_LINK; 433 return (rv); 434 case MII_ANAR: 435 reg = NGE_TBI_ANAR; 436 break; 437 case MII_ANLPAR: 438 reg = NGE_TBI_ANLPAR; 439 break; 440 case MII_ANER: 441 reg = NGE_TBI_ANER; 442 break; 443 case MII_EXTSR: 444 reg = NGE_TBI_ESR; 445 break; 446 case MII_PHYIDR1: 447 case MII_PHYIDR2: 448 return (0); 449 default: 450 device_printf(sc->nge_dev, 451 "bad phy register read : %d\n", reg); 452 return (0); 453 } 454 return (CSR_READ_4(sc, reg)); 455 } 456 457 return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg)); 458 } 459 460 static int 461 nge_miibus_writereg(device_t dev, int phy, int reg, int data) 462 { 463 struct nge_softc *sc; 464 465 sc = device_get_softc(dev); 466 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 467 /* Pretend PHY is at address 0. */ 468 if (phy != 0) 469 return (0); 470 switch (reg) { 471 case MII_BMCR: 472 reg = NGE_TBI_BMCR; 473 break; 474 case MII_BMSR: 475 return (0); 476 case MII_ANAR: 477 reg = NGE_TBI_ANAR; 478 break; 479 case MII_ANLPAR: 480 reg = NGE_TBI_ANLPAR; 481 break; 482 case MII_ANER: 483 reg = NGE_TBI_ANER; 484 break; 485 case MII_EXTSR: 486 reg = NGE_TBI_ESR; 487 break; 488 case MII_PHYIDR1: 489 case MII_PHYIDR2: 490 return (0); 491 default: 492 device_printf(sc->nge_dev, 493 "bad phy register write : %d\n", reg); 494 return (0); 495 } 496 CSR_WRITE_4(sc, reg, data); 497 return (0); 498 } 499 500 mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data); 501 502 return (0); 503 } 504 505 /* 506 * media status/link state change handler. 507 */ 508 static void 509 nge_miibus_statchg(device_t dev) 510 { 511 struct nge_softc *sc; 512 struct mii_data *mii; 513 if_t ifp; 514 struct nge_txdesc *txd; 515 uint32_t done, reg, status; 516 int i; 517 518 sc = device_get_softc(dev); 519 NGE_LOCK_ASSERT(sc); 520 521 mii = device_get_softc(sc->nge_miibus); 522 ifp = sc->nge_ifp; 523 if (mii == NULL || ifp == NULL || 524 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 525 return; 526 527 sc->nge_flags &= ~NGE_FLAG_LINK; 528 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 529 (IFM_AVALID | IFM_ACTIVE)) { 530 switch (IFM_SUBTYPE(mii->mii_media_active)) { 531 case IFM_10_T: 532 case IFM_100_TX: 533 case IFM_1000_T: 534 case IFM_1000_SX: 535 case IFM_1000_LX: 536 case IFM_1000_CX: 537 sc->nge_flags |= NGE_FLAG_LINK; 538 break; 539 default: 540 break; 541 } 542 } 543 544 /* Stop Tx/Rx MACs. */ 545 if (nge_stop_mac(sc) == ETIMEDOUT) 546 device_printf(sc->nge_dev, 547 "%s: unable to stop Tx/Rx MAC\n", __func__); 548 nge_txeof(sc); 549 nge_rxeof(sc); 550 if (sc->nge_head != NULL) { 551 m_freem(sc->nge_head); 552 sc->nge_head = sc->nge_tail = NULL; 553 } 554 555 /* Release queued frames. */ 556 for (i = 0; i < NGE_TX_RING_CNT; i++) { 557 txd = &sc->nge_cdata.nge_txdesc[i]; 558 if (txd->tx_m != NULL) { 559 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 560 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 561 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 562 txd->tx_dmamap); 563 m_freem(txd->tx_m); 564 txd->tx_m = NULL; 565 } 566 } 567 568 /* Program MAC with resolved speed/duplex. */ 569 if ((sc->nge_flags & NGE_FLAG_LINK) != 0) { 570 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 571 NGE_SETBIT(sc, NGE_TX_CFG, 572 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 573 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 574 #ifdef notyet 575 /* Enable flow-control. */ 576 if ((IFM_OPTIONS(mii->mii_media_active) & 577 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) != 0) 578 NGE_SETBIT(sc, NGE_PAUSECSR, 579 NGE_PAUSECSR_PAUSE_ENB); 580 #endif 581 } else { 582 NGE_CLRBIT(sc, NGE_TX_CFG, 583 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 584 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 585 NGE_CLRBIT(sc, NGE_PAUSECSR, NGE_PAUSECSR_PAUSE_ENB); 586 } 587 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 588 reg = CSR_READ_4(sc, NGE_CFG); 589 switch (IFM_SUBTYPE(mii->mii_media_active)) { 590 case IFM_1000_SX: 591 case IFM_1000_LX: 592 case IFM_1000_CX: 593 case IFM_1000_T: 594 reg |= NGE_CFG_MODE_1000; 595 break; 596 default: 597 reg &= ~NGE_CFG_MODE_1000; 598 break; 599 } 600 CSR_WRITE_4(sc, NGE_CFG, reg); 601 602 /* Reset Tx/Rx MAC. */ 603 reg = CSR_READ_4(sc, NGE_CSR); 604 reg |= NGE_CSR_TX_RESET | NGE_CSR_RX_RESET; 605 CSR_WRITE_4(sc, NGE_CSR, reg); 606 /* Check the completion of reset. */ 607 done = 0; 608 for (i = 0; i < NGE_TIMEOUT; i++) { 609 DELAY(1); 610 status = CSR_READ_4(sc, NGE_ISR); 611 if ((status & NGE_ISR_RX_RESET_DONE) != 0) 612 done |= NGE_ISR_RX_RESET_DONE; 613 if ((status & NGE_ISR_TX_RESET_DONE) != 0) 614 done |= NGE_ISR_TX_RESET_DONE; 615 if (done == 616 (NGE_ISR_TX_RESET_DONE | NGE_ISR_RX_RESET_DONE)) 617 break; 618 } 619 if (i == NGE_TIMEOUT) 620 device_printf(sc->nge_dev, 621 "%s: unable to reset Tx/Rx MAC\n", __func__); 622 /* Reuse Rx buffer and reset consumer pointer. */ 623 sc->nge_cdata.nge_rx_cons = 0; 624 /* 625 * It seems that resetting Rx/Tx MAC results in 626 * resetting Tx/Rx descriptor pointer registers such 627 * that reloading Tx/Rx lists address are needed. 628 */ 629 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 630 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 631 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 632 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 633 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 634 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 635 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 636 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 637 /* Reinitialize Tx buffers. */ 638 nge_list_tx_init(sc); 639 640 /* Restart Rx MAC. */ 641 reg = CSR_READ_4(sc, NGE_CSR); 642 reg |= NGE_CSR_RX_ENABLE; 643 CSR_WRITE_4(sc, NGE_CSR, reg); 644 for (i = 0; i < NGE_TIMEOUT; i++) { 645 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0) 646 break; 647 DELAY(1); 648 } 649 if (i == NGE_TIMEOUT) 650 device_printf(sc->nge_dev, 651 "%s: unable to restart Rx MAC\n", __func__); 652 } 653 654 /* Data LED off for TBI mode */ 655 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 656 CSR_WRITE_4(sc, NGE_GPIO, 657 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 658 } 659 660 static u_int 661 nge_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 662 { 663 struct nge_softc *sc = arg; 664 uint32_t h; 665 int bit, index; 666 667 /* 668 * From the 11 bits returned by the crc routine, the top 7 669 * bits represent the 16-bit word in the mcast hash table 670 * that needs to be updated, and the lower 4 bits represent 671 * which bit within that byte needs to be set. 672 */ 673 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 21; 674 index = (h >> 4) & 0x7F; 675 bit = h & 0xF; 676 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + (index * 2)); 677 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 678 679 return (1); 680 } 681 682 static void 683 nge_rxfilter(struct nge_softc *sc) 684 { 685 if_t ifp; 686 uint32_t i, rxfilt; 687 688 NGE_LOCK_ASSERT(sc); 689 ifp = sc->nge_ifp; 690 691 /* Make sure to stop Rx filtering. */ 692 rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL); 693 rxfilt &= ~NGE_RXFILTCTL_ENABLE; 694 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 695 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 696 697 rxfilt &= ~(NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_ALLPHYS); 698 rxfilt &= ~NGE_RXFILTCTL_BROAD; 699 /* 700 * We don't want to use the hash table for matching unicast 701 * addresses. 702 */ 703 rxfilt &= ~(NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 704 705 /* 706 * For the NatSemi chip, we have to explicitly enable the 707 * reception of ARP frames, as well as turn on the 'perfect 708 * match' filter where we store the station address, otherwise 709 * we won't receive unicasts meant for this host. 710 */ 711 rxfilt |= NGE_RXFILTCTL_ARP | NGE_RXFILTCTL_PERFECT; 712 713 /* 714 * Set the capture broadcast bit to capture broadcast frames. 715 */ 716 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 717 rxfilt |= NGE_RXFILTCTL_BROAD; 718 719 if ((if_getflags(ifp) & IFF_PROMISC) != 0 || 720 (if_getflags(ifp) & IFF_ALLMULTI) != 0) { 721 rxfilt |= NGE_RXFILTCTL_ALLMULTI; 722 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 723 rxfilt |= NGE_RXFILTCTL_ALLPHYS; 724 goto done; 725 } 726 727 /* 728 * We have to explicitly enable the multicast hash table 729 * on the NatSemi chip if we want to use it, which we do. 730 */ 731 rxfilt |= NGE_RXFILTCTL_MCHASH; 732 733 /* first, zot all the existing hash bits */ 734 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 735 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 736 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 737 } 738 739 if_foreach_llmaddr(ifp, nge_write_maddr, sc); 740 done: 741 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 742 /* Turn the receive filter on. */ 743 rxfilt |= NGE_RXFILTCTL_ENABLE; 744 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 745 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 746 } 747 748 static void 749 nge_reset(struct nge_softc *sc) 750 { 751 uint32_t v; 752 int i; 753 754 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 755 756 for (i = 0; i < NGE_TIMEOUT; i++) { 757 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 758 break; 759 DELAY(1); 760 } 761 762 if (i == NGE_TIMEOUT) 763 device_printf(sc->nge_dev, "reset never completed\n"); 764 765 /* Wait a little while for the chip to get its brains in order. */ 766 DELAY(1000); 767 768 /* 769 * If this is a NetSemi chip, make sure to clear 770 * PME mode. 771 */ 772 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 773 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 774 775 /* Clear WOL events which may interfere normal Rx filter opertaion. */ 776 CSR_WRITE_4(sc, NGE_WOLCSR, 0); 777 778 /* 779 * Only DP83820 supports 64bits addressing/data transfers and 780 * 64bit addressing requires different descriptor structures. 781 * To make it simple, disable 64bit addressing/data transfers. 782 */ 783 v = CSR_READ_4(sc, NGE_CFG); 784 v &= ~(NGE_CFG_64BIT_ADDR_ENB | NGE_CFG_64BIT_DATA_ENB); 785 CSR_WRITE_4(sc, NGE_CFG, v); 786 } 787 788 /* 789 * Probe for a NatSemi chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792 static int 793 nge_probe(device_t dev) 794 { 795 const struct nge_type *t; 796 797 t = nge_devs; 798 799 while (t->nge_name != NULL) { 800 if ((pci_get_vendor(dev) == t->nge_vid) && 801 (pci_get_device(dev) == t->nge_did)) { 802 device_set_desc(dev, t->nge_name); 803 return (BUS_PROBE_DEFAULT); 804 } 805 t++; 806 } 807 808 return (ENXIO); 809 } 810 811 /* 812 * Attach the interface. Allocate softc structures, do ifmedia 813 * setup and ethernet/BPF attach. 814 */ 815 static int 816 nge_attach(device_t dev) 817 { 818 uint8_t eaddr[ETHER_ADDR_LEN]; 819 uint16_t ea[ETHER_ADDR_LEN/2], ea_temp, reg; 820 struct nge_softc *sc; 821 if_t ifp; 822 int error, i, rid; 823 824 error = 0; 825 sc = device_get_softc(dev); 826 sc->nge_dev = dev; 827 828 NGE_LOCK_INIT(sc, device_get_nameunit(dev)); 829 callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0); 830 831 /* 832 * Map control/status registers. 833 */ 834 pci_enable_busmaster(dev); 835 836 #ifdef NGE_USEIOSPACE 837 sc->nge_res_type = SYS_RES_IOPORT; 838 sc->nge_res_id = PCIR_BAR(0); 839 #else 840 sc->nge_res_type = SYS_RES_MEMORY; 841 sc->nge_res_id = PCIR_BAR(1); 842 #endif 843 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 844 &sc->nge_res_id, RF_ACTIVE); 845 846 if (sc->nge_res == NULL) { 847 if (sc->nge_res_type == SYS_RES_MEMORY) { 848 sc->nge_res_type = SYS_RES_IOPORT; 849 sc->nge_res_id = PCIR_BAR(0); 850 } else { 851 sc->nge_res_type = SYS_RES_MEMORY; 852 sc->nge_res_id = PCIR_BAR(1); 853 } 854 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 855 &sc->nge_res_id, RF_ACTIVE); 856 if (sc->nge_res == NULL) { 857 device_printf(dev, "couldn't allocate %s resources\n", 858 sc->nge_res_type == SYS_RES_MEMORY ? "memory" : 859 "I/O"); 860 NGE_LOCK_DESTROY(sc); 861 return (ENXIO); 862 } 863 } 864 865 /* Allocate interrupt */ 866 rid = 0; 867 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 868 RF_SHAREABLE | RF_ACTIVE); 869 870 if (sc->nge_irq == NULL) { 871 device_printf(dev, "couldn't map interrupt\n"); 872 error = ENXIO; 873 goto fail; 874 } 875 876 /* Enable MWI. */ 877 reg = pci_read_config(dev, PCIR_COMMAND, 2); 878 reg |= PCIM_CMD_MWRICEN; 879 pci_write_config(dev, PCIR_COMMAND, reg, 2); 880 881 /* Reset the adapter. */ 882 nge_reset(sc); 883 884 /* 885 * Get station address from the EEPROM. 886 */ 887 nge_read_eeprom(sc, (caddr_t)ea, NGE_EE_NODEADDR, 3); 888 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 889 ea[i] = le16toh(ea[i]); 890 ea_temp = ea[0]; 891 ea[0] = ea[2]; 892 ea[2] = ea_temp; 893 bcopy(ea, eaddr, sizeof(eaddr)); 894 895 if (nge_dma_alloc(sc) != 0) { 896 error = ENXIO; 897 goto fail; 898 } 899 900 nge_sysctl_node(sc); 901 902 ifp = sc->nge_ifp = if_alloc(IFT_ETHER); 903 if_setsoftc(ifp, sc); 904 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 905 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 906 if_setioctlfn(ifp, nge_ioctl); 907 if_setstartfn(ifp, nge_start); 908 if_setinitfn(ifp, nge_init); 909 if_setsendqlen(ifp, NGE_TX_RING_CNT - 1); 910 if_setsendqready(ifp); 911 if_sethwassist(ifp, NGE_CSUM_FEATURES); 912 if_setcapabilities(ifp, IFCAP_HWCSUM); 913 /* 914 * It seems that some hardwares doesn't provide 3.3V auxiliary 915 * supply(3VAUX) to drive PME such that checking PCI power 916 * management capability is necessary. 917 */ 918 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &i) == 0) 919 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 920 if_setcapenable(ifp, if_getcapabilities(ifp)); 921 922 if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) { 923 sc->nge_flags |= NGE_FLAG_TBI; 924 device_printf(dev, "Using TBI\n"); 925 /* Configure GPIO. */ 926 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 927 | NGE_GPIO_GP4_OUT 928 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 929 | NGE_GPIO_GP3_OUTENB 930 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 931 } 932 933 /* 934 * Do MII setup. 935 */ 936 error = mii_attach(dev, &sc->nge_miibus, ifp, nge_mediachange, 937 nge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 938 if (error != 0) { 939 device_printf(dev, "attaching PHYs failed\n"); 940 goto fail; 941 } 942 943 /* 944 * Call MI attach routine. 945 */ 946 ether_ifattach(ifp, eaddr); 947 948 /* VLAN capability setup. */ 949 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 950 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 951 if_setcapenable(ifp, if_getcapabilities(ifp)); 952 #ifdef DEVICE_POLLING 953 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 954 #endif 955 /* 956 * Tell the upper layer(s) we support long frames. 957 * Must appear after the call to ether_ifattach() because 958 * ether_ifattach() sets ifi_hdrlen to the default value. 959 */ 960 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 961 962 /* 963 * Hookup IRQ last. 964 */ 965 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE, 966 NULL, nge_intr, sc, &sc->nge_intrhand); 967 if (error) { 968 device_printf(dev, "couldn't set up irq\n"); 969 goto fail; 970 } 971 972 fail: 973 if (error != 0) 974 nge_detach(dev); 975 return (error); 976 } 977 978 static int 979 nge_detach(device_t dev) 980 { 981 struct nge_softc *sc; 982 if_t ifp; 983 984 sc = device_get_softc(dev); 985 ifp = sc->nge_ifp; 986 987 #ifdef DEVICE_POLLING 988 if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING) 989 ether_poll_deregister(ifp); 990 #endif 991 992 if (device_is_attached(dev)) { 993 NGE_LOCK(sc); 994 sc->nge_flags |= NGE_FLAG_DETACH; 995 nge_stop(sc); 996 NGE_UNLOCK(sc); 997 callout_drain(&sc->nge_stat_ch); 998 if (ifp != NULL) 999 ether_ifdetach(ifp); 1000 } 1001 1002 bus_generic_detach(dev); 1003 if (sc->nge_intrhand != NULL) 1004 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1005 if (sc->nge_irq != NULL) 1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1007 if (sc->nge_res != NULL) 1008 bus_release_resource(dev, sc->nge_res_type, sc->nge_res_id, 1009 sc->nge_res); 1010 1011 nge_dma_free(sc); 1012 if (ifp != NULL) 1013 if_free(ifp); 1014 1015 NGE_LOCK_DESTROY(sc); 1016 1017 return (0); 1018 } 1019 1020 struct nge_dmamap_arg { 1021 bus_addr_t nge_busaddr; 1022 }; 1023 1024 static void 1025 nge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1026 { 1027 struct nge_dmamap_arg *ctx; 1028 1029 if (error != 0) 1030 return; 1031 ctx = arg; 1032 ctx->nge_busaddr = segs[0].ds_addr; 1033 } 1034 1035 static int 1036 nge_dma_alloc(struct nge_softc *sc) 1037 { 1038 struct nge_dmamap_arg ctx; 1039 struct nge_txdesc *txd; 1040 struct nge_rxdesc *rxd; 1041 int error, i; 1042 1043 /* Create parent DMA tag. */ 1044 error = bus_dma_tag_create( 1045 bus_get_dma_tag(sc->nge_dev), /* parent */ 1046 1, 0, /* alignment, boundary */ 1047 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1048 BUS_SPACE_MAXADDR, /* highaddr */ 1049 NULL, NULL, /* filter, filterarg */ 1050 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1051 0, /* nsegments */ 1052 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1053 0, /* flags */ 1054 NULL, NULL, /* lockfunc, lockarg */ 1055 &sc->nge_cdata.nge_parent_tag); 1056 if (error != 0) { 1057 device_printf(sc->nge_dev, "failed to create parent DMA tag\n"); 1058 goto fail; 1059 } 1060 /* Create tag for Tx ring. */ 1061 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1062 NGE_RING_ALIGN, 0, /* alignment, boundary */ 1063 BUS_SPACE_MAXADDR, /* lowaddr */ 1064 BUS_SPACE_MAXADDR, /* highaddr */ 1065 NULL, NULL, /* filter, filterarg */ 1066 NGE_TX_RING_SIZE, /* maxsize */ 1067 1, /* nsegments */ 1068 NGE_TX_RING_SIZE, /* maxsegsize */ 1069 0, /* flags */ 1070 NULL, NULL, /* lockfunc, lockarg */ 1071 &sc->nge_cdata.nge_tx_ring_tag); 1072 if (error != 0) { 1073 device_printf(sc->nge_dev, "failed to create Tx ring DMA tag\n"); 1074 goto fail; 1075 } 1076 1077 /* Create tag for Rx ring. */ 1078 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1079 NGE_RING_ALIGN, 0, /* alignment, boundary */ 1080 BUS_SPACE_MAXADDR, /* lowaddr */ 1081 BUS_SPACE_MAXADDR, /* highaddr */ 1082 NULL, NULL, /* filter, filterarg */ 1083 NGE_RX_RING_SIZE, /* maxsize */ 1084 1, /* nsegments */ 1085 NGE_RX_RING_SIZE, /* maxsegsize */ 1086 0, /* flags */ 1087 NULL, NULL, /* lockfunc, lockarg */ 1088 &sc->nge_cdata.nge_rx_ring_tag); 1089 if (error != 0) { 1090 device_printf(sc->nge_dev, 1091 "failed to create Rx ring DMA tag\n"); 1092 goto fail; 1093 } 1094 1095 /* Create tag for Tx buffers. */ 1096 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1097 1, 0, /* alignment, boundary */ 1098 BUS_SPACE_MAXADDR, /* lowaddr */ 1099 BUS_SPACE_MAXADDR, /* highaddr */ 1100 NULL, NULL, /* filter, filterarg */ 1101 MCLBYTES * NGE_MAXTXSEGS, /* maxsize */ 1102 NGE_MAXTXSEGS, /* nsegments */ 1103 MCLBYTES, /* maxsegsize */ 1104 0, /* flags */ 1105 NULL, NULL, /* lockfunc, lockarg */ 1106 &sc->nge_cdata.nge_tx_tag); 1107 if (error != 0) { 1108 device_printf(sc->nge_dev, "failed to create Tx DMA tag\n"); 1109 goto fail; 1110 } 1111 1112 /* Create tag for Rx buffers. */ 1113 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1114 NGE_RX_ALIGN, 0, /* alignment, boundary */ 1115 BUS_SPACE_MAXADDR, /* lowaddr */ 1116 BUS_SPACE_MAXADDR, /* highaddr */ 1117 NULL, NULL, /* filter, filterarg */ 1118 MCLBYTES, /* maxsize */ 1119 1, /* nsegments */ 1120 MCLBYTES, /* maxsegsize */ 1121 0, /* flags */ 1122 NULL, NULL, /* lockfunc, lockarg */ 1123 &sc->nge_cdata.nge_rx_tag); 1124 if (error != 0) { 1125 device_printf(sc->nge_dev, "failed to create Rx DMA tag\n"); 1126 goto fail; 1127 } 1128 1129 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1130 error = bus_dmamem_alloc(sc->nge_cdata.nge_tx_ring_tag, 1131 (void **)&sc->nge_rdata.nge_tx_ring, BUS_DMA_WAITOK | 1132 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_tx_ring_map); 1133 if (error != 0) { 1134 device_printf(sc->nge_dev, 1135 "failed to allocate DMA'able memory for Tx ring\n"); 1136 goto fail; 1137 } 1138 1139 ctx.nge_busaddr = 0; 1140 error = bus_dmamap_load(sc->nge_cdata.nge_tx_ring_tag, 1141 sc->nge_cdata.nge_tx_ring_map, sc->nge_rdata.nge_tx_ring, 1142 NGE_TX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1143 if (error != 0 || ctx.nge_busaddr == 0) { 1144 device_printf(sc->nge_dev, 1145 "failed to load DMA'able memory for Tx ring\n"); 1146 goto fail; 1147 } 1148 sc->nge_rdata.nge_tx_ring_paddr = ctx.nge_busaddr; 1149 1150 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1151 error = bus_dmamem_alloc(sc->nge_cdata.nge_rx_ring_tag, 1152 (void **)&sc->nge_rdata.nge_rx_ring, BUS_DMA_WAITOK | 1153 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_rx_ring_map); 1154 if (error != 0) { 1155 device_printf(sc->nge_dev, 1156 "failed to allocate DMA'able memory for Rx ring\n"); 1157 goto fail; 1158 } 1159 1160 ctx.nge_busaddr = 0; 1161 error = bus_dmamap_load(sc->nge_cdata.nge_rx_ring_tag, 1162 sc->nge_cdata.nge_rx_ring_map, sc->nge_rdata.nge_rx_ring, 1163 NGE_RX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1164 if (error != 0 || ctx.nge_busaddr == 0) { 1165 device_printf(sc->nge_dev, 1166 "failed to load DMA'able memory for Rx ring\n"); 1167 goto fail; 1168 } 1169 sc->nge_rdata.nge_rx_ring_paddr = ctx.nge_busaddr; 1170 1171 /* Create DMA maps for Tx buffers. */ 1172 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1173 txd = &sc->nge_cdata.nge_txdesc[i]; 1174 txd->tx_m = NULL; 1175 txd->tx_dmamap = NULL; 1176 error = bus_dmamap_create(sc->nge_cdata.nge_tx_tag, 0, 1177 &txd->tx_dmamap); 1178 if (error != 0) { 1179 device_printf(sc->nge_dev, 1180 "failed to create Tx dmamap\n"); 1181 goto fail; 1182 } 1183 } 1184 /* Create DMA maps for Rx buffers. */ 1185 if ((error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1186 &sc->nge_cdata.nge_rx_sparemap)) != 0) { 1187 device_printf(sc->nge_dev, 1188 "failed to create spare Rx dmamap\n"); 1189 goto fail; 1190 } 1191 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1192 rxd = &sc->nge_cdata.nge_rxdesc[i]; 1193 rxd->rx_m = NULL; 1194 rxd->rx_dmamap = NULL; 1195 error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1196 &rxd->rx_dmamap); 1197 if (error != 0) { 1198 device_printf(sc->nge_dev, 1199 "failed to create Rx dmamap\n"); 1200 goto fail; 1201 } 1202 } 1203 1204 fail: 1205 return (error); 1206 } 1207 1208 static void 1209 nge_dma_free(struct nge_softc *sc) 1210 { 1211 struct nge_txdesc *txd; 1212 struct nge_rxdesc *rxd; 1213 int i; 1214 1215 /* Tx ring. */ 1216 if (sc->nge_cdata.nge_tx_ring_tag) { 1217 if (sc->nge_rdata.nge_tx_ring_paddr) 1218 bus_dmamap_unload(sc->nge_cdata.nge_tx_ring_tag, 1219 sc->nge_cdata.nge_tx_ring_map); 1220 if (sc->nge_rdata.nge_tx_ring) 1221 bus_dmamem_free(sc->nge_cdata.nge_tx_ring_tag, 1222 sc->nge_rdata.nge_tx_ring, 1223 sc->nge_cdata.nge_tx_ring_map); 1224 sc->nge_rdata.nge_tx_ring = NULL; 1225 sc->nge_rdata.nge_tx_ring_paddr = 0; 1226 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_ring_tag); 1227 sc->nge_cdata.nge_tx_ring_tag = NULL; 1228 } 1229 /* Rx ring. */ 1230 if (sc->nge_cdata.nge_rx_ring_tag) { 1231 if (sc->nge_rdata.nge_rx_ring_paddr) 1232 bus_dmamap_unload(sc->nge_cdata.nge_rx_ring_tag, 1233 sc->nge_cdata.nge_rx_ring_map); 1234 if (sc->nge_rdata.nge_rx_ring) 1235 bus_dmamem_free(sc->nge_cdata.nge_rx_ring_tag, 1236 sc->nge_rdata.nge_rx_ring, 1237 sc->nge_cdata.nge_rx_ring_map); 1238 sc->nge_rdata.nge_rx_ring = NULL; 1239 sc->nge_rdata.nge_rx_ring_paddr = 0; 1240 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_ring_tag); 1241 sc->nge_cdata.nge_rx_ring_tag = NULL; 1242 } 1243 /* Tx buffers. */ 1244 if (sc->nge_cdata.nge_tx_tag) { 1245 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1246 txd = &sc->nge_cdata.nge_txdesc[i]; 1247 if (txd->tx_dmamap) { 1248 bus_dmamap_destroy(sc->nge_cdata.nge_tx_tag, 1249 txd->tx_dmamap); 1250 txd->tx_dmamap = NULL; 1251 } 1252 } 1253 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_tag); 1254 sc->nge_cdata.nge_tx_tag = NULL; 1255 } 1256 /* Rx buffers. */ 1257 if (sc->nge_cdata.nge_rx_tag) { 1258 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1259 rxd = &sc->nge_cdata.nge_rxdesc[i]; 1260 if (rxd->rx_dmamap) { 1261 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1262 rxd->rx_dmamap); 1263 rxd->rx_dmamap = NULL; 1264 } 1265 } 1266 if (sc->nge_cdata.nge_rx_sparemap) { 1267 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1268 sc->nge_cdata.nge_rx_sparemap); 1269 sc->nge_cdata.nge_rx_sparemap = 0; 1270 } 1271 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_tag); 1272 sc->nge_cdata.nge_rx_tag = NULL; 1273 } 1274 1275 if (sc->nge_cdata.nge_parent_tag) { 1276 bus_dma_tag_destroy(sc->nge_cdata.nge_parent_tag); 1277 sc->nge_cdata.nge_parent_tag = NULL; 1278 } 1279 } 1280 1281 /* 1282 * Initialize the transmit descriptors. 1283 */ 1284 static int 1285 nge_list_tx_init(struct nge_softc *sc) 1286 { 1287 struct nge_ring_data *rd; 1288 struct nge_txdesc *txd; 1289 bus_addr_t addr; 1290 int i; 1291 1292 sc->nge_cdata.nge_tx_prod = 0; 1293 sc->nge_cdata.nge_tx_cons = 0; 1294 sc->nge_cdata.nge_tx_cnt = 0; 1295 1296 rd = &sc->nge_rdata; 1297 bzero(rd->nge_tx_ring, sizeof(struct nge_desc) * NGE_TX_RING_CNT); 1298 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1299 if (i == NGE_TX_RING_CNT - 1) 1300 addr = NGE_TX_RING_ADDR(sc, 0); 1301 else 1302 addr = NGE_TX_RING_ADDR(sc, i + 1); 1303 rd->nge_tx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 1304 txd = &sc->nge_cdata.nge_txdesc[i]; 1305 txd->tx_m = NULL; 1306 } 1307 1308 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1309 sc->nge_cdata.nge_tx_ring_map, 1310 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1311 1312 return (0); 1313 } 1314 1315 /* 1316 * Initialize the RX descriptors and allocate mbufs for them. Note that 1317 * we arrange the descriptors in a closed ring, so that the last descriptor 1318 * points back to the first. 1319 */ 1320 static int 1321 nge_list_rx_init(struct nge_softc *sc) 1322 { 1323 struct nge_ring_data *rd; 1324 bus_addr_t addr; 1325 int i; 1326 1327 sc->nge_cdata.nge_rx_cons = 0; 1328 sc->nge_head = sc->nge_tail = NULL; 1329 1330 rd = &sc->nge_rdata; 1331 bzero(rd->nge_rx_ring, sizeof(struct nge_desc) * NGE_RX_RING_CNT); 1332 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1333 if (nge_newbuf(sc, i) != 0) 1334 return (ENOBUFS); 1335 if (i == NGE_RX_RING_CNT - 1) 1336 addr = NGE_RX_RING_ADDR(sc, 0); 1337 else 1338 addr = NGE_RX_RING_ADDR(sc, i + 1); 1339 rd->nge_rx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 1340 } 1341 1342 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1343 sc->nge_cdata.nge_rx_ring_map, 1344 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1345 1346 return (0); 1347 } 1348 1349 static __inline void 1350 nge_discard_rxbuf(struct nge_softc *sc, int idx) 1351 { 1352 struct nge_desc *desc; 1353 1354 desc = &sc->nge_rdata.nge_rx_ring[idx]; 1355 desc->nge_cmdsts = htole32(MCLBYTES - sizeof(uint64_t)); 1356 desc->nge_extsts = 0; 1357 } 1358 1359 /* 1360 * Initialize an RX descriptor and attach an MBUF cluster. 1361 */ 1362 static int 1363 nge_newbuf(struct nge_softc *sc, int idx) 1364 { 1365 struct nge_desc *desc; 1366 struct nge_rxdesc *rxd; 1367 struct mbuf *m; 1368 bus_dma_segment_t segs[1]; 1369 bus_dmamap_t map; 1370 int nsegs; 1371 1372 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1373 if (m == NULL) 1374 return (ENOBUFS); 1375 m->m_len = m->m_pkthdr.len = MCLBYTES; 1376 m_adj(m, sizeof(uint64_t)); 1377 1378 if (bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_rx_tag, 1379 sc->nge_cdata.nge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1380 m_freem(m); 1381 return (ENOBUFS); 1382 } 1383 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1384 1385 rxd = &sc->nge_cdata.nge_rxdesc[idx]; 1386 if (rxd->rx_m != NULL) { 1387 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1388 BUS_DMASYNC_POSTREAD); 1389 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap); 1390 } 1391 map = rxd->rx_dmamap; 1392 rxd->rx_dmamap = sc->nge_cdata.nge_rx_sparemap; 1393 sc->nge_cdata.nge_rx_sparemap = map; 1394 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1395 BUS_DMASYNC_PREREAD); 1396 rxd->rx_m = m; 1397 desc = &sc->nge_rdata.nge_rx_ring[idx]; 1398 desc->nge_ptr = htole32(NGE_ADDR_LO(segs[0].ds_addr)); 1399 desc->nge_cmdsts = htole32(segs[0].ds_len); 1400 desc->nge_extsts = 0; 1401 1402 return (0); 1403 } 1404 1405 #ifndef __NO_STRICT_ALIGNMENT 1406 static __inline void 1407 nge_fixup_rx(struct mbuf *m) 1408 { 1409 int i; 1410 uint16_t *src, *dst; 1411 1412 src = mtod(m, uint16_t *); 1413 dst = src - 1; 1414 1415 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1416 *dst++ = *src++; 1417 1418 m->m_data -= ETHER_ALIGN; 1419 } 1420 #endif 1421 1422 /* 1423 * A frame has been uploaded: pass the resulting mbuf chain up to 1424 * the higher level protocols. 1425 */ 1426 static int 1427 nge_rxeof(struct nge_softc *sc) 1428 { 1429 struct mbuf *m; 1430 if_t ifp; 1431 struct nge_desc *cur_rx; 1432 struct nge_rxdesc *rxd; 1433 int cons, prog, rx_npkts, total_len; 1434 uint32_t cmdsts, extsts; 1435 1436 NGE_LOCK_ASSERT(sc); 1437 1438 ifp = sc->nge_ifp; 1439 cons = sc->nge_cdata.nge_rx_cons; 1440 rx_npkts = 0; 1441 1442 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1443 sc->nge_cdata.nge_rx_ring_map, 1444 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1445 1446 for (prog = 0; prog < NGE_RX_RING_CNT && 1447 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 1448 NGE_INC(cons, NGE_RX_RING_CNT)) { 1449 #ifdef DEVICE_POLLING 1450 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1451 if (sc->rxcycles <= 0) 1452 break; 1453 sc->rxcycles--; 1454 } 1455 #endif 1456 cur_rx = &sc->nge_rdata.nge_rx_ring[cons]; 1457 cmdsts = le32toh(cur_rx->nge_cmdsts); 1458 extsts = le32toh(cur_rx->nge_extsts); 1459 if ((cmdsts & NGE_CMDSTS_OWN) == 0) 1460 break; 1461 prog++; 1462 rxd = &sc->nge_cdata.nge_rxdesc[cons]; 1463 m = rxd->rx_m; 1464 total_len = cmdsts & NGE_CMDSTS_BUFLEN; 1465 1466 if ((cmdsts & NGE_CMDSTS_MORE) != 0) { 1467 if (nge_newbuf(sc, cons) != 0) { 1468 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1469 if (sc->nge_head != NULL) { 1470 m_freem(sc->nge_head); 1471 sc->nge_head = sc->nge_tail = NULL; 1472 } 1473 nge_discard_rxbuf(sc, cons); 1474 continue; 1475 } 1476 m->m_len = total_len; 1477 if (sc->nge_head == NULL) { 1478 m->m_pkthdr.len = total_len; 1479 sc->nge_head = sc->nge_tail = m; 1480 } else { 1481 m->m_flags &= ~M_PKTHDR; 1482 sc->nge_head->m_pkthdr.len += total_len; 1483 sc->nge_tail->m_next = m; 1484 sc->nge_tail = m; 1485 } 1486 continue; 1487 } 1488 1489 /* 1490 * If an error occurs, update stats, clear the 1491 * status word and leave the mbuf cluster in place: 1492 * it should simply get re-used next time this descriptor 1493 * comes up in the ring. 1494 */ 1495 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1496 if ((cmdsts & NGE_RXSTAT_RUNT) && 1497 total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 4)) { 1498 /* 1499 * Work-around hardware bug, accept runt frames 1500 * if its length is larger than or equal to 56. 1501 */ 1502 } else { 1503 /* 1504 * Input error counters are updated by hardware. 1505 */ 1506 if (sc->nge_head != NULL) { 1507 m_freem(sc->nge_head); 1508 sc->nge_head = sc->nge_tail = NULL; 1509 } 1510 nge_discard_rxbuf(sc, cons); 1511 continue; 1512 } 1513 } 1514 1515 /* Try conjure up a replacement mbuf. */ 1516 1517 if (nge_newbuf(sc, cons) != 0) { 1518 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1519 if (sc->nge_head != NULL) { 1520 m_freem(sc->nge_head); 1521 sc->nge_head = sc->nge_tail = NULL; 1522 } 1523 nge_discard_rxbuf(sc, cons); 1524 continue; 1525 } 1526 1527 /* Chain received mbufs. */ 1528 if (sc->nge_head != NULL) { 1529 m->m_len = total_len; 1530 m->m_flags &= ~M_PKTHDR; 1531 sc->nge_tail->m_next = m; 1532 m = sc->nge_head; 1533 m->m_pkthdr.len += total_len; 1534 sc->nge_head = sc->nge_tail = NULL; 1535 } else 1536 m->m_pkthdr.len = m->m_len = total_len; 1537 1538 /* 1539 * Ok. NatSemi really screwed up here. This is the 1540 * only gigE chip I know of with alignment constraints 1541 * on receive buffers. RX buffers must be 64-bit aligned. 1542 */ 1543 /* 1544 * By popular demand, ignore the alignment problems 1545 * on the non-strict alignment platform. The performance hit 1546 * incurred due to unaligned accesses is much smaller 1547 * than the hit produced by forcing buffer copies all 1548 * the time, especially with jumbo frames. We still 1549 * need to fix up the alignment everywhere else though. 1550 */ 1551 #ifndef __NO_STRICT_ALIGNMENT 1552 nge_fixup_rx(m); 1553 #endif 1554 m->m_pkthdr.rcvif = ifp; 1555 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1556 1557 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1558 /* Do IP checksum checking. */ 1559 if ((extsts & NGE_RXEXTSTS_IPPKT) != 0) 1560 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1561 if ((extsts & NGE_RXEXTSTS_IPCSUMERR) == 0) 1562 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1563 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1564 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1565 (extsts & NGE_RXEXTSTS_UDPPKT && 1566 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1567 m->m_pkthdr.csum_flags |= 1568 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1569 m->m_pkthdr.csum_data = 0xffff; 1570 } 1571 } 1572 1573 /* 1574 * If we received a packet with a vlan tag, pass it 1575 * to vlan_input() instead of ether_input(). 1576 */ 1577 if ((extsts & NGE_RXEXTSTS_VLANPKT) != 0 && 1578 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1579 m->m_pkthdr.ether_vtag = 1580 bswap16(extsts & NGE_RXEXTSTS_VTCI); 1581 m->m_flags |= M_VLANTAG; 1582 } 1583 NGE_UNLOCK(sc); 1584 if_input(ifp, m); 1585 NGE_LOCK(sc); 1586 rx_npkts++; 1587 } 1588 1589 if (prog > 0) { 1590 sc->nge_cdata.nge_rx_cons = cons; 1591 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1592 sc->nge_cdata.nge_rx_ring_map, 1593 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1594 } 1595 return (rx_npkts); 1596 } 1597 1598 /* 1599 * A frame was downloaded to the chip. It's safe for us to clean up 1600 * the list buffers. 1601 */ 1602 static void 1603 nge_txeof(struct nge_softc *sc) 1604 { 1605 struct nge_desc *cur_tx; 1606 struct nge_txdesc *txd; 1607 if_t ifp; 1608 uint32_t cmdsts; 1609 int cons, prod; 1610 1611 NGE_LOCK_ASSERT(sc); 1612 ifp = sc->nge_ifp; 1613 1614 cons = sc->nge_cdata.nge_tx_cons; 1615 prod = sc->nge_cdata.nge_tx_prod; 1616 if (cons == prod) 1617 return; 1618 1619 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1620 sc->nge_cdata.nge_tx_ring_map, 1621 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1622 1623 /* 1624 * Go through our tx list and free mbufs for those 1625 * frames that have been transmitted. 1626 */ 1627 for (; cons != prod; NGE_INC(cons, NGE_TX_RING_CNT)) { 1628 cur_tx = &sc->nge_rdata.nge_tx_ring[cons]; 1629 cmdsts = le32toh(cur_tx->nge_cmdsts); 1630 if ((cmdsts & NGE_CMDSTS_OWN) != 0) 1631 break; 1632 sc->nge_cdata.nge_tx_cnt--; 1633 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1634 if ((cmdsts & NGE_CMDSTS_MORE) != 0) 1635 continue; 1636 1637 txd = &sc->nge_cdata.nge_txdesc[cons]; 1638 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap, 1639 BUS_DMASYNC_POSTWRITE); 1640 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap); 1641 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1642 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1643 if ((cmdsts & NGE_TXSTAT_EXCESSCOLLS) != 0) 1644 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1645 if ((cmdsts & NGE_TXSTAT_OUTOFWINCOLL) != 0) 1646 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1647 } else 1648 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1649 1650 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (cmdsts & NGE_TXSTAT_COLLCNT) >> 16); 1651 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1652 __func__)); 1653 m_freem(txd->tx_m); 1654 txd->tx_m = NULL; 1655 } 1656 1657 sc->nge_cdata.nge_tx_cons = cons; 1658 if (sc->nge_cdata.nge_tx_cnt == 0) 1659 sc->nge_watchdog_timer = 0; 1660 } 1661 1662 static void 1663 nge_tick(void *xsc) 1664 { 1665 struct nge_softc *sc; 1666 struct mii_data *mii; 1667 1668 sc = xsc; 1669 NGE_LOCK_ASSERT(sc); 1670 mii = device_get_softc(sc->nge_miibus); 1671 mii_tick(mii); 1672 /* 1673 * For PHYs that does not reset established link, it is 1674 * necessary to check whether driver still have a valid 1675 * link(e.g link state change callback is not called). 1676 * Otherwise, driver think it lost link because driver 1677 * initialization routine clears link state flag. 1678 */ 1679 if ((sc->nge_flags & NGE_FLAG_LINK) == 0) 1680 nge_miibus_statchg(sc->nge_dev); 1681 nge_stats_update(sc); 1682 nge_watchdog(sc); 1683 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 1684 } 1685 1686 static void 1687 nge_stats_update(struct nge_softc *sc) 1688 { 1689 if_t ifp; 1690 struct nge_stats now, *stats, *nstats; 1691 1692 NGE_LOCK_ASSERT(sc); 1693 1694 ifp = sc->nge_ifp; 1695 stats = &now; 1696 stats->rx_pkts_errs = 1697 CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF; 1698 stats->rx_crc_errs = 1699 CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF; 1700 stats->rx_fifo_oflows = 1701 CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF; 1702 stats->rx_align_errs = 1703 CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF; 1704 stats->rx_sym_errs = 1705 CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF; 1706 stats->rx_pkts_jumbos = 1707 CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF; 1708 stats->rx_len_errs = 1709 CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF; 1710 stats->rx_unctl_frames = 1711 CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF; 1712 stats->rx_pause = 1713 CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF; 1714 stats->tx_pause = 1715 CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF; 1716 stats->tx_seq_errs = 1717 CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF; 1718 1719 /* 1720 * Since we've accept errored frames exclude Rx length errors. 1721 */ 1722 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1723 stats->rx_pkts_errs + stats->rx_crc_errs + 1724 stats->rx_fifo_oflows + stats->rx_sym_errs); 1725 1726 nstats = &sc->nge_stats; 1727 nstats->rx_pkts_errs += stats->rx_pkts_errs; 1728 nstats->rx_crc_errs += stats->rx_crc_errs; 1729 nstats->rx_fifo_oflows += stats->rx_fifo_oflows; 1730 nstats->rx_align_errs += stats->rx_align_errs; 1731 nstats->rx_sym_errs += stats->rx_sym_errs; 1732 nstats->rx_pkts_jumbos += stats->rx_pkts_jumbos; 1733 nstats->rx_len_errs += stats->rx_len_errs; 1734 nstats->rx_unctl_frames += stats->rx_unctl_frames; 1735 nstats->rx_pause += stats->rx_pause; 1736 nstats->tx_pause += stats->tx_pause; 1737 nstats->tx_seq_errs += stats->tx_seq_errs; 1738 } 1739 1740 #ifdef DEVICE_POLLING 1741 static poll_handler_t nge_poll; 1742 1743 static int 1744 nge_poll(if_t ifp, enum poll_cmd cmd, int count) 1745 { 1746 struct nge_softc *sc; 1747 int rx_npkts = 0; 1748 1749 sc = if_getsoftc(ifp); 1750 1751 NGE_LOCK(sc); 1752 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1753 NGE_UNLOCK(sc); 1754 return (rx_npkts); 1755 } 1756 1757 /* 1758 * On the nge, reading the status register also clears it. 1759 * So before returning to intr mode we must make sure that all 1760 * possible pending sources of interrupts have been served. 1761 * In practice this means run to completion the *eof routines, 1762 * and then call the interrupt routine. 1763 */ 1764 sc->rxcycles = count; 1765 rx_npkts = nge_rxeof(sc); 1766 nge_txeof(sc); 1767 if (!if_sendq_empty(ifp)) 1768 nge_start_locked(ifp); 1769 1770 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1771 uint32_t status; 1772 1773 /* Reading the ISR register clears all interrupts. */ 1774 status = CSR_READ_4(sc, NGE_ISR); 1775 1776 if ((status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) != 0) 1777 rx_npkts += nge_rxeof(sc); 1778 1779 if ((status & NGE_ISR_RX_IDLE) != 0) 1780 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1781 1782 if ((status & NGE_ISR_SYSERR) != 0) { 1783 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1784 nge_init_locked(sc); 1785 } 1786 } 1787 NGE_UNLOCK(sc); 1788 return (rx_npkts); 1789 } 1790 #endif /* DEVICE_POLLING */ 1791 1792 static void 1793 nge_intr(void *arg) 1794 { 1795 struct nge_softc *sc; 1796 if_t ifp; 1797 uint32_t status; 1798 1799 sc = (struct nge_softc *)arg; 1800 ifp = sc->nge_ifp; 1801 1802 NGE_LOCK(sc); 1803 1804 if ((sc->nge_flags & NGE_FLAG_SUSPENDED) != 0) 1805 goto done_locked; 1806 1807 /* Reading the ISR register clears all interrupts. */ 1808 status = CSR_READ_4(sc, NGE_ISR); 1809 if (status == 0xffffffff || (status & NGE_INTRS) == 0) 1810 goto done_locked; 1811 #ifdef DEVICE_POLLING 1812 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) 1813 goto done_locked; 1814 #endif 1815 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1816 goto done_locked; 1817 1818 /* Disable interrupts. */ 1819 CSR_WRITE_4(sc, NGE_IER, 0); 1820 1821 /* Data LED on for TBI mode */ 1822 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1823 CSR_WRITE_4(sc, NGE_GPIO, 1824 CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT); 1825 1826 for (; (status & NGE_INTRS) != 0;) { 1827 if ((status & (NGE_ISR_TX_DESC_OK | NGE_ISR_TX_ERR | 1828 NGE_ISR_TX_OK | NGE_ISR_TX_IDLE)) != 0) 1829 nge_txeof(sc); 1830 1831 if ((status & (NGE_ISR_RX_DESC_OK | NGE_ISR_RX_ERR | 1832 NGE_ISR_RX_OFLOW | NGE_ISR_RX_FIFO_OFLOW | 1833 NGE_ISR_RX_IDLE | NGE_ISR_RX_OK)) != 0) 1834 nge_rxeof(sc); 1835 1836 if ((status & NGE_ISR_RX_IDLE) != 0) 1837 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1838 1839 if ((status & NGE_ISR_SYSERR) != 0) { 1840 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1841 nge_init_locked(sc); 1842 } 1843 /* Reading the ISR register clears all interrupts. */ 1844 status = CSR_READ_4(sc, NGE_ISR); 1845 } 1846 1847 /* Re-enable interrupts. */ 1848 CSR_WRITE_4(sc, NGE_IER, 1); 1849 1850 if (!if_sendq_empty(ifp)) 1851 nge_start_locked(ifp); 1852 1853 /* Data LED off for TBI mode */ 1854 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1855 CSR_WRITE_4(sc, NGE_GPIO, 1856 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 1857 1858 done_locked: 1859 NGE_UNLOCK(sc); 1860 } 1861 1862 /* 1863 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1864 * pointers to the fragment pointers. 1865 */ 1866 static int 1867 nge_encap(struct nge_softc *sc, struct mbuf **m_head) 1868 { 1869 struct nge_txdesc *txd, *txd_last; 1870 struct nge_desc *desc; 1871 struct mbuf *m; 1872 bus_dmamap_t map; 1873 bus_dma_segment_t txsegs[NGE_MAXTXSEGS]; 1874 int error, i, nsegs, prod, si; 1875 1876 NGE_LOCK_ASSERT(sc); 1877 1878 m = *m_head; 1879 prod = sc->nge_cdata.nge_tx_prod; 1880 txd = &sc->nge_cdata.nge_txdesc[prod]; 1881 txd_last = txd; 1882 map = txd->tx_dmamap; 1883 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, map, 1884 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1885 if (error == EFBIG) { 1886 m = m_collapse(*m_head, M_NOWAIT, NGE_MAXTXSEGS); 1887 if (m == NULL) { 1888 m_freem(*m_head); 1889 *m_head = NULL; 1890 return (ENOBUFS); 1891 } 1892 *m_head = m; 1893 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, 1894 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1895 if (error != 0) { 1896 m_freem(*m_head); 1897 *m_head = NULL; 1898 return (error); 1899 } 1900 } else if (error != 0) 1901 return (error); 1902 if (nsegs == 0) { 1903 m_freem(*m_head); 1904 *m_head = NULL; 1905 return (EIO); 1906 } 1907 1908 /* Check number of available descriptors. */ 1909 if (sc->nge_cdata.nge_tx_cnt + nsegs >= (NGE_TX_RING_CNT - 1)) { 1910 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, map); 1911 return (ENOBUFS); 1912 } 1913 1914 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, map, BUS_DMASYNC_PREWRITE); 1915 1916 si = prod; 1917 for (i = 0; i < nsegs; i++) { 1918 desc = &sc->nge_rdata.nge_tx_ring[prod]; 1919 desc->nge_ptr = htole32(NGE_ADDR_LO(txsegs[i].ds_addr)); 1920 if (i == 0) 1921 desc->nge_cmdsts = htole32(txsegs[i].ds_len | 1922 NGE_CMDSTS_MORE); 1923 else 1924 desc->nge_cmdsts = htole32(txsegs[i].ds_len | 1925 NGE_CMDSTS_MORE | NGE_CMDSTS_OWN); 1926 desc->nge_extsts = 0; 1927 sc->nge_cdata.nge_tx_cnt++; 1928 NGE_INC(prod, NGE_TX_RING_CNT); 1929 } 1930 /* Update producer index. */ 1931 sc->nge_cdata.nge_tx_prod = prod; 1932 1933 prod = (prod + NGE_TX_RING_CNT - 1) % NGE_TX_RING_CNT; 1934 desc = &sc->nge_rdata.nge_tx_ring[prod]; 1935 /* Check if we have a VLAN tag to insert. */ 1936 if ((m->m_flags & M_VLANTAG) != 0) 1937 desc->nge_extsts |= htole32(NGE_TXEXTSTS_VLANPKT | 1938 bswap16(m->m_pkthdr.ether_vtag)); 1939 /* Set EOP on the last descriptor. */ 1940 desc->nge_cmdsts &= htole32(~NGE_CMDSTS_MORE); 1941 1942 /* Set checksum offload in the first descriptor. */ 1943 desc = &sc->nge_rdata.nge_tx_ring[si]; 1944 if ((m->m_pkthdr.csum_flags & NGE_CSUM_FEATURES) != 0) { 1945 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1946 desc->nge_extsts |= htole32(NGE_TXEXTSTS_IPCSUM); 1947 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1948 desc->nge_extsts |= htole32(NGE_TXEXTSTS_TCPCSUM); 1949 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1950 desc->nge_extsts |= htole32(NGE_TXEXTSTS_UDPCSUM); 1951 } 1952 /* Lastly, turn the first descriptor ownership to hardware. */ 1953 desc->nge_cmdsts |= htole32(NGE_CMDSTS_OWN); 1954 1955 txd = &sc->nge_cdata.nge_txdesc[prod]; 1956 map = txd_last->tx_dmamap; 1957 txd_last->tx_dmamap = txd->tx_dmamap; 1958 txd->tx_dmamap = map; 1959 txd->tx_m = m; 1960 1961 return (0); 1962 } 1963 1964 /* 1965 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1966 * to the mbuf data regions directly in the transmit lists. We also save a 1967 * copy of the pointers since the transmit list fragment pointers are 1968 * physical addresses. 1969 */ 1970 1971 static void 1972 nge_start(if_t ifp) 1973 { 1974 struct nge_softc *sc; 1975 1976 sc = if_getsoftc(ifp); 1977 NGE_LOCK(sc); 1978 nge_start_locked(ifp); 1979 NGE_UNLOCK(sc); 1980 } 1981 1982 static void 1983 nge_start_locked(if_t ifp) 1984 { 1985 struct nge_softc *sc; 1986 struct mbuf *m_head; 1987 int enq; 1988 1989 sc = if_getsoftc(ifp); 1990 1991 NGE_LOCK_ASSERT(sc); 1992 1993 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1994 IFF_DRV_RUNNING || (sc->nge_flags & NGE_FLAG_LINK) == 0) 1995 return; 1996 1997 for (enq = 0; !if_sendq_empty(ifp) && 1998 sc->nge_cdata.nge_tx_cnt < NGE_TX_RING_CNT - 2; ) { 1999 m_head = if_dequeue(ifp); 2000 if (m_head == NULL) 2001 break; 2002 /* 2003 * Pack the data into the transmit ring. If we 2004 * don't have room, set the OACTIVE flag and wait 2005 * for the NIC to drain the ring. 2006 */ 2007 if (nge_encap(sc, &m_head)) { 2008 if (m_head == NULL) 2009 break; 2010 if_sendq_prepend(ifp, m_head); 2011 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2012 break; 2013 } 2014 2015 enq++; 2016 /* 2017 * If there's a BPF listener, bounce a copy of this frame 2018 * to him. 2019 */ 2020 ETHER_BPF_MTAP(ifp, m_head); 2021 } 2022 2023 if (enq > 0) { 2024 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 2025 sc->nge_cdata.nge_tx_ring_map, 2026 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2027 /* Transmit */ 2028 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 2029 2030 /* Set a timeout in case the chip goes out to lunch. */ 2031 sc->nge_watchdog_timer = 5; 2032 } 2033 } 2034 2035 static void 2036 nge_init(void *xsc) 2037 { 2038 struct nge_softc *sc = xsc; 2039 2040 NGE_LOCK(sc); 2041 nge_init_locked(sc); 2042 NGE_UNLOCK(sc); 2043 } 2044 2045 static void 2046 nge_init_locked(struct nge_softc *sc) 2047 { 2048 if_t ifp = sc->nge_ifp; 2049 struct mii_data *mii; 2050 uint8_t *eaddr; 2051 uint32_t reg; 2052 2053 NGE_LOCK_ASSERT(sc); 2054 2055 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2056 return; 2057 2058 /* 2059 * Cancel pending I/O and free all RX/TX buffers. 2060 */ 2061 nge_stop(sc); 2062 2063 /* Reset the adapter. */ 2064 nge_reset(sc); 2065 2066 /* Disable Rx filter prior to programming Rx filter. */ 2067 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 0); 2068 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 2069 2070 mii = device_get_softc(sc->nge_miibus); 2071 2072 /* Set MAC address. */ 2073 eaddr = if_getlladdr(sc->nge_ifp); 2074 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 2075 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[1] << 8) | eaddr[0]); 2076 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 2077 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[3] << 8) | eaddr[2]); 2078 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 2079 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[5] << 8) | eaddr[4]); 2080 2081 /* Init circular RX list. */ 2082 if (nge_list_rx_init(sc) == ENOBUFS) { 2083 device_printf(sc->nge_dev, "initialization failed: no " 2084 "memory for rx buffers\n"); 2085 nge_stop(sc); 2086 return; 2087 } 2088 2089 /* 2090 * Init tx descriptors. 2091 */ 2092 nge_list_tx_init(sc); 2093 2094 /* Set Rx filter. */ 2095 nge_rxfilter(sc); 2096 2097 /* Disable PRIQ ctl. */ 2098 CSR_WRITE_4(sc, NGE_PRIOQCTL, 0); 2099 2100 /* 2101 * Set pause frames parameters. 2102 * Rx stat FIFO hi-threshold : 2 or more packets 2103 * Rx stat FIFO lo-threshold : less than 2 packets 2104 * Rx data FIFO hi-threshold : 2K or more bytes 2105 * Rx data FIFO lo-threshold : less than 2K bytes 2106 * pause time : (512ns * 0xffff) -> 33.55ms 2107 */ 2108 CSR_WRITE_4(sc, NGE_PAUSECSR, 2109 NGE_PAUSECSR_PAUSE_ON_MCAST | 2110 NGE_PAUSECSR_PAUSE_ON_DA | 2111 ((1 << 24) & NGE_PAUSECSR_RX_STATFIFO_THR_HI) | 2112 ((1 << 22) & NGE_PAUSECSR_RX_STATFIFO_THR_LO) | 2113 ((1 << 20) & NGE_PAUSECSR_RX_DATAFIFO_THR_HI) | 2114 ((1 << 18) & NGE_PAUSECSR_RX_DATAFIFO_THR_LO) | 2115 NGE_PAUSECSR_CNT); 2116 2117 /* 2118 * Load the address of the RX and TX lists. 2119 */ 2120 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 2121 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 2122 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 2123 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 2124 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 2125 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 2126 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 2127 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 2128 2129 /* Set RX configuration. */ 2130 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 2131 2132 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, 0); 2133 /* 2134 * Enable hardware checksum validation for all IPv4 2135 * packets, do not reject packets with bad checksums. 2136 */ 2137 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2138 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 2139 2140 /* 2141 * Tell the chip to detect and strip VLAN tag info from 2142 * received frames. The tag will be provided in the extsts 2143 * field in the RX descriptors. 2144 */ 2145 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_DETECT_ENB); 2146 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2147 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_STRIP_ENB); 2148 2149 /* Set TX configuration. */ 2150 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 2151 2152 /* 2153 * Enable TX IPv4 checksumming on a per-packet basis. 2154 */ 2155 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 2156 2157 /* 2158 * Tell the chip to insert VLAN tags on a per-packet basis as 2159 * dictated by the code in the frame encapsulation routine. 2160 */ 2161 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 2162 2163 /* 2164 * Enable the delivery of PHY interrupts based on 2165 * link/speed/duplex status changes. Also enable the 2166 * extsts field in the DMA descriptors (needed for 2167 * TCP/IP checksum offload on transmit). 2168 */ 2169 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 2170 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 2171 2172 /* 2173 * Configure interrupt holdoff (moderation). We can 2174 * have the chip delay interrupt delivery for a certain 2175 * period. Units are in 100us, and the max setting 2176 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 2177 */ 2178 CSR_WRITE_4(sc, NGE_IHR, sc->nge_int_holdoff); 2179 2180 /* 2181 * Enable MAC statistics counters and clear. 2182 */ 2183 reg = CSR_READ_4(sc, NGE_MIBCTL); 2184 reg &= ~NGE_MIBCTL_FREEZE_CNT; 2185 reg |= NGE_MIBCTL_CLEAR_CNT; 2186 CSR_WRITE_4(sc, NGE_MIBCTL, reg); 2187 2188 /* 2189 * Enable interrupts. 2190 */ 2191 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2192 #ifdef DEVICE_POLLING 2193 /* 2194 * ... only enable interrupts if we are not polling, make sure 2195 * they are off otherwise. 2196 */ 2197 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) 2198 CSR_WRITE_4(sc, NGE_IER, 0); 2199 else 2200 #endif 2201 CSR_WRITE_4(sc, NGE_IER, 1); 2202 2203 sc->nge_flags &= ~NGE_FLAG_LINK; 2204 mii_mediachg(mii); 2205 2206 sc->nge_watchdog_timer = 0; 2207 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 2208 2209 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2210 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2211 } 2212 2213 /* 2214 * Set media options. 2215 */ 2216 static int 2217 nge_mediachange(if_t ifp) 2218 { 2219 struct nge_softc *sc; 2220 struct mii_data *mii; 2221 struct mii_softc *miisc; 2222 int error; 2223 2224 sc = if_getsoftc(ifp); 2225 NGE_LOCK(sc); 2226 mii = device_get_softc(sc->nge_miibus); 2227 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2228 PHY_RESET(miisc); 2229 error = mii_mediachg(mii); 2230 NGE_UNLOCK(sc); 2231 2232 return (error); 2233 } 2234 2235 /* 2236 * Report current media status. 2237 */ 2238 static void 2239 nge_mediastatus(if_t ifp, struct ifmediareq *ifmr) 2240 { 2241 struct nge_softc *sc; 2242 struct mii_data *mii; 2243 2244 sc = if_getsoftc(ifp); 2245 NGE_LOCK(sc); 2246 mii = device_get_softc(sc->nge_miibus); 2247 mii_pollstat(mii); 2248 ifmr->ifm_active = mii->mii_media_active; 2249 ifmr->ifm_status = mii->mii_media_status; 2250 NGE_UNLOCK(sc); 2251 } 2252 2253 static int 2254 nge_ioctl(if_t ifp, u_long command, caddr_t data) 2255 { 2256 struct nge_softc *sc = if_getsoftc(ifp); 2257 struct ifreq *ifr = (struct ifreq *) data; 2258 struct mii_data *mii; 2259 int error = 0, mask; 2260 2261 switch (command) { 2262 case SIOCSIFMTU: 2263 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NGE_JUMBO_MTU) 2264 error = EINVAL; 2265 else { 2266 NGE_LOCK(sc); 2267 if_setmtu(ifp, ifr->ifr_mtu); 2268 /* 2269 * Workaround: if the MTU is larger than 2270 * 8152 (TX FIFO size minus 64 minus 18), turn off 2271 * TX checksum offloading. 2272 */ 2273 if (ifr->ifr_mtu >= 8152) { 2274 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 2275 if_sethwassistbits(ifp, 0, NGE_CSUM_FEATURES); 2276 } else { 2277 if_setcapenablebit(ifp, IFCAP_TXCSUM, 0); 2278 if_sethwassistbits(ifp, NGE_CSUM_FEATURES, 0); 2279 } 2280 NGE_UNLOCK(sc); 2281 VLAN_CAPABILITIES(ifp); 2282 } 2283 break; 2284 case SIOCSIFFLAGS: 2285 NGE_LOCK(sc); 2286 if ((if_getflags(ifp) & IFF_UP) != 0) { 2287 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2288 if ((if_getflags(ifp) ^ sc->nge_if_flags) & 2289 (IFF_PROMISC | IFF_ALLMULTI)) 2290 nge_rxfilter(sc); 2291 } else { 2292 if ((sc->nge_flags & NGE_FLAG_DETACH) == 0) 2293 nge_init_locked(sc); 2294 } 2295 } else { 2296 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2297 nge_stop(sc); 2298 } 2299 sc->nge_if_flags = if_getflags(ifp); 2300 NGE_UNLOCK(sc); 2301 error = 0; 2302 break; 2303 case SIOCADDMULTI: 2304 case SIOCDELMULTI: 2305 NGE_LOCK(sc); 2306 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2307 nge_rxfilter(sc); 2308 NGE_UNLOCK(sc); 2309 break; 2310 case SIOCGIFMEDIA: 2311 case SIOCSIFMEDIA: 2312 mii = device_get_softc(sc->nge_miibus); 2313 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2314 break; 2315 case SIOCSIFCAP: 2316 NGE_LOCK(sc); 2317 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2318 #ifdef DEVICE_POLLING 2319 if ((mask & IFCAP_POLLING) != 0 && 2320 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) { 2321 if_togglecapenable(ifp, IFCAP_POLLING); 2322 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) { 2323 error = ether_poll_register(nge_poll, ifp); 2324 if (error != 0) { 2325 NGE_UNLOCK(sc); 2326 break; 2327 } 2328 /* Disable interrupts. */ 2329 CSR_WRITE_4(sc, NGE_IER, 0); 2330 } else { 2331 error = ether_poll_deregister(ifp); 2332 /* Enable interrupts. */ 2333 CSR_WRITE_4(sc, NGE_IER, 1); 2334 } 2335 } 2336 #endif /* DEVICE_POLLING */ 2337 if ((mask & IFCAP_TXCSUM) != 0 && 2338 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 2339 if_togglecapenable(ifp, IFCAP_TXCSUM); 2340 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 2341 if_sethwassistbits(ifp, NGE_CSUM_FEATURES, 0); 2342 else 2343 if_sethwassistbits(ifp, 0, NGE_CSUM_FEATURES); 2344 } 2345 if ((mask & IFCAP_RXCSUM) != 0 && 2346 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) 2347 if_togglecapenable(ifp, IFCAP_RXCSUM); 2348 2349 if ((mask & IFCAP_WOL) != 0 && 2350 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 2351 if ((mask & IFCAP_WOL_UCAST) != 0) 2352 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 2353 if ((mask & IFCAP_WOL_MCAST) != 0) 2354 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2355 if ((mask & IFCAP_WOL_MAGIC) != 0) 2356 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2357 } 2358 2359 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2360 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2361 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2362 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2363 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2364 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2365 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2366 if ((if_getcapenable(ifp) & 2367 IFCAP_VLAN_HWTAGGING) != 0) 2368 NGE_SETBIT(sc, 2369 NGE_VLAN_IP_RXCTL, 2370 NGE_VIPRXCTL_TAG_STRIP_ENB); 2371 else 2372 NGE_CLRBIT(sc, 2373 NGE_VLAN_IP_RXCTL, 2374 NGE_VIPRXCTL_TAG_STRIP_ENB); 2375 } 2376 } 2377 /* 2378 * Both VLAN hardware tagging and checksum offload is 2379 * required to do checksum offload on VLAN interface. 2380 */ 2381 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) == 0) 2382 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM); 2383 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2384 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM); 2385 NGE_UNLOCK(sc); 2386 VLAN_CAPABILITIES(ifp); 2387 break; 2388 default: 2389 error = ether_ioctl(ifp, command, data); 2390 break; 2391 } 2392 2393 return (error); 2394 } 2395 2396 static void 2397 nge_watchdog(struct nge_softc *sc) 2398 { 2399 if_t ifp; 2400 2401 NGE_LOCK_ASSERT(sc); 2402 2403 if (sc->nge_watchdog_timer == 0 || --sc->nge_watchdog_timer) 2404 return; 2405 2406 ifp = sc->nge_ifp; 2407 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2408 if_printf(ifp, "watchdog timeout\n"); 2409 2410 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2411 nge_init_locked(sc); 2412 2413 if (!if_sendq_empty(ifp)) 2414 nge_start_locked(ifp); 2415 } 2416 2417 static int 2418 nge_stop_mac(struct nge_softc *sc) 2419 { 2420 uint32_t reg; 2421 int i; 2422 2423 NGE_LOCK_ASSERT(sc); 2424 2425 reg = CSR_READ_4(sc, NGE_CSR); 2426 if ((reg & (NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE)) != 0) { 2427 reg &= ~(NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE); 2428 reg |= NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE; 2429 CSR_WRITE_4(sc, NGE_CSR, reg); 2430 for (i = 0; i < NGE_TIMEOUT; i++) { 2431 DELAY(1); 2432 if ((CSR_READ_4(sc, NGE_CSR) & 2433 (NGE_CSR_RX_ENABLE | NGE_CSR_TX_ENABLE)) == 0) 2434 break; 2435 } 2436 if (i == NGE_TIMEOUT) 2437 return (ETIMEDOUT); 2438 } 2439 2440 return (0); 2441 } 2442 2443 /* 2444 * Stop the adapter and free any mbufs allocated to the 2445 * RX and TX lists. 2446 */ 2447 static void 2448 nge_stop(struct nge_softc *sc) 2449 { 2450 struct nge_txdesc *txd; 2451 struct nge_rxdesc *rxd; 2452 int i; 2453 if_t ifp; 2454 2455 NGE_LOCK_ASSERT(sc); 2456 ifp = sc->nge_ifp; 2457 2458 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2459 sc->nge_flags &= ~NGE_FLAG_LINK; 2460 callout_stop(&sc->nge_stat_ch); 2461 sc->nge_watchdog_timer = 0; 2462 2463 CSR_WRITE_4(sc, NGE_IER, 0); 2464 CSR_WRITE_4(sc, NGE_IMR, 0); 2465 if (nge_stop_mac(sc) == ETIMEDOUT) 2466 device_printf(sc->nge_dev, 2467 "%s: unable to stop Tx/Rx MAC\n", __func__); 2468 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 0); 2469 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 0); 2470 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2471 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2472 nge_stats_update(sc); 2473 if (sc->nge_head != NULL) { 2474 m_freem(sc->nge_head); 2475 sc->nge_head = sc->nge_tail = NULL; 2476 } 2477 2478 /* 2479 * Free RX and TX mbufs still in the queues. 2480 */ 2481 for (i = 0; i < NGE_RX_RING_CNT; i++) { 2482 rxd = &sc->nge_cdata.nge_rxdesc[i]; 2483 if (rxd->rx_m != NULL) { 2484 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, 2485 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2486 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, 2487 rxd->rx_dmamap); 2488 m_freem(rxd->rx_m); 2489 rxd->rx_m = NULL; 2490 } 2491 } 2492 for (i = 0; i < NGE_TX_RING_CNT; i++) { 2493 txd = &sc->nge_cdata.nge_txdesc[i]; 2494 if (txd->tx_m != NULL) { 2495 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 2496 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2497 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 2498 txd->tx_dmamap); 2499 m_freem(txd->tx_m); 2500 txd->tx_m = NULL; 2501 } 2502 } 2503 } 2504 2505 /* 2506 * Before setting WOL bits, caller should have stopped Receiver. 2507 */ 2508 static void 2509 nge_wol(struct nge_softc *sc) 2510 { 2511 if_t ifp; 2512 uint32_t reg; 2513 uint16_t pmstat; 2514 int pmc; 2515 2516 NGE_LOCK_ASSERT(sc); 2517 2518 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) != 0) 2519 return; 2520 2521 ifp = sc->nge_ifp; 2522 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2523 /* Disable WOL & disconnect CLKRUN to save power. */ 2524 CSR_WRITE_4(sc, NGE_WOLCSR, 0); 2525 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 2526 } else { 2527 if (nge_stop_mac(sc) == ETIMEDOUT) 2528 device_printf(sc->nge_dev, 2529 "%s: unable to stop Tx/Rx MAC\n", __func__); 2530 /* 2531 * Make sure wake frames will be buffered in the Rx FIFO. 2532 * (i.e. Silent Rx mode.) 2533 */ 2534 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2535 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_HI, BUS_SPACE_BARRIER_WRITE); 2536 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2537 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_LO, BUS_SPACE_BARRIER_WRITE); 2538 /* Enable Rx again. */ 2539 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2540 CSR_BARRIER_4(sc, NGE_CSR, BUS_SPACE_BARRIER_WRITE); 2541 2542 /* Configure WOL events. */ 2543 reg = 0; 2544 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 2545 reg |= NGE_WOLCSR_WAKE_ON_UNICAST; 2546 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2547 reg |= NGE_WOLCSR_WAKE_ON_MULTICAST; 2548 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2549 reg |= NGE_WOLCSR_WAKE_ON_MAGICPKT; 2550 CSR_WRITE_4(sc, NGE_WOLCSR, reg); 2551 2552 /* Activate CLKRUN. */ 2553 reg = CSR_READ_4(sc, NGE_CLKRUN); 2554 reg |= NGE_CLKRUN_PMEENB | NGE_CLNRUN_CLKRUN_ENB; 2555 CSR_WRITE_4(sc, NGE_CLKRUN, reg); 2556 } 2557 2558 /* Request PME. */ 2559 pmstat = pci_read_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, 2); 2560 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2561 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2562 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2563 pci_write_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2564 } 2565 2566 /* 2567 * Stop all chip I/O so that the kernel's probe routines don't 2568 * get confused by errant DMAs when rebooting. 2569 */ 2570 static int 2571 nge_shutdown(device_t dev) 2572 { 2573 2574 return (nge_suspend(dev)); 2575 } 2576 2577 static int 2578 nge_suspend(device_t dev) 2579 { 2580 struct nge_softc *sc; 2581 2582 sc = device_get_softc(dev); 2583 2584 NGE_LOCK(sc); 2585 nge_stop(sc); 2586 nge_wol(sc); 2587 sc->nge_flags |= NGE_FLAG_SUSPENDED; 2588 NGE_UNLOCK(sc); 2589 2590 return (0); 2591 } 2592 2593 static int 2594 nge_resume(device_t dev) 2595 { 2596 struct nge_softc *sc; 2597 if_t ifp; 2598 uint16_t pmstat; 2599 int pmc; 2600 2601 sc = device_get_softc(dev); 2602 2603 NGE_LOCK(sc); 2604 ifp = sc->nge_ifp; 2605 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) == 0) { 2606 /* Disable PME and clear PME status. */ 2607 pmstat = pci_read_config(sc->nge_dev, 2608 pmc + PCIR_POWER_STATUS, 2); 2609 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2610 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2611 pci_write_config(sc->nge_dev, 2612 pmc + PCIR_POWER_STATUS, pmstat, 2); 2613 } 2614 } 2615 if (if_getflags(ifp) & IFF_UP) { 2616 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2617 nge_init_locked(sc); 2618 } 2619 2620 sc->nge_flags &= ~NGE_FLAG_SUSPENDED; 2621 NGE_UNLOCK(sc); 2622 2623 return (0); 2624 } 2625 2626 #define NGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2627 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2628 2629 static void 2630 nge_sysctl_node(struct nge_softc *sc) 2631 { 2632 struct sysctl_ctx_list *ctx; 2633 struct sysctl_oid_list *child, *parent; 2634 struct sysctl_oid *tree; 2635 struct nge_stats *stats; 2636 int error; 2637 2638 ctx = device_get_sysctl_ctx(sc->nge_dev); 2639 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nge_dev)); 2640 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_holdoff", 2641 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->nge_int_holdoff, 2642 0, sysctl_hw_nge_int_holdoff, "I", "NGE interrupt moderation"); 2643 /* Pull in device tunables. */ 2644 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2645 error = resource_int_value(device_get_name(sc->nge_dev), 2646 device_get_unit(sc->nge_dev), "int_holdoff", &sc->nge_int_holdoff); 2647 if (error == 0) { 2648 if (sc->nge_int_holdoff < NGE_INT_HOLDOFF_MIN || 2649 sc->nge_int_holdoff > NGE_INT_HOLDOFF_MAX ) { 2650 device_printf(sc->nge_dev, 2651 "int_holdoff value out of range; " 2652 "using default: %d(%d us)\n", 2653 NGE_INT_HOLDOFF_DEFAULT, 2654 NGE_INT_HOLDOFF_DEFAULT * 100); 2655 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2656 } 2657 } 2658 2659 stats = &sc->nge_stats; 2660 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2661 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NGE statistics"); 2662 parent = SYSCTL_CHILDREN(tree); 2663 2664 /* Rx statistics. */ 2665 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2666 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 2667 child = SYSCTL_CHILDREN(tree); 2668 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_errs", 2669 &stats->rx_pkts_errs, 2670 "Packet errors including both wire errors and FIFO overruns"); 2671 NGE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 2672 &stats->rx_crc_errs, "CRC errors"); 2673 NGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2674 &stats->rx_fifo_oflows, "FIFO overflows"); 2675 NGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2676 &stats->rx_align_errs, "Frame alignment errors"); 2677 NGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2678 &stats->rx_sym_errs, "One or more symbol errors"); 2679 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_jumbos", 2680 &stats->rx_pkts_jumbos, 2681 "Packets received with length greater than 1518 bytes"); 2682 NGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2683 &stats->rx_len_errs, "In Range Length errors"); 2684 NGE_SYSCTL_STAT_ADD32(ctx, child, "unctl_frames", 2685 &stats->rx_unctl_frames, "Control frames with unsupported opcode"); 2686 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2687 &stats->rx_pause, "Pause frames"); 2688 2689 /* Tx statistics. */ 2690 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2691 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 2692 child = SYSCTL_CHILDREN(tree); 2693 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2694 &stats->tx_pause, "Pause frames"); 2695 NGE_SYSCTL_STAT_ADD32(ctx, child, "seq_errs", 2696 &stats->tx_seq_errs, 2697 "Loss of collision heartbeat during transmission"); 2698 } 2699 2700 #undef NGE_SYSCTL_STAT_ADD32 2701 2702 static int 2703 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2704 { 2705 int error, value; 2706 2707 if (arg1 == NULL) 2708 return (EINVAL); 2709 value = *(int *)arg1; 2710 error = sysctl_handle_int(oidp, &value, 0, req); 2711 if (error != 0 || req->newptr == NULL) 2712 return (error); 2713 if (value < low || value > high) 2714 return (EINVAL); 2715 *(int *)arg1 = value; 2716 2717 return (0); 2718 } 2719 2720 static int 2721 sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS) 2722 { 2723 2724 return (sysctl_int_range(oidp, arg1, arg2, req, NGE_INT_HOLDOFF_MIN, 2725 NGE_INT_HOLDOFF_MAX)); 2726 } 2727