1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_types.h> 105 #include <net/if_vlan_var.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/clock.h> /* for DELAY */ 112 #include <machine/bus_pio.h> 113 #include <machine/bus_memio.h> 114 #include <machine/bus.h> 115 #include <machine/resource.h> 116 #include <sys/bus.h> 117 #include <sys/rman.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 125 #define NGE_USEIOSPACE 126 127 #include <dev/nge/if_ngereg.h> 128 129 MODULE_DEPEND(nge, pci, 1, 1, 1); 130 MODULE_DEPEND(nge, ether, 1, 1, 1); 131 MODULE_DEPEND(nge, miibus, 1, 1, 1); 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct nge_type nge_devs[] = { 142 { NGE_VENDORID, NGE_DEVICEID, 143 "National Semiconductor Gigabit Ethernet" }, 144 { 0, 0, NULL } 145 }; 146 147 static int nge_probe(device_t); 148 static int nge_attach(device_t); 149 static int nge_detach(device_t); 150 151 static int nge_alloc_jumbo_mem(struct nge_softc *); 152 static void nge_free_jumbo_mem(struct nge_softc *); 153 static void *nge_jalloc(struct nge_softc *); 154 static void nge_jfree(void *, void *); 155 156 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *); 157 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 158 static void nge_rxeof(struct nge_softc *); 159 static void nge_txeof(struct nge_softc *); 160 static void nge_intr(void *); 161 static void nge_tick(void *); 162 static void nge_start(struct ifnet *); 163 static int nge_ioctl(struct ifnet *, u_long, caddr_t); 164 static void nge_init(void *); 165 static void nge_stop(struct nge_softc *); 166 static void nge_watchdog(struct ifnet *); 167 static void nge_shutdown(device_t); 168 static int nge_ifmedia_upd(struct ifnet *); 169 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 170 171 static void nge_delay(struct nge_softc *); 172 static void nge_eeprom_idle(struct nge_softc *); 173 static void nge_eeprom_putbyte(struct nge_softc *, int); 174 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 175 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 176 177 static void nge_mii_sync(struct nge_softc *); 178 static void nge_mii_send(struct nge_softc *, u_int32_t, int); 179 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 180 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 181 182 static int nge_miibus_readreg(device_t, int, int); 183 static int nge_miibus_writereg(device_t, int, int, int); 184 static void nge_miibus_statchg(device_t); 185 186 static void nge_setmulti(struct nge_softc *); 187 static uint32_t nge_mchash(const uint8_t *); 188 static void nge_reset(struct nge_softc *); 189 static int nge_list_rx_init(struct nge_softc *); 190 static int nge_list_tx_init(struct nge_softc *); 191 192 #ifdef NGE_USEIOSPACE 193 #define NGE_RES SYS_RES_IOPORT 194 #define NGE_RID NGE_PCI_LOIO 195 #else 196 #define NGE_RES SYS_RES_MEMORY 197 #define NGE_RID NGE_PCI_LOMEM 198 #endif 199 200 static device_method_t nge_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, nge_probe), 203 DEVMETHOD(device_attach, nge_attach), 204 DEVMETHOD(device_detach, nge_detach), 205 DEVMETHOD(device_shutdown, nge_shutdown), 206 207 /* bus interface */ 208 DEVMETHOD(bus_print_child, bus_generic_print_child), 209 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 210 211 /* MII interface */ 212 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 213 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 214 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 215 216 { 0, 0 } 217 }; 218 219 static driver_t nge_driver = { 220 "nge", 221 nge_methods, 222 sizeof(struct nge_softc) 223 }; 224 225 static devclass_t nge_devclass; 226 227 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 228 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 229 230 #define NGE_SETBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) | (x)) 233 234 #define NGE_CLRBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) & ~(x)) 237 238 #define SIO_SET(x) \ 239 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 240 241 #define SIO_CLR(x) \ 242 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 243 244 static void 245 nge_delay(sc) 246 struct nge_softc *sc; 247 { 248 int idx; 249 250 for (idx = (300 / 33) + 1; idx > 0; idx--) 251 CSR_READ_4(sc, NGE_CSR); 252 253 return; 254 } 255 256 static void 257 nge_eeprom_idle(sc) 258 struct nge_softc *sc; 259 { 260 register int i; 261 262 SIO_SET(NGE_MEAR_EE_CSEL); 263 nge_delay(sc); 264 SIO_SET(NGE_MEAR_EE_CLK); 265 nge_delay(sc); 266 267 for (i = 0; i < 25; i++) { 268 SIO_CLR(NGE_MEAR_EE_CLK); 269 nge_delay(sc); 270 SIO_SET(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 } 273 274 SIO_CLR(NGE_MEAR_EE_CLK); 275 nge_delay(sc); 276 SIO_CLR(NGE_MEAR_EE_CSEL); 277 nge_delay(sc); 278 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 279 280 return; 281 } 282 283 /* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286 static void 287 nge_eeprom_putbyte(sc, addr) 288 struct nge_softc *sc; 289 int addr; 290 { 291 register int d, i; 292 293 d = addr | NGE_EECMD_READ; 294 295 /* 296 * Feed in each bit and stobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 SIO_SET(NGE_MEAR_EE_DIN); 301 } else { 302 SIO_CLR(NGE_MEAR_EE_DIN); 303 } 304 nge_delay(sc); 305 SIO_SET(NGE_MEAR_EE_CLK); 306 nge_delay(sc); 307 SIO_CLR(NGE_MEAR_EE_CLK); 308 nge_delay(sc); 309 } 310 311 return; 312 } 313 314 /* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317 static void 318 nge_eeprom_getword(sc, addr, dest) 319 struct nge_softc *sc; 320 int addr; 321 u_int16_t *dest; 322 { 323 register int i; 324 u_int16_t word = 0; 325 326 /* Force EEPROM to idle state. */ 327 nge_eeprom_idle(sc); 328 329 /* Enter EEPROM access mode. */ 330 nge_delay(sc); 331 SIO_CLR(NGE_MEAR_EE_CLK); 332 nge_delay(sc); 333 SIO_SET(NGE_MEAR_EE_CSEL); 334 nge_delay(sc); 335 336 /* 337 * Send address of word we want to read. 338 */ 339 nge_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_SET(NGE_MEAR_EE_CLK); 346 nge_delay(sc); 347 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 348 word |= i; 349 nge_delay(sc); 350 SIO_CLR(NGE_MEAR_EE_CLK); 351 nge_delay(sc); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 nge_eeprom_idle(sc); 356 357 *dest = word; 358 359 return; 360 } 361 362 /* 363 * Read a sequence of words from the EEPROM. 364 */ 365 static void 366 nge_read_eeprom(sc, dest, off, cnt, swap) 367 struct nge_softc *sc; 368 caddr_t dest; 369 int off; 370 int cnt; 371 int swap; 372 { 373 int i; 374 u_int16_t word = 0, *ptr; 375 376 for (i = 0; i < cnt; i++) { 377 nge_eeprom_getword(sc, off + i, &word); 378 ptr = (u_int16_t *)(dest + (i * 2)); 379 if (swap) 380 *ptr = ntohs(word); 381 else 382 *ptr = word; 383 } 384 385 return; 386 } 387 388 /* 389 * Sync the PHYs by setting data bit and strobing the clock 32 times. 390 */ 391 static void 392 nge_mii_sync(sc) 393 struct nge_softc *sc; 394 { 395 register int i; 396 397 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 398 399 for (i = 0; i < 32; i++) { 400 SIO_SET(NGE_MEAR_MII_CLK); 401 DELAY(1); 402 SIO_CLR(NGE_MEAR_MII_CLK); 403 DELAY(1); 404 } 405 406 return; 407 } 408 409 /* 410 * Clock a series of bits through the MII. 411 */ 412 static void 413 nge_mii_send(sc, bits, cnt) 414 struct nge_softc *sc; 415 u_int32_t bits; 416 int cnt; 417 { 418 int i; 419 420 SIO_CLR(NGE_MEAR_MII_CLK); 421 422 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 423 if (bits & i) { 424 SIO_SET(NGE_MEAR_MII_DATA); 425 } else { 426 SIO_CLR(NGE_MEAR_MII_DATA); 427 } 428 DELAY(1); 429 SIO_CLR(NGE_MEAR_MII_CLK); 430 DELAY(1); 431 SIO_SET(NGE_MEAR_MII_CLK); 432 } 433 } 434 435 /* 436 * Read an PHY register through the MII. 437 */ 438 static int 439 nge_mii_readreg(sc, frame) 440 struct nge_softc *sc; 441 struct nge_mii_frame *frame; 442 443 { 444 int i, ack, s; 445 446 s = splimp(); 447 448 /* 449 * Set up frame for RX. 450 */ 451 frame->mii_stdelim = NGE_MII_STARTDELIM; 452 frame->mii_opcode = NGE_MII_READOP; 453 frame->mii_turnaround = 0; 454 frame->mii_data = 0; 455 456 CSR_WRITE_4(sc, NGE_MEAR, 0); 457 458 /* 459 * Turn on data xmit. 460 */ 461 SIO_SET(NGE_MEAR_MII_DIR); 462 463 nge_mii_sync(sc); 464 465 /* 466 * Send command/address info. 467 */ 468 nge_mii_send(sc, frame->mii_stdelim, 2); 469 nge_mii_send(sc, frame->mii_opcode, 2); 470 nge_mii_send(sc, frame->mii_phyaddr, 5); 471 nge_mii_send(sc, frame->mii_regaddr, 5); 472 473 /* Idle bit */ 474 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 475 DELAY(1); 476 SIO_SET(NGE_MEAR_MII_CLK); 477 DELAY(1); 478 479 /* Turn off xmit. */ 480 SIO_CLR(NGE_MEAR_MII_DIR); 481 /* Check for ack */ 482 SIO_CLR(NGE_MEAR_MII_CLK); 483 DELAY(1); 484 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 485 SIO_SET(NGE_MEAR_MII_CLK); 486 DELAY(1); 487 488 /* 489 * Now try reading data bits. If the ack failed, we still 490 * need to clock through 16 cycles to keep the PHY(s) in sync. 491 */ 492 if (ack) { 493 for(i = 0; i < 16; i++) { 494 SIO_CLR(NGE_MEAR_MII_CLK); 495 DELAY(1); 496 SIO_SET(NGE_MEAR_MII_CLK); 497 DELAY(1); 498 } 499 goto fail; 500 } 501 502 for (i = 0x8000; i; i >>= 1) { 503 SIO_CLR(NGE_MEAR_MII_CLK); 504 DELAY(1); 505 if (!ack) { 506 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 507 frame->mii_data |= i; 508 DELAY(1); 509 } 510 SIO_SET(NGE_MEAR_MII_CLK); 511 DELAY(1); 512 } 513 514 fail: 515 516 SIO_CLR(NGE_MEAR_MII_CLK); 517 DELAY(1); 518 SIO_SET(NGE_MEAR_MII_CLK); 519 DELAY(1); 520 521 splx(s); 522 523 if (ack) 524 return(1); 525 return(0); 526 } 527 528 /* 529 * Write to a PHY register through the MII. 530 */ 531 static int 532 nge_mii_writereg(sc, frame) 533 struct nge_softc *sc; 534 struct nge_mii_frame *frame; 535 536 { 537 int s; 538 539 s = splimp(); 540 /* 541 * Set up frame for TX. 542 */ 543 544 frame->mii_stdelim = NGE_MII_STARTDELIM; 545 frame->mii_opcode = NGE_MII_WRITEOP; 546 frame->mii_turnaround = NGE_MII_TURNAROUND; 547 548 /* 549 * Turn on data output. 550 */ 551 SIO_SET(NGE_MEAR_MII_DIR); 552 553 nge_mii_sync(sc); 554 555 nge_mii_send(sc, frame->mii_stdelim, 2); 556 nge_mii_send(sc, frame->mii_opcode, 2); 557 nge_mii_send(sc, frame->mii_phyaddr, 5); 558 nge_mii_send(sc, frame->mii_regaddr, 5); 559 nge_mii_send(sc, frame->mii_turnaround, 2); 560 nge_mii_send(sc, frame->mii_data, 16); 561 562 /* Idle bit. */ 563 SIO_SET(NGE_MEAR_MII_CLK); 564 DELAY(1); 565 SIO_CLR(NGE_MEAR_MII_CLK); 566 DELAY(1); 567 568 /* 569 * Turn off xmit. 570 */ 571 SIO_CLR(NGE_MEAR_MII_DIR); 572 573 splx(s); 574 575 return(0); 576 } 577 578 static int 579 nge_miibus_readreg(dev, phy, reg) 580 device_t dev; 581 int phy, reg; 582 { 583 struct nge_softc *sc; 584 struct nge_mii_frame frame; 585 586 sc = device_get_softc(dev); 587 588 bzero((char *)&frame, sizeof(frame)); 589 590 frame.mii_phyaddr = phy; 591 frame.mii_regaddr = reg; 592 nge_mii_readreg(sc, &frame); 593 594 return(frame.mii_data); 595 } 596 597 static int 598 nge_miibus_writereg(dev, phy, reg, data) 599 device_t dev; 600 int phy, reg, data; 601 { 602 struct nge_softc *sc; 603 struct nge_mii_frame frame; 604 605 sc = device_get_softc(dev); 606 607 bzero((char *)&frame, sizeof(frame)); 608 609 frame.mii_phyaddr = phy; 610 frame.mii_regaddr = reg; 611 frame.mii_data = data; 612 nge_mii_writereg(sc, &frame); 613 614 return(0); 615 } 616 617 static void 618 nge_miibus_statchg(dev) 619 device_t dev; 620 { 621 int status; 622 struct nge_softc *sc; 623 struct mii_data *mii; 624 625 sc = device_get_softc(dev); 626 if (sc->nge_tbi) { 627 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 628 == IFM_AUTO) { 629 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 630 if (status == 0 || status & NGE_TBIANAR_FDX) { 631 NGE_SETBIT(sc, NGE_TX_CFG, 632 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 633 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 634 } else { 635 NGE_CLRBIT(sc, NGE_TX_CFG, 636 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 637 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 638 } 639 640 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 641 != IFM_FDX) { 642 NGE_CLRBIT(sc, NGE_TX_CFG, 643 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 644 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 645 } else { 646 NGE_SETBIT(sc, NGE_TX_CFG, 647 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 648 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 649 } 650 } else { 651 mii = device_get_softc(sc->nge_miibus); 652 653 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 654 NGE_SETBIT(sc, NGE_TX_CFG, 655 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 656 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 657 } else { 658 NGE_CLRBIT(sc, NGE_TX_CFG, 659 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 660 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 661 } 662 663 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 664 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 665 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 666 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 667 } else { 668 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 669 } 670 } 671 return; 672 } 673 674 static u_int32_t 675 nge_mchash(addr) 676 const uint8_t *addr; 677 { 678 uint32_t crc, carry; 679 int idx, bit; 680 uint8_t data; 681 682 /* Compute CRC for the address value. */ 683 crc = 0xFFFFFFFF; /* initial value */ 684 685 for (idx = 0; idx < 6; idx++) { 686 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 687 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 688 crc <<= 1; 689 if (carry) 690 crc = (crc ^ 0x04c11db6) | carry; 691 } 692 } 693 694 /* 695 * return the filter bit position 696 */ 697 698 return((crc >> 21) & 0x00000FFF); 699 } 700 701 static void 702 nge_setmulti(sc) 703 struct nge_softc *sc; 704 { 705 struct ifnet *ifp; 706 struct ifmultiaddr *ifma; 707 u_int32_t h = 0, i, filtsave; 708 int bit, index; 709 710 ifp = &sc->arpcom.ac_if; 711 712 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 713 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 714 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 715 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 716 return; 717 } 718 719 /* 720 * We have to explicitly enable the multicast hash table 721 * on the NatSemi chip if we want to use it, which we do. 722 * We also have to tell it that we don't want to use the 723 * hash table for matching unicast addresses. 724 */ 725 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 726 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 727 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 728 729 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 730 731 /* first, zot all the existing hash bits */ 732 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 733 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 734 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 735 } 736 737 /* 738 * From the 11 bits returned by the crc routine, the top 7 739 * bits represent the 16-bit word in the mcast hash table 740 * that needs to be updated, and the lower 4 bits represent 741 * which bit within that byte needs to be set. 742 */ 743 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 744 if (ifma->ifma_addr->sa_family != AF_LINK) 745 continue; 746 h = nge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 747 index = (h >> 4) & 0x7F; 748 bit = h & 0xF; 749 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 750 NGE_FILTADDR_MCAST_LO + (index * 2)); 751 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 752 } 753 754 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 755 756 return; 757 } 758 759 static void 760 nge_reset(sc) 761 struct nge_softc *sc; 762 { 763 register int i; 764 765 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 766 767 for (i = 0; i < NGE_TIMEOUT; i++) { 768 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 769 break; 770 } 771 772 if (i == NGE_TIMEOUT) 773 printf("nge%d: reset never completed\n", sc->nge_unit); 774 775 /* Wait a little while for the chip to get its brains in order. */ 776 DELAY(1000); 777 778 /* 779 * If this is a NetSemi chip, make sure to clear 780 * PME mode. 781 */ 782 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 783 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 784 785 return; 786 } 787 788 /* 789 * Probe for a NatSemi chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792 static int 793 nge_probe(dev) 794 device_t dev; 795 { 796 struct nge_type *t; 797 798 t = nge_devs; 799 800 while(t->nge_name != NULL) { 801 if ((pci_get_vendor(dev) == t->nge_vid) && 802 (pci_get_device(dev) == t->nge_did)) { 803 device_set_desc(dev, t->nge_name); 804 return(0); 805 } 806 t++; 807 } 808 809 return(ENXIO); 810 } 811 812 /* 813 * Attach the interface. Allocate softc structures, do ifmedia 814 * setup and ethernet/BPF attach. 815 */ 816 static int 817 nge_attach(dev) 818 device_t dev; 819 { 820 int s; 821 u_char eaddr[ETHER_ADDR_LEN]; 822 struct nge_softc *sc; 823 struct ifnet *ifp; 824 int unit, error = 0, rid; 825 const char *sep = ""; 826 827 s = splimp(); 828 829 sc = device_get_softc(dev); 830 unit = device_get_unit(dev); 831 bzero(sc, sizeof(struct nge_softc)); 832 833 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 834 MTX_DEF | MTX_RECURSE); 835 #ifndef BURN_BRIDGES 836 /* 837 * Handle power management nonsense. 838 */ 839 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 840 u_int32_t iobase, membase, irq; 841 842 /* Save important PCI config data. */ 843 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 844 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 845 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 846 847 /* Reset the power state. */ 848 printf("nge%d: chip is in D%d power mode " 849 "-- setting to D0\n", unit, 850 pci_get_powerstate(dev)); 851 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 852 853 /* Restore PCI config data. */ 854 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 855 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 856 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 857 } 858 #endif 859 /* 860 * Map control/status registers. 861 */ 862 pci_enable_busmaster(dev); 863 864 rid = NGE_RID; 865 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 866 867 if (sc->nge_res == NULL) { 868 printf("nge%d: couldn't map ports/memory\n", unit); 869 error = ENXIO; 870 goto fail; 871 } 872 873 sc->nge_btag = rman_get_bustag(sc->nge_res); 874 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 875 876 /* Allocate interrupt */ 877 rid = 0; 878 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 879 RF_SHAREABLE | RF_ACTIVE); 880 881 if (sc->nge_irq == NULL) { 882 printf("nge%d: couldn't map interrupt\n", unit); 883 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 884 error = ENXIO; 885 goto fail; 886 } 887 888 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 889 nge_intr, sc, &sc->nge_intrhand); 890 891 if (error) { 892 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 893 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 894 printf("nge%d: couldn't set up irq\n", unit); 895 goto fail; 896 } 897 898 /* Reset the adapter. */ 899 nge_reset(sc); 900 901 /* 902 * Get station address from the EEPROM. 903 */ 904 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 905 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 906 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 907 908 sc->nge_unit = unit; 909 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 910 911 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 912 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 913 914 if (sc->nge_ldata == NULL) { 915 printf("nge%d: no memory for list buffers!\n", unit); 916 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 917 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 918 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 919 error = ENXIO; 920 goto fail; 921 } 922 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 923 924 /* Try to allocate memory for jumbo buffers. */ 925 if (nge_alloc_jumbo_mem(sc)) { 926 printf("nge%d: jumbo buffer allocation failed\n", 927 sc->nge_unit); 928 contigfree(sc->nge_ldata, 929 sizeof(struct nge_list_data), M_DEVBUF); 930 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 931 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 932 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 933 error = ENXIO; 934 goto fail; 935 } 936 937 ifp = &sc->arpcom.ac_if; 938 ifp->if_softc = sc; 939 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 940 ifp->if_mtu = ETHERMTU; 941 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 942 ifp->if_ioctl = nge_ioctl; 943 ifp->if_start = nge_start; 944 ifp->if_watchdog = nge_watchdog; 945 ifp->if_init = nge_init; 946 ifp->if_baudrate = 1000000000; 947 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 948 ifp->if_hwassist = NGE_CSUM_FEATURES; 949 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 950 #ifdef DEVICE_POLLING 951 ifp->if_capabilities |= IFCAP_POLLING; 952 #endif 953 ifp->if_capenable = ifp->if_capabilities; 954 955 /* 956 * Do MII setup. 957 */ 958 if (mii_phy_probe(dev, &sc->nge_miibus, 959 nge_ifmedia_upd, nge_ifmedia_sts)) { 960 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 961 sc->nge_tbi = 1; 962 device_printf(dev, "Using TBI\n"); 963 964 sc->nge_miibus = dev; 965 966 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 967 nge_ifmedia_sts); 968 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 969 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 970 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 971 device_printf(dev, " "); 972 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 973 PRINT("1000baseSX"); 974 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 975 PRINT("1000baseSX-FDX"); 976 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 977 PRINT("auto"); 978 979 printf("\n"); 980 #undef ADD 981 #undef PRINT 982 ifmedia_set(&sc->nge_ifmedia, 983 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 984 985 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 986 | NGE_GPIO_GP4_OUT 987 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 988 | NGE_GPIO_GP3_OUTENB 989 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 990 991 } else { 992 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 993 nge_free_jumbo_mem(sc); 994 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 995 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 996 bus_release_resource(dev, NGE_RES, NGE_RID, 997 sc->nge_res); 998 error = ENXIO; 999 goto fail; 1000 } 1001 } 1002 1003 /* 1004 * Call MI attach routine. 1005 */ 1006 ether_ifattach(ifp, eaddr); 1007 callout_handle_init(&sc->nge_stat_ch); 1008 1009 fail: 1010 1011 splx(s); 1012 mtx_destroy(&sc->nge_mtx); 1013 return(error); 1014 } 1015 1016 static int 1017 nge_detach(dev) 1018 device_t dev; 1019 { 1020 struct nge_softc *sc; 1021 struct ifnet *ifp; 1022 int s; 1023 1024 s = splimp(); 1025 1026 sc = device_get_softc(dev); 1027 ifp = &sc->arpcom.ac_if; 1028 1029 nge_reset(sc); 1030 nge_stop(sc); 1031 ether_ifdetach(ifp); 1032 1033 bus_generic_detach(dev); 1034 if (!sc->nge_tbi) { 1035 device_delete_child(dev, sc->nge_miibus); 1036 } 1037 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1038 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1039 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 1040 1041 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 1042 nge_free_jumbo_mem(sc); 1043 1044 splx(s); 1045 mtx_destroy(&sc->nge_mtx); 1046 1047 return(0); 1048 } 1049 1050 /* 1051 * Initialize the transmit descriptors. 1052 */ 1053 static int 1054 nge_list_tx_init(sc) 1055 struct nge_softc *sc; 1056 { 1057 struct nge_list_data *ld; 1058 struct nge_ring_data *cd; 1059 int i; 1060 1061 cd = &sc->nge_cdata; 1062 ld = sc->nge_ldata; 1063 1064 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1065 if (i == (NGE_TX_LIST_CNT - 1)) { 1066 ld->nge_tx_list[i].nge_nextdesc = 1067 &ld->nge_tx_list[0]; 1068 ld->nge_tx_list[i].nge_next = 1069 vtophys(&ld->nge_tx_list[0]); 1070 } else { 1071 ld->nge_tx_list[i].nge_nextdesc = 1072 &ld->nge_tx_list[i + 1]; 1073 ld->nge_tx_list[i].nge_next = 1074 vtophys(&ld->nge_tx_list[i + 1]); 1075 } 1076 ld->nge_tx_list[i].nge_mbuf = NULL; 1077 ld->nge_tx_list[i].nge_ptr = 0; 1078 ld->nge_tx_list[i].nge_ctl = 0; 1079 } 1080 1081 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1082 1083 return(0); 1084 } 1085 1086 1087 /* 1088 * Initialize the RX descriptors and allocate mbufs for them. Note that 1089 * we arrange the descriptors in a closed ring, so that the last descriptor 1090 * points back to the first. 1091 */ 1092 static int 1093 nge_list_rx_init(sc) 1094 struct nge_softc *sc; 1095 { 1096 struct nge_list_data *ld; 1097 struct nge_ring_data *cd; 1098 int i; 1099 1100 ld = sc->nge_ldata; 1101 cd = &sc->nge_cdata; 1102 1103 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1104 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1105 return(ENOBUFS); 1106 if (i == (NGE_RX_LIST_CNT - 1)) { 1107 ld->nge_rx_list[i].nge_nextdesc = 1108 &ld->nge_rx_list[0]; 1109 ld->nge_rx_list[i].nge_next = 1110 vtophys(&ld->nge_rx_list[0]); 1111 } else { 1112 ld->nge_rx_list[i].nge_nextdesc = 1113 &ld->nge_rx_list[i + 1]; 1114 ld->nge_rx_list[i].nge_next = 1115 vtophys(&ld->nge_rx_list[i + 1]); 1116 } 1117 } 1118 1119 cd->nge_rx_prod = 0; 1120 1121 return(0); 1122 } 1123 1124 /* 1125 * Initialize an RX descriptor and attach an MBUF cluster. 1126 */ 1127 static int 1128 nge_newbuf(sc, c, m) 1129 struct nge_softc *sc; 1130 struct nge_desc *c; 1131 struct mbuf *m; 1132 { 1133 struct mbuf *m_new = NULL; 1134 caddr_t *buf = NULL; 1135 1136 if (m == NULL) { 1137 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1138 if (m_new == NULL) { 1139 printf("nge%d: no memory for rx list " 1140 "-- packet dropped!\n", sc->nge_unit); 1141 return(ENOBUFS); 1142 } 1143 1144 /* Allocate the jumbo buffer */ 1145 buf = nge_jalloc(sc); 1146 if (buf == NULL) { 1147 #ifdef NGE_VERBOSE 1148 printf("nge%d: jumbo allocation failed " 1149 "-- packet dropped!\n", sc->nge_unit); 1150 #endif 1151 m_freem(m_new); 1152 return(ENOBUFS); 1153 } 1154 /* Attach the buffer to the mbuf */ 1155 m_new->m_data = (void *)buf; 1156 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1157 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1158 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1159 } else { 1160 m_new = m; 1161 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1162 m_new->m_data = m_new->m_ext.ext_buf; 1163 } 1164 1165 m_adj(m_new, sizeof(u_int64_t)); 1166 1167 c->nge_mbuf = m_new; 1168 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1169 c->nge_ctl = m_new->m_len; 1170 c->nge_extsts = 0; 1171 1172 return(0); 1173 } 1174 1175 static int 1176 nge_alloc_jumbo_mem(sc) 1177 struct nge_softc *sc; 1178 { 1179 caddr_t ptr; 1180 register int i; 1181 struct nge_jpool_entry *entry; 1182 1183 /* Grab a big chunk o' storage. */ 1184 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1185 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1186 1187 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1188 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1189 return(ENOBUFS); 1190 } 1191 1192 SLIST_INIT(&sc->nge_jfree_listhead); 1193 SLIST_INIT(&sc->nge_jinuse_listhead); 1194 1195 /* 1196 * Now divide it up into 9K pieces and save the addresses 1197 * in an array. 1198 */ 1199 ptr = sc->nge_cdata.nge_jumbo_buf; 1200 for (i = 0; i < NGE_JSLOTS; i++) { 1201 sc->nge_cdata.nge_jslots[i] = ptr; 1202 ptr += NGE_JLEN; 1203 entry = malloc(sizeof(struct nge_jpool_entry), 1204 M_DEVBUF, M_NOWAIT); 1205 if (entry == NULL) { 1206 printf("nge%d: no memory for jumbo " 1207 "buffer queue!\n", sc->nge_unit); 1208 return(ENOBUFS); 1209 } 1210 entry->slot = i; 1211 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1212 entry, jpool_entries); 1213 } 1214 1215 return(0); 1216 } 1217 1218 static void 1219 nge_free_jumbo_mem(sc) 1220 struct nge_softc *sc; 1221 { 1222 register int i; 1223 struct nge_jpool_entry *entry; 1224 1225 for (i = 0; i < NGE_JSLOTS; i++) { 1226 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1227 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1228 free(entry, M_DEVBUF); 1229 } 1230 1231 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1232 1233 return; 1234 } 1235 1236 /* 1237 * Allocate a jumbo buffer. 1238 */ 1239 static void * 1240 nge_jalloc(sc) 1241 struct nge_softc *sc; 1242 { 1243 struct nge_jpool_entry *entry; 1244 1245 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1246 1247 if (entry == NULL) { 1248 #ifdef NGE_VERBOSE 1249 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1250 #endif 1251 return(NULL); 1252 } 1253 1254 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1255 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1256 return(sc->nge_cdata.nge_jslots[entry->slot]); 1257 } 1258 1259 /* 1260 * Release a jumbo buffer. 1261 */ 1262 static void 1263 nge_jfree(buf, args) 1264 void *buf; 1265 void *args; 1266 { 1267 struct nge_softc *sc; 1268 int i; 1269 struct nge_jpool_entry *entry; 1270 1271 /* Extract the softc struct pointer. */ 1272 sc = args; 1273 1274 if (sc == NULL) 1275 panic("nge_jfree: can't find softc pointer!"); 1276 1277 /* calculate the slot this buffer belongs to */ 1278 i = ((vm_offset_t)buf 1279 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1280 1281 if ((i < 0) || (i >= NGE_JSLOTS)) 1282 panic("nge_jfree: asked to free buffer that we don't manage!"); 1283 1284 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1285 if (entry == NULL) 1286 panic("nge_jfree: buffer not in use!"); 1287 entry->slot = i; 1288 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1289 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1290 1291 return; 1292 } 1293 /* 1294 * A frame has been uploaded: pass the resulting mbuf chain up to 1295 * the higher level protocols. 1296 */ 1297 static void 1298 nge_rxeof(sc) 1299 struct nge_softc *sc; 1300 { 1301 struct mbuf *m; 1302 struct ifnet *ifp; 1303 struct nge_desc *cur_rx; 1304 int i, total_len = 0; 1305 u_int32_t rxstat; 1306 1307 ifp = &sc->arpcom.ac_if; 1308 i = sc->nge_cdata.nge_rx_prod; 1309 1310 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1311 struct mbuf *m0 = NULL; 1312 u_int32_t extsts; 1313 1314 #ifdef DEVICE_POLLING 1315 if (ifp->if_flags & IFF_POLLING) { 1316 if (sc->rxcycles <= 0) 1317 break; 1318 sc->rxcycles--; 1319 } 1320 #endif /* DEVICE_POLLING */ 1321 1322 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1323 rxstat = cur_rx->nge_rxstat; 1324 extsts = cur_rx->nge_extsts; 1325 m = cur_rx->nge_mbuf; 1326 cur_rx->nge_mbuf = NULL; 1327 total_len = NGE_RXBYTES(cur_rx); 1328 NGE_INC(i, NGE_RX_LIST_CNT); 1329 /* 1330 * If an error occurs, update stats, clear the 1331 * status word and leave the mbuf cluster in place: 1332 * it should simply get re-used next time this descriptor 1333 * comes up in the ring. 1334 */ 1335 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1336 ifp->if_ierrors++; 1337 nge_newbuf(sc, cur_rx, m); 1338 continue; 1339 } 1340 1341 /* 1342 * Ok. NatSemi really screwed up here. This is the 1343 * only gigE chip I know of with alignment constraints 1344 * on receive buffers. RX buffers must be 64-bit aligned. 1345 */ 1346 #ifdef __i386__ 1347 /* 1348 * By popular demand, ignore the alignment problems 1349 * on the Intel x86 platform. The performance hit 1350 * incurred due to unaligned accesses is much smaller 1351 * than the hit produced by forcing buffer copies all 1352 * the time, especially with jumbo frames. We still 1353 * need to fix up the alignment everywhere else though. 1354 */ 1355 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1356 #endif 1357 m0 = m_devget(mtod(m, char *), total_len, 1358 ETHER_ALIGN, ifp, NULL); 1359 nge_newbuf(sc, cur_rx, m); 1360 if (m0 == NULL) { 1361 printf("nge%d: no receive buffers " 1362 "available -- packet dropped!\n", 1363 sc->nge_unit); 1364 ifp->if_ierrors++; 1365 continue; 1366 } 1367 m = m0; 1368 #ifdef __i386__ 1369 } else { 1370 m->m_pkthdr.rcvif = ifp; 1371 m->m_pkthdr.len = m->m_len = total_len; 1372 } 1373 #endif 1374 1375 ifp->if_ipackets++; 1376 1377 /* Do IP checksum checking. */ 1378 if (extsts & NGE_RXEXTSTS_IPPKT) 1379 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1380 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1381 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1382 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1383 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1384 (extsts & NGE_RXEXTSTS_UDPPKT && 1385 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1386 m->m_pkthdr.csum_flags |= 1387 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1388 m->m_pkthdr.csum_data = 0xffff; 1389 } 1390 1391 /* 1392 * If we received a packet with a vlan tag, pass it 1393 * to vlan_input() instead of ether_input(). 1394 */ 1395 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1396 VLAN_INPUT_TAG(ifp, m, 1397 ntohs(extsts & NGE_RXEXTSTS_VTCI), continue); 1398 } 1399 1400 (*ifp->if_input)(ifp, m); 1401 } 1402 1403 sc->nge_cdata.nge_rx_prod = i; 1404 1405 return; 1406 } 1407 1408 /* 1409 * A frame was downloaded to the chip. It's safe for us to clean up 1410 * the list buffers. 1411 */ 1412 1413 static void 1414 nge_txeof(sc) 1415 struct nge_softc *sc; 1416 { 1417 struct nge_desc *cur_tx; 1418 struct ifnet *ifp; 1419 u_int32_t idx; 1420 1421 ifp = &sc->arpcom.ac_if; 1422 1423 /* 1424 * Go through our tx list and free mbufs for those 1425 * frames that have been transmitted. 1426 */ 1427 idx = sc->nge_cdata.nge_tx_cons; 1428 while (idx != sc->nge_cdata.nge_tx_prod) { 1429 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1430 1431 if (NGE_OWNDESC(cur_tx)) 1432 break; 1433 1434 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1435 sc->nge_cdata.nge_tx_cnt--; 1436 NGE_INC(idx, NGE_TX_LIST_CNT); 1437 continue; 1438 } 1439 1440 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1441 ifp->if_oerrors++; 1442 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1443 ifp->if_collisions++; 1444 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1445 ifp->if_collisions++; 1446 } 1447 1448 ifp->if_collisions += 1449 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1450 1451 ifp->if_opackets++; 1452 if (cur_tx->nge_mbuf != NULL) { 1453 m_freem(cur_tx->nge_mbuf); 1454 cur_tx->nge_mbuf = NULL; 1455 ifp->if_flags &= ~IFF_OACTIVE; 1456 } 1457 1458 sc->nge_cdata.nge_tx_cnt--; 1459 NGE_INC(idx, NGE_TX_LIST_CNT); 1460 } 1461 1462 sc->nge_cdata.nge_tx_cons = idx; 1463 1464 if (idx == sc->nge_cdata.nge_tx_prod) 1465 ifp->if_timer = 0; 1466 1467 return; 1468 } 1469 1470 static void 1471 nge_tick(xsc) 1472 void *xsc; 1473 { 1474 struct nge_softc *sc; 1475 struct mii_data *mii; 1476 struct ifnet *ifp; 1477 int s; 1478 1479 s = splimp(); 1480 1481 sc = xsc; 1482 ifp = &sc->arpcom.ac_if; 1483 1484 if (sc->nge_tbi) { 1485 if (!sc->nge_link) { 1486 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1487 & NGE_TBIBMSR_ANEG_DONE) { 1488 printf("nge%d: gigabit link up\n", 1489 sc->nge_unit); 1490 nge_miibus_statchg(sc->nge_miibus); 1491 sc->nge_link++; 1492 if (ifp->if_snd.ifq_head != NULL) 1493 nge_start(ifp); 1494 } 1495 } 1496 } else { 1497 mii = device_get_softc(sc->nge_miibus); 1498 mii_tick(mii); 1499 1500 if (!sc->nge_link) { 1501 if (mii->mii_media_status & IFM_ACTIVE && 1502 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1503 sc->nge_link++; 1504 if (IFM_SUBTYPE(mii->mii_media_active) 1505 == IFM_1000_T) 1506 printf("nge%d: gigabit link up\n", 1507 sc->nge_unit); 1508 if (ifp->if_snd.ifq_head != NULL) 1509 nge_start(ifp); 1510 } 1511 } 1512 } 1513 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1514 1515 splx(s); 1516 1517 return; 1518 } 1519 1520 #ifdef DEVICE_POLLING 1521 static poll_handler_t nge_poll; 1522 1523 static void 1524 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1525 { 1526 struct nge_softc *sc = ifp->if_softc; 1527 1528 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1529 ether_poll_deregister(ifp); 1530 cmd = POLL_DEREGISTER; 1531 } 1532 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1533 CSR_WRITE_4(sc, NGE_IER, 1); 1534 return; 1535 } 1536 1537 /* 1538 * On the nge, reading the status register also clears it. 1539 * So before returning to intr mode we must make sure that all 1540 * possible pending sources of interrupts have been served. 1541 * In practice this means run to completion the *eof routines, 1542 * and then call the interrupt routine 1543 */ 1544 sc->rxcycles = count; 1545 nge_rxeof(sc); 1546 nge_txeof(sc); 1547 if (ifp->if_snd.ifq_head != NULL) 1548 nge_start(ifp); 1549 1550 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1551 u_int32_t status; 1552 1553 /* Reading the ISR register clears all interrupts. */ 1554 status = CSR_READ_4(sc, NGE_ISR); 1555 1556 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1557 nge_rxeof(sc); 1558 1559 if (status & (NGE_ISR_RX_IDLE)) 1560 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1561 1562 if (status & NGE_ISR_SYSERR) { 1563 nge_reset(sc); 1564 nge_init(sc); 1565 } 1566 } 1567 } 1568 #endif /* DEVICE_POLLING */ 1569 1570 static void 1571 nge_intr(arg) 1572 void *arg; 1573 { 1574 struct nge_softc *sc; 1575 struct ifnet *ifp; 1576 u_int32_t status; 1577 1578 sc = arg; 1579 ifp = &sc->arpcom.ac_if; 1580 1581 #ifdef DEVICE_POLLING 1582 if (ifp->if_flags & IFF_POLLING) 1583 return; 1584 if ((ifp->if_capenable & IFCAP_POLLING) && 1585 ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1586 CSR_WRITE_4(sc, NGE_IER, 0); 1587 nge_poll(ifp, 0, 1); 1588 return; 1589 } 1590 #endif /* DEVICE_POLLING */ 1591 1592 /* Supress unwanted interrupts */ 1593 if (!(ifp->if_flags & IFF_UP)) { 1594 nge_stop(sc); 1595 return; 1596 } 1597 1598 /* Disable interrupts. */ 1599 CSR_WRITE_4(sc, NGE_IER, 0); 1600 1601 /* Data LED on for TBI mode */ 1602 if(sc->nge_tbi) 1603 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1604 | NGE_GPIO_GP3_OUT); 1605 1606 for (;;) { 1607 /* Reading the ISR register clears all interrupts. */ 1608 status = CSR_READ_4(sc, NGE_ISR); 1609 1610 if ((status & NGE_INTRS) == 0) 1611 break; 1612 1613 if ((status & NGE_ISR_TX_DESC_OK) || 1614 (status & NGE_ISR_TX_ERR) || 1615 (status & NGE_ISR_TX_OK) || 1616 (status & NGE_ISR_TX_IDLE)) 1617 nge_txeof(sc); 1618 1619 if ((status & NGE_ISR_RX_DESC_OK) || 1620 (status & NGE_ISR_RX_ERR) || 1621 (status & NGE_ISR_RX_OFLOW) || 1622 (status & NGE_ISR_RX_FIFO_OFLOW) || 1623 (status & NGE_ISR_RX_IDLE) || 1624 (status & NGE_ISR_RX_OK)) 1625 nge_rxeof(sc); 1626 1627 if ((status & NGE_ISR_RX_IDLE)) 1628 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1629 1630 if (status & NGE_ISR_SYSERR) { 1631 nge_reset(sc); 1632 ifp->if_flags &= ~IFF_RUNNING; 1633 nge_init(sc); 1634 } 1635 1636 #if 0 1637 /* 1638 * XXX: nge_tick() is not ready to be called this way 1639 * it screws up the aneg timeout because mii_tick() is 1640 * only to be called once per second. 1641 */ 1642 if (status & NGE_IMR_PHY_INTR) { 1643 sc->nge_link = 0; 1644 nge_tick(sc); 1645 } 1646 #endif 1647 } 1648 1649 /* Re-enable interrupts. */ 1650 CSR_WRITE_4(sc, NGE_IER, 1); 1651 1652 if (ifp->if_snd.ifq_head != NULL) 1653 nge_start(ifp); 1654 1655 /* Data LED off for TBI mode */ 1656 1657 if(sc->nge_tbi) 1658 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1659 & ~NGE_GPIO_GP3_OUT); 1660 1661 return; 1662 } 1663 1664 /* 1665 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1666 * pointers to the fragment pointers. 1667 */ 1668 static int 1669 nge_encap(sc, m_head, txidx) 1670 struct nge_softc *sc; 1671 struct mbuf *m_head; 1672 u_int32_t *txidx; 1673 { 1674 struct nge_desc *f = NULL; 1675 struct mbuf *m; 1676 int frag, cur, cnt = 0; 1677 struct m_tag *mtag; 1678 1679 /* 1680 * Start packing the mbufs in this chain into 1681 * the fragment pointers. Stop when we run out 1682 * of fragments or hit the end of the mbuf chain. 1683 */ 1684 m = m_head; 1685 cur = frag = *txidx; 1686 1687 for (m = m_head; m != NULL; m = m->m_next) { 1688 if (m->m_len != 0) { 1689 if ((NGE_TX_LIST_CNT - 1690 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1691 return(ENOBUFS); 1692 f = &sc->nge_ldata->nge_tx_list[frag]; 1693 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1694 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1695 if (cnt != 0) 1696 f->nge_ctl |= NGE_CMDSTS_OWN; 1697 cur = frag; 1698 NGE_INC(frag, NGE_TX_LIST_CNT); 1699 cnt++; 1700 } 1701 } 1702 1703 if (m != NULL) 1704 return(ENOBUFS); 1705 1706 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1707 if (m_head->m_pkthdr.csum_flags) { 1708 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1709 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1710 NGE_TXEXTSTS_IPCSUM; 1711 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1712 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1713 NGE_TXEXTSTS_TCPCSUM; 1714 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1715 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1716 NGE_TXEXTSTS_UDPCSUM; 1717 } 1718 1719 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 1720 if (mtag != NULL) { 1721 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1722 (NGE_TXEXTSTS_VLANPKT|htons(VLAN_TAG_VALUE(mtag))); 1723 } 1724 1725 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1726 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1727 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1728 sc->nge_cdata.nge_tx_cnt += cnt; 1729 *txidx = frag; 1730 1731 return(0); 1732 } 1733 1734 /* 1735 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1736 * to the mbuf data regions directly in the transmit lists. We also save a 1737 * copy of the pointers since the transmit list fragment pointers are 1738 * physical addresses. 1739 */ 1740 1741 static void 1742 nge_start(ifp) 1743 struct ifnet *ifp; 1744 { 1745 struct nge_softc *sc; 1746 struct mbuf *m_head = NULL; 1747 u_int32_t idx; 1748 1749 sc = ifp->if_softc; 1750 1751 if (!sc->nge_link) 1752 return; 1753 1754 idx = sc->nge_cdata.nge_tx_prod; 1755 1756 if (ifp->if_flags & IFF_OACTIVE) 1757 return; 1758 1759 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1760 IF_DEQUEUE(&ifp->if_snd, m_head); 1761 if (m_head == NULL) 1762 break; 1763 1764 if (nge_encap(sc, m_head, &idx)) { 1765 IF_PREPEND(&ifp->if_snd, m_head); 1766 ifp->if_flags |= IFF_OACTIVE; 1767 break; 1768 } 1769 1770 /* 1771 * If there's a BPF listener, bounce a copy of this frame 1772 * to him. 1773 */ 1774 BPF_MTAP(ifp, m_head); 1775 1776 } 1777 1778 /* Transmit */ 1779 sc->nge_cdata.nge_tx_prod = idx; 1780 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1781 1782 /* 1783 * Set a timeout in case the chip goes out to lunch. 1784 */ 1785 ifp->if_timer = 5; 1786 1787 return; 1788 } 1789 1790 static void 1791 nge_init(xsc) 1792 void *xsc; 1793 { 1794 struct nge_softc *sc = xsc; 1795 struct ifnet *ifp = &sc->arpcom.ac_if; 1796 struct mii_data *mii; 1797 int s; 1798 1799 if (ifp->if_flags & IFF_RUNNING) 1800 return; 1801 1802 s = splimp(); 1803 1804 /* 1805 * Cancel pending I/O and free all RX/TX buffers. 1806 */ 1807 nge_stop(sc); 1808 1809 if (sc->nge_tbi) { 1810 mii = NULL; 1811 } else { 1812 mii = device_get_softc(sc->nge_miibus); 1813 } 1814 1815 /* Set MAC address */ 1816 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1817 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1818 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1819 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1820 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1821 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1822 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1823 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1824 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1825 1826 /* Init circular RX list. */ 1827 if (nge_list_rx_init(sc) == ENOBUFS) { 1828 printf("nge%d: initialization failed: no " 1829 "memory for rx buffers\n", sc->nge_unit); 1830 nge_stop(sc); 1831 (void)splx(s); 1832 return; 1833 } 1834 1835 /* 1836 * Init tx descriptors. 1837 */ 1838 nge_list_tx_init(sc); 1839 1840 /* 1841 * For the NatSemi chip, we have to explicitly enable the 1842 * reception of ARP frames, as well as turn on the 'perfect 1843 * match' filter where we store the station address, otherwise 1844 * we won't receive unicasts meant for this host. 1845 */ 1846 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1847 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1848 1849 /* If we want promiscuous mode, set the allframes bit. */ 1850 if (ifp->if_flags & IFF_PROMISC) { 1851 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1852 } else { 1853 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1854 } 1855 1856 /* 1857 * Set the capture broadcast bit to capture broadcast frames. 1858 */ 1859 if (ifp->if_flags & IFF_BROADCAST) { 1860 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1861 } else { 1862 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1863 } 1864 1865 /* 1866 * Load the multicast filter. 1867 */ 1868 nge_setmulti(sc); 1869 1870 /* Turn the receive filter on */ 1871 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1872 1873 /* 1874 * Load the address of the RX and TX lists. 1875 */ 1876 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1877 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1878 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1879 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1880 1881 /* Set RX configuration */ 1882 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1883 /* 1884 * Enable hardware checksum validation for all IPv4 1885 * packets, do not reject packets with bad checksums. 1886 */ 1887 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1888 1889 /* 1890 * Tell the chip to detect and strip VLAN tag info from 1891 * received frames. The tag will be provided in the extsts 1892 * field in the RX descriptors. 1893 */ 1894 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1895 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1896 1897 /* Set TX configuration */ 1898 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1899 1900 /* 1901 * Enable TX IPv4 checksumming on a per-packet basis. 1902 */ 1903 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1904 1905 /* 1906 * Tell the chip to insert VLAN tags on a per-packet basis as 1907 * dictated by the code in the frame encapsulation routine. 1908 */ 1909 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1910 1911 /* Set full/half duplex mode. */ 1912 if (sc->nge_tbi) { 1913 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1914 == IFM_FDX) { 1915 NGE_SETBIT(sc, NGE_TX_CFG, 1916 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1917 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1918 } else { 1919 NGE_CLRBIT(sc, NGE_TX_CFG, 1920 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1921 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1922 } 1923 } else { 1924 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1925 NGE_SETBIT(sc, NGE_TX_CFG, 1926 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1927 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1928 } else { 1929 NGE_CLRBIT(sc, NGE_TX_CFG, 1930 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1931 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1932 } 1933 } 1934 1935 nge_tick(sc); 1936 1937 /* 1938 * Enable the delivery of PHY interrupts based on 1939 * link/speed/duplex status changes. Also enable the 1940 * extsts field in the DMA descriptors (needed for 1941 * TCP/IP checksum offload on transmit). 1942 */ 1943 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1944 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1945 1946 /* 1947 * Configure interrupt holdoff (moderation). We can 1948 * have the chip delay interrupt delivery for a certain 1949 * period. Units are in 100us, and the max setting 1950 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1951 */ 1952 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1953 1954 /* 1955 * Enable interrupts. 1956 */ 1957 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1958 #ifdef DEVICE_POLLING 1959 /* 1960 * ... only enable interrupts if we are not polling, make sure 1961 * they are off otherwise. 1962 */ 1963 if (ifp->if_flags & IFF_POLLING) 1964 CSR_WRITE_4(sc, NGE_IER, 0); 1965 else 1966 #endif /* DEVICE_POLLING */ 1967 CSR_WRITE_4(sc, NGE_IER, 1); 1968 1969 /* Enable receiver and transmitter. */ 1970 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1971 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1972 1973 nge_ifmedia_upd(ifp); 1974 1975 ifp->if_flags |= IFF_RUNNING; 1976 ifp->if_flags &= ~IFF_OACTIVE; 1977 1978 (void)splx(s); 1979 1980 return; 1981 } 1982 1983 /* 1984 * Set media options. 1985 */ 1986 static int 1987 nge_ifmedia_upd(ifp) 1988 struct ifnet *ifp; 1989 { 1990 struct nge_softc *sc; 1991 struct mii_data *mii; 1992 1993 sc = ifp->if_softc; 1994 1995 if (sc->nge_tbi) { 1996 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1997 == IFM_AUTO) { 1998 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1999 CSR_READ_4(sc, NGE_TBI_ANAR) 2000 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 2001 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 2002 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 2003 | NGE_TBIBMCR_RESTART_ANEG); 2004 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 2005 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 2006 & IFM_GMASK) == IFM_FDX) { 2007 NGE_SETBIT(sc, NGE_TX_CFG, 2008 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2009 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2010 2011 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2012 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2013 } else { 2014 NGE_CLRBIT(sc, NGE_TX_CFG, 2015 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2016 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2017 2018 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2019 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2020 } 2021 2022 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 2023 & ~NGE_GPIO_GP3_OUT); 2024 } else { 2025 mii = device_get_softc(sc->nge_miibus); 2026 sc->nge_link = 0; 2027 if (mii->mii_instance) { 2028 struct mii_softc *miisc; 2029 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2030 miisc = LIST_NEXT(miisc, mii_list)) 2031 mii_phy_reset(miisc); 2032 } 2033 mii_mediachg(mii); 2034 } 2035 2036 return(0); 2037 } 2038 2039 /* 2040 * Report current media status. 2041 */ 2042 static void 2043 nge_ifmedia_sts(ifp, ifmr) 2044 struct ifnet *ifp; 2045 struct ifmediareq *ifmr; 2046 { 2047 struct nge_softc *sc; 2048 struct mii_data *mii; 2049 2050 sc = ifp->if_softc; 2051 2052 if (sc->nge_tbi) { 2053 ifmr->ifm_status = IFM_AVALID; 2054 ifmr->ifm_active = IFM_ETHER; 2055 2056 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2057 ifmr->ifm_status |= IFM_ACTIVE; 2058 } 2059 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2060 ifmr->ifm_active |= IFM_LOOP; 2061 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2062 ifmr->ifm_active |= IFM_NONE; 2063 ifmr->ifm_status = 0; 2064 return; 2065 } 2066 ifmr->ifm_active |= IFM_1000_SX; 2067 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2068 == IFM_AUTO) { 2069 ifmr->ifm_active |= IFM_AUTO; 2070 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2071 & NGE_TBIANAR_FDX) { 2072 ifmr->ifm_active |= IFM_FDX; 2073 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2074 & NGE_TBIANAR_HDX) { 2075 ifmr->ifm_active |= IFM_HDX; 2076 } 2077 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2078 == IFM_FDX) 2079 ifmr->ifm_active |= IFM_FDX; 2080 else 2081 ifmr->ifm_active |= IFM_HDX; 2082 2083 } else { 2084 mii = device_get_softc(sc->nge_miibus); 2085 mii_pollstat(mii); 2086 ifmr->ifm_active = mii->mii_media_active; 2087 ifmr->ifm_status = mii->mii_media_status; 2088 } 2089 2090 return; 2091 } 2092 2093 static int 2094 nge_ioctl(ifp, command, data) 2095 struct ifnet *ifp; 2096 u_long command; 2097 caddr_t data; 2098 { 2099 struct nge_softc *sc = ifp->if_softc; 2100 struct ifreq *ifr = (struct ifreq *) data; 2101 struct mii_data *mii; 2102 int s, error = 0; 2103 2104 s = splimp(); 2105 2106 switch(command) { 2107 case SIOCSIFMTU: 2108 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2109 error = EINVAL; 2110 else { 2111 ifp->if_mtu = ifr->ifr_mtu; 2112 /* 2113 * Workaround: if the MTU is larger than 2114 * 8152 (TX FIFO size minus 64 minus 18), turn off 2115 * TX checksum offloading. 2116 */ 2117 if (ifr->ifr_mtu >= 8152) { 2118 ifp->if_capenable &= ~IFCAP_TXCSUM; 2119 ifp->if_hwassist = 0; 2120 } else { 2121 ifp->if_capenable |= IFCAP_TXCSUM; 2122 ifp->if_hwassist = NGE_CSUM_FEATURES; 2123 } 2124 } 2125 break; 2126 case SIOCSIFFLAGS: 2127 if (ifp->if_flags & IFF_UP) { 2128 if (ifp->if_flags & IFF_RUNNING && 2129 ifp->if_flags & IFF_PROMISC && 2130 !(sc->nge_if_flags & IFF_PROMISC)) { 2131 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2132 NGE_RXFILTCTL_ALLPHYS| 2133 NGE_RXFILTCTL_ALLMULTI); 2134 } else if (ifp->if_flags & IFF_RUNNING && 2135 !(ifp->if_flags & IFF_PROMISC) && 2136 sc->nge_if_flags & IFF_PROMISC) { 2137 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2138 NGE_RXFILTCTL_ALLPHYS); 2139 if (!(ifp->if_flags & IFF_ALLMULTI)) 2140 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2141 NGE_RXFILTCTL_ALLMULTI); 2142 } else { 2143 ifp->if_flags &= ~IFF_RUNNING; 2144 nge_init(sc); 2145 } 2146 } else { 2147 if (ifp->if_flags & IFF_RUNNING) 2148 nge_stop(sc); 2149 } 2150 sc->nge_if_flags = ifp->if_flags; 2151 error = 0; 2152 break; 2153 case SIOCADDMULTI: 2154 case SIOCDELMULTI: 2155 nge_setmulti(sc); 2156 error = 0; 2157 break; 2158 case SIOCGIFMEDIA: 2159 case SIOCSIFMEDIA: 2160 if (sc->nge_tbi) { 2161 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2162 command); 2163 } else { 2164 mii = device_get_softc(sc->nge_miibus); 2165 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2166 command); 2167 } 2168 break; 2169 case SIOCSIFCAP: 2170 ifp->if_capenable &= ~IFCAP_POLLING; 2171 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2172 break; 2173 default: 2174 error = ether_ioctl(ifp, command, data); 2175 break; 2176 } 2177 2178 (void)splx(s); 2179 2180 return(error); 2181 } 2182 2183 static void 2184 nge_watchdog(ifp) 2185 struct ifnet *ifp; 2186 { 2187 struct nge_softc *sc; 2188 2189 sc = ifp->if_softc; 2190 2191 ifp->if_oerrors++; 2192 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2193 2194 nge_stop(sc); 2195 nge_reset(sc); 2196 ifp->if_flags &= ~IFF_RUNNING; 2197 nge_init(sc); 2198 2199 if (ifp->if_snd.ifq_head != NULL) 2200 nge_start(ifp); 2201 2202 return; 2203 } 2204 2205 /* 2206 * Stop the adapter and free any mbufs allocated to the 2207 * RX and TX lists. 2208 */ 2209 static void 2210 nge_stop(sc) 2211 struct nge_softc *sc; 2212 { 2213 register int i; 2214 struct ifnet *ifp; 2215 struct mii_data *mii; 2216 2217 ifp = &sc->arpcom.ac_if; 2218 ifp->if_timer = 0; 2219 if (sc->nge_tbi) { 2220 mii = NULL; 2221 } else { 2222 mii = device_get_softc(sc->nge_miibus); 2223 } 2224 2225 untimeout(nge_tick, sc, sc->nge_stat_ch); 2226 #ifdef DEVICE_POLLING 2227 ether_poll_deregister(ifp); 2228 #endif 2229 CSR_WRITE_4(sc, NGE_IER, 0); 2230 CSR_WRITE_4(sc, NGE_IMR, 0); 2231 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2232 DELAY(1000); 2233 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2234 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2235 2236 if (!sc->nge_tbi) 2237 mii_down(mii); 2238 2239 sc->nge_link = 0; 2240 2241 /* 2242 * Free data in the RX lists. 2243 */ 2244 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2245 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2246 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2247 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2248 } 2249 } 2250 bzero((char *)&sc->nge_ldata->nge_rx_list, 2251 sizeof(sc->nge_ldata->nge_rx_list)); 2252 2253 /* 2254 * Free the TX list buffers. 2255 */ 2256 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2257 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2258 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2259 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2260 } 2261 } 2262 2263 bzero((char *)&sc->nge_ldata->nge_tx_list, 2264 sizeof(sc->nge_ldata->nge_tx_list)); 2265 2266 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2267 2268 return; 2269 } 2270 2271 /* 2272 * Stop all chip I/O so that the kernel's probe routines don't 2273 * get confused by errant DMAs when rebooting. 2274 */ 2275 static void 2276 nge_shutdown(dev) 2277 device_t dev; 2278 { 2279 struct nge_softc *sc; 2280 2281 sc = device_get_softc(dev); 2282 2283 nge_reset(sc); 2284 nge_stop(sc); 2285 2286 return; 2287 } 2288