1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/module.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 100 #include <net/if.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_types.h> 106 #include <net/if_vlan_var.h> 107 108 #include <net/bpf.h> 109 110 #include <vm/vm.h> /* for vtophys */ 111 #include <vm/pmap.h> /* for vtophys */ 112 #include <machine/clock.h> /* for DELAY */ 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 124 #define NGE_USEIOSPACE 125 126 #include <dev/nge/if_ngereg.h> 127 128 MODULE_DEPEND(nge, pci, 1, 1, 1); 129 MODULE_DEPEND(nge, ether, 1, 1, 1); 130 MODULE_DEPEND(nge, miibus, 1, 1, 1); 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 136 137 /* 138 * Various supported device vendors/types and their names. 139 */ 140 static struct nge_type nge_devs[] = { 141 { NGE_VENDORID, NGE_DEVICEID, 142 "National Semiconductor Gigabit Ethernet" }, 143 { 0, 0, NULL } 144 }; 145 146 static int nge_probe(device_t); 147 static int nge_attach(device_t); 148 static int nge_detach(device_t); 149 150 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *); 151 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 152 #ifdef NGE_FIXUP_RX 153 static __inline void nge_fixup_rx (struct mbuf *); 154 #endif 155 static void nge_rxeof(struct nge_softc *); 156 static void nge_txeof(struct nge_softc *); 157 static void nge_intr(void *); 158 static void nge_tick(void *); 159 static void nge_tick_locked(struct nge_softc *); 160 static void nge_start(struct ifnet *); 161 static void nge_start_locked(struct ifnet *); 162 static int nge_ioctl(struct ifnet *, u_long, caddr_t); 163 static void nge_init(void *); 164 static void nge_init_locked(struct nge_softc *); 165 static void nge_stop(struct nge_softc *); 166 static void nge_watchdog(struct ifnet *); 167 static void nge_shutdown(device_t); 168 static int nge_ifmedia_upd(struct ifnet *); 169 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 170 171 static void nge_delay(struct nge_softc *); 172 static void nge_eeprom_idle(struct nge_softc *); 173 static void nge_eeprom_putbyte(struct nge_softc *, int); 174 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 175 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 176 177 static void nge_mii_sync(struct nge_softc *); 178 static void nge_mii_send(struct nge_softc *, u_int32_t, int); 179 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 180 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 181 182 static int nge_miibus_readreg(device_t, int, int); 183 static int nge_miibus_writereg(device_t, int, int, int); 184 static void nge_miibus_statchg(device_t); 185 186 static void nge_setmulti(struct nge_softc *); 187 static void nge_reset(struct nge_softc *); 188 static int nge_list_rx_init(struct nge_softc *); 189 static int nge_list_tx_init(struct nge_softc *); 190 191 #ifdef NGE_USEIOSPACE 192 #define NGE_RES SYS_RES_IOPORT 193 #define NGE_RID NGE_PCI_LOIO 194 #else 195 #define NGE_RES SYS_RES_MEMORY 196 #define NGE_RID NGE_PCI_LOMEM 197 #endif 198 199 static device_method_t nge_methods[] = { 200 /* Device interface */ 201 DEVMETHOD(device_probe, nge_probe), 202 DEVMETHOD(device_attach, nge_attach), 203 DEVMETHOD(device_detach, nge_detach), 204 DEVMETHOD(device_shutdown, nge_shutdown), 205 206 /* bus interface */ 207 DEVMETHOD(bus_print_child, bus_generic_print_child), 208 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 209 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 212 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 213 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 214 215 { 0, 0 } 216 }; 217 218 static driver_t nge_driver = { 219 "nge", 220 nge_methods, 221 sizeof(struct nge_softc) 222 }; 223 224 static devclass_t nge_devclass; 225 226 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 227 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 228 229 #define NGE_SETBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) | (x)) 232 233 #define NGE_CLRBIT(sc, reg, x) \ 234 CSR_WRITE_4(sc, reg, \ 235 CSR_READ_4(sc, reg) & ~(x)) 236 237 #define SIO_SET(x) \ 238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 239 240 #define SIO_CLR(x) \ 241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 242 243 static void 244 nge_delay(sc) 245 struct nge_softc *sc; 246 { 247 int idx; 248 249 for (idx = (300 / 33) + 1; idx > 0; idx--) 250 CSR_READ_4(sc, NGE_CSR); 251 252 return; 253 } 254 255 static void 256 nge_eeprom_idle(sc) 257 struct nge_softc *sc; 258 { 259 register int i; 260 261 SIO_SET(NGE_MEAR_EE_CSEL); 262 nge_delay(sc); 263 SIO_SET(NGE_MEAR_EE_CLK); 264 nge_delay(sc); 265 266 for (i = 0; i < 25; i++) { 267 SIO_CLR(NGE_MEAR_EE_CLK); 268 nge_delay(sc); 269 SIO_SET(NGE_MEAR_EE_CLK); 270 nge_delay(sc); 271 } 272 273 SIO_CLR(NGE_MEAR_EE_CLK); 274 nge_delay(sc); 275 SIO_CLR(NGE_MEAR_EE_CSEL); 276 nge_delay(sc); 277 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 278 279 return; 280 } 281 282 /* 283 * Send a read command and address to the EEPROM, check for ACK. 284 */ 285 static void 286 nge_eeprom_putbyte(sc, addr) 287 struct nge_softc *sc; 288 int addr; 289 { 290 register int d, i; 291 292 d = addr | NGE_EECMD_READ; 293 294 /* 295 * Feed in each bit and stobe the clock. 296 */ 297 for (i = 0x400; i; i >>= 1) { 298 if (d & i) { 299 SIO_SET(NGE_MEAR_EE_DIN); 300 } else { 301 SIO_CLR(NGE_MEAR_EE_DIN); 302 } 303 nge_delay(sc); 304 SIO_SET(NGE_MEAR_EE_CLK); 305 nge_delay(sc); 306 SIO_CLR(NGE_MEAR_EE_CLK); 307 nge_delay(sc); 308 } 309 310 return; 311 } 312 313 /* 314 * Read a word of data stored in the EEPROM at address 'addr.' 315 */ 316 static void 317 nge_eeprom_getword(sc, addr, dest) 318 struct nge_softc *sc; 319 int addr; 320 u_int16_t *dest; 321 { 322 register int i; 323 u_int16_t word = 0; 324 325 /* Force EEPROM to idle state. */ 326 nge_eeprom_idle(sc); 327 328 /* Enter EEPROM access mode. */ 329 nge_delay(sc); 330 SIO_CLR(NGE_MEAR_EE_CLK); 331 nge_delay(sc); 332 SIO_SET(NGE_MEAR_EE_CSEL); 333 nge_delay(sc); 334 335 /* 336 * Send address of word we want to read. 337 */ 338 nge_eeprom_putbyte(sc, addr); 339 340 /* 341 * Start reading bits from EEPROM. 342 */ 343 for (i = 0x8000; i; i >>= 1) { 344 SIO_SET(NGE_MEAR_EE_CLK); 345 nge_delay(sc); 346 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 347 word |= i; 348 nge_delay(sc); 349 SIO_CLR(NGE_MEAR_EE_CLK); 350 nge_delay(sc); 351 } 352 353 /* Turn off EEPROM access mode. */ 354 nge_eeprom_idle(sc); 355 356 *dest = word; 357 358 return; 359 } 360 361 /* 362 * Read a sequence of words from the EEPROM. 363 */ 364 static void 365 nge_read_eeprom(sc, dest, off, cnt, swap) 366 struct nge_softc *sc; 367 caddr_t dest; 368 int off; 369 int cnt; 370 int swap; 371 { 372 int i; 373 u_int16_t word = 0, *ptr; 374 375 for (i = 0; i < cnt; i++) { 376 nge_eeprom_getword(sc, off + i, &word); 377 ptr = (u_int16_t *)(dest + (i * 2)); 378 if (swap) 379 *ptr = ntohs(word); 380 else 381 *ptr = word; 382 } 383 384 return; 385 } 386 387 /* 388 * Sync the PHYs by setting data bit and strobing the clock 32 times. 389 */ 390 static void 391 nge_mii_sync(sc) 392 struct nge_softc *sc; 393 { 394 register int i; 395 396 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 397 398 for (i = 0; i < 32; i++) { 399 SIO_SET(NGE_MEAR_MII_CLK); 400 DELAY(1); 401 SIO_CLR(NGE_MEAR_MII_CLK); 402 DELAY(1); 403 } 404 405 return; 406 } 407 408 /* 409 * Clock a series of bits through the MII. 410 */ 411 static void 412 nge_mii_send(sc, bits, cnt) 413 struct nge_softc *sc; 414 u_int32_t bits; 415 int cnt; 416 { 417 int i; 418 419 SIO_CLR(NGE_MEAR_MII_CLK); 420 421 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 422 if (bits & i) { 423 SIO_SET(NGE_MEAR_MII_DATA); 424 } else { 425 SIO_CLR(NGE_MEAR_MII_DATA); 426 } 427 DELAY(1); 428 SIO_CLR(NGE_MEAR_MII_CLK); 429 DELAY(1); 430 SIO_SET(NGE_MEAR_MII_CLK); 431 } 432 } 433 434 /* 435 * Read an PHY register through the MII. 436 */ 437 static int 438 nge_mii_readreg(sc, frame) 439 struct nge_softc *sc; 440 struct nge_mii_frame *frame; 441 442 { 443 int i, ack; 444 445 /* 446 * Set up frame for RX. 447 */ 448 frame->mii_stdelim = NGE_MII_STARTDELIM; 449 frame->mii_opcode = NGE_MII_READOP; 450 frame->mii_turnaround = 0; 451 frame->mii_data = 0; 452 453 CSR_WRITE_4(sc, NGE_MEAR, 0); 454 455 /* 456 * Turn on data xmit. 457 */ 458 SIO_SET(NGE_MEAR_MII_DIR); 459 460 nge_mii_sync(sc); 461 462 /* 463 * Send command/address info. 464 */ 465 nge_mii_send(sc, frame->mii_stdelim, 2); 466 nge_mii_send(sc, frame->mii_opcode, 2); 467 nge_mii_send(sc, frame->mii_phyaddr, 5); 468 nge_mii_send(sc, frame->mii_regaddr, 5); 469 470 /* Idle bit */ 471 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 472 DELAY(1); 473 SIO_SET(NGE_MEAR_MII_CLK); 474 DELAY(1); 475 476 /* Turn off xmit. */ 477 SIO_CLR(NGE_MEAR_MII_DIR); 478 /* Check for ack */ 479 SIO_CLR(NGE_MEAR_MII_CLK); 480 DELAY(1); 481 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 482 SIO_SET(NGE_MEAR_MII_CLK); 483 DELAY(1); 484 485 /* 486 * Now try reading data bits. If the ack failed, we still 487 * need to clock through 16 cycles to keep the PHY(s) in sync. 488 */ 489 if (ack) { 490 for(i = 0; i < 16; i++) { 491 SIO_CLR(NGE_MEAR_MII_CLK); 492 DELAY(1); 493 SIO_SET(NGE_MEAR_MII_CLK); 494 DELAY(1); 495 } 496 goto fail; 497 } 498 499 for (i = 0x8000; i; i >>= 1) { 500 SIO_CLR(NGE_MEAR_MII_CLK); 501 DELAY(1); 502 if (!ack) { 503 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 504 frame->mii_data |= i; 505 DELAY(1); 506 } 507 SIO_SET(NGE_MEAR_MII_CLK); 508 DELAY(1); 509 } 510 511 fail: 512 513 SIO_CLR(NGE_MEAR_MII_CLK); 514 DELAY(1); 515 SIO_SET(NGE_MEAR_MII_CLK); 516 DELAY(1); 517 518 if (ack) 519 return(1); 520 return(0); 521 } 522 523 /* 524 * Write to a PHY register through the MII. 525 */ 526 static int 527 nge_mii_writereg(sc, frame) 528 struct nge_softc *sc; 529 struct nge_mii_frame *frame; 530 531 { 532 533 /* 534 * Set up frame for TX. 535 */ 536 537 frame->mii_stdelim = NGE_MII_STARTDELIM; 538 frame->mii_opcode = NGE_MII_WRITEOP; 539 frame->mii_turnaround = NGE_MII_TURNAROUND; 540 541 /* 542 * Turn on data output. 543 */ 544 SIO_SET(NGE_MEAR_MII_DIR); 545 546 nge_mii_sync(sc); 547 548 nge_mii_send(sc, frame->mii_stdelim, 2); 549 nge_mii_send(sc, frame->mii_opcode, 2); 550 nge_mii_send(sc, frame->mii_phyaddr, 5); 551 nge_mii_send(sc, frame->mii_regaddr, 5); 552 nge_mii_send(sc, frame->mii_turnaround, 2); 553 nge_mii_send(sc, frame->mii_data, 16); 554 555 /* Idle bit. */ 556 SIO_SET(NGE_MEAR_MII_CLK); 557 DELAY(1); 558 SIO_CLR(NGE_MEAR_MII_CLK); 559 DELAY(1); 560 561 /* 562 * Turn off xmit. 563 */ 564 SIO_CLR(NGE_MEAR_MII_DIR); 565 566 return(0); 567 } 568 569 static int 570 nge_miibus_readreg(dev, phy, reg) 571 device_t dev; 572 int phy, reg; 573 { 574 struct nge_softc *sc; 575 struct nge_mii_frame frame; 576 577 sc = device_get_softc(dev); 578 579 bzero((char *)&frame, sizeof(frame)); 580 581 frame.mii_phyaddr = phy; 582 frame.mii_regaddr = reg; 583 nge_mii_readreg(sc, &frame); 584 585 return(frame.mii_data); 586 } 587 588 static int 589 nge_miibus_writereg(dev, phy, reg, data) 590 device_t dev; 591 int phy, reg, data; 592 { 593 struct nge_softc *sc; 594 struct nge_mii_frame frame; 595 596 sc = device_get_softc(dev); 597 598 bzero((char *)&frame, sizeof(frame)); 599 600 frame.mii_phyaddr = phy; 601 frame.mii_regaddr = reg; 602 frame.mii_data = data; 603 nge_mii_writereg(sc, &frame); 604 605 return(0); 606 } 607 608 static void 609 nge_miibus_statchg(dev) 610 device_t dev; 611 { 612 int status; 613 struct nge_softc *sc; 614 struct mii_data *mii; 615 616 sc = device_get_softc(dev); 617 if (sc->nge_tbi) { 618 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 619 == IFM_AUTO) { 620 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 621 if (status == 0 || status & NGE_TBIANAR_FDX) { 622 NGE_SETBIT(sc, NGE_TX_CFG, 623 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 624 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 625 } else { 626 NGE_CLRBIT(sc, NGE_TX_CFG, 627 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 628 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 629 } 630 631 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 632 != IFM_FDX) { 633 NGE_CLRBIT(sc, NGE_TX_CFG, 634 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 635 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 636 } else { 637 NGE_SETBIT(sc, NGE_TX_CFG, 638 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 639 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 640 } 641 } else { 642 mii = device_get_softc(sc->nge_miibus); 643 644 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 645 NGE_SETBIT(sc, NGE_TX_CFG, 646 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 647 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 648 } else { 649 NGE_CLRBIT(sc, NGE_TX_CFG, 650 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 651 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 652 } 653 654 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 655 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 656 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 657 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 658 } else { 659 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 660 } 661 } 662 return; 663 } 664 665 static void 666 nge_setmulti(sc) 667 struct nge_softc *sc; 668 { 669 struct ifnet *ifp; 670 struct ifmultiaddr *ifma; 671 u_int32_t h = 0, i, filtsave; 672 int bit, index; 673 674 NGE_LOCK_ASSERT(sc); 675 ifp = sc->nge_ifp; 676 677 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 678 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 679 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 680 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 681 return; 682 } 683 684 /* 685 * We have to explicitly enable the multicast hash table 686 * on the NatSemi chip if we want to use it, which we do. 687 * We also have to tell it that we don't want to use the 688 * hash table for matching unicast addresses. 689 */ 690 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 691 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 692 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 693 694 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 695 696 /* first, zot all the existing hash bits */ 697 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 698 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 699 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 700 } 701 702 /* 703 * From the 11 bits returned by the crc routine, the top 7 704 * bits represent the 16-bit word in the mcast hash table 705 * that needs to be updated, and the lower 4 bits represent 706 * which bit within that byte needs to be set. 707 */ 708 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 709 if (ifma->ifma_addr->sa_family != AF_LINK) 710 continue; 711 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 712 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 713 index = (h >> 4) & 0x7F; 714 bit = h & 0xF; 715 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 716 NGE_FILTADDR_MCAST_LO + (index * 2)); 717 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 718 } 719 720 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 721 722 return; 723 } 724 725 static void 726 nge_reset(sc) 727 struct nge_softc *sc; 728 { 729 register int i; 730 731 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 732 733 for (i = 0; i < NGE_TIMEOUT; i++) { 734 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 735 break; 736 } 737 738 if (i == NGE_TIMEOUT) 739 printf("nge%d: reset never completed\n", sc->nge_unit); 740 741 /* Wait a little while for the chip to get its brains in order. */ 742 DELAY(1000); 743 744 /* 745 * If this is a NetSemi chip, make sure to clear 746 * PME mode. 747 */ 748 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 749 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 750 751 return; 752 } 753 754 /* 755 * Probe for a NatSemi chip. Check the PCI vendor and device 756 * IDs against our list and return a device name if we find a match. 757 */ 758 static int 759 nge_probe(dev) 760 device_t dev; 761 { 762 struct nge_type *t; 763 764 t = nge_devs; 765 766 while(t->nge_name != NULL) { 767 if ((pci_get_vendor(dev) == t->nge_vid) && 768 (pci_get_device(dev) == t->nge_did)) { 769 device_set_desc(dev, t->nge_name); 770 return(BUS_PROBE_DEFAULT); 771 } 772 t++; 773 } 774 775 return(ENXIO); 776 } 777 778 /* 779 * Attach the interface. Allocate softc structures, do ifmedia 780 * setup and ethernet/BPF attach. 781 */ 782 static int 783 nge_attach(dev) 784 device_t dev; 785 { 786 u_char eaddr[ETHER_ADDR_LEN]; 787 struct nge_softc *sc; 788 struct ifnet *ifp; 789 int unit, error = 0, rid; 790 const char *sep = ""; 791 792 sc = device_get_softc(dev); 793 unit = device_get_unit(dev); 794 bzero(sc, sizeof(struct nge_softc)); 795 796 NGE_LOCK_INIT(sc, device_get_nameunit(dev)); 797 /* 798 * Map control/status registers. 799 */ 800 pci_enable_busmaster(dev); 801 802 rid = NGE_RID; 803 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 804 805 if (sc->nge_res == NULL) { 806 printf("nge%d: couldn't map ports/memory\n", unit); 807 error = ENXIO; 808 goto fail; 809 } 810 811 sc->nge_btag = rman_get_bustag(sc->nge_res); 812 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 813 814 /* Allocate interrupt */ 815 rid = 0; 816 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 817 RF_SHAREABLE | RF_ACTIVE); 818 819 if (sc->nge_irq == NULL) { 820 printf("nge%d: couldn't map interrupt\n", unit); 821 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 822 error = ENXIO; 823 goto fail; 824 } 825 826 /* Reset the adapter. */ 827 nge_reset(sc); 828 829 /* 830 * Get station address from the EEPROM. 831 */ 832 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 833 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 834 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 835 836 sc->nge_unit = unit; 837 838 /* XXX: leaked on error */ 839 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 840 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 841 842 if (sc->nge_ldata == NULL) { 843 printf("nge%d: no memory for list buffers!\n", unit); 844 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 845 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 846 error = ENXIO; 847 goto fail; 848 } 849 850 ifp = sc->nge_ifp = if_alloc(IFT_ETHER); 851 if (ifp == NULL) { 852 printf("nge%d: can not if_alloc()\n", unit); 853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 854 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 855 error = ENOSPC; 856 goto fail; 857 } 858 ifp->if_softc = sc; 859 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 860 ifp->if_mtu = ETHERMTU; 861 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 862 ifp->if_ioctl = nge_ioctl; 863 ifp->if_start = nge_start; 864 ifp->if_watchdog = nge_watchdog; 865 ifp->if_init = nge_init; 866 ifp->if_baudrate = 1000000000; 867 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 868 ifp->if_hwassist = NGE_CSUM_FEATURES; 869 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 870 #ifdef DEVICE_POLLING 871 ifp->if_capabilities |= IFCAP_POLLING; 872 #endif 873 ifp->if_capenable = ifp->if_capabilities; 874 875 /* 876 * Do MII setup. 877 */ 878 if (mii_phy_probe(dev, &sc->nge_miibus, 879 nge_ifmedia_upd, nge_ifmedia_sts)) { 880 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 881 sc->nge_tbi = 1; 882 device_printf(dev, "Using TBI\n"); 883 884 sc->nge_miibus = dev; 885 886 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 887 nge_ifmedia_sts); 888 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 889 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 890 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 891 device_printf(dev, " "); 892 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 893 PRINT("1000baseSX"); 894 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 895 PRINT("1000baseSX-FDX"); 896 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 897 PRINT("auto"); 898 899 printf("\n"); 900 #undef ADD 901 #undef PRINT 902 ifmedia_set(&sc->nge_ifmedia, 903 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 904 905 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 906 | NGE_GPIO_GP4_OUT 907 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 908 | NGE_GPIO_GP3_OUTENB 909 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 910 911 } else { 912 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 913 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 914 bus_release_resource(dev, NGE_RES, NGE_RID, 915 sc->nge_res); 916 error = ENXIO; 917 goto fail; 918 } 919 } 920 921 /* 922 * Call MI attach routine. 923 */ 924 ether_ifattach(ifp, eaddr); 925 callout_init(&sc->nge_stat_ch, CALLOUT_MPSAFE); 926 927 /* 928 * Hookup IRQ last. 929 */ 930 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE, 931 nge_intr, sc, &sc->nge_intrhand); 932 if (error) { 933 /* XXX: resource leaks */ 934 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 935 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 936 printf("nge%d: couldn't set up irq\n", unit); 937 } 938 939 fail: 940 941 if (error) 942 NGE_LOCK_DESTROY(sc); 943 return(error); 944 } 945 946 static int 947 nge_detach(dev) 948 device_t dev; 949 { 950 struct nge_softc *sc; 951 struct ifnet *ifp; 952 953 sc = device_get_softc(dev); 954 ifp = sc->nge_ifp; 955 956 NGE_LOCK(sc); 957 nge_reset(sc); 958 nge_stop(sc); 959 NGE_UNLOCK(sc); 960 ether_ifdetach(ifp); 961 if_free(ifp); 962 963 bus_generic_detach(dev); 964 if (!sc->nge_tbi) { 965 device_delete_child(dev, sc->nge_miibus); 966 } 967 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 968 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 969 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 970 971 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 972 973 NGE_LOCK_DESTROY(sc); 974 975 return(0); 976 } 977 978 /* 979 * Initialize the transmit descriptors. 980 */ 981 static int 982 nge_list_tx_init(sc) 983 struct nge_softc *sc; 984 { 985 struct nge_list_data *ld; 986 struct nge_ring_data *cd; 987 int i; 988 989 cd = &sc->nge_cdata; 990 ld = sc->nge_ldata; 991 992 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 993 if (i == (NGE_TX_LIST_CNT - 1)) { 994 ld->nge_tx_list[i].nge_nextdesc = 995 &ld->nge_tx_list[0]; 996 ld->nge_tx_list[i].nge_next = 997 vtophys(&ld->nge_tx_list[0]); 998 } else { 999 ld->nge_tx_list[i].nge_nextdesc = 1000 &ld->nge_tx_list[i + 1]; 1001 ld->nge_tx_list[i].nge_next = 1002 vtophys(&ld->nge_tx_list[i + 1]); 1003 } 1004 ld->nge_tx_list[i].nge_mbuf = NULL; 1005 ld->nge_tx_list[i].nge_ptr = 0; 1006 ld->nge_tx_list[i].nge_ctl = 0; 1007 } 1008 1009 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1010 1011 return(0); 1012 } 1013 1014 1015 /* 1016 * Initialize the RX descriptors and allocate mbufs for them. Note that 1017 * we arrange the descriptors in a closed ring, so that the last descriptor 1018 * points back to the first. 1019 */ 1020 static int 1021 nge_list_rx_init(sc) 1022 struct nge_softc *sc; 1023 { 1024 struct nge_list_data *ld; 1025 struct nge_ring_data *cd; 1026 int i; 1027 1028 ld = sc->nge_ldata; 1029 cd = &sc->nge_cdata; 1030 1031 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1032 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1033 return(ENOBUFS); 1034 if (i == (NGE_RX_LIST_CNT - 1)) { 1035 ld->nge_rx_list[i].nge_nextdesc = 1036 &ld->nge_rx_list[0]; 1037 ld->nge_rx_list[i].nge_next = 1038 vtophys(&ld->nge_rx_list[0]); 1039 } else { 1040 ld->nge_rx_list[i].nge_nextdesc = 1041 &ld->nge_rx_list[i + 1]; 1042 ld->nge_rx_list[i].nge_next = 1043 vtophys(&ld->nge_rx_list[i + 1]); 1044 } 1045 } 1046 1047 cd->nge_rx_prod = 0; 1048 sc->nge_head = sc->nge_tail = NULL; 1049 1050 return(0); 1051 } 1052 1053 /* 1054 * Initialize an RX descriptor and attach an MBUF cluster. 1055 */ 1056 static int 1057 nge_newbuf(sc, c, m) 1058 struct nge_softc *sc; 1059 struct nge_desc *c; 1060 struct mbuf *m; 1061 { 1062 1063 if (m == NULL) { 1064 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1065 if (m == NULL) 1066 return (ENOBUFS); 1067 } else 1068 m->m_data = m->m_ext.ext_buf; 1069 1070 m->m_len = m->m_pkthdr.len = MCLBYTES; 1071 1072 m_adj(m, sizeof(u_int64_t)); 1073 1074 c->nge_mbuf = m; 1075 c->nge_ptr = vtophys(mtod(m, caddr_t)); 1076 c->nge_ctl = m->m_len; 1077 c->nge_extsts = 0; 1078 1079 return(0); 1080 } 1081 1082 #ifdef NGE_FIXUP_RX 1083 static __inline void 1084 nge_fixup_rx(m) 1085 struct mbuf *m; 1086 { 1087 int i; 1088 uint16_t *src, *dst; 1089 1090 src = mtod(m, uint16_t *); 1091 dst = src - 1; 1092 1093 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1094 *dst++ = *src++; 1095 1096 m->m_data -= ETHER_ALIGN; 1097 1098 return; 1099 } 1100 #endif 1101 1102 /* 1103 * A frame has been uploaded: pass the resulting mbuf chain up to 1104 * the higher level protocols. 1105 */ 1106 static void 1107 nge_rxeof(sc) 1108 struct nge_softc *sc; 1109 { 1110 struct mbuf *m; 1111 struct ifnet *ifp; 1112 struct nge_desc *cur_rx; 1113 int i, total_len = 0; 1114 u_int32_t rxstat; 1115 1116 NGE_LOCK_ASSERT(sc); 1117 ifp = sc->nge_ifp; 1118 i = sc->nge_cdata.nge_rx_prod; 1119 1120 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1121 u_int32_t extsts; 1122 1123 #ifdef DEVICE_POLLING 1124 if (ifp->if_flags & IFF_POLLING) { 1125 if (sc->rxcycles <= 0) 1126 break; 1127 sc->rxcycles--; 1128 } 1129 #endif /* DEVICE_POLLING */ 1130 1131 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1132 rxstat = cur_rx->nge_rxstat; 1133 extsts = cur_rx->nge_extsts; 1134 m = cur_rx->nge_mbuf; 1135 cur_rx->nge_mbuf = NULL; 1136 total_len = NGE_RXBYTES(cur_rx); 1137 NGE_INC(i, NGE_RX_LIST_CNT); 1138 1139 if (rxstat & NGE_CMDSTS_MORE) { 1140 m->m_len = total_len; 1141 if (sc->nge_head == NULL) { 1142 m->m_pkthdr.len = total_len; 1143 sc->nge_head = sc->nge_tail = m; 1144 } else { 1145 m->m_flags &= ~M_PKTHDR; 1146 sc->nge_head->m_pkthdr.len += total_len; 1147 sc->nge_tail->m_next = m; 1148 sc->nge_tail = m; 1149 } 1150 nge_newbuf(sc, cur_rx, NULL); 1151 continue; 1152 } 1153 1154 /* 1155 * If an error occurs, update stats, clear the 1156 * status word and leave the mbuf cluster in place: 1157 * it should simply get re-used next time this descriptor 1158 * comes up in the ring. 1159 */ 1160 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1161 ifp->if_ierrors++; 1162 if (sc->nge_head != NULL) { 1163 m_freem(sc->nge_head); 1164 sc->nge_head = sc->nge_tail = NULL; 1165 } 1166 nge_newbuf(sc, cur_rx, m); 1167 continue; 1168 } 1169 1170 /* Try conjure up a replacement mbuf. */ 1171 1172 if (nge_newbuf(sc, cur_rx, NULL)) { 1173 ifp->if_ierrors++; 1174 if (sc->nge_head != NULL) { 1175 m_freem(sc->nge_head); 1176 sc->nge_head = sc->nge_tail = NULL; 1177 } 1178 nge_newbuf(sc, cur_rx, m); 1179 continue; 1180 } 1181 1182 if (sc->nge_head != NULL) { 1183 m->m_len = total_len; 1184 m->m_flags &= ~M_PKTHDR; 1185 sc->nge_tail->m_next = m; 1186 m = sc->nge_head; 1187 m->m_pkthdr.len += total_len; 1188 sc->nge_head = sc->nge_tail = NULL; 1189 } else 1190 m->m_pkthdr.len = m->m_len = total_len; 1191 1192 /* 1193 * Ok. NatSemi really screwed up here. This is the 1194 * only gigE chip I know of with alignment constraints 1195 * on receive buffers. RX buffers must be 64-bit aligned. 1196 */ 1197 /* 1198 * By popular demand, ignore the alignment problems 1199 * on the Intel x86 platform. The performance hit 1200 * incurred due to unaligned accesses is much smaller 1201 * than the hit produced by forcing buffer copies all 1202 * the time, especially with jumbo frames. We still 1203 * need to fix up the alignment everywhere else though. 1204 */ 1205 #ifdef NGE_FIXUP_RX 1206 nge_fixup_rx(m); 1207 #endif 1208 1209 ifp->if_ipackets++; 1210 m->m_pkthdr.rcvif = ifp; 1211 1212 /* Do IP checksum checking. */ 1213 if (extsts & NGE_RXEXTSTS_IPPKT) 1214 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1215 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1216 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1217 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1218 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1219 (extsts & NGE_RXEXTSTS_UDPPKT && 1220 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1221 m->m_pkthdr.csum_flags |= 1222 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1223 m->m_pkthdr.csum_data = 0xffff; 1224 } 1225 1226 /* 1227 * If we received a packet with a vlan tag, pass it 1228 * to vlan_input() instead of ether_input(). 1229 */ 1230 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1231 VLAN_INPUT_TAG(ifp, m, 1232 ntohs(extsts & NGE_RXEXTSTS_VTCI), continue); 1233 } 1234 NGE_UNLOCK(sc); 1235 (*ifp->if_input)(ifp, m); 1236 NGE_LOCK(sc); 1237 } 1238 1239 sc->nge_cdata.nge_rx_prod = i; 1240 1241 return; 1242 } 1243 1244 /* 1245 * A frame was downloaded to the chip. It's safe for us to clean up 1246 * the list buffers. 1247 */ 1248 1249 static void 1250 nge_txeof(sc) 1251 struct nge_softc *sc; 1252 { 1253 struct nge_desc *cur_tx; 1254 struct ifnet *ifp; 1255 u_int32_t idx; 1256 1257 NGE_LOCK_ASSERT(sc); 1258 ifp = sc->nge_ifp; 1259 1260 /* 1261 * Go through our tx list and free mbufs for those 1262 * frames that have been transmitted. 1263 */ 1264 idx = sc->nge_cdata.nge_tx_cons; 1265 while (idx != sc->nge_cdata.nge_tx_prod) { 1266 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1267 1268 if (NGE_OWNDESC(cur_tx)) 1269 break; 1270 1271 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1272 sc->nge_cdata.nge_tx_cnt--; 1273 NGE_INC(idx, NGE_TX_LIST_CNT); 1274 continue; 1275 } 1276 1277 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1278 ifp->if_oerrors++; 1279 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1280 ifp->if_collisions++; 1281 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1282 ifp->if_collisions++; 1283 } 1284 1285 ifp->if_collisions += 1286 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1287 1288 ifp->if_opackets++; 1289 if (cur_tx->nge_mbuf != NULL) { 1290 m_freem(cur_tx->nge_mbuf); 1291 cur_tx->nge_mbuf = NULL; 1292 ifp->if_flags &= ~IFF_OACTIVE; 1293 } 1294 1295 sc->nge_cdata.nge_tx_cnt--; 1296 NGE_INC(idx, NGE_TX_LIST_CNT); 1297 } 1298 1299 sc->nge_cdata.nge_tx_cons = idx; 1300 1301 if (idx == sc->nge_cdata.nge_tx_prod) 1302 ifp->if_timer = 0; 1303 1304 return; 1305 } 1306 1307 static void 1308 nge_tick(xsc) 1309 void *xsc; 1310 { 1311 struct nge_softc *sc; 1312 1313 sc = xsc; 1314 1315 NGE_LOCK(sc); 1316 nge_tick_locked(sc); 1317 NGE_UNLOCK(sc); 1318 } 1319 1320 static void 1321 nge_tick_locked(sc) 1322 struct nge_softc *sc; 1323 { 1324 struct mii_data *mii; 1325 struct ifnet *ifp; 1326 1327 NGE_LOCK_ASSERT(sc); 1328 ifp = sc->nge_ifp; 1329 1330 if (sc->nge_tbi) { 1331 if (!sc->nge_link) { 1332 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1333 & NGE_TBIBMSR_ANEG_DONE) { 1334 if (bootverbose) 1335 printf("nge%d: gigabit link up\n", 1336 sc->nge_unit); 1337 nge_miibus_statchg(sc->nge_miibus); 1338 sc->nge_link++; 1339 if (ifp->if_snd.ifq_head != NULL) 1340 nge_start_locked(ifp); 1341 } 1342 } 1343 } else { 1344 mii = device_get_softc(sc->nge_miibus); 1345 mii_tick(mii); 1346 1347 if (!sc->nge_link) { 1348 if (mii->mii_media_status & IFM_ACTIVE && 1349 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1350 sc->nge_link++; 1351 if (IFM_SUBTYPE(mii->mii_media_active) 1352 == IFM_1000_T && bootverbose) 1353 printf("nge%d: gigabit link up\n", 1354 sc->nge_unit); 1355 if (ifp->if_snd.ifq_head != NULL) 1356 nge_start_locked(ifp); 1357 } 1358 } 1359 } 1360 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 1361 1362 return; 1363 } 1364 1365 #ifdef DEVICE_POLLING 1366 static poll_handler_t nge_poll; 1367 1368 static void 1369 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1370 { 1371 struct nge_softc *sc = ifp->if_softc; 1372 1373 NGE_LOCK(sc); 1374 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1375 ether_poll_deregister(ifp); 1376 cmd = POLL_DEREGISTER; 1377 } 1378 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1379 CSR_WRITE_4(sc, NGE_IER, 1); 1380 NGE_UNLOCK(sc); 1381 return; 1382 } 1383 1384 /* 1385 * On the nge, reading the status register also clears it. 1386 * So before returning to intr mode we must make sure that all 1387 * possible pending sources of interrupts have been served. 1388 * In practice this means run to completion the *eof routines, 1389 * and then call the interrupt routine 1390 */ 1391 sc->rxcycles = count; 1392 nge_rxeof(sc); 1393 nge_txeof(sc); 1394 if (ifp->if_snd.ifq_head != NULL) 1395 nge_start_locked(ifp); 1396 1397 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1398 u_int32_t status; 1399 1400 /* Reading the ISR register clears all interrupts. */ 1401 status = CSR_READ_4(sc, NGE_ISR); 1402 1403 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1404 nge_rxeof(sc); 1405 1406 if (status & (NGE_ISR_RX_IDLE)) 1407 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1408 1409 if (status & NGE_ISR_SYSERR) { 1410 nge_reset(sc); 1411 nge_init_locked(sc); 1412 } 1413 } 1414 NGE_UNLOCK(sc); 1415 } 1416 #endif /* DEVICE_POLLING */ 1417 1418 static void 1419 nge_intr(arg) 1420 void *arg; 1421 { 1422 struct nge_softc *sc; 1423 struct ifnet *ifp; 1424 u_int32_t status; 1425 1426 sc = arg; 1427 ifp = sc->nge_ifp; 1428 1429 NGE_LOCK(sc); 1430 #ifdef DEVICE_POLLING 1431 if (ifp->if_flags & IFF_POLLING) { 1432 NGE_UNLOCK(sc); 1433 return; 1434 } 1435 if ((ifp->if_capenable & IFCAP_POLLING) && 1436 ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1437 CSR_WRITE_4(sc, NGE_IER, 0); 1438 NGE_UNLOCK(sc); 1439 nge_poll(ifp, 0, 1); 1440 return; 1441 } 1442 #endif /* DEVICE_POLLING */ 1443 1444 /* Supress unwanted interrupts */ 1445 if (!(ifp->if_flags & IFF_UP)) { 1446 nge_stop(sc); 1447 NGE_UNLOCK(sc); 1448 return; 1449 } 1450 1451 /* Disable interrupts. */ 1452 CSR_WRITE_4(sc, NGE_IER, 0); 1453 1454 /* Data LED on for TBI mode */ 1455 if(sc->nge_tbi) 1456 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1457 | NGE_GPIO_GP3_OUT); 1458 1459 for (;;) { 1460 /* Reading the ISR register clears all interrupts. */ 1461 status = CSR_READ_4(sc, NGE_ISR); 1462 1463 if ((status & NGE_INTRS) == 0) 1464 break; 1465 1466 if ((status & NGE_ISR_TX_DESC_OK) || 1467 (status & NGE_ISR_TX_ERR) || 1468 (status & NGE_ISR_TX_OK) || 1469 (status & NGE_ISR_TX_IDLE)) 1470 nge_txeof(sc); 1471 1472 if ((status & NGE_ISR_RX_DESC_OK) || 1473 (status & NGE_ISR_RX_ERR) || 1474 (status & NGE_ISR_RX_OFLOW) || 1475 (status & NGE_ISR_RX_FIFO_OFLOW) || 1476 (status & NGE_ISR_RX_IDLE) || 1477 (status & NGE_ISR_RX_OK)) 1478 nge_rxeof(sc); 1479 1480 if ((status & NGE_ISR_RX_IDLE)) 1481 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1482 1483 if (status & NGE_ISR_SYSERR) { 1484 nge_reset(sc); 1485 ifp->if_flags &= ~IFF_RUNNING; 1486 nge_init_locked(sc); 1487 } 1488 1489 #if 0 1490 /* 1491 * XXX: nge_tick() is not ready to be called this way 1492 * it screws up the aneg timeout because mii_tick() is 1493 * only to be called once per second. 1494 */ 1495 if (status & NGE_IMR_PHY_INTR) { 1496 sc->nge_link = 0; 1497 nge_tick_locked(sc); 1498 } 1499 #endif 1500 } 1501 1502 /* Re-enable interrupts. */ 1503 CSR_WRITE_4(sc, NGE_IER, 1); 1504 1505 if (ifp->if_snd.ifq_head != NULL) 1506 nge_start_locked(ifp); 1507 1508 /* Data LED off for TBI mode */ 1509 1510 if(sc->nge_tbi) 1511 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1512 & ~NGE_GPIO_GP3_OUT); 1513 1514 NGE_UNLOCK(sc); 1515 1516 return; 1517 } 1518 1519 /* 1520 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1521 * pointers to the fragment pointers. 1522 */ 1523 static int 1524 nge_encap(sc, m_head, txidx) 1525 struct nge_softc *sc; 1526 struct mbuf *m_head; 1527 u_int32_t *txidx; 1528 { 1529 struct nge_desc *f = NULL; 1530 struct mbuf *m; 1531 int frag, cur, cnt = 0; 1532 struct m_tag *mtag; 1533 1534 /* 1535 * Start packing the mbufs in this chain into 1536 * the fragment pointers. Stop when we run out 1537 * of fragments or hit the end of the mbuf chain. 1538 */ 1539 m = m_head; 1540 cur = frag = *txidx; 1541 1542 for (m = m_head; m != NULL; m = m->m_next) { 1543 if (m->m_len != 0) { 1544 if ((NGE_TX_LIST_CNT - 1545 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1546 return(ENOBUFS); 1547 f = &sc->nge_ldata->nge_tx_list[frag]; 1548 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1549 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1550 if (cnt != 0) 1551 f->nge_ctl |= NGE_CMDSTS_OWN; 1552 cur = frag; 1553 NGE_INC(frag, NGE_TX_LIST_CNT); 1554 cnt++; 1555 } 1556 } 1557 1558 if (m != NULL) 1559 return(ENOBUFS); 1560 1561 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1562 if (m_head->m_pkthdr.csum_flags) { 1563 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1564 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1565 NGE_TXEXTSTS_IPCSUM; 1566 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1567 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1568 NGE_TXEXTSTS_TCPCSUM; 1569 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1570 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1571 NGE_TXEXTSTS_UDPCSUM; 1572 } 1573 1574 mtag = VLAN_OUTPUT_TAG(sc->nge_ifp, m_head); 1575 if (mtag != NULL) { 1576 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1577 (NGE_TXEXTSTS_VLANPKT|htons(VLAN_TAG_VALUE(mtag))); 1578 } 1579 1580 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1581 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1582 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1583 sc->nge_cdata.nge_tx_cnt += cnt; 1584 *txidx = frag; 1585 1586 return(0); 1587 } 1588 1589 /* 1590 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1591 * to the mbuf data regions directly in the transmit lists. We also save a 1592 * copy of the pointers since the transmit list fragment pointers are 1593 * physical addresses. 1594 */ 1595 1596 static void 1597 nge_start(ifp) 1598 struct ifnet *ifp; 1599 { 1600 struct nge_softc *sc; 1601 1602 sc = ifp->if_softc; 1603 NGE_LOCK(sc); 1604 nge_start_locked(ifp); 1605 NGE_UNLOCK(sc); 1606 } 1607 1608 static void 1609 nge_start_locked(ifp) 1610 struct ifnet *ifp; 1611 { 1612 struct nge_softc *sc; 1613 struct mbuf *m_head = NULL; 1614 u_int32_t idx; 1615 1616 sc = ifp->if_softc; 1617 1618 if (!sc->nge_link) 1619 return; 1620 1621 idx = sc->nge_cdata.nge_tx_prod; 1622 1623 if (ifp->if_flags & IFF_OACTIVE) 1624 return; 1625 1626 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1627 IF_DEQUEUE(&ifp->if_snd, m_head); 1628 if (m_head == NULL) 1629 break; 1630 1631 if (nge_encap(sc, m_head, &idx)) { 1632 IF_PREPEND(&ifp->if_snd, m_head); 1633 ifp->if_flags |= IFF_OACTIVE; 1634 break; 1635 } 1636 1637 /* 1638 * If there's a BPF listener, bounce a copy of this frame 1639 * to him. 1640 */ 1641 BPF_MTAP(ifp, m_head); 1642 1643 } 1644 1645 /* Transmit */ 1646 sc->nge_cdata.nge_tx_prod = idx; 1647 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1648 1649 /* 1650 * Set a timeout in case the chip goes out to lunch. 1651 */ 1652 ifp->if_timer = 5; 1653 1654 return; 1655 } 1656 1657 static void 1658 nge_init(xsc) 1659 void *xsc; 1660 { 1661 struct nge_softc *sc = xsc; 1662 1663 NGE_LOCK(sc); 1664 nge_init_locked(sc); 1665 NGE_UNLOCK(sc); 1666 } 1667 1668 static void 1669 nge_init_locked(sc) 1670 struct nge_softc *sc; 1671 { 1672 struct ifnet *ifp = sc->nge_ifp; 1673 struct mii_data *mii; 1674 1675 NGE_LOCK_ASSERT(sc); 1676 1677 if (ifp->if_flags & IFF_RUNNING) 1678 return; 1679 1680 /* 1681 * Cancel pending I/O and free all RX/TX buffers. 1682 */ 1683 nge_stop(sc); 1684 1685 if (sc->nge_tbi) { 1686 mii = NULL; 1687 } else { 1688 mii = device_get_softc(sc->nge_miibus); 1689 } 1690 1691 /* Set MAC address */ 1692 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1693 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1694 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[0]); 1695 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1696 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1697 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[1]); 1698 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1699 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1700 ((u_int16_t *)IFP2ENADDR(sc->nge_ifp))[2]); 1701 1702 /* Init circular RX list. */ 1703 if (nge_list_rx_init(sc) == ENOBUFS) { 1704 printf("nge%d: initialization failed: no " 1705 "memory for rx buffers\n", sc->nge_unit); 1706 nge_stop(sc); 1707 return; 1708 } 1709 1710 /* 1711 * Init tx descriptors. 1712 */ 1713 nge_list_tx_init(sc); 1714 1715 /* 1716 * For the NatSemi chip, we have to explicitly enable the 1717 * reception of ARP frames, as well as turn on the 'perfect 1718 * match' filter where we store the station address, otherwise 1719 * we won't receive unicasts meant for this host. 1720 */ 1721 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1722 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1723 1724 /* If we want promiscuous mode, set the allframes bit. */ 1725 if (ifp->if_flags & IFF_PROMISC) { 1726 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1727 } else { 1728 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1729 } 1730 1731 /* 1732 * Set the capture broadcast bit to capture broadcast frames. 1733 */ 1734 if (ifp->if_flags & IFF_BROADCAST) { 1735 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1736 } else { 1737 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1738 } 1739 1740 /* 1741 * Load the multicast filter. 1742 */ 1743 nge_setmulti(sc); 1744 1745 /* Turn the receive filter on */ 1746 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1747 1748 /* 1749 * Load the address of the RX and TX lists. 1750 */ 1751 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1752 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1753 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1754 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1755 1756 /* Set RX configuration */ 1757 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1758 /* 1759 * Enable hardware checksum validation for all IPv4 1760 * packets, do not reject packets with bad checksums. 1761 */ 1762 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1763 1764 /* 1765 * Tell the chip to detect and strip VLAN tag info from 1766 * received frames. The tag will be provided in the extsts 1767 * field in the RX descriptors. 1768 */ 1769 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1770 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1771 1772 /* Set TX configuration */ 1773 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1774 1775 /* 1776 * Enable TX IPv4 checksumming on a per-packet basis. 1777 */ 1778 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1779 1780 /* 1781 * Tell the chip to insert VLAN tags on a per-packet basis as 1782 * dictated by the code in the frame encapsulation routine. 1783 */ 1784 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1785 1786 /* Set full/half duplex mode. */ 1787 if (sc->nge_tbi) { 1788 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1789 == IFM_FDX) { 1790 NGE_SETBIT(sc, NGE_TX_CFG, 1791 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1792 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1793 } else { 1794 NGE_CLRBIT(sc, NGE_TX_CFG, 1795 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1796 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1797 } 1798 } else { 1799 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1800 NGE_SETBIT(sc, NGE_TX_CFG, 1801 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1802 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1803 } else { 1804 NGE_CLRBIT(sc, NGE_TX_CFG, 1805 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1806 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1807 } 1808 } 1809 1810 nge_tick_locked(sc); 1811 1812 /* 1813 * Enable the delivery of PHY interrupts based on 1814 * link/speed/duplex status changes. Also enable the 1815 * extsts field in the DMA descriptors (needed for 1816 * TCP/IP checksum offload on transmit). 1817 */ 1818 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1819 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1820 1821 /* 1822 * Configure interrupt holdoff (moderation). We can 1823 * have the chip delay interrupt delivery for a certain 1824 * period. Units are in 100us, and the max setting 1825 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1826 */ 1827 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1828 1829 /* 1830 * Enable interrupts. 1831 */ 1832 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1833 #ifdef DEVICE_POLLING 1834 /* 1835 * ... only enable interrupts if we are not polling, make sure 1836 * they are off otherwise. 1837 */ 1838 if (ifp->if_flags & IFF_POLLING) 1839 CSR_WRITE_4(sc, NGE_IER, 0); 1840 else 1841 #endif /* DEVICE_POLLING */ 1842 CSR_WRITE_4(sc, NGE_IER, 1); 1843 1844 /* Enable receiver and transmitter. */ 1845 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1846 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1847 1848 nge_ifmedia_upd(ifp); 1849 1850 ifp->if_flags |= IFF_RUNNING; 1851 ifp->if_flags &= ~IFF_OACTIVE; 1852 1853 return; 1854 } 1855 1856 /* 1857 * Set media options. 1858 */ 1859 static int 1860 nge_ifmedia_upd(ifp) 1861 struct ifnet *ifp; 1862 { 1863 struct nge_softc *sc; 1864 struct mii_data *mii; 1865 1866 sc = ifp->if_softc; 1867 1868 if (sc->nge_tbi) { 1869 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1870 == IFM_AUTO) { 1871 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1872 CSR_READ_4(sc, NGE_TBI_ANAR) 1873 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 1874 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 1875 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 1876 | NGE_TBIBMCR_RESTART_ANEG); 1877 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 1878 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 1879 & IFM_GMASK) == IFM_FDX) { 1880 NGE_SETBIT(sc, NGE_TX_CFG, 1881 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1882 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1883 1884 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1885 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1886 } else { 1887 NGE_CLRBIT(sc, NGE_TX_CFG, 1888 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1889 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1890 1891 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1892 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1893 } 1894 1895 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1896 & ~NGE_GPIO_GP3_OUT); 1897 } else { 1898 mii = device_get_softc(sc->nge_miibus); 1899 sc->nge_link = 0; 1900 if (mii->mii_instance) { 1901 struct mii_softc *miisc; 1902 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1903 miisc = LIST_NEXT(miisc, mii_list)) 1904 mii_phy_reset(miisc); 1905 } 1906 mii_mediachg(mii); 1907 } 1908 1909 return(0); 1910 } 1911 1912 /* 1913 * Report current media status. 1914 */ 1915 static void 1916 nge_ifmedia_sts(ifp, ifmr) 1917 struct ifnet *ifp; 1918 struct ifmediareq *ifmr; 1919 { 1920 struct nge_softc *sc; 1921 struct mii_data *mii; 1922 1923 sc = ifp->if_softc; 1924 1925 if (sc->nge_tbi) { 1926 ifmr->ifm_status = IFM_AVALID; 1927 ifmr->ifm_active = IFM_ETHER; 1928 1929 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1930 ifmr->ifm_status |= IFM_ACTIVE; 1931 } 1932 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 1933 ifmr->ifm_active |= IFM_LOOP; 1934 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1935 ifmr->ifm_active |= IFM_NONE; 1936 ifmr->ifm_status = 0; 1937 return; 1938 } 1939 ifmr->ifm_active |= IFM_1000_SX; 1940 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1941 == IFM_AUTO) { 1942 ifmr->ifm_active |= IFM_AUTO; 1943 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1944 & NGE_TBIANAR_FDX) { 1945 ifmr->ifm_active |= IFM_FDX; 1946 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1947 & NGE_TBIANAR_HDX) { 1948 ifmr->ifm_active |= IFM_HDX; 1949 } 1950 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1951 == IFM_FDX) 1952 ifmr->ifm_active |= IFM_FDX; 1953 else 1954 ifmr->ifm_active |= IFM_HDX; 1955 1956 } else { 1957 mii = device_get_softc(sc->nge_miibus); 1958 mii_pollstat(mii); 1959 ifmr->ifm_active = mii->mii_media_active; 1960 ifmr->ifm_status = mii->mii_media_status; 1961 } 1962 1963 return; 1964 } 1965 1966 static int 1967 nge_ioctl(ifp, command, data) 1968 struct ifnet *ifp; 1969 u_long command; 1970 caddr_t data; 1971 { 1972 struct nge_softc *sc = ifp->if_softc; 1973 struct ifreq *ifr = (struct ifreq *) data; 1974 struct mii_data *mii; 1975 int error = 0; 1976 1977 switch(command) { 1978 case SIOCSIFMTU: 1979 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 1980 error = EINVAL; 1981 else { 1982 ifp->if_mtu = ifr->ifr_mtu; 1983 /* 1984 * Workaround: if the MTU is larger than 1985 * 8152 (TX FIFO size minus 64 minus 18), turn off 1986 * TX checksum offloading. 1987 */ 1988 if (ifr->ifr_mtu >= 8152) { 1989 ifp->if_capenable &= ~IFCAP_TXCSUM; 1990 ifp->if_hwassist = 0; 1991 } else { 1992 ifp->if_capenable |= IFCAP_TXCSUM; 1993 ifp->if_hwassist = NGE_CSUM_FEATURES; 1994 } 1995 } 1996 break; 1997 case SIOCSIFFLAGS: 1998 NGE_LOCK(sc); 1999 if (ifp->if_flags & IFF_UP) { 2000 if (ifp->if_flags & IFF_RUNNING && 2001 ifp->if_flags & IFF_PROMISC && 2002 !(sc->nge_if_flags & IFF_PROMISC)) { 2003 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2004 NGE_RXFILTCTL_ALLPHYS| 2005 NGE_RXFILTCTL_ALLMULTI); 2006 } else if (ifp->if_flags & IFF_RUNNING && 2007 !(ifp->if_flags & IFF_PROMISC) && 2008 sc->nge_if_flags & IFF_PROMISC) { 2009 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2010 NGE_RXFILTCTL_ALLPHYS); 2011 if (!(ifp->if_flags & IFF_ALLMULTI)) 2012 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2013 NGE_RXFILTCTL_ALLMULTI); 2014 } else { 2015 ifp->if_flags &= ~IFF_RUNNING; 2016 nge_init_locked(sc); 2017 } 2018 } else { 2019 if (ifp->if_flags & IFF_RUNNING) 2020 nge_stop(sc); 2021 } 2022 sc->nge_if_flags = ifp->if_flags; 2023 NGE_UNLOCK(sc); 2024 error = 0; 2025 break; 2026 case SIOCADDMULTI: 2027 case SIOCDELMULTI: 2028 NGE_LOCK(sc); 2029 nge_setmulti(sc); 2030 NGE_UNLOCK(sc); 2031 error = 0; 2032 break; 2033 case SIOCGIFMEDIA: 2034 case SIOCSIFMEDIA: 2035 if (sc->nge_tbi) { 2036 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2037 command); 2038 } else { 2039 mii = device_get_softc(sc->nge_miibus); 2040 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2041 command); 2042 } 2043 break; 2044 case SIOCSIFCAP: 2045 ifp->if_capenable &= ~IFCAP_POLLING; 2046 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2047 break; 2048 default: 2049 error = ether_ioctl(ifp, command, data); 2050 break; 2051 } 2052 2053 return(error); 2054 } 2055 2056 static void 2057 nge_watchdog(ifp) 2058 struct ifnet *ifp; 2059 { 2060 struct nge_softc *sc; 2061 2062 sc = ifp->if_softc; 2063 2064 ifp->if_oerrors++; 2065 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2066 2067 NGE_LOCK(sc); 2068 nge_stop(sc); 2069 nge_reset(sc); 2070 ifp->if_flags &= ~IFF_RUNNING; 2071 nge_init_locked(sc); 2072 2073 if (ifp->if_snd.ifq_head != NULL) 2074 nge_start_locked(ifp); 2075 2076 NGE_UNLOCK(sc); 2077 2078 return; 2079 } 2080 2081 /* 2082 * Stop the adapter and free any mbufs allocated to the 2083 * RX and TX lists. 2084 */ 2085 static void 2086 nge_stop(sc) 2087 struct nge_softc *sc; 2088 { 2089 register int i; 2090 struct ifnet *ifp; 2091 struct mii_data *mii; 2092 2093 NGE_LOCK_ASSERT(sc); 2094 ifp = sc->nge_ifp; 2095 ifp->if_timer = 0; 2096 if (sc->nge_tbi) { 2097 mii = NULL; 2098 } else { 2099 mii = device_get_softc(sc->nge_miibus); 2100 } 2101 2102 callout_stop(&sc->nge_stat_ch); 2103 #ifdef DEVICE_POLLING 2104 ether_poll_deregister(ifp); 2105 #endif 2106 CSR_WRITE_4(sc, NGE_IER, 0); 2107 CSR_WRITE_4(sc, NGE_IMR, 0); 2108 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2109 DELAY(1000); 2110 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2111 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2112 2113 if (!sc->nge_tbi) 2114 mii_down(mii); 2115 2116 sc->nge_link = 0; 2117 2118 /* 2119 * Free data in the RX lists. 2120 */ 2121 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2122 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2123 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2124 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2125 } 2126 } 2127 bzero((char *)&sc->nge_ldata->nge_rx_list, 2128 sizeof(sc->nge_ldata->nge_rx_list)); 2129 2130 /* 2131 * Free the TX list buffers. 2132 */ 2133 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2134 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2135 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2136 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2137 } 2138 } 2139 2140 bzero((char *)&sc->nge_ldata->nge_tx_list, 2141 sizeof(sc->nge_ldata->nge_tx_list)); 2142 2143 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2144 2145 return; 2146 } 2147 2148 /* 2149 * Stop all chip I/O so that the kernel's probe routines don't 2150 * get confused by errant DMAs when rebooting. 2151 */ 2152 static void 2153 nge_shutdown(dev) 2154 device_t dev; 2155 { 2156 struct nge_softc *sc; 2157 2158 sc = device_get_softc(dev); 2159 2160 NGE_LOCK(sc); 2161 nge_reset(sc); 2162 nge_stop(sc); 2163 NGE_UNLOCK(sc); 2164 2165 return; 2166 } 2167