1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/module.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 100 #include <net/if.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_types.h> 106 #include <net/if_vlan_var.h> 107 108 #include <net/bpf.h> 109 110 #include <vm/vm.h> /* for vtophys */ 111 #include <vm/pmap.h> /* for vtophys */ 112 #include <machine/clock.h> /* for DELAY */ 113 #include <machine/bus_pio.h> 114 #include <machine/bus_memio.h> 115 #include <machine/bus.h> 116 #include <machine/resource.h> 117 #include <sys/bus.h> 118 #include <sys/rman.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <dev/pci/pcireg.h> 124 #include <dev/pci/pcivar.h> 125 126 #define NGE_USEIOSPACE 127 128 #include <dev/nge/if_ngereg.h> 129 130 MODULE_DEPEND(nge, pci, 1, 1, 1); 131 MODULE_DEPEND(nge, ether, 1, 1, 1); 132 MODULE_DEPEND(nge, miibus, 1, 1, 1); 133 134 /* "controller miibus0" required. See GENERIC if you get errors here. */ 135 #include "miibus_if.h" 136 137 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 138 139 /* 140 * Various supported device vendors/types and their names. 141 */ 142 static struct nge_type nge_devs[] = { 143 { NGE_VENDORID, NGE_DEVICEID, 144 "National Semiconductor Gigabit Ethernet" }, 145 { 0, 0, NULL } 146 }; 147 148 static int nge_probe(device_t); 149 static int nge_attach(device_t); 150 static int nge_detach(device_t); 151 152 static int nge_alloc_jumbo_mem(struct nge_softc *); 153 static void nge_free_jumbo_mem(struct nge_softc *); 154 static void *nge_jalloc(struct nge_softc *); 155 static void nge_jfree(void *, void *); 156 157 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *); 158 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 159 static void nge_rxeof(struct nge_softc *); 160 static void nge_txeof(struct nge_softc *); 161 static void nge_intr(void *); 162 static void nge_tick(void *); 163 static void nge_start(struct ifnet *); 164 static int nge_ioctl(struct ifnet *, u_long, caddr_t); 165 static void nge_init(void *); 166 static void nge_stop(struct nge_softc *); 167 static void nge_watchdog(struct ifnet *); 168 static void nge_shutdown(device_t); 169 static int nge_ifmedia_upd(struct ifnet *); 170 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 171 172 static void nge_delay(struct nge_softc *); 173 static void nge_eeprom_idle(struct nge_softc *); 174 static void nge_eeprom_putbyte(struct nge_softc *, int); 175 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 176 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 177 178 static void nge_mii_sync(struct nge_softc *); 179 static void nge_mii_send(struct nge_softc *, u_int32_t, int); 180 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 181 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 182 183 static int nge_miibus_readreg(device_t, int, int); 184 static int nge_miibus_writereg(device_t, int, int, int); 185 static void nge_miibus_statchg(device_t); 186 187 static void nge_setmulti(struct nge_softc *); 188 static void nge_reset(struct nge_softc *); 189 static int nge_list_rx_init(struct nge_softc *); 190 static int nge_list_tx_init(struct nge_softc *); 191 192 #ifdef NGE_USEIOSPACE 193 #define NGE_RES SYS_RES_IOPORT 194 #define NGE_RID NGE_PCI_LOIO 195 #else 196 #define NGE_RES SYS_RES_MEMORY 197 #define NGE_RID NGE_PCI_LOMEM 198 #endif 199 200 static device_method_t nge_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, nge_probe), 203 DEVMETHOD(device_attach, nge_attach), 204 DEVMETHOD(device_detach, nge_detach), 205 DEVMETHOD(device_shutdown, nge_shutdown), 206 207 /* bus interface */ 208 DEVMETHOD(bus_print_child, bus_generic_print_child), 209 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 210 211 /* MII interface */ 212 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 213 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 214 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 215 216 { 0, 0 } 217 }; 218 219 static driver_t nge_driver = { 220 "nge", 221 nge_methods, 222 sizeof(struct nge_softc) 223 }; 224 225 static devclass_t nge_devclass; 226 227 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 228 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 229 230 #define NGE_SETBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) | (x)) 233 234 #define NGE_CLRBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) & ~(x)) 237 238 #define SIO_SET(x) \ 239 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 240 241 #define SIO_CLR(x) \ 242 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 243 244 static void 245 nge_delay(sc) 246 struct nge_softc *sc; 247 { 248 int idx; 249 250 for (idx = (300 / 33) + 1; idx > 0; idx--) 251 CSR_READ_4(sc, NGE_CSR); 252 253 return; 254 } 255 256 static void 257 nge_eeprom_idle(sc) 258 struct nge_softc *sc; 259 { 260 register int i; 261 262 SIO_SET(NGE_MEAR_EE_CSEL); 263 nge_delay(sc); 264 SIO_SET(NGE_MEAR_EE_CLK); 265 nge_delay(sc); 266 267 for (i = 0; i < 25; i++) { 268 SIO_CLR(NGE_MEAR_EE_CLK); 269 nge_delay(sc); 270 SIO_SET(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 } 273 274 SIO_CLR(NGE_MEAR_EE_CLK); 275 nge_delay(sc); 276 SIO_CLR(NGE_MEAR_EE_CSEL); 277 nge_delay(sc); 278 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 279 280 return; 281 } 282 283 /* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286 static void 287 nge_eeprom_putbyte(sc, addr) 288 struct nge_softc *sc; 289 int addr; 290 { 291 register int d, i; 292 293 d = addr | NGE_EECMD_READ; 294 295 /* 296 * Feed in each bit and stobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 SIO_SET(NGE_MEAR_EE_DIN); 301 } else { 302 SIO_CLR(NGE_MEAR_EE_DIN); 303 } 304 nge_delay(sc); 305 SIO_SET(NGE_MEAR_EE_CLK); 306 nge_delay(sc); 307 SIO_CLR(NGE_MEAR_EE_CLK); 308 nge_delay(sc); 309 } 310 311 return; 312 } 313 314 /* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317 static void 318 nge_eeprom_getword(sc, addr, dest) 319 struct nge_softc *sc; 320 int addr; 321 u_int16_t *dest; 322 { 323 register int i; 324 u_int16_t word = 0; 325 326 /* Force EEPROM to idle state. */ 327 nge_eeprom_idle(sc); 328 329 /* Enter EEPROM access mode. */ 330 nge_delay(sc); 331 SIO_CLR(NGE_MEAR_EE_CLK); 332 nge_delay(sc); 333 SIO_SET(NGE_MEAR_EE_CSEL); 334 nge_delay(sc); 335 336 /* 337 * Send address of word we want to read. 338 */ 339 nge_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_SET(NGE_MEAR_EE_CLK); 346 nge_delay(sc); 347 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 348 word |= i; 349 nge_delay(sc); 350 SIO_CLR(NGE_MEAR_EE_CLK); 351 nge_delay(sc); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 nge_eeprom_idle(sc); 356 357 *dest = word; 358 359 return; 360 } 361 362 /* 363 * Read a sequence of words from the EEPROM. 364 */ 365 static void 366 nge_read_eeprom(sc, dest, off, cnt, swap) 367 struct nge_softc *sc; 368 caddr_t dest; 369 int off; 370 int cnt; 371 int swap; 372 { 373 int i; 374 u_int16_t word = 0, *ptr; 375 376 for (i = 0; i < cnt; i++) { 377 nge_eeprom_getword(sc, off + i, &word); 378 ptr = (u_int16_t *)(dest + (i * 2)); 379 if (swap) 380 *ptr = ntohs(word); 381 else 382 *ptr = word; 383 } 384 385 return; 386 } 387 388 /* 389 * Sync the PHYs by setting data bit and strobing the clock 32 times. 390 */ 391 static void 392 nge_mii_sync(sc) 393 struct nge_softc *sc; 394 { 395 register int i; 396 397 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 398 399 for (i = 0; i < 32; i++) { 400 SIO_SET(NGE_MEAR_MII_CLK); 401 DELAY(1); 402 SIO_CLR(NGE_MEAR_MII_CLK); 403 DELAY(1); 404 } 405 406 return; 407 } 408 409 /* 410 * Clock a series of bits through the MII. 411 */ 412 static void 413 nge_mii_send(sc, bits, cnt) 414 struct nge_softc *sc; 415 u_int32_t bits; 416 int cnt; 417 { 418 int i; 419 420 SIO_CLR(NGE_MEAR_MII_CLK); 421 422 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 423 if (bits & i) { 424 SIO_SET(NGE_MEAR_MII_DATA); 425 } else { 426 SIO_CLR(NGE_MEAR_MII_DATA); 427 } 428 DELAY(1); 429 SIO_CLR(NGE_MEAR_MII_CLK); 430 DELAY(1); 431 SIO_SET(NGE_MEAR_MII_CLK); 432 } 433 } 434 435 /* 436 * Read an PHY register through the MII. 437 */ 438 static int 439 nge_mii_readreg(sc, frame) 440 struct nge_softc *sc; 441 struct nge_mii_frame *frame; 442 443 { 444 int i, ack, s; 445 446 s = splimp(); 447 448 /* 449 * Set up frame for RX. 450 */ 451 frame->mii_stdelim = NGE_MII_STARTDELIM; 452 frame->mii_opcode = NGE_MII_READOP; 453 frame->mii_turnaround = 0; 454 frame->mii_data = 0; 455 456 CSR_WRITE_4(sc, NGE_MEAR, 0); 457 458 /* 459 * Turn on data xmit. 460 */ 461 SIO_SET(NGE_MEAR_MII_DIR); 462 463 nge_mii_sync(sc); 464 465 /* 466 * Send command/address info. 467 */ 468 nge_mii_send(sc, frame->mii_stdelim, 2); 469 nge_mii_send(sc, frame->mii_opcode, 2); 470 nge_mii_send(sc, frame->mii_phyaddr, 5); 471 nge_mii_send(sc, frame->mii_regaddr, 5); 472 473 /* Idle bit */ 474 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 475 DELAY(1); 476 SIO_SET(NGE_MEAR_MII_CLK); 477 DELAY(1); 478 479 /* Turn off xmit. */ 480 SIO_CLR(NGE_MEAR_MII_DIR); 481 /* Check for ack */ 482 SIO_CLR(NGE_MEAR_MII_CLK); 483 DELAY(1); 484 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 485 SIO_SET(NGE_MEAR_MII_CLK); 486 DELAY(1); 487 488 /* 489 * Now try reading data bits. If the ack failed, we still 490 * need to clock through 16 cycles to keep the PHY(s) in sync. 491 */ 492 if (ack) { 493 for(i = 0; i < 16; i++) { 494 SIO_CLR(NGE_MEAR_MII_CLK); 495 DELAY(1); 496 SIO_SET(NGE_MEAR_MII_CLK); 497 DELAY(1); 498 } 499 goto fail; 500 } 501 502 for (i = 0x8000; i; i >>= 1) { 503 SIO_CLR(NGE_MEAR_MII_CLK); 504 DELAY(1); 505 if (!ack) { 506 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 507 frame->mii_data |= i; 508 DELAY(1); 509 } 510 SIO_SET(NGE_MEAR_MII_CLK); 511 DELAY(1); 512 } 513 514 fail: 515 516 SIO_CLR(NGE_MEAR_MII_CLK); 517 DELAY(1); 518 SIO_SET(NGE_MEAR_MII_CLK); 519 DELAY(1); 520 521 splx(s); 522 523 if (ack) 524 return(1); 525 return(0); 526 } 527 528 /* 529 * Write to a PHY register through the MII. 530 */ 531 static int 532 nge_mii_writereg(sc, frame) 533 struct nge_softc *sc; 534 struct nge_mii_frame *frame; 535 536 { 537 int s; 538 539 s = splimp(); 540 /* 541 * Set up frame for TX. 542 */ 543 544 frame->mii_stdelim = NGE_MII_STARTDELIM; 545 frame->mii_opcode = NGE_MII_WRITEOP; 546 frame->mii_turnaround = NGE_MII_TURNAROUND; 547 548 /* 549 * Turn on data output. 550 */ 551 SIO_SET(NGE_MEAR_MII_DIR); 552 553 nge_mii_sync(sc); 554 555 nge_mii_send(sc, frame->mii_stdelim, 2); 556 nge_mii_send(sc, frame->mii_opcode, 2); 557 nge_mii_send(sc, frame->mii_phyaddr, 5); 558 nge_mii_send(sc, frame->mii_regaddr, 5); 559 nge_mii_send(sc, frame->mii_turnaround, 2); 560 nge_mii_send(sc, frame->mii_data, 16); 561 562 /* Idle bit. */ 563 SIO_SET(NGE_MEAR_MII_CLK); 564 DELAY(1); 565 SIO_CLR(NGE_MEAR_MII_CLK); 566 DELAY(1); 567 568 /* 569 * Turn off xmit. 570 */ 571 SIO_CLR(NGE_MEAR_MII_DIR); 572 573 splx(s); 574 575 return(0); 576 } 577 578 static int 579 nge_miibus_readreg(dev, phy, reg) 580 device_t dev; 581 int phy, reg; 582 { 583 struct nge_softc *sc; 584 struct nge_mii_frame frame; 585 586 sc = device_get_softc(dev); 587 588 bzero((char *)&frame, sizeof(frame)); 589 590 frame.mii_phyaddr = phy; 591 frame.mii_regaddr = reg; 592 nge_mii_readreg(sc, &frame); 593 594 return(frame.mii_data); 595 } 596 597 static int 598 nge_miibus_writereg(dev, phy, reg, data) 599 device_t dev; 600 int phy, reg, data; 601 { 602 struct nge_softc *sc; 603 struct nge_mii_frame frame; 604 605 sc = device_get_softc(dev); 606 607 bzero((char *)&frame, sizeof(frame)); 608 609 frame.mii_phyaddr = phy; 610 frame.mii_regaddr = reg; 611 frame.mii_data = data; 612 nge_mii_writereg(sc, &frame); 613 614 return(0); 615 } 616 617 static void 618 nge_miibus_statchg(dev) 619 device_t dev; 620 { 621 int status; 622 struct nge_softc *sc; 623 struct mii_data *mii; 624 625 sc = device_get_softc(dev); 626 if (sc->nge_tbi) { 627 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 628 == IFM_AUTO) { 629 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 630 if (status == 0 || status & NGE_TBIANAR_FDX) { 631 NGE_SETBIT(sc, NGE_TX_CFG, 632 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 633 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 634 } else { 635 NGE_CLRBIT(sc, NGE_TX_CFG, 636 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 637 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 638 } 639 640 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 641 != IFM_FDX) { 642 NGE_CLRBIT(sc, NGE_TX_CFG, 643 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 644 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 645 } else { 646 NGE_SETBIT(sc, NGE_TX_CFG, 647 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 648 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 649 } 650 } else { 651 mii = device_get_softc(sc->nge_miibus); 652 653 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 654 NGE_SETBIT(sc, NGE_TX_CFG, 655 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 656 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 657 } else { 658 NGE_CLRBIT(sc, NGE_TX_CFG, 659 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 660 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 661 } 662 663 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 664 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 665 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 666 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 667 } else { 668 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 669 } 670 } 671 return; 672 } 673 674 static void 675 nge_setmulti(sc) 676 struct nge_softc *sc; 677 { 678 struct ifnet *ifp; 679 struct ifmultiaddr *ifma; 680 u_int32_t h = 0, i, filtsave; 681 int bit, index; 682 683 ifp = &sc->arpcom.ac_if; 684 685 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 686 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 687 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 688 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 689 return; 690 } 691 692 /* 693 * We have to explicitly enable the multicast hash table 694 * on the NatSemi chip if we want to use it, which we do. 695 * We also have to tell it that we don't want to use the 696 * hash table for matching unicast addresses. 697 */ 698 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 699 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 700 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 701 702 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 703 704 /* first, zot all the existing hash bits */ 705 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 706 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 707 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 708 } 709 710 /* 711 * From the 11 bits returned by the crc routine, the top 7 712 * bits represent the 16-bit word in the mcast hash table 713 * that needs to be updated, and the lower 4 bits represent 714 * which bit within that byte needs to be set. 715 */ 716 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 717 if (ifma->ifma_addr->sa_family != AF_LINK) 718 continue; 719 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 720 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 721 index = (h >> 4) & 0x7F; 722 bit = h & 0xF; 723 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 724 NGE_FILTADDR_MCAST_LO + (index * 2)); 725 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 726 } 727 728 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 729 730 return; 731 } 732 733 static void 734 nge_reset(sc) 735 struct nge_softc *sc; 736 { 737 register int i; 738 739 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 740 741 for (i = 0; i < NGE_TIMEOUT; i++) { 742 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 743 break; 744 } 745 746 if (i == NGE_TIMEOUT) 747 printf("nge%d: reset never completed\n", sc->nge_unit); 748 749 /* Wait a little while for the chip to get its brains in order. */ 750 DELAY(1000); 751 752 /* 753 * If this is a NetSemi chip, make sure to clear 754 * PME mode. 755 */ 756 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 757 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 758 759 return; 760 } 761 762 /* 763 * Probe for a NatSemi chip. Check the PCI vendor and device 764 * IDs against our list and return a device name if we find a match. 765 */ 766 static int 767 nge_probe(dev) 768 device_t dev; 769 { 770 struct nge_type *t; 771 772 t = nge_devs; 773 774 while(t->nge_name != NULL) { 775 if ((pci_get_vendor(dev) == t->nge_vid) && 776 (pci_get_device(dev) == t->nge_did)) { 777 device_set_desc(dev, t->nge_name); 778 return(0); 779 } 780 t++; 781 } 782 783 return(ENXIO); 784 } 785 786 /* 787 * Attach the interface. Allocate softc structures, do ifmedia 788 * setup and ethernet/BPF attach. 789 */ 790 static int 791 nge_attach(dev) 792 device_t dev; 793 { 794 int s; 795 u_char eaddr[ETHER_ADDR_LEN]; 796 struct nge_softc *sc; 797 struct ifnet *ifp; 798 int unit, error = 0, rid; 799 const char *sep = ""; 800 801 s = splimp(); 802 803 sc = device_get_softc(dev); 804 unit = device_get_unit(dev); 805 bzero(sc, sizeof(struct nge_softc)); 806 807 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 808 MTX_DEF | MTX_RECURSE); 809 /* 810 * Map control/status registers. 811 */ 812 pci_enable_busmaster(dev); 813 814 rid = NGE_RID; 815 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 816 817 if (sc->nge_res == NULL) { 818 printf("nge%d: couldn't map ports/memory\n", unit); 819 error = ENXIO; 820 goto fail; 821 } 822 823 sc->nge_btag = rman_get_bustag(sc->nge_res); 824 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 825 826 /* Allocate interrupt */ 827 rid = 0; 828 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 829 RF_SHAREABLE | RF_ACTIVE); 830 831 if (sc->nge_irq == NULL) { 832 printf("nge%d: couldn't map interrupt\n", unit); 833 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 834 error = ENXIO; 835 goto fail; 836 } 837 838 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 839 nge_intr, sc, &sc->nge_intrhand); 840 841 if (error) { 842 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 843 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 844 printf("nge%d: couldn't set up irq\n", unit); 845 goto fail; 846 } 847 848 /* Reset the adapter. */ 849 nge_reset(sc); 850 851 /* 852 * Get station address from the EEPROM. 853 */ 854 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 855 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 856 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 857 858 sc->nge_unit = unit; 859 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 860 861 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 862 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 863 864 if (sc->nge_ldata == NULL) { 865 printf("nge%d: no memory for list buffers!\n", unit); 866 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 867 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 868 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 869 error = ENXIO; 870 goto fail; 871 } 872 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 873 874 /* Try to allocate memory for jumbo buffers. */ 875 if (nge_alloc_jumbo_mem(sc)) { 876 printf("nge%d: jumbo buffer allocation failed\n", 877 sc->nge_unit); 878 contigfree(sc->nge_ldata, 879 sizeof(struct nge_list_data), M_DEVBUF); 880 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 881 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 882 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 883 error = ENXIO; 884 goto fail; 885 } 886 887 ifp = &sc->arpcom.ac_if; 888 ifp->if_softc = sc; 889 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 890 ifp->if_mtu = ETHERMTU; 891 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 892 IFF_NEEDSGIANT; 893 ifp->if_ioctl = nge_ioctl; 894 ifp->if_start = nge_start; 895 ifp->if_watchdog = nge_watchdog; 896 ifp->if_init = nge_init; 897 ifp->if_baudrate = 1000000000; 898 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 899 ifp->if_hwassist = NGE_CSUM_FEATURES; 900 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 901 #ifdef DEVICE_POLLING 902 ifp->if_capabilities |= IFCAP_POLLING; 903 #endif 904 ifp->if_capenable = ifp->if_capabilities; 905 906 /* 907 * Do MII setup. 908 */ 909 if (mii_phy_probe(dev, &sc->nge_miibus, 910 nge_ifmedia_upd, nge_ifmedia_sts)) { 911 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 912 sc->nge_tbi = 1; 913 device_printf(dev, "Using TBI\n"); 914 915 sc->nge_miibus = dev; 916 917 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 918 nge_ifmedia_sts); 919 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 920 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 921 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 922 device_printf(dev, " "); 923 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 924 PRINT("1000baseSX"); 925 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 926 PRINT("1000baseSX-FDX"); 927 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 928 PRINT("auto"); 929 930 printf("\n"); 931 #undef ADD 932 #undef PRINT 933 ifmedia_set(&sc->nge_ifmedia, 934 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 935 936 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 937 | NGE_GPIO_GP4_OUT 938 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 939 | NGE_GPIO_GP3_OUTENB 940 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 941 942 } else { 943 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 944 nge_free_jumbo_mem(sc); 945 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 946 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 947 bus_release_resource(dev, NGE_RES, NGE_RID, 948 sc->nge_res); 949 error = ENXIO; 950 goto fail; 951 } 952 } 953 954 /* 955 * Call MI attach routine. 956 */ 957 ether_ifattach(ifp, eaddr); 958 callout_handle_init(&sc->nge_stat_ch); 959 960 fail: 961 962 splx(s); 963 mtx_destroy(&sc->nge_mtx); 964 return(error); 965 } 966 967 static int 968 nge_detach(dev) 969 device_t dev; 970 { 971 struct nge_softc *sc; 972 struct ifnet *ifp; 973 int s; 974 975 s = splimp(); 976 977 sc = device_get_softc(dev); 978 ifp = &sc->arpcom.ac_if; 979 980 nge_reset(sc); 981 nge_stop(sc); 982 ether_ifdetach(ifp); 983 984 bus_generic_detach(dev); 985 if (!sc->nge_tbi) { 986 device_delete_child(dev, sc->nge_miibus); 987 } 988 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 989 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 990 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 991 992 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 993 nge_free_jumbo_mem(sc); 994 995 splx(s); 996 mtx_destroy(&sc->nge_mtx); 997 998 return(0); 999 } 1000 1001 /* 1002 * Initialize the transmit descriptors. 1003 */ 1004 static int 1005 nge_list_tx_init(sc) 1006 struct nge_softc *sc; 1007 { 1008 struct nge_list_data *ld; 1009 struct nge_ring_data *cd; 1010 int i; 1011 1012 cd = &sc->nge_cdata; 1013 ld = sc->nge_ldata; 1014 1015 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1016 if (i == (NGE_TX_LIST_CNT - 1)) { 1017 ld->nge_tx_list[i].nge_nextdesc = 1018 &ld->nge_tx_list[0]; 1019 ld->nge_tx_list[i].nge_next = 1020 vtophys(&ld->nge_tx_list[0]); 1021 } else { 1022 ld->nge_tx_list[i].nge_nextdesc = 1023 &ld->nge_tx_list[i + 1]; 1024 ld->nge_tx_list[i].nge_next = 1025 vtophys(&ld->nge_tx_list[i + 1]); 1026 } 1027 ld->nge_tx_list[i].nge_mbuf = NULL; 1028 ld->nge_tx_list[i].nge_ptr = 0; 1029 ld->nge_tx_list[i].nge_ctl = 0; 1030 } 1031 1032 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1033 1034 return(0); 1035 } 1036 1037 1038 /* 1039 * Initialize the RX descriptors and allocate mbufs for them. Note that 1040 * we arrange the descriptors in a closed ring, so that the last descriptor 1041 * points back to the first. 1042 */ 1043 static int 1044 nge_list_rx_init(sc) 1045 struct nge_softc *sc; 1046 { 1047 struct nge_list_data *ld; 1048 struct nge_ring_data *cd; 1049 int i; 1050 1051 ld = sc->nge_ldata; 1052 cd = &sc->nge_cdata; 1053 1054 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1055 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1056 return(ENOBUFS); 1057 if (i == (NGE_RX_LIST_CNT - 1)) { 1058 ld->nge_rx_list[i].nge_nextdesc = 1059 &ld->nge_rx_list[0]; 1060 ld->nge_rx_list[i].nge_next = 1061 vtophys(&ld->nge_rx_list[0]); 1062 } else { 1063 ld->nge_rx_list[i].nge_nextdesc = 1064 &ld->nge_rx_list[i + 1]; 1065 ld->nge_rx_list[i].nge_next = 1066 vtophys(&ld->nge_rx_list[i + 1]); 1067 } 1068 } 1069 1070 cd->nge_rx_prod = 0; 1071 1072 return(0); 1073 } 1074 1075 /* 1076 * Initialize an RX descriptor and attach an MBUF cluster. 1077 */ 1078 static int 1079 nge_newbuf(sc, c, m) 1080 struct nge_softc *sc; 1081 struct nge_desc *c; 1082 struct mbuf *m; 1083 { 1084 struct mbuf *m_new = NULL; 1085 caddr_t *buf = NULL; 1086 1087 if (m == NULL) { 1088 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1089 if (m_new == NULL) { 1090 printf("nge%d: no memory for rx list " 1091 "-- packet dropped!\n", sc->nge_unit); 1092 return(ENOBUFS); 1093 } 1094 1095 /* Allocate the jumbo buffer */ 1096 buf = nge_jalloc(sc); 1097 if (buf == NULL) { 1098 #ifdef NGE_VERBOSE 1099 printf("nge%d: jumbo allocation failed " 1100 "-- packet dropped!\n", sc->nge_unit); 1101 #endif 1102 m_freem(m_new); 1103 return(ENOBUFS); 1104 } 1105 /* Attach the buffer to the mbuf */ 1106 m_new->m_data = (void *)buf; 1107 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1108 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1109 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1110 } else { 1111 m_new = m; 1112 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1113 m_new->m_data = m_new->m_ext.ext_buf; 1114 } 1115 1116 m_adj(m_new, sizeof(u_int64_t)); 1117 1118 c->nge_mbuf = m_new; 1119 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1120 c->nge_ctl = m_new->m_len; 1121 c->nge_extsts = 0; 1122 1123 return(0); 1124 } 1125 1126 static int 1127 nge_alloc_jumbo_mem(sc) 1128 struct nge_softc *sc; 1129 { 1130 caddr_t ptr; 1131 register int i; 1132 struct nge_jpool_entry *entry; 1133 1134 /* Grab a big chunk o' storage. */ 1135 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1136 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1137 1138 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1139 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1140 return(ENOBUFS); 1141 } 1142 1143 SLIST_INIT(&sc->nge_jfree_listhead); 1144 SLIST_INIT(&sc->nge_jinuse_listhead); 1145 1146 /* 1147 * Now divide it up into 9K pieces and save the addresses 1148 * in an array. 1149 */ 1150 ptr = sc->nge_cdata.nge_jumbo_buf; 1151 for (i = 0; i < NGE_JSLOTS; i++) { 1152 sc->nge_cdata.nge_jslots[i] = ptr; 1153 ptr += NGE_JLEN; 1154 entry = malloc(sizeof(struct nge_jpool_entry), 1155 M_DEVBUF, M_NOWAIT); 1156 if (entry == NULL) { 1157 printf("nge%d: no memory for jumbo " 1158 "buffer queue!\n", sc->nge_unit); 1159 return(ENOBUFS); 1160 } 1161 entry->slot = i; 1162 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1163 entry, jpool_entries); 1164 } 1165 1166 return(0); 1167 } 1168 1169 static void 1170 nge_free_jumbo_mem(sc) 1171 struct nge_softc *sc; 1172 { 1173 register int i; 1174 struct nge_jpool_entry *entry; 1175 1176 for (i = 0; i < NGE_JSLOTS; i++) { 1177 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1178 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1179 free(entry, M_DEVBUF); 1180 } 1181 1182 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1183 1184 return; 1185 } 1186 1187 /* 1188 * Allocate a jumbo buffer. 1189 */ 1190 static void * 1191 nge_jalloc(sc) 1192 struct nge_softc *sc; 1193 { 1194 struct nge_jpool_entry *entry; 1195 1196 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1197 1198 if (entry == NULL) { 1199 #ifdef NGE_VERBOSE 1200 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1201 #endif 1202 return(NULL); 1203 } 1204 1205 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1206 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1207 return(sc->nge_cdata.nge_jslots[entry->slot]); 1208 } 1209 1210 /* 1211 * Release a jumbo buffer. 1212 */ 1213 static void 1214 nge_jfree(buf, args) 1215 void *buf; 1216 void *args; 1217 { 1218 struct nge_softc *sc; 1219 int i; 1220 struct nge_jpool_entry *entry; 1221 1222 /* Extract the softc struct pointer. */ 1223 sc = args; 1224 1225 if (sc == NULL) 1226 panic("nge_jfree: can't find softc pointer!"); 1227 1228 /* calculate the slot this buffer belongs to */ 1229 i = ((vm_offset_t)buf 1230 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1231 1232 if ((i < 0) || (i >= NGE_JSLOTS)) 1233 panic("nge_jfree: asked to free buffer that we don't manage!"); 1234 1235 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1236 if (entry == NULL) 1237 panic("nge_jfree: buffer not in use!"); 1238 entry->slot = i; 1239 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1240 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1241 1242 return; 1243 } 1244 /* 1245 * A frame has been uploaded: pass the resulting mbuf chain up to 1246 * the higher level protocols. 1247 */ 1248 static void 1249 nge_rxeof(sc) 1250 struct nge_softc *sc; 1251 { 1252 struct mbuf *m; 1253 struct ifnet *ifp; 1254 struct nge_desc *cur_rx; 1255 int i, total_len = 0; 1256 u_int32_t rxstat; 1257 1258 ifp = &sc->arpcom.ac_if; 1259 i = sc->nge_cdata.nge_rx_prod; 1260 1261 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1262 struct mbuf *m0 = NULL; 1263 u_int32_t extsts; 1264 1265 #ifdef DEVICE_POLLING 1266 if (ifp->if_flags & IFF_POLLING) { 1267 if (sc->rxcycles <= 0) 1268 break; 1269 sc->rxcycles--; 1270 } 1271 #endif /* DEVICE_POLLING */ 1272 1273 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1274 rxstat = cur_rx->nge_rxstat; 1275 extsts = cur_rx->nge_extsts; 1276 m = cur_rx->nge_mbuf; 1277 cur_rx->nge_mbuf = NULL; 1278 total_len = NGE_RXBYTES(cur_rx); 1279 NGE_INC(i, NGE_RX_LIST_CNT); 1280 /* 1281 * If an error occurs, update stats, clear the 1282 * status word and leave the mbuf cluster in place: 1283 * it should simply get re-used next time this descriptor 1284 * comes up in the ring. 1285 */ 1286 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1287 ifp->if_ierrors++; 1288 nge_newbuf(sc, cur_rx, m); 1289 continue; 1290 } 1291 1292 /* 1293 * Ok. NatSemi really screwed up here. This is the 1294 * only gigE chip I know of with alignment constraints 1295 * on receive buffers. RX buffers must be 64-bit aligned. 1296 */ 1297 #ifdef __i386__ 1298 /* 1299 * By popular demand, ignore the alignment problems 1300 * on the Intel x86 platform. The performance hit 1301 * incurred due to unaligned accesses is much smaller 1302 * than the hit produced by forcing buffer copies all 1303 * the time, especially with jumbo frames. We still 1304 * need to fix up the alignment everywhere else though. 1305 */ 1306 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1307 #endif 1308 m0 = m_devget(mtod(m, char *), total_len, 1309 ETHER_ALIGN, ifp, NULL); 1310 nge_newbuf(sc, cur_rx, m); 1311 if (m0 == NULL) { 1312 printf("nge%d: no receive buffers " 1313 "available -- packet dropped!\n", 1314 sc->nge_unit); 1315 ifp->if_ierrors++; 1316 continue; 1317 } 1318 m = m0; 1319 #ifdef __i386__ 1320 } else { 1321 m->m_pkthdr.rcvif = ifp; 1322 m->m_pkthdr.len = m->m_len = total_len; 1323 } 1324 #endif 1325 1326 ifp->if_ipackets++; 1327 1328 /* Do IP checksum checking. */ 1329 if (extsts & NGE_RXEXTSTS_IPPKT) 1330 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1331 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1332 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1333 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1334 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1335 (extsts & NGE_RXEXTSTS_UDPPKT && 1336 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1337 m->m_pkthdr.csum_flags |= 1338 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1339 m->m_pkthdr.csum_data = 0xffff; 1340 } 1341 1342 /* 1343 * If we received a packet with a vlan tag, pass it 1344 * to vlan_input() instead of ether_input(). 1345 */ 1346 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1347 VLAN_INPUT_TAG(ifp, m, 1348 ntohs(extsts & NGE_RXEXTSTS_VTCI), continue); 1349 } 1350 1351 (*ifp->if_input)(ifp, m); 1352 } 1353 1354 sc->nge_cdata.nge_rx_prod = i; 1355 1356 return; 1357 } 1358 1359 /* 1360 * A frame was downloaded to the chip. It's safe for us to clean up 1361 * the list buffers. 1362 */ 1363 1364 static void 1365 nge_txeof(sc) 1366 struct nge_softc *sc; 1367 { 1368 struct nge_desc *cur_tx; 1369 struct ifnet *ifp; 1370 u_int32_t idx; 1371 1372 ifp = &sc->arpcom.ac_if; 1373 1374 /* 1375 * Go through our tx list and free mbufs for those 1376 * frames that have been transmitted. 1377 */ 1378 idx = sc->nge_cdata.nge_tx_cons; 1379 while (idx != sc->nge_cdata.nge_tx_prod) { 1380 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1381 1382 if (NGE_OWNDESC(cur_tx)) 1383 break; 1384 1385 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1386 sc->nge_cdata.nge_tx_cnt--; 1387 NGE_INC(idx, NGE_TX_LIST_CNT); 1388 continue; 1389 } 1390 1391 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1392 ifp->if_oerrors++; 1393 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1394 ifp->if_collisions++; 1395 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1396 ifp->if_collisions++; 1397 } 1398 1399 ifp->if_collisions += 1400 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1401 1402 ifp->if_opackets++; 1403 if (cur_tx->nge_mbuf != NULL) { 1404 m_freem(cur_tx->nge_mbuf); 1405 cur_tx->nge_mbuf = NULL; 1406 ifp->if_flags &= ~IFF_OACTIVE; 1407 } 1408 1409 sc->nge_cdata.nge_tx_cnt--; 1410 NGE_INC(idx, NGE_TX_LIST_CNT); 1411 } 1412 1413 sc->nge_cdata.nge_tx_cons = idx; 1414 1415 if (idx == sc->nge_cdata.nge_tx_prod) 1416 ifp->if_timer = 0; 1417 1418 return; 1419 } 1420 1421 static void 1422 nge_tick(xsc) 1423 void *xsc; 1424 { 1425 struct nge_softc *sc; 1426 struct mii_data *mii; 1427 struct ifnet *ifp; 1428 int s; 1429 1430 s = splimp(); 1431 1432 sc = xsc; 1433 ifp = &sc->arpcom.ac_if; 1434 1435 if (sc->nge_tbi) { 1436 if (!sc->nge_link) { 1437 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1438 & NGE_TBIBMSR_ANEG_DONE) { 1439 printf("nge%d: gigabit link up\n", 1440 sc->nge_unit); 1441 nge_miibus_statchg(sc->nge_miibus); 1442 sc->nge_link++; 1443 if (ifp->if_snd.ifq_head != NULL) 1444 nge_start(ifp); 1445 } 1446 } 1447 } else { 1448 mii = device_get_softc(sc->nge_miibus); 1449 mii_tick(mii); 1450 1451 if (!sc->nge_link) { 1452 if (mii->mii_media_status & IFM_ACTIVE && 1453 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1454 sc->nge_link++; 1455 if (IFM_SUBTYPE(mii->mii_media_active) 1456 == IFM_1000_T) 1457 printf("nge%d: gigabit link up\n", 1458 sc->nge_unit); 1459 if (ifp->if_snd.ifq_head != NULL) 1460 nge_start(ifp); 1461 } 1462 } 1463 } 1464 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1465 1466 splx(s); 1467 1468 return; 1469 } 1470 1471 #ifdef DEVICE_POLLING 1472 static poll_handler_t nge_poll; 1473 1474 static void 1475 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1476 { 1477 struct nge_softc *sc = ifp->if_softc; 1478 1479 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1480 ether_poll_deregister(ifp); 1481 cmd = POLL_DEREGISTER; 1482 } 1483 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1484 CSR_WRITE_4(sc, NGE_IER, 1); 1485 return; 1486 } 1487 1488 /* 1489 * On the nge, reading the status register also clears it. 1490 * So before returning to intr mode we must make sure that all 1491 * possible pending sources of interrupts have been served. 1492 * In practice this means run to completion the *eof routines, 1493 * and then call the interrupt routine 1494 */ 1495 sc->rxcycles = count; 1496 nge_rxeof(sc); 1497 nge_txeof(sc); 1498 if (ifp->if_snd.ifq_head != NULL) 1499 nge_start(ifp); 1500 1501 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1502 u_int32_t status; 1503 1504 /* Reading the ISR register clears all interrupts. */ 1505 status = CSR_READ_4(sc, NGE_ISR); 1506 1507 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1508 nge_rxeof(sc); 1509 1510 if (status & (NGE_ISR_RX_IDLE)) 1511 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1512 1513 if (status & NGE_ISR_SYSERR) { 1514 nge_reset(sc); 1515 nge_init(sc); 1516 } 1517 } 1518 } 1519 #endif /* DEVICE_POLLING */ 1520 1521 static void 1522 nge_intr(arg) 1523 void *arg; 1524 { 1525 struct nge_softc *sc; 1526 struct ifnet *ifp; 1527 u_int32_t status; 1528 1529 sc = arg; 1530 ifp = &sc->arpcom.ac_if; 1531 1532 #ifdef DEVICE_POLLING 1533 if (ifp->if_flags & IFF_POLLING) 1534 return; 1535 if ((ifp->if_capenable & IFCAP_POLLING) && 1536 ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1537 CSR_WRITE_4(sc, NGE_IER, 0); 1538 nge_poll(ifp, 0, 1); 1539 return; 1540 } 1541 #endif /* DEVICE_POLLING */ 1542 1543 /* Supress unwanted interrupts */ 1544 if (!(ifp->if_flags & IFF_UP)) { 1545 nge_stop(sc); 1546 return; 1547 } 1548 1549 /* Disable interrupts. */ 1550 CSR_WRITE_4(sc, NGE_IER, 0); 1551 1552 /* Data LED on for TBI mode */ 1553 if(sc->nge_tbi) 1554 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1555 | NGE_GPIO_GP3_OUT); 1556 1557 for (;;) { 1558 /* Reading the ISR register clears all interrupts. */ 1559 status = CSR_READ_4(sc, NGE_ISR); 1560 1561 if ((status & NGE_INTRS) == 0) 1562 break; 1563 1564 if ((status & NGE_ISR_TX_DESC_OK) || 1565 (status & NGE_ISR_TX_ERR) || 1566 (status & NGE_ISR_TX_OK) || 1567 (status & NGE_ISR_TX_IDLE)) 1568 nge_txeof(sc); 1569 1570 if ((status & NGE_ISR_RX_DESC_OK) || 1571 (status & NGE_ISR_RX_ERR) || 1572 (status & NGE_ISR_RX_OFLOW) || 1573 (status & NGE_ISR_RX_FIFO_OFLOW) || 1574 (status & NGE_ISR_RX_IDLE) || 1575 (status & NGE_ISR_RX_OK)) 1576 nge_rxeof(sc); 1577 1578 if ((status & NGE_ISR_RX_IDLE)) 1579 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1580 1581 if (status & NGE_ISR_SYSERR) { 1582 nge_reset(sc); 1583 ifp->if_flags &= ~IFF_RUNNING; 1584 nge_init(sc); 1585 } 1586 1587 #if 0 1588 /* 1589 * XXX: nge_tick() is not ready to be called this way 1590 * it screws up the aneg timeout because mii_tick() is 1591 * only to be called once per second. 1592 */ 1593 if (status & NGE_IMR_PHY_INTR) { 1594 sc->nge_link = 0; 1595 nge_tick(sc); 1596 } 1597 #endif 1598 } 1599 1600 /* Re-enable interrupts. */ 1601 CSR_WRITE_4(sc, NGE_IER, 1); 1602 1603 if (ifp->if_snd.ifq_head != NULL) 1604 nge_start(ifp); 1605 1606 /* Data LED off for TBI mode */ 1607 1608 if(sc->nge_tbi) 1609 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1610 & ~NGE_GPIO_GP3_OUT); 1611 1612 return; 1613 } 1614 1615 /* 1616 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1617 * pointers to the fragment pointers. 1618 */ 1619 static int 1620 nge_encap(sc, m_head, txidx) 1621 struct nge_softc *sc; 1622 struct mbuf *m_head; 1623 u_int32_t *txidx; 1624 { 1625 struct nge_desc *f = NULL; 1626 struct mbuf *m; 1627 int frag, cur, cnt = 0; 1628 struct m_tag *mtag; 1629 1630 /* 1631 * Start packing the mbufs in this chain into 1632 * the fragment pointers. Stop when we run out 1633 * of fragments or hit the end of the mbuf chain. 1634 */ 1635 m = m_head; 1636 cur = frag = *txidx; 1637 1638 for (m = m_head; m != NULL; m = m->m_next) { 1639 if (m->m_len != 0) { 1640 if ((NGE_TX_LIST_CNT - 1641 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1642 return(ENOBUFS); 1643 f = &sc->nge_ldata->nge_tx_list[frag]; 1644 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1645 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1646 if (cnt != 0) 1647 f->nge_ctl |= NGE_CMDSTS_OWN; 1648 cur = frag; 1649 NGE_INC(frag, NGE_TX_LIST_CNT); 1650 cnt++; 1651 } 1652 } 1653 1654 if (m != NULL) 1655 return(ENOBUFS); 1656 1657 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1658 if (m_head->m_pkthdr.csum_flags) { 1659 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1660 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1661 NGE_TXEXTSTS_IPCSUM; 1662 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1663 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1664 NGE_TXEXTSTS_TCPCSUM; 1665 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1666 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1667 NGE_TXEXTSTS_UDPCSUM; 1668 } 1669 1670 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 1671 if (mtag != NULL) { 1672 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1673 (NGE_TXEXTSTS_VLANPKT|htons(VLAN_TAG_VALUE(mtag))); 1674 } 1675 1676 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1677 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1678 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1679 sc->nge_cdata.nge_tx_cnt += cnt; 1680 *txidx = frag; 1681 1682 return(0); 1683 } 1684 1685 /* 1686 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1687 * to the mbuf data regions directly in the transmit lists. We also save a 1688 * copy of the pointers since the transmit list fragment pointers are 1689 * physical addresses. 1690 */ 1691 1692 static void 1693 nge_start(ifp) 1694 struct ifnet *ifp; 1695 { 1696 struct nge_softc *sc; 1697 struct mbuf *m_head = NULL; 1698 u_int32_t idx; 1699 1700 sc = ifp->if_softc; 1701 1702 if (!sc->nge_link) 1703 return; 1704 1705 idx = sc->nge_cdata.nge_tx_prod; 1706 1707 if (ifp->if_flags & IFF_OACTIVE) 1708 return; 1709 1710 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1711 IF_DEQUEUE(&ifp->if_snd, m_head); 1712 if (m_head == NULL) 1713 break; 1714 1715 if (nge_encap(sc, m_head, &idx)) { 1716 IF_PREPEND(&ifp->if_snd, m_head); 1717 ifp->if_flags |= IFF_OACTIVE; 1718 break; 1719 } 1720 1721 /* 1722 * If there's a BPF listener, bounce a copy of this frame 1723 * to him. 1724 */ 1725 BPF_MTAP(ifp, m_head); 1726 1727 } 1728 1729 /* Transmit */ 1730 sc->nge_cdata.nge_tx_prod = idx; 1731 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1732 1733 /* 1734 * Set a timeout in case the chip goes out to lunch. 1735 */ 1736 ifp->if_timer = 5; 1737 1738 return; 1739 } 1740 1741 static void 1742 nge_init(xsc) 1743 void *xsc; 1744 { 1745 struct nge_softc *sc = xsc; 1746 struct ifnet *ifp = &sc->arpcom.ac_if; 1747 struct mii_data *mii; 1748 int s; 1749 1750 if (ifp->if_flags & IFF_RUNNING) 1751 return; 1752 1753 s = splimp(); 1754 1755 /* 1756 * Cancel pending I/O and free all RX/TX buffers. 1757 */ 1758 nge_stop(sc); 1759 1760 if (sc->nge_tbi) { 1761 mii = NULL; 1762 } else { 1763 mii = device_get_softc(sc->nge_miibus); 1764 } 1765 1766 /* Set MAC address */ 1767 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1768 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1769 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1770 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1771 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1772 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1773 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1774 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1775 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1776 1777 /* Init circular RX list. */ 1778 if (nge_list_rx_init(sc) == ENOBUFS) { 1779 printf("nge%d: initialization failed: no " 1780 "memory for rx buffers\n", sc->nge_unit); 1781 nge_stop(sc); 1782 (void)splx(s); 1783 return; 1784 } 1785 1786 /* 1787 * Init tx descriptors. 1788 */ 1789 nge_list_tx_init(sc); 1790 1791 /* 1792 * For the NatSemi chip, we have to explicitly enable the 1793 * reception of ARP frames, as well as turn on the 'perfect 1794 * match' filter where we store the station address, otherwise 1795 * we won't receive unicasts meant for this host. 1796 */ 1797 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1798 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1799 1800 /* If we want promiscuous mode, set the allframes bit. */ 1801 if (ifp->if_flags & IFF_PROMISC) { 1802 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1803 } else { 1804 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1805 } 1806 1807 /* 1808 * Set the capture broadcast bit to capture broadcast frames. 1809 */ 1810 if (ifp->if_flags & IFF_BROADCAST) { 1811 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1812 } else { 1813 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1814 } 1815 1816 /* 1817 * Load the multicast filter. 1818 */ 1819 nge_setmulti(sc); 1820 1821 /* Turn the receive filter on */ 1822 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1823 1824 /* 1825 * Load the address of the RX and TX lists. 1826 */ 1827 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1828 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1829 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1830 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1831 1832 /* Set RX configuration */ 1833 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1834 /* 1835 * Enable hardware checksum validation for all IPv4 1836 * packets, do not reject packets with bad checksums. 1837 */ 1838 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1839 1840 /* 1841 * Tell the chip to detect and strip VLAN tag info from 1842 * received frames. The tag will be provided in the extsts 1843 * field in the RX descriptors. 1844 */ 1845 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1846 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1847 1848 /* Set TX configuration */ 1849 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1850 1851 /* 1852 * Enable TX IPv4 checksumming on a per-packet basis. 1853 */ 1854 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1855 1856 /* 1857 * Tell the chip to insert VLAN tags on a per-packet basis as 1858 * dictated by the code in the frame encapsulation routine. 1859 */ 1860 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1861 1862 /* Set full/half duplex mode. */ 1863 if (sc->nge_tbi) { 1864 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1865 == IFM_FDX) { 1866 NGE_SETBIT(sc, NGE_TX_CFG, 1867 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1868 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1869 } else { 1870 NGE_CLRBIT(sc, NGE_TX_CFG, 1871 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1872 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1873 } 1874 } else { 1875 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1876 NGE_SETBIT(sc, NGE_TX_CFG, 1877 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1878 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1879 } else { 1880 NGE_CLRBIT(sc, NGE_TX_CFG, 1881 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1882 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1883 } 1884 } 1885 1886 nge_tick(sc); 1887 1888 /* 1889 * Enable the delivery of PHY interrupts based on 1890 * link/speed/duplex status changes. Also enable the 1891 * extsts field in the DMA descriptors (needed for 1892 * TCP/IP checksum offload on transmit). 1893 */ 1894 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1895 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1896 1897 /* 1898 * Configure interrupt holdoff (moderation). We can 1899 * have the chip delay interrupt delivery for a certain 1900 * period. Units are in 100us, and the max setting 1901 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1902 */ 1903 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1904 1905 /* 1906 * Enable interrupts. 1907 */ 1908 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1909 #ifdef DEVICE_POLLING 1910 /* 1911 * ... only enable interrupts if we are not polling, make sure 1912 * they are off otherwise. 1913 */ 1914 if (ifp->if_flags & IFF_POLLING) 1915 CSR_WRITE_4(sc, NGE_IER, 0); 1916 else 1917 #endif /* DEVICE_POLLING */ 1918 CSR_WRITE_4(sc, NGE_IER, 1); 1919 1920 /* Enable receiver and transmitter. */ 1921 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1922 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1923 1924 nge_ifmedia_upd(ifp); 1925 1926 ifp->if_flags |= IFF_RUNNING; 1927 ifp->if_flags &= ~IFF_OACTIVE; 1928 1929 (void)splx(s); 1930 1931 return; 1932 } 1933 1934 /* 1935 * Set media options. 1936 */ 1937 static int 1938 nge_ifmedia_upd(ifp) 1939 struct ifnet *ifp; 1940 { 1941 struct nge_softc *sc; 1942 struct mii_data *mii; 1943 1944 sc = ifp->if_softc; 1945 1946 if (sc->nge_tbi) { 1947 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1948 == IFM_AUTO) { 1949 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1950 CSR_READ_4(sc, NGE_TBI_ANAR) 1951 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 1952 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 1953 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 1954 | NGE_TBIBMCR_RESTART_ANEG); 1955 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 1956 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 1957 & IFM_GMASK) == IFM_FDX) { 1958 NGE_SETBIT(sc, NGE_TX_CFG, 1959 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1960 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1961 1962 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1963 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1964 } else { 1965 NGE_CLRBIT(sc, NGE_TX_CFG, 1966 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1967 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1968 1969 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1970 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1971 } 1972 1973 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1974 & ~NGE_GPIO_GP3_OUT); 1975 } else { 1976 mii = device_get_softc(sc->nge_miibus); 1977 sc->nge_link = 0; 1978 if (mii->mii_instance) { 1979 struct mii_softc *miisc; 1980 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1981 miisc = LIST_NEXT(miisc, mii_list)) 1982 mii_phy_reset(miisc); 1983 } 1984 mii_mediachg(mii); 1985 } 1986 1987 return(0); 1988 } 1989 1990 /* 1991 * Report current media status. 1992 */ 1993 static void 1994 nge_ifmedia_sts(ifp, ifmr) 1995 struct ifnet *ifp; 1996 struct ifmediareq *ifmr; 1997 { 1998 struct nge_softc *sc; 1999 struct mii_data *mii; 2000 2001 sc = ifp->if_softc; 2002 2003 if (sc->nge_tbi) { 2004 ifmr->ifm_status = IFM_AVALID; 2005 ifmr->ifm_active = IFM_ETHER; 2006 2007 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2008 ifmr->ifm_status |= IFM_ACTIVE; 2009 } 2010 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2011 ifmr->ifm_active |= IFM_LOOP; 2012 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2013 ifmr->ifm_active |= IFM_NONE; 2014 ifmr->ifm_status = 0; 2015 return; 2016 } 2017 ifmr->ifm_active |= IFM_1000_SX; 2018 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2019 == IFM_AUTO) { 2020 ifmr->ifm_active |= IFM_AUTO; 2021 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2022 & NGE_TBIANAR_FDX) { 2023 ifmr->ifm_active |= IFM_FDX; 2024 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2025 & NGE_TBIANAR_HDX) { 2026 ifmr->ifm_active |= IFM_HDX; 2027 } 2028 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2029 == IFM_FDX) 2030 ifmr->ifm_active |= IFM_FDX; 2031 else 2032 ifmr->ifm_active |= IFM_HDX; 2033 2034 } else { 2035 mii = device_get_softc(sc->nge_miibus); 2036 mii_pollstat(mii); 2037 ifmr->ifm_active = mii->mii_media_active; 2038 ifmr->ifm_status = mii->mii_media_status; 2039 } 2040 2041 return; 2042 } 2043 2044 static int 2045 nge_ioctl(ifp, command, data) 2046 struct ifnet *ifp; 2047 u_long command; 2048 caddr_t data; 2049 { 2050 struct nge_softc *sc = ifp->if_softc; 2051 struct ifreq *ifr = (struct ifreq *) data; 2052 struct mii_data *mii; 2053 int s, error = 0; 2054 2055 s = splimp(); 2056 2057 switch(command) { 2058 case SIOCSIFMTU: 2059 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2060 error = EINVAL; 2061 else { 2062 ifp->if_mtu = ifr->ifr_mtu; 2063 /* 2064 * Workaround: if the MTU is larger than 2065 * 8152 (TX FIFO size minus 64 minus 18), turn off 2066 * TX checksum offloading. 2067 */ 2068 if (ifr->ifr_mtu >= 8152) { 2069 ifp->if_capenable &= ~IFCAP_TXCSUM; 2070 ifp->if_hwassist = 0; 2071 } else { 2072 ifp->if_capenable |= IFCAP_TXCSUM; 2073 ifp->if_hwassist = NGE_CSUM_FEATURES; 2074 } 2075 } 2076 break; 2077 case SIOCSIFFLAGS: 2078 if (ifp->if_flags & IFF_UP) { 2079 if (ifp->if_flags & IFF_RUNNING && 2080 ifp->if_flags & IFF_PROMISC && 2081 !(sc->nge_if_flags & IFF_PROMISC)) { 2082 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2083 NGE_RXFILTCTL_ALLPHYS| 2084 NGE_RXFILTCTL_ALLMULTI); 2085 } else if (ifp->if_flags & IFF_RUNNING && 2086 !(ifp->if_flags & IFF_PROMISC) && 2087 sc->nge_if_flags & IFF_PROMISC) { 2088 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2089 NGE_RXFILTCTL_ALLPHYS); 2090 if (!(ifp->if_flags & IFF_ALLMULTI)) 2091 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2092 NGE_RXFILTCTL_ALLMULTI); 2093 } else { 2094 ifp->if_flags &= ~IFF_RUNNING; 2095 nge_init(sc); 2096 } 2097 } else { 2098 if (ifp->if_flags & IFF_RUNNING) 2099 nge_stop(sc); 2100 } 2101 sc->nge_if_flags = ifp->if_flags; 2102 error = 0; 2103 break; 2104 case SIOCADDMULTI: 2105 case SIOCDELMULTI: 2106 nge_setmulti(sc); 2107 error = 0; 2108 break; 2109 case SIOCGIFMEDIA: 2110 case SIOCSIFMEDIA: 2111 if (sc->nge_tbi) { 2112 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2113 command); 2114 } else { 2115 mii = device_get_softc(sc->nge_miibus); 2116 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2117 command); 2118 } 2119 break; 2120 case SIOCSIFCAP: 2121 ifp->if_capenable &= ~IFCAP_POLLING; 2122 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2123 break; 2124 default: 2125 error = ether_ioctl(ifp, command, data); 2126 break; 2127 } 2128 2129 (void)splx(s); 2130 2131 return(error); 2132 } 2133 2134 static void 2135 nge_watchdog(ifp) 2136 struct ifnet *ifp; 2137 { 2138 struct nge_softc *sc; 2139 2140 sc = ifp->if_softc; 2141 2142 ifp->if_oerrors++; 2143 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2144 2145 nge_stop(sc); 2146 nge_reset(sc); 2147 ifp->if_flags &= ~IFF_RUNNING; 2148 nge_init(sc); 2149 2150 if (ifp->if_snd.ifq_head != NULL) 2151 nge_start(ifp); 2152 2153 return; 2154 } 2155 2156 /* 2157 * Stop the adapter and free any mbufs allocated to the 2158 * RX and TX lists. 2159 */ 2160 static void 2161 nge_stop(sc) 2162 struct nge_softc *sc; 2163 { 2164 register int i; 2165 struct ifnet *ifp; 2166 struct mii_data *mii; 2167 2168 ifp = &sc->arpcom.ac_if; 2169 ifp->if_timer = 0; 2170 if (sc->nge_tbi) { 2171 mii = NULL; 2172 } else { 2173 mii = device_get_softc(sc->nge_miibus); 2174 } 2175 2176 untimeout(nge_tick, sc, sc->nge_stat_ch); 2177 #ifdef DEVICE_POLLING 2178 ether_poll_deregister(ifp); 2179 #endif 2180 CSR_WRITE_4(sc, NGE_IER, 0); 2181 CSR_WRITE_4(sc, NGE_IMR, 0); 2182 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2183 DELAY(1000); 2184 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2185 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2186 2187 if (!sc->nge_tbi) 2188 mii_down(mii); 2189 2190 sc->nge_link = 0; 2191 2192 /* 2193 * Free data in the RX lists. 2194 */ 2195 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2196 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2197 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2198 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2199 } 2200 } 2201 bzero((char *)&sc->nge_ldata->nge_rx_list, 2202 sizeof(sc->nge_ldata->nge_rx_list)); 2203 2204 /* 2205 * Free the TX list buffers. 2206 */ 2207 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2208 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2209 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2210 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2211 } 2212 } 2213 2214 bzero((char *)&sc->nge_ldata->nge_tx_list, 2215 sizeof(sc->nge_ldata->nge_tx_list)); 2216 2217 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2218 2219 return; 2220 } 2221 2222 /* 2223 * Stop all chip I/O so that the kernel's probe routines don't 2224 * get confused by errant DMAs when rebooting. 2225 */ 2226 static void 2227 nge_shutdown(dev) 2228 device_t dev; 2229 { 2230 struct nge_softc *sc; 2231 2232 sc = device_get_softc(dev); 2233 2234 nge_reset(sc); 2235 nge_stop(sc); 2236 2237 return; 2238 } 2239