1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/module.h> 97 #include <sys/kernel.h> 98 #include <sys/socket.h> 99 100 #include <net/if.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_types.h> 106 #include <net/if_vlan_var.h> 107 108 #include <net/bpf.h> 109 110 #include <vm/vm.h> /* for vtophys */ 111 #include <vm/pmap.h> /* for vtophys */ 112 #include <machine/clock.h> /* for DELAY */ 113 #include <machine/bus.h> 114 #include <machine/resource.h> 115 #include <sys/bus.h> 116 #include <sys/rman.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/pci/pcireg.h> 122 #include <dev/pci/pcivar.h> 123 124 #define NGE_USEIOSPACE 125 126 #include <dev/nge/if_ngereg.h> 127 128 MODULE_DEPEND(nge, pci, 1, 1, 1); 129 MODULE_DEPEND(nge, ether, 1, 1, 1); 130 MODULE_DEPEND(nge, miibus, 1, 1, 1); 131 132 /* "controller miibus0" required. See GENERIC if you get errors here. */ 133 #include "miibus_if.h" 134 135 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 136 137 /* 138 * Various supported device vendors/types and their names. 139 */ 140 static struct nge_type nge_devs[] = { 141 { NGE_VENDORID, NGE_DEVICEID, 142 "National Semiconductor Gigabit Ethernet" }, 143 { 0, 0, NULL } 144 }; 145 146 static int nge_probe(device_t); 147 static int nge_attach(device_t); 148 static int nge_detach(device_t); 149 150 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *); 151 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 152 #ifdef NGE_FIXUP_RX 153 static __inline void nge_fixup_rx (struct mbuf *); 154 #endif 155 static void nge_rxeof(struct nge_softc *); 156 static void nge_txeof(struct nge_softc *); 157 static void nge_intr(void *); 158 static void nge_tick(void *); 159 static void nge_tick_locked(struct nge_softc *); 160 static void nge_start(struct ifnet *); 161 static void nge_start_locked(struct ifnet *); 162 static int nge_ioctl(struct ifnet *, u_long, caddr_t); 163 static void nge_init(void *); 164 static void nge_init_locked(struct nge_softc *); 165 static void nge_stop(struct nge_softc *); 166 static void nge_watchdog(struct ifnet *); 167 static void nge_shutdown(device_t); 168 static int nge_ifmedia_upd(struct ifnet *); 169 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 170 171 static void nge_delay(struct nge_softc *); 172 static void nge_eeprom_idle(struct nge_softc *); 173 static void nge_eeprom_putbyte(struct nge_softc *, int); 174 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 175 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 176 177 static void nge_mii_sync(struct nge_softc *); 178 static void nge_mii_send(struct nge_softc *, u_int32_t, int); 179 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 180 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 181 182 static int nge_miibus_readreg(device_t, int, int); 183 static int nge_miibus_writereg(device_t, int, int, int); 184 static void nge_miibus_statchg(device_t); 185 186 static void nge_setmulti(struct nge_softc *); 187 static void nge_reset(struct nge_softc *); 188 static int nge_list_rx_init(struct nge_softc *); 189 static int nge_list_tx_init(struct nge_softc *); 190 191 #ifdef NGE_USEIOSPACE 192 #define NGE_RES SYS_RES_IOPORT 193 #define NGE_RID NGE_PCI_LOIO 194 #else 195 #define NGE_RES SYS_RES_MEMORY 196 #define NGE_RID NGE_PCI_LOMEM 197 #endif 198 199 static device_method_t nge_methods[] = { 200 /* Device interface */ 201 DEVMETHOD(device_probe, nge_probe), 202 DEVMETHOD(device_attach, nge_attach), 203 DEVMETHOD(device_detach, nge_detach), 204 DEVMETHOD(device_shutdown, nge_shutdown), 205 206 /* bus interface */ 207 DEVMETHOD(bus_print_child, bus_generic_print_child), 208 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 209 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 212 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 213 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 214 215 { 0, 0 } 216 }; 217 218 static driver_t nge_driver = { 219 "nge", 220 nge_methods, 221 sizeof(struct nge_softc) 222 }; 223 224 static devclass_t nge_devclass; 225 226 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 227 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 228 229 #define NGE_SETBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) | (x)) 232 233 #define NGE_CLRBIT(sc, reg, x) \ 234 CSR_WRITE_4(sc, reg, \ 235 CSR_READ_4(sc, reg) & ~(x)) 236 237 #define SIO_SET(x) \ 238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 239 240 #define SIO_CLR(x) \ 241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 242 243 static void 244 nge_delay(sc) 245 struct nge_softc *sc; 246 { 247 int idx; 248 249 for (idx = (300 / 33) + 1; idx > 0; idx--) 250 CSR_READ_4(sc, NGE_CSR); 251 252 return; 253 } 254 255 static void 256 nge_eeprom_idle(sc) 257 struct nge_softc *sc; 258 { 259 register int i; 260 261 SIO_SET(NGE_MEAR_EE_CSEL); 262 nge_delay(sc); 263 SIO_SET(NGE_MEAR_EE_CLK); 264 nge_delay(sc); 265 266 for (i = 0; i < 25; i++) { 267 SIO_CLR(NGE_MEAR_EE_CLK); 268 nge_delay(sc); 269 SIO_SET(NGE_MEAR_EE_CLK); 270 nge_delay(sc); 271 } 272 273 SIO_CLR(NGE_MEAR_EE_CLK); 274 nge_delay(sc); 275 SIO_CLR(NGE_MEAR_EE_CSEL); 276 nge_delay(sc); 277 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 278 279 return; 280 } 281 282 /* 283 * Send a read command and address to the EEPROM, check for ACK. 284 */ 285 static void 286 nge_eeprom_putbyte(sc, addr) 287 struct nge_softc *sc; 288 int addr; 289 { 290 register int d, i; 291 292 d = addr | NGE_EECMD_READ; 293 294 /* 295 * Feed in each bit and stobe the clock. 296 */ 297 for (i = 0x400; i; i >>= 1) { 298 if (d & i) { 299 SIO_SET(NGE_MEAR_EE_DIN); 300 } else { 301 SIO_CLR(NGE_MEAR_EE_DIN); 302 } 303 nge_delay(sc); 304 SIO_SET(NGE_MEAR_EE_CLK); 305 nge_delay(sc); 306 SIO_CLR(NGE_MEAR_EE_CLK); 307 nge_delay(sc); 308 } 309 310 return; 311 } 312 313 /* 314 * Read a word of data stored in the EEPROM at address 'addr.' 315 */ 316 static void 317 nge_eeprom_getword(sc, addr, dest) 318 struct nge_softc *sc; 319 int addr; 320 u_int16_t *dest; 321 { 322 register int i; 323 u_int16_t word = 0; 324 325 /* Force EEPROM to idle state. */ 326 nge_eeprom_idle(sc); 327 328 /* Enter EEPROM access mode. */ 329 nge_delay(sc); 330 SIO_CLR(NGE_MEAR_EE_CLK); 331 nge_delay(sc); 332 SIO_SET(NGE_MEAR_EE_CSEL); 333 nge_delay(sc); 334 335 /* 336 * Send address of word we want to read. 337 */ 338 nge_eeprom_putbyte(sc, addr); 339 340 /* 341 * Start reading bits from EEPROM. 342 */ 343 for (i = 0x8000; i; i >>= 1) { 344 SIO_SET(NGE_MEAR_EE_CLK); 345 nge_delay(sc); 346 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 347 word |= i; 348 nge_delay(sc); 349 SIO_CLR(NGE_MEAR_EE_CLK); 350 nge_delay(sc); 351 } 352 353 /* Turn off EEPROM access mode. */ 354 nge_eeprom_idle(sc); 355 356 *dest = word; 357 358 return; 359 } 360 361 /* 362 * Read a sequence of words from the EEPROM. 363 */ 364 static void 365 nge_read_eeprom(sc, dest, off, cnt, swap) 366 struct nge_softc *sc; 367 caddr_t dest; 368 int off; 369 int cnt; 370 int swap; 371 { 372 int i; 373 u_int16_t word = 0, *ptr; 374 375 for (i = 0; i < cnt; i++) { 376 nge_eeprom_getword(sc, off + i, &word); 377 ptr = (u_int16_t *)(dest + (i * 2)); 378 if (swap) 379 *ptr = ntohs(word); 380 else 381 *ptr = word; 382 } 383 384 return; 385 } 386 387 /* 388 * Sync the PHYs by setting data bit and strobing the clock 32 times. 389 */ 390 static void 391 nge_mii_sync(sc) 392 struct nge_softc *sc; 393 { 394 register int i; 395 396 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 397 398 for (i = 0; i < 32; i++) { 399 SIO_SET(NGE_MEAR_MII_CLK); 400 DELAY(1); 401 SIO_CLR(NGE_MEAR_MII_CLK); 402 DELAY(1); 403 } 404 405 return; 406 } 407 408 /* 409 * Clock a series of bits through the MII. 410 */ 411 static void 412 nge_mii_send(sc, bits, cnt) 413 struct nge_softc *sc; 414 u_int32_t bits; 415 int cnt; 416 { 417 int i; 418 419 SIO_CLR(NGE_MEAR_MII_CLK); 420 421 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 422 if (bits & i) { 423 SIO_SET(NGE_MEAR_MII_DATA); 424 } else { 425 SIO_CLR(NGE_MEAR_MII_DATA); 426 } 427 DELAY(1); 428 SIO_CLR(NGE_MEAR_MII_CLK); 429 DELAY(1); 430 SIO_SET(NGE_MEAR_MII_CLK); 431 } 432 } 433 434 /* 435 * Read an PHY register through the MII. 436 */ 437 static int 438 nge_mii_readreg(sc, frame) 439 struct nge_softc *sc; 440 struct nge_mii_frame *frame; 441 442 { 443 int i, ack; 444 445 /* 446 * Set up frame for RX. 447 */ 448 frame->mii_stdelim = NGE_MII_STARTDELIM; 449 frame->mii_opcode = NGE_MII_READOP; 450 frame->mii_turnaround = 0; 451 frame->mii_data = 0; 452 453 CSR_WRITE_4(sc, NGE_MEAR, 0); 454 455 /* 456 * Turn on data xmit. 457 */ 458 SIO_SET(NGE_MEAR_MII_DIR); 459 460 nge_mii_sync(sc); 461 462 /* 463 * Send command/address info. 464 */ 465 nge_mii_send(sc, frame->mii_stdelim, 2); 466 nge_mii_send(sc, frame->mii_opcode, 2); 467 nge_mii_send(sc, frame->mii_phyaddr, 5); 468 nge_mii_send(sc, frame->mii_regaddr, 5); 469 470 /* Idle bit */ 471 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 472 DELAY(1); 473 SIO_SET(NGE_MEAR_MII_CLK); 474 DELAY(1); 475 476 /* Turn off xmit. */ 477 SIO_CLR(NGE_MEAR_MII_DIR); 478 /* Check for ack */ 479 SIO_CLR(NGE_MEAR_MII_CLK); 480 DELAY(1); 481 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 482 SIO_SET(NGE_MEAR_MII_CLK); 483 DELAY(1); 484 485 /* 486 * Now try reading data bits. If the ack failed, we still 487 * need to clock through 16 cycles to keep the PHY(s) in sync. 488 */ 489 if (ack) { 490 for(i = 0; i < 16; i++) { 491 SIO_CLR(NGE_MEAR_MII_CLK); 492 DELAY(1); 493 SIO_SET(NGE_MEAR_MII_CLK); 494 DELAY(1); 495 } 496 goto fail; 497 } 498 499 for (i = 0x8000; i; i >>= 1) { 500 SIO_CLR(NGE_MEAR_MII_CLK); 501 DELAY(1); 502 if (!ack) { 503 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 504 frame->mii_data |= i; 505 DELAY(1); 506 } 507 SIO_SET(NGE_MEAR_MII_CLK); 508 DELAY(1); 509 } 510 511 fail: 512 513 SIO_CLR(NGE_MEAR_MII_CLK); 514 DELAY(1); 515 SIO_SET(NGE_MEAR_MII_CLK); 516 DELAY(1); 517 518 if (ack) 519 return(1); 520 return(0); 521 } 522 523 /* 524 * Write to a PHY register through the MII. 525 */ 526 static int 527 nge_mii_writereg(sc, frame) 528 struct nge_softc *sc; 529 struct nge_mii_frame *frame; 530 531 { 532 533 /* 534 * Set up frame for TX. 535 */ 536 537 frame->mii_stdelim = NGE_MII_STARTDELIM; 538 frame->mii_opcode = NGE_MII_WRITEOP; 539 frame->mii_turnaround = NGE_MII_TURNAROUND; 540 541 /* 542 * Turn on data output. 543 */ 544 SIO_SET(NGE_MEAR_MII_DIR); 545 546 nge_mii_sync(sc); 547 548 nge_mii_send(sc, frame->mii_stdelim, 2); 549 nge_mii_send(sc, frame->mii_opcode, 2); 550 nge_mii_send(sc, frame->mii_phyaddr, 5); 551 nge_mii_send(sc, frame->mii_regaddr, 5); 552 nge_mii_send(sc, frame->mii_turnaround, 2); 553 nge_mii_send(sc, frame->mii_data, 16); 554 555 /* Idle bit. */ 556 SIO_SET(NGE_MEAR_MII_CLK); 557 DELAY(1); 558 SIO_CLR(NGE_MEAR_MII_CLK); 559 DELAY(1); 560 561 /* 562 * Turn off xmit. 563 */ 564 SIO_CLR(NGE_MEAR_MII_DIR); 565 566 return(0); 567 } 568 569 static int 570 nge_miibus_readreg(dev, phy, reg) 571 device_t dev; 572 int phy, reg; 573 { 574 struct nge_softc *sc; 575 struct nge_mii_frame frame; 576 577 sc = device_get_softc(dev); 578 579 bzero((char *)&frame, sizeof(frame)); 580 581 frame.mii_phyaddr = phy; 582 frame.mii_regaddr = reg; 583 nge_mii_readreg(sc, &frame); 584 585 return(frame.mii_data); 586 } 587 588 static int 589 nge_miibus_writereg(dev, phy, reg, data) 590 device_t dev; 591 int phy, reg, data; 592 { 593 struct nge_softc *sc; 594 struct nge_mii_frame frame; 595 596 sc = device_get_softc(dev); 597 598 bzero((char *)&frame, sizeof(frame)); 599 600 frame.mii_phyaddr = phy; 601 frame.mii_regaddr = reg; 602 frame.mii_data = data; 603 nge_mii_writereg(sc, &frame); 604 605 return(0); 606 } 607 608 static void 609 nge_miibus_statchg(dev) 610 device_t dev; 611 { 612 int status; 613 struct nge_softc *sc; 614 struct mii_data *mii; 615 616 sc = device_get_softc(dev); 617 if (sc->nge_tbi) { 618 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 619 == IFM_AUTO) { 620 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 621 if (status == 0 || status & NGE_TBIANAR_FDX) { 622 NGE_SETBIT(sc, NGE_TX_CFG, 623 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 624 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 625 } else { 626 NGE_CLRBIT(sc, NGE_TX_CFG, 627 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 628 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 629 } 630 631 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 632 != IFM_FDX) { 633 NGE_CLRBIT(sc, NGE_TX_CFG, 634 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 635 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 636 } else { 637 NGE_SETBIT(sc, NGE_TX_CFG, 638 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 639 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 640 } 641 } else { 642 mii = device_get_softc(sc->nge_miibus); 643 644 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 645 NGE_SETBIT(sc, NGE_TX_CFG, 646 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 647 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 648 } else { 649 NGE_CLRBIT(sc, NGE_TX_CFG, 650 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 651 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 652 } 653 654 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 655 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 656 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 657 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 658 } else { 659 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 660 } 661 } 662 return; 663 } 664 665 static void 666 nge_setmulti(sc) 667 struct nge_softc *sc; 668 { 669 struct ifnet *ifp; 670 struct ifmultiaddr *ifma; 671 u_int32_t h = 0, i, filtsave; 672 int bit, index; 673 674 NGE_LOCK_ASSERT(sc); 675 ifp = &sc->arpcom.ac_if; 676 677 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 678 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 679 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 680 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 681 return; 682 } 683 684 /* 685 * We have to explicitly enable the multicast hash table 686 * on the NatSemi chip if we want to use it, which we do. 687 * We also have to tell it that we don't want to use the 688 * hash table for matching unicast addresses. 689 */ 690 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 691 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 692 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 693 694 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 695 696 /* first, zot all the existing hash bits */ 697 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 698 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 699 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 700 } 701 702 /* 703 * From the 11 bits returned by the crc routine, the top 7 704 * bits represent the 16-bit word in the mcast hash table 705 * that needs to be updated, and the lower 4 bits represent 706 * which bit within that byte needs to be set. 707 */ 708 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 709 if (ifma->ifma_addr->sa_family != AF_LINK) 710 continue; 711 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 712 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21; 713 index = (h >> 4) & 0x7F; 714 bit = h & 0xF; 715 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 716 NGE_FILTADDR_MCAST_LO + (index * 2)); 717 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 718 } 719 720 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 721 722 return; 723 } 724 725 static void 726 nge_reset(sc) 727 struct nge_softc *sc; 728 { 729 register int i; 730 731 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 732 733 for (i = 0; i < NGE_TIMEOUT; i++) { 734 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 735 break; 736 } 737 738 if (i == NGE_TIMEOUT) 739 printf("nge%d: reset never completed\n", sc->nge_unit); 740 741 /* Wait a little while for the chip to get its brains in order. */ 742 DELAY(1000); 743 744 /* 745 * If this is a NetSemi chip, make sure to clear 746 * PME mode. 747 */ 748 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 749 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 750 751 return; 752 } 753 754 /* 755 * Probe for a NatSemi chip. Check the PCI vendor and device 756 * IDs against our list and return a device name if we find a match. 757 */ 758 static int 759 nge_probe(dev) 760 device_t dev; 761 { 762 struct nge_type *t; 763 764 t = nge_devs; 765 766 while(t->nge_name != NULL) { 767 if ((pci_get_vendor(dev) == t->nge_vid) && 768 (pci_get_device(dev) == t->nge_did)) { 769 device_set_desc(dev, t->nge_name); 770 return(BUS_PROBE_DEFAULT); 771 } 772 t++; 773 } 774 775 return(ENXIO); 776 } 777 778 /* 779 * Attach the interface. Allocate softc structures, do ifmedia 780 * setup and ethernet/BPF attach. 781 */ 782 static int 783 nge_attach(dev) 784 device_t dev; 785 { 786 u_char eaddr[ETHER_ADDR_LEN]; 787 struct nge_softc *sc; 788 struct ifnet *ifp; 789 int unit, error = 0, rid; 790 const char *sep = ""; 791 792 sc = device_get_softc(dev); 793 unit = device_get_unit(dev); 794 bzero(sc, sizeof(struct nge_softc)); 795 796 NGE_LOCK_INIT(sc, device_get_nameunit(dev)); 797 /* 798 * Map control/status registers. 799 */ 800 pci_enable_busmaster(dev); 801 802 rid = NGE_RID; 803 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE); 804 805 if (sc->nge_res == NULL) { 806 printf("nge%d: couldn't map ports/memory\n", unit); 807 error = ENXIO; 808 goto fail; 809 } 810 811 sc->nge_btag = rman_get_bustag(sc->nge_res); 812 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 813 814 /* Allocate interrupt */ 815 rid = 0; 816 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 817 RF_SHAREABLE | RF_ACTIVE); 818 819 if (sc->nge_irq == NULL) { 820 printf("nge%d: couldn't map interrupt\n", unit); 821 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 822 error = ENXIO; 823 goto fail; 824 } 825 826 /* Reset the adapter. */ 827 nge_reset(sc); 828 829 /* 830 * Get station address from the EEPROM. 831 */ 832 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 833 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 834 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 835 836 sc->nge_unit = unit; 837 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 838 839 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 840 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 841 842 if (sc->nge_ldata == NULL) { 843 printf("nge%d: no memory for list buffers!\n", unit); 844 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 845 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 846 error = ENXIO; 847 goto fail; 848 } 849 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 850 851 ifp = &sc->arpcom.ac_if; 852 ifp->if_softc = sc; 853 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 854 ifp->if_mtu = ETHERMTU; 855 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 856 ifp->if_ioctl = nge_ioctl; 857 ifp->if_start = nge_start; 858 ifp->if_watchdog = nge_watchdog; 859 ifp->if_init = nge_init; 860 ifp->if_baudrate = 1000000000; 861 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 862 ifp->if_hwassist = NGE_CSUM_FEATURES; 863 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 864 #ifdef DEVICE_POLLING 865 ifp->if_capabilities |= IFCAP_POLLING; 866 #endif 867 ifp->if_capenable = ifp->if_capabilities; 868 869 /* 870 * Do MII setup. 871 */ 872 if (mii_phy_probe(dev, &sc->nge_miibus, 873 nge_ifmedia_upd, nge_ifmedia_sts)) { 874 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 875 sc->nge_tbi = 1; 876 device_printf(dev, "Using TBI\n"); 877 878 sc->nge_miibus = dev; 879 880 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 881 nge_ifmedia_sts); 882 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 883 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 884 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 885 device_printf(dev, " "); 886 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 887 PRINT("1000baseSX"); 888 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 889 PRINT("1000baseSX-FDX"); 890 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 891 PRINT("auto"); 892 893 printf("\n"); 894 #undef ADD 895 #undef PRINT 896 ifmedia_set(&sc->nge_ifmedia, 897 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 898 899 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 900 | NGE_GPIO_GP4_OUT 901 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 902 | NGE_GPIO_GP3_OUTENB 903 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 904 905 } else { 906 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 907 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 908 bus_release_resource(dev, NGE_RES, NGE_RID, 909 sc->nge_res); 910 error = ENXIO; 911 goto fail; 912 } 913 } 914 915 /* 916 * Call MI attach routine. 917 */ 918 ether_ifattach(ifp, eaddr); 919 callout_init(&sc->nge_stat_ch, CALLOUT_MPSAFE); 920 921 /* 922 * Hookup IRQ last. 923 */ 924 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE, 925 nge_intr, sc, &sc->nge_intrhand); 926 if (error) { 927 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 928 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 929 printf("nge%d: couldn't set up irq\n", unit); 930 } 931 932 fail: 933 934 if (error) 935 NGE_LOCK_DESTROY(sc); 936 return(error); 937 } 938 939 static int 940 nge_detach(dev) 941 device_t dev; 942 { 943 struct nge_softc *sc; 944 struct ifnet *ifp; 945 946 sc = device_get_softc(dev); 947 ifp = &sc->arpcom.ac_if; 948 949 NGE_LOCK(sc); 950 nge_reset(sc); 951 nge_stop(sc); 952 NGE_UNLOCK(sc); 953 ether_ifdetach(ifp); 954 955 bus_generic_detach(dev); 956 if (!sc->nge_tbi) { 957 device_delete_child(dev, sc->nge_miibus); 958 } 959 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 961 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 962 963 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 964 965 NGE_LOCK_DESTROY(sc); 966 967 return(0); 968 } 969 970 /* 971 * Initialize the transmit descriptors. 972 */ 973 static int 974 nge_list_tx_init(sc) 975 struct nge_softc *sc; 976 { 977 struct nge_list_data *ld; 978 struct nge_ring_data *cd; 979 int i; 980 981 cd = &sc->nge_cdata; 982 ld = sc->nge_ldata; 983 984 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 985 if (i == (NGE_TX_LIST_CNT - 1)) { 986 ld->nge_tx_list[i].nge_nextdesc = 987 &ld->nge_tx_list[0]; 988 ld->nge_tx_list[i].nge_next = 989 vtophys(&ld->nge_tx_list[0]); 990 } else { 991 ld->nge_tx_list[i].nge_nextdesc = 992 &ld->nge_tx_list[i + 1]; 993 ld->nge_tx_list[i].nge_next = 994 vtophys(&ld->nge_tx_list[i + 1]); 995 } 996 ld->nge_tx_list[i].nge_mbuf = NULL; 997 ld->nge_tx_list[i].nge_ptr = 0; 998 ld->nge_tx_list[i].nge_ctl = 0; 999 } 1000 1001 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1002 1003 return(0); 1004 } 1005 1006 1007 /* 1008 * Initialize the RX descriptors and allocate mbufs for them. Note that 1009 * we arrange the descriptors in a closed ring, so that the last descriptor 1010 * points back to the first. 1011 */ 1012 static int 1013 nge_list_rx_init(sc) 1014 struct nge_softc *sc; 1015 { 1016 struct nge_list_data *ld; 1017 struct nge_ring_data *cd; 1018 int i; 1019 1020 ld = sc->nge_ldata; 1021 cd = &sc->nge_cdata; 1022 1023 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1024 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1025 return(ENOBUFS); 1026 if (i == (NGE_RX_LIST_CNT - 1)) { 1027 ld->nge_rx_list[i].nge_nextdesc = 1028 &ld->nge_rx_list[0]; 1029 ld->nge_rx_list[i].nge_next = 1030 vtophys(&ld->nge_rx_list[0]); 1031 } else { 1032 ld->nge_rx_list[i].nge_nextdesc = 1033 &ld->nge_rx_list[i + 1]; 1034 ld->nge_rx_list[i].nge_next = 1035 vtophys(&ld->nge_rx_list[i + 1]); 1036 } 1037 } 1038 1039 cd->nge_rx_prod = 0; 1040 sc->nge_head = sc->nge_tail = NULL; 1041 1042 return(0); 1043 } 1044 1045 /* 1046 * Initialize an RX descriptor and attach an MBUF cluster. 1047 */ 1048 static int 1049 nge_newbuf(sc, c, m) 1050 struct nge_softc *sc; 1051 struct nge_desc *c; 1052 struct mbuf *m; 1053 { 1054 1055 if (m == NULL) { 1056 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1057 if (m == NULL) 1058 return (ENOBUFS); 1059 } else 1060 m->m_data = m->m_ext.ext_buf; 1061 1062 m->m_len = m->m_pkthdr.len = MCLBYTES; 1063 1064 m_adj(m, sizeof(u_int64_t)); 1065 1066 c->nge_mbuf = m; 1067 c->nge_ptr = vtophys(mtod(m, caddr_t)); 1068 c->nge_ctl = m->m_len; 1069 c->nge_extsts = 0; 1070 1071 return(0); 1072 } 1073 1074 #ifdef NGE_FIXUP_RX 1075 static __inline void 1076 nge_fixup_rx(m) 1077 struct mbuf *m; 1078 { 1079 int i; 1080 uint16_t *src, *dst; 1081 1082 src = mtod(m, uint16_t *); 1083 dst = src - 1; 1084 1085 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1086 *dst++ = *src++; 1087 1088 m->m_data -= ETHER_ALIGN; 1089 1090 return; 1091 } 1092 #endif 1093 1094 /* 1095 * A frame has been uploaded: pass the resulting mbuf chain up to 1096 * the higher level protocols. 1097 */ 1098 static void 1099 nge_rxeof(sc) 1100 struct nge_softc *sc; 1101 { 1102 struct mbuf *m; 1103 struct ifnet *ifp; 1104 struct nge_desc *cur_rx; 1105 int i, total_len = 0; 1106 u_int32_t rxstat; 1107 1108 NGE_LOCK_ASSERT(sc); 1109 ifp = &sc->arpcom.ac_if; 1110 i = sc->nge_cdata.nge_rx_prod; 1111 1112 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1113 u_int32_t extsts; 1114 1115 #ifdef DEVICE_POLLING 1116 if (ifp->if_flags & IFF_POLLING) { 1117 if (sc->rxcycles <= 0) 1118 break; 1119 sc->rxcycles--; 1120 } 1121 #endif /* DEVICE_POLLING */ 1122 1123 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1124 rxstat = cur_rx->nge_rxstat; 1125 extsts = cur_rx->nge_extsts; 1126 m = cur_rx->nge_mbuf; 1127 cur_rx->nge_mbuf = NULL; 1128 total_len = NGE_RXBYTES(cur_rx); 1129 NGE_INC(i, NGE_RX_LIST_CNT); 1130 1131 if (rxstat & NGE_CMDSTS_MORE) { 1132 m->m_len = total_len; 1133 if (sc->nge_head == NULL) { 1134 m->m_pkthdr.len = total_len; 1135 sc->nge_head = sc->nge_tail = m; 1136 } else { 1137 m->m_flags &= ~M_PKTHDR; 1138 sc->nge_head->m_pkthdr.len += total_len; 1139 sc->nge_tail->m_next = m; 1140 sc->nge_tail = m; 1141 } 1142 nge_newbuf(sc, cur_rx, NULL); 1143 continue; 1144 } 1145 1146 /* 1147 * If an error occurs, update stats, clear the 1148 * status word and leave the mbuf cluster in place: 1149 * it should simply get re-used next time this descriptor 1150 * comes up in the ring. 1151 */ 1152 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1153 ifp->if_ierrors++; 1154 if (sc->nge_head != NULL) { 1155 m_freem(sc->nge_head); 1156 sc->nge_head = sc->nge_tail = NULL; 1157 } 1158 nge_newbuf(sc, cur_rx, m); 1159 continue; 1160 } 1161 1162 /* Try conjure up a replacement mbuf. */ 1163 1164 if (nge_newbuf(sc, cur_rx, NULL)) { 1165 ifp->if_ierrors++; 1166 if (sc->nge_head != NULL) { 1167 m_freem(sc->nge_head); 1168 sc->nge_head = sc->nge_tail = NULL; 1169 } 1170 nge_newbuf(sc, cur_rx, m); 1171 continue; 1172 } 1173 1174 if (sc->nge_head != NULL) { 1175 m->m_len = total_len; 1176 m->m_flags &= ~M_PKTHDR; 1177 sc->nge_tail->m_next = m; 1178 m = sc->nge_head; 1179 m->m_pkthdr.len += total_len; 1180 sc->nge_head = sc->nge_tail = NULL; 1181 } else 1182 m->m_pkthdr.len = m->m_len = total_len; 1183 1184 /* 1185 * Ok. NatSemi really screwed up here. This is the 1186 * only gigE chip I know of with alignment constraints 1187 * on receive buffers. RX buffers must be 64-bit aligned. 1188 */ 1189 /* 1190 * By popular demand, ignore the alignment problems 1191 * on the Intel x86 platform. The performance hit 1192 * incurred due to unaligned accesses is much smaller 1193 * than the hit produced by forcing buffer copies all 1194 * the time, especially with jumbo frames. We still 1195 * need to fix up the alignment everywhere else though. 1196 */ 1197 #ifdef NGE_FIXUP_RX 1198 nge_fixup_rx(m); 1199 #endif 1200 1201 ifp->if_ipackets++; 1202 m->m_pkthdr.rcvif = ifp; 1203 1204 /* Do IP checksum checking. */ 1205 if (extsts & NGE_RXEXTSTS_IPPKT) 1206 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1207 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1208 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1209 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1210 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1211 (extsts & NGE_RXEXTSTS_UDPPKT && 1212 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1213 m->m_pkthdr.csum_flags |= 1214 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1215 m->m_pkthdr.csum_data = 0xffff; 1216 } 1217 1218 /* 1219 * If we received a packet with a vlan tag, pass it 1220 * to vlan_input() instead of ether_input(). 1221 */ 1222 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1223 VLAN_INPUT_TAG(ifp, m, 1224 ntohs(extsts & NGE_RXEXTSTS_VTCI), continue); 1225 } 1226 NGE_UNLOCK(sc); 1227 (*ifp->if_input)(ifp, m); 1228 NGE_LOCK(sc); 1229 } 1230 1231 sc->nge_cdata.nge_rx_prod = i; 1232 1233 return; 1234 } 1235 1236 /* 1237 * A frame was downloaded to the chip. It's safe for us to clean up 1238 * the list buffers. 1239 */ 1240 1241 static void 1242 nge_txeof(sc) 1243 struct nge_softc *sc; 1244 { 1245 struct nge_desc *cur_tx; 1246 struct ifnet *ifp; 1247 u_int32_t idx; 1248 1249 NGE_LOCK_ASSERT(sc); 1250 ifp = &sc->arpcom.ac_if; 1251 1252 /* 1253 * Go through our tx list and free mbufs for those 1254 * frames that have been transmitted. 1255 */ 1256 idx = sc->nge_cdata.nge_tx_cons; 1257 while (idx != sc->nge_cdata.nge_tx_prod) { 1258 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1259 1260 if (NGE_OWNDESC(cur_tx)) 1261 break; 1262 1263 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1264 sc->nge_cdata.nge_tx_cnt--; 1265 NGE_INC(idx, NGE_TX_LIST_CNT); 1266 continue; 1267 } 1268 1269 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1270 ifp->if_oerrors++; 1271 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1272 ifp->if_collisions++; 1273 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1274 ifp->if_collisions++; 1275 } 1276 1277 ifp->if_collisions += 1278 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1279 1280 ifp->if_opackets++; 1281 if (cur_tx->nge_mbuf != NULL) { 1282 m_freem(cur_tx->nge_mbuf); 1283 cur_tx->nge_mbuf = NULL; 1284 ifp->if_flags &= ~IFF_OACTIVE; 1285 } 1286 1287 sc->nge_cdata.nge_tx_cnt--; 1288 NGE_INC(idx, NGE_TX_LIST_CNT); 1289 } 1290 1291 sc->nge_cdata.nge_tx_cons = idx; 1292 1293 if (idx == sc->nge_cdata.nge_tx_prod) 1294 ifp->if_timer = 0; 1295 1296 return; 1297 } 1298 1299 static void 1300 nge_tick(xsc) 1301 void *xsc; 1302 { 1303 struct nge_softc *sc; 1304 1305 sc = xsc; 1306 1307 NGE_LOCK(sc); 1308 nge_tick_locked(sc); 1309 NGE_UNLOCK(sc); 1310 } 1311 1312 static void 1313 nge_tick_locked(sc) 1314 struct nge_softc *sc; 1315 { 1316 struct mii_data *mii; 1317 struct ifnet *ifp; 1318 1319 NGE_LOCK_ASSERT(sc); 1320 ifp = &sc->arpcom.ac_if; 1321 1322 if (sc->nge_tbi) { 1323 if (!sc->nge_link) { 1324 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1325 & NGE_TBIBMSR_ANEG_DONE) { 1326 if (bootverbose) 1327 printf("nge%d: gigabit link up\n", 1328 sc->nge_unit); 1329 nge_miibus_statchg(sc->nge_miibus); 1330 sc->nge_link++; 1331 if (ifp->if_snd.ifq_head != NULL) 1332 nge_start_locked(ifp); 1333 } 1334 } 1335 } else { 1336 mii = device_get_softc(sc->nge_miibus); 1337 mii_tick(mii); 1338 1339 if (!sc->nge_link) { 1340 if (mii->mii_media_status & IFM_ACTIVE && 1341 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1342 sc->nge_link++; 1343 if (IFM_SUBTYPE(mii->mii_media_active) 1344 == IFM_1000_T && bootverbose) 1345 printf("nge%d: gigabit link up\n", 1346 sc->nge_unit); 1347 if (ifp->if_snd.ifq_head != NULL) 1348 nge_start_locked(ifp); 1349 } 1350 } 1351 } 1352 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 1353 1354 return; 1355 } 1356 1357 #ifdef DEVICE_POLLING 1358 static poll_handler_t nge_poll; 1359 1360 static void 1361 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1362 { 1363 struct nge_softc *sc = ifp->if_softc; 1364 1365 NGE_LOCK(sc); 1366 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1367 ether_poll_deregister(ifp); 1368 cmd = POLL_DEREGISTER; 1369 } 1370 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1371 CSR_WRITE_4(sc, NGE_IER, 1); 1372 NGE_UNLOCK(sc); 1373 return; 1374 } 1375 1376 /* 1377 * On the nge, reading the status register also clears it. 1378 * So before returning to intr mode we must make sure that all 1379 * possible pending sources of interrupts have been served. 1380 * In practice this means run to completion the *eof routines, 1381 * and then call the interrupt routine 1382 */ 1383 sc->rxcycles = count; 1384 nge_rxeof(sc); 1385 nge_txeof(sc); 1386 if (ifp->if_snd.ifq_head != NULL) 1387 nge_start_locked(ifp); 1388 1389 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1390 u_int32_t status; 1391 1392 /* Reading the ISR register clears all interrupts. */ 1393 status = CSR_READ_4(sc, NGE_ISR); 1394 1395 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1396 nge_rxeof(sc); 1397 1398 if (status & (NGE_ISR_RX_IDLE)) 1399 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1400 1401 if (status & NGE_ISR_SYSERR) { 1402 nge_reset(sc); 1403 nge_init_locked(sc); 1404 } 1405 } 1406 NGE_UNLOCK(sc); 1407 } 1408 #endif /* DEVICE_POLLING */ 1409 1410 static void 1411 nge_intr(arg) 1412 void *arg; 1413 { 1414 struct nge_softc *sc; 1415 struct ifnet *ifp; 1416 u_int32_t status; 1417 1418 sc = arg; 1419 ifp = &sc->arpcom.ac_if; 1420 1421 NGE_LOCK(sc); 1422 #ifdef DEVICE_POLLING 1423 if (ifp->if_flags & IFF_POLLING) { 1424 NGE_UNLOCK(sc); 1425 return; 1426 } 1427 if ((ifp->if_capenable & IFCAP_POLLING) && 1428 ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1429 CSR_WRITE_4(sc, NGE_IER, 0); 1430 NGE_UNLOCK(sc); 1431 nge_poll(ifp, 0, 1); 1432 return; 1433 } 1434 #endif /* DEVICE_POLLING */ 1435 1436 /* Supress unwanted interrupts */ 1437 if (!(ifp->if_flags & IFF_UP)) { 1438 nge_stop(sc); 1439 NGE_UNLOCK(sc); 1440 return; 1441 } 1442 1443 /* Disable interrupts. */ 1444 CSR_WRITE_4(sc, NGE_IER, 0); 1445 1446 /* Data LED on for TBI mode */ 1447 if(sc->nge_tbi) 1448 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1449 | NGE_GPIO_GP3_OUT); 1450 1451 for (;;) { 1452 /* Reading the ISR register clears all interrupts. */ 1453 status = CSR_READ_4(sc, NGE_ISR); 1454 1455 if ((status & NGE_INTRS) == 0) 1456 break; 1457 1458 if ((status & NGE_ISR_TX_DESC_OK) || 1459 (status & NGE_ISR_TX_ERR) || 1460 (status & NGE_ISR_TX_OK) || 1461 (status & NGE_ISR_TX_IDLE)) 1462 nge_txeof(sc); 1463 1464 if ((status & NGE_ISR_RX_DESC_OK) || 1465 (status & NGE_ISR_RX_ERR) || 1466 (status & NGE_ISR_RX_OFLOW) || 1467 (status & NGE_ISR_RX_FIFO_OFLOW) || 1468 (status & NGE_ISR_RX_IDLE) || 1469 (status & NGE_ISR_RX_OK)) 1470 nge_rxeof(sc); 1471 1472 if ((status & NGE_ISR_RX_IDLE)) 1473 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1474 1475 if (status & NGE_ISR_SYSERR) { 1476 nge_reset(sc); 1477 ifp->if_flags &= ~IFF_RUNNING; 1478 nge_init_locked(sc); 1479 } 1480 1481 #if 0 1482 /* 1483 * XXX: nge_tick() is not ready to be called this way 1484 * it screws up the aneg timeout because mii_tick() is 1485 * only to be called once per second. 1486 */ 1487 if (status & NGE_IMR_PHY_INTR) { 1488 sc->nge_link = 0; 1489 nge_tick_locked(sc); 1490 } 1491 #endif 1492 } 1493 1494 /* Re-enable interrupts. */ 1495 CSR_WRITE_4(sc, NGE_IER, 1); 1496 1497 if (ifp->if_snd.ifq_head != NULL) 1498 nge_start_locked(ifp); 1499 1500 /* Data LED off for TBI mode */ 1501 1502 if(sc->nge_tbi) 1503 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1504 & ~NGE_GPIO_GP3_OUT); 1505 1506 NGE_UNLOCK(sc); 1507 1508 return; 1509 } 1510 1511 /* 1512 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1513 * pointers to the fragment pointers. 1514 */ 1515 static int 1516 nge_encap(sc, m_head, txidx) 1517 struct nge_softc *sc; 1518 struct mbuf *m_head; 1519 u_int32_t *txidx; 1520 { 1521 struct nge_desc *f = NULL; 1522 struct mbuf *m; 1523 int frag, cur, cnt = 0; 1524 struct m_tag *mtag; 1525 1526 /* 1527 * Start packing the mbufs in this chain into 1528 * the fragment pointers. Stop when we run out 1529 * of fragments or hit the end of the mbuf chain. 1530 */ 1531 m = m_head; 1532 cur = frag = *txidx; 1533 1534 for (m = m_head; m != NULL; m = m->m_next) { 1535 if (m->m_len != 0) { 1536 if ((NGE_TX_LIST_CNT - 1537 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1538 return(ENOBUFS); 1539 f = &sc->nge_ldata->nge_tx_list[frag]; 1540 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1541 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1542 if (cnt != 0) 1543 f->nge_ctl |= NGE_CMDSTS_OWN; 1544 cur = frag; 1545 NGE_INC(frag, NGE_TX_LIST_CNT); 1546 cnt++; 1547 } 1548 } 1549 1550 if (m != NULL) 1551 return(ENOBUFS); 1552 1553 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1554 if (m_head->m_pkthdr.csum_flags) { 1555 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1556 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1557 NGE_TXEXTSTS_IPCSUM; 1558 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1559 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1560 NGE_TXEXTSTS_TCPCSUM; 1561 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1562 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1563 NGE_TXEXTSTS_UDPCSUM; 1564 } 1565 1566 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1567 if (mtag != NULL) { 1568 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1569 (NGE_TXEXTSTS_VLANPKT|htons(VLAN_TAG_VALUE(mtag))); 1570 } 1571 1572 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1573 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1574 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1575 sc->nge_cdata.nge_tx_cnt += cnt; 1576 *txidx = frag; 1577 1578 return(0); 1579 } 1580 1581 /* 1582 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1583 * to the mbuf data regions directly in the transmit lists. We also save a 1584 * copy of the pointers since the transmit list fragment pointers are 1585 * physical addresses. 1586 */ 1587 1588 static void 1589 nge_start(ifp) 1590 struct ifnet *ifp; 1591 { 1592 struct nge_softc *sc; 1593 1594 sc = ifp->if_softc; 1595 NGE_LOCK(sc); 1596 nge_start_locked(ifp); 1597 NGE_UNLOCK(sc); 1598 } 1599 1600 static void 1601 nge_start_locked(ifp) 1602 struct ifnet *ifp; 1603 { 1604 struct nge_softc *sc; 1605 struct mbuf *m_head = NULL; 1606 u_int32_t idx; 1607 1608 sc = ifp->if_softc; 1609 1610 if (!sc->nge_link) 1611 return; 1612 1613 idx = sc->nge_cdata.nge_tx_prod; 1614 1615 if (ifp->if_flags & IFF_OACTIVE) 1616 return; 1617 1618 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1619 IF_DEQUEUE(&ifp->if_snd, m_head); 1620 if (m_head == NULL) 1621 break; 1622 1623 if (nge_encap(sc, m_head, &idx)) { 1624 IF_PREPEND(&ifp->if_snd, m_head); 1625 ifp->if_flags |= IFF_OACTIVE; 1626 break; 1627 } 1628 1629 /* 1630 * If there's a BPF listener, bounce a copy of this frame 1631 * to him. 1632 */ 1633 BPF_MTAP(ifp, m_head); 1634 1635 } 1636 1637 /* Transmit */ 1638 sc->nge_cdata.nge_tx_prod = idx; 1639 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1640 1641 /* 1642 * Set a timeout in case the chip goes out to lunch. 1643 */ 1644 ifp->if_timer = 5; 1645 1646 return; 1647 } 1648 1649 static void 1650 nge_init(xsc) 1651 void *xsc; 1652 { 1653 struct nge_softc *sc = xsc; 1654 1655 NGE_LOCK(sc); 1656 nge_init_locked(sc); 1657 NGE_UNLOCK(sc); 1658 } 1659 1660 static void 1661 nge_init_locked(sc) 1662 struct nge_softc *sc; 1663 { 1664 struct ifnet *ifp = &sc->arpcom.ac_if; 1665 struct mii_data *mii; 1666 1667 NGE_LOCK_ASSERT(sc); 1668 1669 if (ifp->if_flags & IFF_RUNNING) 1670 return; 1671 1672 /* 1673 * Cancel pending I/O and free all RX/TX buffers. 1674 */ 1675 nge_stop(sc); 1676 1677 if (sc->nge_tbi) { 1678 mii = NULL; 1679 } else { 1680 mii = device_get_softc(sc->nge_miibus); 1681 } 1682 1683 /* Set MAC address */ 1684 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1685 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1686 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1687 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1688 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1689 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1690 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1691 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1692 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1693 1694 /* Init circular RX list. */ 1695 if (nge_list_rx_init(sc) == ENOBUFS) { 1696 printf("nge%d: initialization failed: no " 1697 "memory for rx buffers\n", sc->nge_unit); 1698 nge_stop(sc); 1699 return; 1700 } 1701 1702 /* 1703 * Init tx descriptors. 1704 */ 1705 nge_list_tx_init(sc); 1706 1707 /* 1708 * For the NatSemi chip, we have to explicitly enable the 1709 * reception of ARP frames, as well as turn on the 'perfect 1710 * match' filter where we store the station address, otherwise 1711 * we won't receive unicasts meant for this host. 1712 */ 1713 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1714 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1715 1716 /* If we want promiscuous mode, set the allframes bit. */ 1717 if (ifp->if_flags & IFF_PROMISC) { 1718 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1719 } else { 1720 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1721 } 1722 1723 /* 1724 * Set the capture broadcast bit to capture broadcast frames. 1725 */ 1726 if (ifp->if_flags & IFF_BROADCAST) { 1727 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1728 } else { 1729 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1730 } 1731 1732 /* 1733 * Load the multicast filter. 1734 */ 1735 nge_setmulti(sc); 1736 1737 /* Turn the receive filter on */ 1738 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1739 1740 /* 1741 * Load the address of the RX and TX lists. 1742 */ 1743 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1744 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1745 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1746 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1747 1748 /* Set RX configuration */ 1749 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1750 /* 1751 * Enable hardware checksum validation for all IPv4 1752 * packets, do not reject packets with bad checksums. 1753 */ 1754 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1755 1756 /* 1757 * Tell the chip to detect and strip VLAN tag info from 1758 * received frames. The tag will be provided in the extsts 1759 * field in the RX descriptors. 1760 */ 1761 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1762 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1763 1764 /* Set TX configuration */ 1765 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1766 1767 /* 1768 * Enable TX IPv4 checksumming on a per-packet basis. 1769 */ 1770 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1771 1772 /* 1773 * Tell the chip to insert VLAN tags on a per-packet basis as 1774 * dictated by the code in the frame encapsulation routine. 1775 */ 1776 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1777 1778 /* Set full/half duplex mode. */ 1779 if (sc->nge_tbi) { 1780 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1781 == IFM_FDX) { 1782 NGE_SETBIT(sc, NGE_TX_CFG, 1783 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1784 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1785 } else { 1786 NGE_CLRBIT(sc, NGE_TX_CFG, 1787 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1788 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1789 } 1790 } else { 1791 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1792 NGE_SETBIT(sc, NGE_TX_CFG, 1793 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1794 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1795 } else { 1796 NGE_CLRBIT(sc, NGE_TX_CFG, 1797 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1798 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1799 } 1800 } 1801 1802 nge_tick_locked(sc); 1803 1804 /* 1805 * Enable the delivery of PHY interrupts based on 1806 * link/speed/duplex status changes. Also enable the 1807 * extsts field in the DMA descriptors (needed for 1808 * TCP/IP checksum offload on transmit). 1809 */ 1810 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1811 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1812 1813 /* 1814 * Configure interrupt holdoff (moderation). We can 1815 * have the chip delay interrupt delivery for a certain 1816 * period. Units are in 100us, and the max setting 1817 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1818 */ 1819 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1820 1821 /* 1822 * Enable interrupts. 1823 */ 1824 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1825 #ifdef DEVICE_POLLING 1826 /* 1827 * ... only enable interrupts if we are not polling, make sure 1828 * they are off otherwise. 1829 */ 1830 if (ifp->if_flags & IFF_POLLING) 1831 CSR_WRITE_4(sc, NGE_IER, 0); 1832 else 1833 #endif /* DEVICE_POLLING */ 1834 CSR_WRITE_4(sc, NGE_IER, 1); 1835 1836 /* Enable receiver and transmitter. */ 1837 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1838 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1839 1840 nge_ifmedia_upd(ifp); 1841 1842 ifp->if_flags |= IFF_RUNNING; 1843 ifp->if_flags &= ~IFF_OACTIVE; 1844 1845 return; 1846 } 1847 1848 /* 1849 * Set media options. 1850 */ 1851 static int 1852 nge_ifmedia_upd(ifp) 1853 struct ifnet *ifp; 1854 { 1855 struct nge_softc *sc; 1856 struct mii_data *mii; 1857 1858 sc = ifp->if_softc; 1859 1860 if (sc->nge_tbi) { 1861 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1862 == IFM_AUTO) { 1863 CSR_WRITE_4(sc, NGE_TBI_ANAR, 1864 CSR_READ_4(sc, NGE_TBI_ANAR) 1865 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 1866 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 1867 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 1868 | NGE_TBIBMCR_RESTART_ANEG); 1869 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 1870 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 1871 & IFM_GMASK) == IFM_FDX) { 1872 NGE_SETBIT(sc, NGE_TX_CFG, 1873 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1874 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1875 1876 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1877 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1878 } else { 1879 NGE_CLRBIT(sc, NGE_TX_CFG, 1880 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1881 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1882 1883 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 1884 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 1885 } 1886 1887 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1888 & ~NGE_GPIO_GP3_OUT); 1889 } else { 1890 mii = device_get_softc(sc->nge_miibus); 1891 sc->nge_link = 0; 1892 if (mii->mii_instance) { 1893 struct mii_softc *miisc; 1894 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1895 miisc = LIST_NEXT(miisc, mii_list)) 1896 mii_phy_reset(miisc); 1897 } 1898 mii_mediachg(mii); 1899 } 1900 1901 return(0); 1902 } 1903 1904 /* 1905 * Report current media status. 1906 */ 1907 static void 1908 nge_ifmedia_sts(ifp, ifmr) 1909 struct ifnet *ifp; 1910 struct ifmediareq *ifmr; 1911 { 1912 struct nge_softc *sc; 1913 struct mii_data *mii; 1914 1915 sc = ifp->if_softc; 1916 1917 if (sc->nge_tbi) { 1918 ifmr->ifm_status = IFM_AVALID; 1919 ifmr->ifm_active = IFM_ETHER; 1920 1921 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1922 ifmr->ifm_status |= IFM_ACTIVE; 1923 } 1924 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 1925 ifmr->ifm_active |= IFM_LOOP; 1926 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 1927 ifmr->ifm_active |= IFM_NONE; 1928 ifmr->ifm_status = 0; 1929 return; 1930 } 1931 ifmr->ifm_active |= IFM_1000_SX; 1932 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1933 == IFM_AUTO) { 1934 ifmr->ifm_active |= IFM_AUTO; 1935 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1936 & NGE_TBIANAR_FDX) { 1937 ifmr->ifm_active |= IFM_FDX; 1938 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 1939 & NGE_TBIANAR_HDX) { 1940 ifmr->ifm_active |= IFM_HDX; 1941 } 1942 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1943 == IFM_FDX) 1944 ifmr->ifm_active |= IFM_FDX; 1945 else 1946 ifmr->ifm_active |= IFM_HDX; 1947 1948 } else { 1949 mii = device_get_softc(sc->nge_miibus); 1950 mii_pollstat(mii); 1951 ifmr->ifm_active = mii->mii_media_active; 1952 ifmr->ifm_status = mii->mii_media_status; 1953 } 1954 1955 return; 1956 } 1957 1958 static int 1959 nge_ioctl(ifp, command, data) 1960 struct ifnet *ifp; 1961 u_long command; 1962 caddr_t data; 1963 { 1964 struct nge_softc *sc = ifp->if_softc; 1965 struct ifreq *ifr = (struct ifreq *) data; 1966 struct mii_data *mii; 1967 int error = 0; 1968 1969 switch(command) { 1970 case SIOCSIFMTU: 1971 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 1972 error = EINVAL; 1973 else { 1974 ifp->if_mtu = ifr->ifr_mtu; 1975 /* 1976 * Workaround: if the MTU is larger than 1977 * 8152 (TX FIFO size minus 64 minus 18), turn off 1978 * TX checksum offloading. 1979 */ 1980 if (ifr->ifr_mtu >= 8152) { 1981 ifp->if_capenable &= ~IFCAP_TXCSUM; 1982 ifp->if_hwassist = 0; 1983 } else { 1984 ifp->if_capenable |= IFCAP_TXCSUM; 1985 ifp->if_hwassist = NGE_CSUM_FEATURES; 1986 } 1987 } 1988 break; 1989 case SIOCSIFFLAGS: 1990 NGE_LOCK(sc); 1991 if (ifp->if_flags & IFF_UP) { 1992 if (ifp->if_flags & IFF_RUNNING && 1993 ifp->if_flags & IFF_PROMISC && 1994 !(sc->nge_if_flags & IFF_PROMISC)) { 1995 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1996 NGE_RXFILTCTL_ALLPHYS| 1997 NGE_RXFILTCTL_ALLMULTI); 1998 } else if (ifp->if_flags & IFF_RUNNING && 1999 !(ifp->if_flags & IFF_PROMISC) && 2000 sc->nge_if_flags & IFF_PROMISC) { 2001 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2002 NGE_RXFILTCTL_ALLPHYS); 2003 if (!(ifp->if_flags & IFF_ALLMULTI)) 2004 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2005 NGE_RXFILTCTL_ALLMULTI); 2006 } else { 2007 ifp->if_flags &= ~IFF_RUNNING; 2008 nge_init_locked(sc); 2009 } 2010 } else { 2011 if (ifp->if_flags & IFF_RUNNING) 2012 nge_stop(sc); 2013 } 2014 sc->nge_if_flags = ifp->if_flags; 2015 NGE_UNLOCK(sc); 2016 error = 0; 2017 break; 2018 case SIOCADDMULTI: 2019 case SIOCDELMULTI: 2020 NGE_LOCK(sc); 2021 nge_setmulti(sc); 2022 NGE_UNLOCK(sc); 2023 error = 0; 2024 break; 2025 case SIOCGIFMEDIA: 2026 case SIOCSIFMEDIA: 2027 if (sc->nge_tbi) { 2028 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2029 command); 2030 } else { 2031 mii = device_get_softc(sc->nge_miibus); 2032 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2033 command); 2034 } 2035 break; 2036 case SIOCSIFCAP: 2037 ifp->if_capenable &= ~IFCAP_POLLING; 2038 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_POLLING; 2039 break; 2040 default: 2041 error = ether_ioctl(ifp, command, data); 2042 break; 2043 } 2044 2045 return(error); 2046 } 2047 2048 static void 2049 nge_watchdog(ifp) 2050 struct ifnet *ifp; 2051 { 2052 struct nge_softc *sc; 2053 2054 sc = ifp->if_softc; 2055 2056 ifp->if_oerrors++; 2057 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2058 2059 NGE_LOCK(sc); 2060 nge_stop(sc); 2061 nge_reset(sc); 2062 ifp->if_flags &= ~IFF_RUNNING; 2063 nge_init_locked(sc); 2064 2065 if (ifp->if_snd.ifq_head != NULL) 2066 nge_start_locked(ifp); 2067 2068 NGE_UNLOCK(sc); 2069 2070 return; 2071 } 2072 2073 /* 2074 * Stop the adapter and free any mbufs allocated to the 2075 * RX and TX lists. 2076 */ 2077 static void 2078 nge_stop(sc) 2079 struct nge_softc *sc; 2080 { 2081 register int i; 2082 struct ifnet *ifp; 2083 struct mii_data *mii; 2084 2085 NGE_LOCK_ASSERT(sc); 2086 ifp = &sc->arpcom.ac_if; 2087 ifp->if_timer = 0; 2088 if (sc->nge_tbi) { 2089 mii = NULL; 2090 } else { 2091 mii = device_get_softc(sc->nge_miibus); 2092 } 2093 2094 callout_stop(&sc->nge_stat_ch); 2095 #ifdef DEVICE_POLLING 2096 ether_poll_deregister(ifp); 2097 #endif 2098 CSR_WRITE_4(sc, NGE_IER, 0); 2099 CSR_WRITE_4(sc, NGE_IMR, 0); 2100 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2101 DELAY(1000); 2102 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2103 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2104 2105 if (!sc->nge_tbi) 2106 mii_down(mii); 2107 2108 sc->nge_link = 0; 2109 2110 /* 2111 * Free data in the RX lists. 2112 */ 2113 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2114 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2115 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2116 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2117 } 2118 } 2119 bzero((char *)&sc->nge_ldata->nge_rx_list, 2120 sizeof(sc->nge_ldata->nge_rx_list)); 2121 2122 /* 2123 * Free the TX list buffers. 2124 */ 2125 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2126 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2127 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2128 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2129 } 2130 } 2131 2132 bzero((char *)&sc->nge_ldata->nge_tx_list, 2133 sizeof(sc->nge_ldata->nge_tx_list)); 2134 2135 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2136 2137 return; 2138 } 2139 2140 /* 2141 * Stop all chip I/O so that the kernel's probe routines don't 2142 * get confused by errant DMAs when rebooting. 2143 */ 2144 static void 2145 nge_shutdown(dev) 2146 device_t dev; 2147 { 2148 struct nge_softc *sc; 2149 2150 sc = device_get_softc(dev); 2151 2152 NGE_LOCK(sc); 2153 nge_reset(sc); 2154 nge_stop(sc); 2155 NGE_UNLOCK(sc); 2156 2157 return; 2158 } 2159