1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include <sys/cdefs.h> 92 __FBSDID("$FreeBSD$"); 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/sockio.h> 97 #include <sys/mbuf.h> 98 #include <sys/malloc.h> 99 #include <sys/kernel.h> 100 #include <sys/socket.h> 101 102 #include <net/if.h> 103 #include <net/if_arp.h> 104 #include <net/ethernet.h> 105 #include <net/if_dl.h> 106 #include <net/if_media.h> 107 #include <net/if_types.h> 108 #include <net/if_vlan_var.h> 109 110 #include <net/bpf.h> 111 112 #include <vm/vm.h> /* for vtophys */ 113 #include <vm/pmap.h> /* for vtophys */ 114 #include <machine/clock.h> /* for DELAY */ 115 #include <machine/bus_pio.h> 116 #include <machine/bus_memio.h> 117 #include <machine/bus.h> 118 #include <machine/resource.h> 119 #include <sys/bus.h> 120 #include <sys/rman.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/pci/pcireg.h> 126 #include <dev/pci/pcivar.h> 127 128 #define NGE_USEIOSPACE 129 130 #include <dev/nge/if_ngereg.h> 131 132 MODULE_DEPEND(nge, pci, 1, 1, 1); 133 MODULE_DEPEND(nge, ether, 1, 1, 1); 134 MODULE_DEPEND(nge, miibus, 1, 1, 1); 135 136 /* "controller miibus0" required. See GENERIC if you get errors here. */ 137 #include "miibus_if.h" 138 139 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 140 141 /* 142 * Various supported device vendors/types and their names. 143 */ 144 static struct nge_type nge_devs[] = { 145 { NGE_VENDORID, NGE_DEVICEID, 146 "National Semiconductor Gigabit Ethernet" }, 147 { 0, 0, NULL } 148 }; 149 150 static int nge_probe(device_t); 151 static int nge_attach(device_t); 152 static int nge_detach(device_t); 153 154 static int nge_alloc_jumbo_mem(struct nge_softc *); 155 static void nge_free_jumbo_mem(struct nge_softc *); 156 static void *nge_jalloc(struct nge_softc *); 157 static void nge_jfree(void *, void *); 158 159 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *); 160 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 161 static void nge_rxeof(struct nge_softc *); 162 static void nge_txeof(struct nge_softc *); 163 static void nge_intr(void *); 164 static void nge_tick(void *); 165 static void nge_start(struct ifnet *); 166 static int nge_ioctl(struct ifnet *, u_long, caddr_t); 167 static void nge_init(void *); 168 static void nge_stop(struct nge_softc *); 169 static void nge_watchdog(struct ifnet *); 170 static void nge_shutdown(device_t); 171 static int nge_ifmedia_upd(struct ifnet *); 172 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 173 174 static void nge_delay(struct nge_softc *); 175 static void nge_eeprom_idle(struct nge_softc *); 176 static void nge_eeprom_putbyte(struct nge_softc *, int); 177 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 178 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 179 180 static void nge_mii_sync(struct nge_softc *); 181 static void nge_mii_send(struct nge_softc *, u_int32_t, int); 182 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 183 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 184 185 static int nge_miibus_readreg(device_t, int, int); 186 static int nge_miibus_writereg(device_t, int, int, int); 187 static void nge_miibus_statchg(device_t); 188 189 static void nge_setmulti(struct nge_softc *); 190 static u_int32_t nge_crc(struct nge_softc *, caddr_t); 191 static void nge_reset(struct nge_softc *); 192 static int nge_list_rx_init(struct nge_softc *); 193 static int nge_list_tx_init(struct nge_softc *); 194 195 #ifdef NGE_USEIOSPACE 196 #define NGE_RES SYS_RES_IOPORT 197 #define NGE_RID NGE_PCI_LOIO 198 #else 199 #define NGE_RES SYS_RES_MEMORY 200 #define NGE_RID NGE_PCI_LOMEM 201 #endif 202 203 static device_method_t nge_methods[] = { 204 /* Device interface */ 205 DEVMETHOD(device_probe, nge_probe), 206 DEVMETHOD(device_attach, nge_attach), 207 DEVMETHOD(device_detach, nge_detach), 208 DEVMETHOD(device_shutdown, nge_shutdown), 209 210 /* bus interface */ 211 DEVMETHOD(bus_print_child, bus_generic_print_child), 212 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 213 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 216 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 217 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 218 219 { 0, 0 } 220 }; 221 222 static driver_t nge_driver = { 223 "nge", 224 nge_methods, 225 sizeof(struct nge_softc) 226 }; 227 228 static devclass_t nge_devclass; 229 230 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 231 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 232 233 #define NGE_SETBIT(sc, reg, x) \ 234 CSR_WRITE_4(sc, reg, \ 235 CSR_READ_4(sc, reg) | (x)) 236 237 #define NGE_CLRBIT(sc, reg, x) \ 238 CSR_WRITE_4(sc, reg, \ 239 CSR_READ_4(sc, reg) & ~(x)) 240 241 #define SIO_SET(x) \ 242 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 243 244 #define SIO_CLR(x) \ 245 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 246 247 static void 248 nge_delay(sc) 249 struct nge_softc *sc; 250 { 251 int idx; 252 253 for (idx = (300 / 33) + 1; idx > 0; idx--) 254 CSR_READ_4(sc, NGE_CSR); 255 256 return; 257 } 258 259 static void 260 nge_eeprom_idle(sc) 261 struct nge_softc *sc; 262 { 263 register int i; 264 265 SIO_SET(NGE_MEAR_EE_CSEL); 266 nge_delay(sc); 267 SIO_SET(NGE_MEAR_EE_CLK); 268 nge_delay(sc); 269 270 for (i = 0; i < 25; i++) { 271 SIO_CLR(NGE_MEAR_EE_CLK); 272 nge_delay(sc); 273 SIO_SET(NGE_MEAR_EE_CLK); 274 nge_delay(sc); 275 } 276 277 SIO_CLR(NGE_MEAR_EE_CLK); 278 nge_delay(sc); 279 SIO_CLR(NGE_MEAR_EE_CSEL); 280 nge_delay(sc); 281 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 282 283 return; 284 } 285 286 /* 287 * Send a read command and address to the EEPROM, check for ACK. 288 */ 289 static void 290 nge_eeprom_putbyte(sc, addr) 291 struct nge_softc *sc; 292 int addr; 293 { 294 register int d, i; 295 296 d = addr | NGE_EECMD_READ; 297 298 /* 299 * Feed in each bit and stobe the clock. 300 */ 301 for (i = 0x400; i; i >>= 1) { 302 if (d & i) { 303 SIO_SET(NGE_MEAR_EE_DIN); 304 } else { 305 SIO_CLR(NGE_MEAR_EE_DIN); 306 } 307 nge_delay(sc); 308 SIO_SET(NGE_MEAR_EE_CLK); 309 nge_delay(sc); 310 SIO_CLR(NGE_MEAR_EE_CLK); 311 nge_delay(sc); 312 } 313 314 return; 315 } 316 317 /* 318 * Read a word of data stored in the EEPROM at address 'addr.' 319 */ 320 static void 321 nge_eeprom_getword(sc, addr, dest) 322 struct nge_softc *sc; 323 int addr; 324 u_int16_t *dest; 325 { 326 register int i; 327 u_int16_t word = 0; 328 329 /* Force EEPROM to idle state. */ 330 nge_eeprom_idle(sc); 331 332 /* Enter EEPROM access mode. */ 333 nge_delay(sc); 334 SIO_CLR(NGE_MEAR_EE_CLK); 335 nge_delay(sc); 336 SIO_SET(NGE_MEAR_EE_CSEL); 337 nge_delay(sc); 338 339 /* 340 * Send address of word we want to read. 341 */ 342 nge_eeprom_putbyte(sc, addr); 343 344 /* 345 * Start reading bits from EEPROM. 346 */ 347 for (i = 0x8000; i; i >>= 1) { 348 SIO_SET(NGE_MEAR_EE_CLK); 349 nge_delay(sc); 350 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 351 word |= i; 352 nge_delay(sc); 353 SIO_CLR(NGE_MEAR_EE_CLK); 354 nge_delay(sc); 355 } 356 357 /* Turn off EEPROM access mode. */ 358 nge_eeprom_idle(sc); 359 360 *dest = word; 361 362 return; 363 } 364 365 /* 366 * Read a sequence of words from the EEPROM. 367 */ 368 static void 369 nge_read_eeprom(sc, dest, off, cnt, swap) 370 struct nge_softc *sc; 371 caddr_t dest; 372 int off; 373 int cnt; 374 int swap; 375 { 376 int i; 377 u_int16_t word = 0, *ptr; 378 379 for (i = 0; i < cnt; i++) { 380 nge_eeprom_getword(sc, off + i, &word); 381 ptr = (u_int16_t *)(dest + (i * 2)); 382 if (swap) 383 *ptr = ntohs(word); 384 else 385 *ptr = word; 386 } 387 388 return; 389 } 390 391 /* 392 * Sync the PHYs by setting data bit and strobing the clock 32 times. 393 */ 394 static void 395 nge_mii_sync(sc) 396 struct nge_softc *sc; 397 { 398 register int i; 399 400 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 401 402 for (i = 0; i < 32; i++) { 403 SIO_SET(NGE_MEAR_MII_CLK); 404 DELAY(1); 405 SIO_CLR(NGE_MEAR_MII_CLK); 406 DELAY(1); 407 } 408 409 return; 410 } 411 412 /* 413 * Clock a series of bits through the MII. 414 */ 415 static void 416 nge_mii_send(sc, bits, cnt) 417 struct nge_softc *sc; 418 u_int32_t bits; 419 int cnt; 420 { 421 int i; 422 423 SIO_CLR(NGE_MEAR_MII_CLK); 424 425 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 426 if (bits & i) { 427 SIO_SET(NGE_MEAR_MII_DATA); 428 } else { 429 SIO_CLR(NGE_MEAR_MII_DATA); 430 } 431 DELAY(1); 432 SIO_CLR(NGE_MEAR_MII_CLK); 433 DELAY(1); 434 SIO_SET(NGE_MEAR_MII_CLK); 435 } 436 } 437 438 /* 439 * Read an PHY register through the MII. 440 */ 441 static int 442 nge_mii_readreg(sc, frame) 443 struct nge_softc *sc; 444 struct nge_mii_frame *frame; 445 446 { 447 int i, ack, s; 448 449 s = splimp(); 450 451 /* 452 * Set up frame for RX. 453 */ 454 frame->mii_stdelim = NGE_MII_STARTDELIM; 455 frame->mii_opcode = NGE_MII_READOP; 456 frame->mii_turnaround = 0; 457 frame->mii_data = 0; 458 459 CSR_WRITE_4(sc, NGE_MEAR, 0); 460 461 /* 462 * Turn on data xmit. 463 */ 464 SIO_SET(NGE_MEAR_MII_DIR); 465 466 nge_mii_sync(sc); 467 468 /* 469 * Send command/address info. 470 */ 471 nge_mii_send(sc, frame->mii_stdelim, 2); 472 nge_mii_send(sc, frame->mii_opcode, 2); 473 nge_mii_send(sc, frame->mii_phyaddr, 5); 474 nge_mii_send(sc, frame->mii_regaddr, 5); 475 476 /* Idle bit */ 477 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 478 DELAY(1); 479 SIO_SET(NGE_MEAR_MII_CLK); 480 DELAY(1); 481 482 /* Turn off xmit. */ 483 SIO_CLR(NGE_MEAR_MII_DIR); 484 /* Check for ack */ 485 SIO_CLR(NGE_MEAR_MII_CLK); 486 DELAY(1); 487 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 488 SIO_SET(NGE_MEAR_MII_CLK); 489 DELAY(1); 490 491 /* 492 * Now try reading data bits. If the ack failed, we still 493 * need to clock through 16 cycles to keep the PHY(s) in sync. 494 */ 495 if (ack) { 496 for(i = 0; i < 16; i++) { 497 SIO_CLR(NGE_MEAR_MII_CLK); 498 DELAY(1); 499 SIO_SET(NGE_MEAR_MII_CLK); 500 DELAY(1); 501 } 502 goto fail; 503 } 504 505 for (i = 0x8000; i; i >>= 1) { 506 SIO_CLR(NGE_MEAR_MII_CLK); 507 DELAY(1); 508 if (!ack) { 509 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 510 frame->mii_data |= i; 511 DELAY(1); 512 } 513 SIO_SET(NGE_MEAR_MII_CLK); 514 DELAY(1); 515 } 516 517 fail: 518 519 SIO_CLR(NGE_MEAR_MII_CLK); 520 DELAY(1); 521 SIO_SET(NGE_MEAR_MII_CLK); 522 DELAY(1); 523 524 splx(s); 525 526 if (ack) 527 return(1); 528 return(0); 529 } 530 531 /* 532 * Write to a PHY register through the MII. 533 */ 534 static int 535 nge_mii_writereg(sc, frame) 536 struct nge_softc *sc; 537 struct nge_mii_frame *frame; 538 539 { 540 int s; 541 542 s = splimp(); 543 /* 544 * Set up frame for TX. 545 */ 546 547 frame->mii_stdelim = NGE_MII_STARTDELIM; 548 frame->mii_opcode = NGE_MII_WRITEOP; 549 frame->mii_turnaround = NGE_MII_TURNAROUND; 550 551 /* 552 * Turn on data output. 553 */ 554 SIO_SET(NGE_MEAR_MII_DIR); 555 556 nge_mii_sync(sc); 557 558 nge_mii_send(sc, frame->mii_stdelim, 2); 559 nge_mii_send(sc, frame->mii_opcode, 2); 560 nge_mii_send(sc, frame->mii_phyaddr, 5); 561 nge_mii_send(sc, frame->mii_regaddr, 5); 562 nge_mii_send(sc, frame->mii_turnaround, 2); 563 nge_mii_send(sc, frame->mii_data, 16); 564 565 /* Idle bit. */ 566 SIO_SET(NGE_MEAR_MII_CLK); 567 DELAY(1); 568 SIO_CLR(NGE_MEAR_MII_CLK); 569 DELAY(1); 570 571 /* 572 * Turn off xmit. 573 */ 574 SIO_CLR(NGE_MEAR_MII_DIR); 575 576 splx(s); 577 578 return(0); 579 } 580 581 static int 582 nge_miibus_readreg(dev, phy, reg) 583 device_t dev; 584 int phy, reg; 585 { 586 struct nge_softc *sc; 587 struct nge_mii_frame frame; 588 589 sc = device_get_softc(dev); 590 591 bzero((char *)&frame, sizeof(frame)); 592 593 frame.mii_phyaddr = phy; 594 frame.mii_regaddr = reg; 595 nge_mii_readreg(sc, &frame); 596 597 return(frame.mii_data); 598 } 599 600 static int 601 nge_miibus_writereg(dev, phy, reg, data) 602 device_t dev; 603 int phy, reg, data; 604 { 605 struct nge_softc *sc; 606 struct nge_mii_frame frame; 607 608 sc = device_get_softc(dev); 609 610 bzero((char *)&frame, sizeof(frame)); 611 612 frame.mii_phyaddr = phy; 613 frame.mii_regaddr = reg; 614 frame.mii_data = data; 615 nge_mii_writereg(sc, &frame); 616 617 return(0); 618 } 619 620 static void 621 nge_miibus_statchg(dev) 622 device_t dev; 623 { 624 int status; 625 struct nge_softc *sc; 626 struct mii_data *mii; 627 628 sc = device_get_softc(dev); 629 if (sc->nge_tbi) { 630 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 631 == IFM_AUTO) { 632 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 633 if (status == 0 || status & NGE_TBIANAR_FDX) { 634 NGE_SETBIT(sc, NGE_TX_CFG, 635 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 636 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 637 } else { 638 NGE_CLRBIT(sc, NGE_TX_CFG, 639 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 640 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 641 } 642 643 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 644 != IFM_FDX) { 645 NGE_CLRBIT(sc, NGE_TX_CFG, 646 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 647 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 648 } else { 649 NGE_SETBIT(sc, NGE_TX_CFG, 650 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 651 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 652 } 653 } else { 654 mii = device_get_softc(sc->nge_miibus); 655 656 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 657 NGE_SETBIT(sc, NGE_TX_CFG, 658 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 659 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 660 } else { 661 NGE_CLRBIT(sc, NGE_TX_CFG, 662 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 663 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 664 } 665 666 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 667 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 668 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 669 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 670 } else { 671 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 672 } 673 } 674 return; 675 } 676 677 static u_int32_t 678 nge_crc(sc, addr) 679 struct nge_softc *sc; 680 caddr_t addr; 681 { 682 u_int32_t crc, carry; 683 int i, j; 684 u_int8_t c; 685 686 /* Compute CRC for the address value. */ 687 crc = 0xFFFFFFFF; /* initial value */ 688 689 for (i = 0; i < 6; i++) { 690 c = *(addr + i); 691 for (j = 0; j < 8; j++) { 692 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 693 crc <<= 1; 694 c >>= 1; 695 if (carry) 696 crc = (crc ^ 0x04c11db6) | carry; 697 } 698 } 699 700 /* 701 * return the filter bit position 702 */ 703 704 return((crc >> 21) & 0x00000FFF); 705 } 706 707 static void 708 nge_setmulti(sc) 709 struct nge_softc *sc; 710 { 711 struct ifnet *ifp; 712 struct ifmultiaddr *ifma; 713 u_int32_t h = 0, i, filtsave; 714 int bit, index; 715 716 ifp = &sc->arpcom.ac_if; 717 718 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 719 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 720 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 721 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 722 return; 723 } 724 725 /* 726 * We have to explicitly enable the multicast hash table 727 * on the NatSemi chip if we want to use it, which we do. 728 * We also have to tell it that we don't want to use the 729 * hash table for matching unicast addresses. 730 */ 731 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 732 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 733 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 734 735 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 736 737 /* first, zot all the existing hash bits */ 738 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 739 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 740 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 741 } 742 743 /* 744 * From the 11 bits returned by the crc routine, the top 7 745 * bits represent the 16-bit word in the mcast hash table 746 * that needs to be updated, and the lower 4 bits represent 747 * which bit within that byte needs to be set. 748 */ 749 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 750 if (ifma->ifma_addr->sa_family != AF_LINK) 751 continue; 752 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 753 index = (h >> 4) & 0x7F; 754 bit = h & 0xF; 755 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 756 NGE_FILTADDR_MCAST_LO + (index * 2)); 757 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 758 } 759 760 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 761 762 return; 763 } 764 765 static void 766 nge_reset(sc) 767 struct nge_softc *sc; 768 { 769 register int i; 770 771 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 772 773 for (i = 0; i < NGE_TIMEOUT; i++) { 774 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 775 break; 776 } 777 778 if (i == NGE_TIMEOUT) 779 printf("nge%d: reset never completed\n", sc->nge_unit); 780 781 /* Wait a little while for the chip to get its brains in order. */ 782 DELAY(1000); 783 784 /* 785 * If this is a NetSemi chip, make sure to clear 786 * PME mode. 787 */ 788 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 789 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 790 791 return; 792 } 793 794 /* 795 * Probe for a NatSemi chip. Check the PCI vendor and device 796 * IDs against our list and return a device name if we find a match. 797 */ 798 static int 799 nge_probe(dev) 800 device_t dev; 801 { 802 struct nge_type *t; 803 804 t = nge_devs; 805 806 while(t->nge_name != NULL) { 807 if ((pci_get_vendor(dev) == t->nge_vid) && 808 (pci_get_device(dev) == t->nge_did)) { 809 device_set_desc(dev, t->nge_name); 810 return(0); 811 } 812 t++; 813 } 814 815 return(ENXIO); 816 } 817 818 /* 819 * Attach the interface. Allocate softc structures, do ifmedia 820 * setup and ethernet/BPF attach. 821 */ 822 static int 823 nge_attach(dev) 824 device_t dev; 825 { 826 int s; 827 u_char eaddr[ETHER_ADDR_LEN]; 828 struct nge_softc *sc; 829 struct ifnet *ifp; 830 int unit, error = 0, rid; 831 const char *sep = ""; 832 833 s = splimp(); 834 835 sc = device_get_softc(dev); 836 unit = device_get_unit(dev); 837 bzero(sc, sizeof(struct nge_softc)); 838 839 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 840 MTX_DEF | MTX_RECURSE); 841 #ifndef BURN_BRIDGES 842 /* 843 * Handle power management nonsense. 844 */ 845 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 846 u_int32_t iobase, membase, irq; 847 848 /* Save important PCI config data. */ 849 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 850 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 851 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 852 853 /* Reset the power state. */ 854 printf("nge%d: chip is in D%d power mode " 855 "-- setting to D0\n", unit, 856 pci_get_powerstate(dev)); 857 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 858 859 /* Restore PCI config data. */ 860 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 861 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 862 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 863 } 864 #endif 865 /* 866 * Map control/status registers. 867 */ 868 pci_enable_busmaster(dev); 869 870 rid = NGE_RID; 871 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 872 0, ~0, 1, RF_ACTIVE); 873 874 if (sc->nge_res == NULL) { 875 printf("nge%d: couldn't map ports/memory\n", unit); 876 error = ENXIO; 877 goto fail; 878 } 879 880 sc->nge_btag = rman_get_bustag(sc->nge_res); 881 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 882 883 /* Allocate interrupt */ 884 rid = 0; 885 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 886 RF_SHAREABLE | RF_ACTIVE); 887 888 if (sc->nge_irq == NULL) { 889 printf("nge%d: couldn't map interrupt\n", unit); 890 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 891 error = ENXIO; 892 goto fail; 893 } 894 895 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 896 nge_intr, sc, &sc->nge_intrhand); 897 898 if (error) { 899 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 900 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 901 printf("nge%d: couldn't set up irq\n", unit); 902 goto fail; 903 } 904 905 /* Reset the adapter. */ 906 nge_reset(sc); 907 908 /* 909 * Get station address from the EEPROM. 910 */ 911 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 912 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 913 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 914 915 /* 916 * A NatSemi chip was detected. Inform the world. 917 */ 918 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 919 920 sc->nge_unit = unit; 921 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 922 923 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 924 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 925 926 if (sc->nge_ldata == NULL) { 927 printf("nge%d: no memory for list buffers!\n", unit); 928 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 929 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 930 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 931 error = ENXIO; 932 goto fail; 933 } 934 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 935 936 /* Try to allocate memory for jumbo buffers. */ 937 if (nge_alloc_jumbo_mem(sc)) { 938 printf("nge%d: jumbo buffer allocation failed\n", 939 sc->nge_unit); 940 contigfree(sc->nge_ldata, 941 sizeof(struct nge_list_data), M_DEVBUF); 942 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 943 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 944 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 945 error = ENXIO; 946 goto fail; 947 } 948 949 ifp = &sc->arpcom.ac_if; 950 ifp->if_softc = sc; 951 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 952 ifp->if_mtu = ETHERMTU; 953 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 954 ifp->if_ioctl = nge_ioctl; 955 ifp->if_output = ether_output; 956 ifp->if_start = nge_start; 957 ifp->if_watchdog = nge_watchdog; 958 ifp->if_init = nge_init; 959 ifp->if_baudrate = 1000000000; 960 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 961 ifp->if_hwassist = NGE_CSUM_FEATURES; 962 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 963 ifp->if_capenable = ifp->if_capabilities; 964 965 /* 966 * Do MII setup. 967 */ 968 if (mii_phy_probe(dev, &sc->nge_miibus, 969 nge_ifmedia_upd, nge_ifmedia_sts)) { 970 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 971 sc->nge_tbi = 1; 972 device_printf(dev, "Using TBI\n"); 973 974 sc->nge_miibus = dev; 975 976 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 977 nge_ifmedia_sts); 978 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 979 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 980 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 981 device_printf(dev, " "); 982 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 983 PRINT("1000baseSX"); 984 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 985 PRINT("1000baseSX-FDX"); 986 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 987 PRINT("auto"); 988 989 printf("\n"); 990 #undef ADD 991 #undef PRINT 992 ifmedia_set(&sc->nge_ifmedia, 993 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 994 995 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 996 | NGE_GPIO_GP4_OUT 997 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 998 | NGE_GPIO_GP3_OUTENB 999 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 1000 1001 } else { 1002 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 1003 nge_free_jumbo_mem(sc); 1004 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1005 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1006 bus_release_resource(dev, NGE_RES, NGE_RID, 1007 sc->nge_res); 1008 error = ENXIO; 1009 goto fail; 1010 } 1011 } 1012 1013 /* 1014 * Call MI attach routine. 1015 */ 1016 ether_ifattach(ifp, eaddr); 1017 callout_handle_init(&sc->nge_stat_ch); 1018 1019 fail: 1020 1021 splx(s); 1022 mtx_destroy(&sc->nge_mtx); 1023 return(error); 1024 } 1025 1026 static int 1027 nge_detach(dev) 1028 device_t dev; 1029 { 1030 struct nge_softc *sc; 1031 struct ifnet *ifp; 1032 int s; 1033 1034 s = splimp(); 1035 1036 sc = device_get_softc(dev); 1037 ifp = &sc->arpcom.ac_if; 1038 1039 nge_reset(sc); 1040 nge_stop(sc); 1041 ether_ifdetach(ifp); 1042 1043 bus_generic_detach(dev); 1044 if (!sc->nge_tbi) { 1045 device_delete_child(dev, sc->nge_miibus); 1046 } 1047 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1048 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1049 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 1050 1051 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 1052 nge_free_jumbo_mem(sc); 1053 1054 splx(s); 1055 mtx_destroy(&sc->nge_mtx); 1056 1057 return(0); 1058 } 1059 1060 /* 1061 * Initialize the transmit descriptors. 1062 */ 1063 static int 1064 nge_list_tx_init(sc) 1065 struct nge_softc *sc; 1066 { 1067 struct nge_list_data *ld; 1068 struct nge_ring_data *cd; 1069 int i; 1070 1071 cd = &sc->nge_cdata; 1072 ld = sc->nge_ldata; 1073 1074 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1075 if (i == (NGE_TX_LIST_CNT - 1)) { 1076 ld->nge_tx_list[i].nge_nextdesc = 1077 &ld->nge_tx_list[0]; 1078 ld->nge_tx_list[i].nge_next = 1079 vtophys(&ld->nge_tx_list[0]); 1080 } else { 1081 ld->nge_tx_list[i].nge_nextdesc = 1082 &ld->nge_tx_list[i + 1]; 1083 ld->nge_tx_list[i].nge_next = 1084 vtophys(&ld->nge_tx_list[i + 1]); 1085 } 1086 ld->nge_tx_list[i].nge_mbuf = NULL; 1087 ld->nge_tx_list[i].nge_ptr = 0; 1088 ld->nge_tx_list[i].nge_ctl = 0; 1089 } 1090 1091 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1092 1093 return(0); 1094 } 1095 1096 1097 /* 1098 * Initialize the RX descriptors and allocate mbufs for them. Note that 1099 * we arrange the descriptors in a closed ring, so that the last descriptor 1100 * points back to the first. 1101 */ 1102 static int 1103 nge_list_rx_init(sc) 1104 struct nge_softc *sc; 1105 { 1106 struct nge_list_data *ld; 1107 struct nge_ring_data *cd; 1108 int i; 1109 1110 ld = sc->nge_ldata; 1111 cd = &sc->nge_cdata; 1112 1113 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1114 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1115 return(ENOBUFS); 1116 if (i == (NGE_RX_LIST_CNT - 1)) { 1117 ld->nge_rx_list[i].nge_nextdesc = 1118 &ld->nge_rx_list[0]; 1119 ld->nge_rx_list[i].nge_next = 1120 vtophys(&ld->nge_rx_list[0]); 1121 } else { 1122 ld->nge_rx_list[i].nge_nextdesc = 1123 &ld->nge_rx_list[i + 1]; 1124 ld->nge_rx_list[i].nge_next = 1125 vtophys(&ld->nge_rx_list[i + 1]); 1126 } 1127 } 1128 1129 cd->nge_rx_prod = 0; 1130 1131 return(0); 1132 } 1133 1134 /* 1135 * Initialize an RX descriptor and attach an MBUF cluster. 1136 */ 1137 static int 1138 nge_newbuf(sc, c, m) 1139 struct nge_softc *sc; 1140 struct nge_desc *c; 1141 struct mbuf *m; 1142 { 1143 struct mbuf *m_new = NULL; 1144 caddr_t *buf = NULL; 1145 1146 if (m == NULL) { 1147 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1148 if (m_new == NULL) { 1149 printf("nge%d: no memory for rx list " 1150 "-- packet dropped!\n", sc->nge_unit); 1151 return(ENOBUFS); 1152 } 1153 1154 /* Allocate the jumbo buffer */ 1155 buf = nge_jalloc(sc); 1156 if (buf == NULL) { 1157 #ifdef NGE_VERBOSE 1158 printf("nge%d: jumbo allocation failed " 1159 "-- packet dropped!\n", sc->nge_unit); 1160 #endif 1161 m_freem(m_new); 1162 return(ENOBUFS); 1163 } 1164 /* Attach the buffer to the mbuf */ 1165 m_new->m_data = (void *)buf; 1166 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1167 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1168 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1169 } else { 1170 m_new = m; 1171 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1172 m_new->m_data = m_new->m_ext.ext_buf; 1173 } 1174 1175 m_adj(m_new, sizeof(u_int64_t)); 1176 1177 c->nge_mbuf = m_new; 1178 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1179 c->nge_ctl = m_new->m_len; 1180 c->nge_extsts = 0; 1181 1182 return(0); 1183 } 1184 1185 static int 1186 nge_alloc_jumbo_mem(sc) 1187 struct nge_softc *sc; 1188 { 1189 caddr_t ptr; 1190 register int i; 1191 struct nge_jpool_entry *entry; 1192 1193 /* Grab a big chunk o' storage. */ 1194 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1195 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1196 1197 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1198 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1199 return(ENOBUFS); 1200 } 1201 1202 SLIST_INIT(&sc->nge_jfree_listhead); 1203 SLIST_INIT(&sc->nge_jinuse_listhead); 1204 1205 /* 1206 * Now divide it up into 9K pieces and save the addresses 1207 * in an array. 1208 */ 1209 ptr = sc->nge_cdata.nge_jumbo_buf; 1210 for (i = 0; i < NGE_JSLOTS; i++) { 1211 sc->nge_cdata.nge_jslots[i] = ptr; 1212 ptr += NGE_JLEN; 1213 entry = malloc(sizeof(struct nge_jpool_entry), 1214 M_DEVBUF, M_NOWAIT); 1215 if (entry == NULL) { 1216 printf("nge%d: no memory for jumbo " 1217 "buffer queue!\n", sc->nge_unit); 1218 return(ENOBUFS); 1219 } 1220 entry->slot = i; 1221 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1222 entry, jpool_entries); 1223 } 1224 1225 return(0); 1226 } 1227 1228 static void 1229 nge_free_jumbo_mem(sc) 1230 struct nge_softc *sc; 1231 { 1232 register int i; 1233 struct nge_jpool_entry *entry; 1234 1235 for (i = 0; i < NGE_JSLOTS; i++) { 1236 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1237 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1238 free(entry, M_DEVBUF); 1239 } 1240 1241 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1242 1243 return; 1244 } 1245 1246 /* 1247 * Allocate a jumbo buffer. 1248 */ 1249 static void * 1250 nge_jalloc(sc) 1251 struct nge_softc *sc; 1252 { 1253 struct nge_jpool_entry *entry; 1254 1255 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1256 1257 if (entry == NULL) { 1258 #ifdef NGE_VERBOSE 1259 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1260 #endif 1261 return(NULL); 1262 } 1263 1264 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1265 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1266 return(sc->nge_cdata.nge_jslots[entry->slot]); 1267 } 1268 1269 /* 1270 * Release a jumbo buffer. 1271 */ 1272 static void 1273 nge_jfree(buf, args) 1274 void *buf; 1275 void *args; 1276 { 1277 struct nge_softc *sc; 1278 int i; 1279 struct nge_jpool_entry *entry; 1280 1281 /* Extract the softc struct pointer. */ 1282 sc = args; 1283 1284 if (sc == NULL) 1285 panic("nge_jfree: can't find softc pointer!"); 1286 1287 /* calculate the slot this buffer belongs to */ 1288 i = ((vm_offset_t)buf 1289 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1290 1291 if ((i < 0) || (i >= NGE_JSLOTS)) 1292 panic("nge_jfree: asked to free buffer that we don't manage!"); 1293 1294 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1295 if (entry == NULL) 1296 panic("nge_jfree: buffer not in use!"); 1297 entry->slot = i; 1298 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1299 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1300 1301 return; 1302 } 1303 /* 1304 * A frame has been uploaded: pass the resulting mbuf chain up to 1305 * the higher level protocols. 1306 */ 1307 static void 1308 nge_rxeof(sc) 1309 struct nge_softc *sc; 1310 { 1311 struct mbuf *m; 1312 struct ifnet *ifp; 1313 struct nge_desc *cur_rx; 1314 int i, total_len = 0; 1315 u_int32_t rxstat; 1316 1317 ifp = &sc->arpcom.ac_if; 1318 i = sc->nge_cdata.nge_rx_prod; 1319 1320 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1321 struct mbuf *m0 = NULL; 1322 u_int32_t extsts; 1323 1324 #ifdef DEVICE_POLLING 1325 if (ifp->if_ipending & IFF_POLLING) { 1326 if (sc->rxcycles <= 0) 1327 break; 1328 sc->rxcycles--; 1329 } 1330 #endif /* DEVICE_POLLING */ 1331 1332 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1333 rxstat = cur_rx->nge_rxstat; 1334 extsts = cur_rx->nge_extsts; 1335 m = cur_rx->nge_mbuf; 1336 cur_rx->nge_mbuf = NULL; 1337 total_len = NGE_RXBYTES(cur_rx); 1338 NGE_INC(i, NGE_RX_LIST_CNT); 1339 /* 1340 * If an error occurs, update stats, clear the 1341 * status word and leave the mbuf cluster in place: 1342 * it should simply get re-used next time this descriptor 1343 * comes up in the ring. 1344 */ 1345 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1346 ifp->if_ierrors++; 1347 nge_newbuf(sc, cur_rx, m); 1348 continue; 1349 } 1350 1351 /* 1352 * Ok. NatSemi really screwed up here. This is the 1353 * only gigE chip I know of with alignment constraints 1354 * on receive buffers. RX buffers must be 64-bit aligned. 1355 */ 1356 #ifdef __i386__ 1357 /* 1358 * By popular demand, ignore the alignment problems 1359 * on the Intel x86 platform. The performance hit 1360 * incurred due to unaligned accesses is much smaller 1361 * than the hit produced by forcing buffer copies all 1362 * the time, especially with jumbo frames. We still 1363 * need to fix up the alignment everywhere else though. 1364 */ 1365 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1366 #endif 1367 m0 = m_devget(mtod(m, char *), total_len, 1368 ETHER_ALIGN, ifp, NULL); 1369 nge_newbuf(sc, cur_rx, m); 1370 if (m0 == NULL) { 1371 printf("nge%d: no receive buffers " 1372 "available -- packet dropped!\n", 1373 sc->nge_unit); 1374 ifp->if_ierrors++; 1375 continue; 1376 } 1377 m = m0; 1378 #ifdef __i386__ 1379 } else { 1380 m->m_pkthdr.rcvif = ifp; 1381 m->m_pkthdr.len = m->m_len = total_len; 1382 } 1383 #endif 1384 1385 ifp->if_ipackets++; 1386 1387 /* Do IP checksum checking. */ 1388 if (extsts & NGE_RXEXTSTS_IPPKT) 1389 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1390 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1391 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1392 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1393 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1394 (extsts & NGE_RXEXTSTS_UDPPKT && 1395 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1396 m->m_pkthdr.csum_flags |= 1397 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1398 m->m_pkthdr.csum_data = 0xffff; 1399 } 1400 1401 /* 1402 * If we received a packet with a vlan tag, pass it 1403 * to vlan_input() instead of ether_input(). 1404 */ 1405 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1406 VLAN_INPUT_TAG(ifp, m, 1407 extsts & NGE_RXEXTSTS_VTCI, continue); 1408 } 1409 1410 (*ifp->if_input)(ifp, m); 1411 } 1412 1413 sc->nge_cdata.nge_rx_prod = i; 1414 1415 return; 1416 } 1417 1418 /* 1419 * A frame was downloaded to the chip. It's safe for us to clean up 1420 * the list buffers. 1421 */ 1422 1423 static void 1424 nge_txeof(sc) 1425 struct nge_softc *sc; 1426 { 1427 struct nge_desc *cur_tx = NULL; 1428 struct ifnet *ifp; 1429 u_int32_t idx; 1430 1431 ifp = &sc->arpcom.ac_if; 1432 1433 /* Clear the timeout timer. */ 1434 ifp->if_timer = 0; 1435 1436 /* 1437 * Go through our tx list and free mbufs for those 1438 * frames that have been transmitted. 1439 */ 1440 idx = sc->nge_cdata.nge_tx_cons; 1441 while (idx != sc->nge_cdata.nge_tx_prod) { 1442 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1443 1444 if (NGE_OWNDESC(cur_tx)) 1445 break; 1446 1447 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1448 sc->nge_cdata.nge_tx_cnt--; 1449 NGE_INC(idx, NGE_TX_LIST_CNT); 1450 continue; 1451 } 1452 1453 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1454 ifp->if_oerrors++; 1455 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1456 ifp->if_collisions++; 1457 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1458 ifp->if_collisions++; 1459 } 1460 1461 ifp->if_collisions += 1462 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1463 1464 ifp->if_opackets++; 1465 if (cur_tx->nge_mbuf != NULL) { 1466 m_freem(cur_tx->nge_mbuf); 1467 cur_tx->nge_mbuf = NULL; 1468 } 1469 1470 sc->nge_cdata.nge_tx_cnt--; 1471 NGE_INC(idx, NGE_TX_LIST_CNT); 1472 ifp->if_timer = 0; 1473 } 1474 1475 sc->nge_cdata.nge_tx_cons = idx; 1476 1477 if (cur_tx != NULL) 1478 ifp->if_flags &= ~IFF_OACTIVE; 1479 1480 return; 1481 } 1482 1483 static void 1484 nge_tick(xsc) 1485 void *xsc; 1486 { 1487 struct nge_softc *sc; 1488 struct mii_data *mii; 1489 struct ifnet *ifp; 1490 int s; 1491 1492 s = splimp(); 1493 1494 sc = xsc; 1495 ifp = &sc->arpcom.ac_if; 1496 1497 if (sc->nge_tbi) { 1498 if (!sc->nge_link) { 1499 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1500 & NGE_TBIBMSR_ANEG_DONE) { 1501 printf("nge%d: gigabit link up\n", 1502 sc->nge_unit); 1503 nge_miibus_statchg(sc->nge_miibus); 1504 sc->nge_link++; 1505 if (ifp->if_snd.ifq_head != NULL) 1506 nge_start(ifp); 1507 } 1508 } 1509 } else { 1510 mii = device_get_softc(sc->nge_miibus); 1511 mii_tick(mii); 1512 1513 if (!sc->nge_link) { 1514 if (mii->mii_media_status & IFM_ACTIVE && 1515 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1516 sc->nge_link++; 1517 if (IFM_SUBTYPE(mii->mii_media_active) 1518 == IFM_1000_T) 1519 printf("nge%d: gigabit link up\n", 1520 sc->nge_unit); 1521 if (ifp->if_snd.ifq_head != NULL) 1522 nge_start(ifp); 1523 } 1524 } 1525 } 1526 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1527 1528 splx(s); 1529 1530 return; 1531 } 1532 1533 #ifdef DEVICE_POLLING 1534 static poll_handler_t nge_poll; 1535 1536 static void 1537 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1538 { 1539 struct nge_softc *sc = ifp->if_softc; 1540 1541 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1542 CSR_WRITE_4(sc, NGE_IER, 1); 1543 return; 1544 } 1545 1546 /* 1547 * On the nge, reading the status register also clears it. 1548 * So before returning to intr mode we must make sure that all 1549 * possible pending sources of interrupts have been served. 1550 * In practice this means run to completion the *eof routines, 1551 * and then call the interrupt routine 1552 */ 1553 sc->rxcycles = count; 1554 nge_rxeof(sc); 1555 nge_txeof(sc); 1556 if (ifp->if_snd.ifq_head != NULL) 1557 nge_start(ifp); 1558 1559 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1560 u_int32_t status; 1561 1562 /* Reading the ISR register clears all interrupts. */ 1563 status = CSR_READ_4(sc, NGE_ISR); 1564 1565 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1566 nge_rxeof(sc); 1567 1568 if (status & (NGE_ISR_RX_IDLE)) 1569 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1570 1571 if (status & NGE_ISR_SYSERR) { 1572 nge_reset(sc); 1573 nge_init(sc); 1574 } 1575 } 1576 } 1577 #endif /* DEVICE_POLLING */ 1578 1579 static void 1580 nge_intr(arg) 1581 void *arg; 1582 { 1583 struct nge_softc *sc; 1584 struct ifnet *ifp; 1585 u_int32_t status; 1586 1587 sc = arg; 1588 ifp = &sc->arpcom.ac_if; 1589 1590 #ifdef DEVICE_POLLING 1591 if (ifp->if_ipending & IFF_POLLING) 1592 return; 1593 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1594 CSR_WRITE_4(sc, NGE_IER, 0); 1595 nge_poll(ifp, 0, 1); 1596 return; 1597 } 1598 #endif /* DEVICE_POLLING */ 1599 1600 /* Supress unwanted interrupts */ 1601 if (!(ifp->if_flags & IFF_UP)) { 1602 nge_stop(sc); 1603 return; 1604 } 1605 1606 /* Disable interrupts. */ 1607 CSR_WRITE_4(sc, NGE_IER, 0); 1608 1609 /* Data LED on for TBI mode */ 1610 if(sc->nge_tbi) 1611 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1612 | NGE_GPIO_GP3_OUT); 1613 1614 for (;;) { 1615 /* Reading the ISR register clears all interrupts. */ 1616 status = CSR_READ_4(sc, NGE_ISR); 1617 1618 if ((status & NGE_INTRS) == 0) 1619 break; 1620 1621 if ((status & NGE_ISR_TX_DESC_OK) || 1622 (status & NGE_ISR_TX_ERR) || 1623 (status & NGE_ISR_TX_OK) || 1624 (status & NGE_ISR_TX_IDLE)) 1625 nge_txeof(sc); 1626 1627 if ((status & NGE_ISR_RX_DESC_OK) || 1628 (status & NGE_ISR_RX_ERR) || 1629 (status & NGE_ISR_RX_OFLOW) || 1630 (status & NGE_ISR_RX_FIFO_OFLOW) || 1631 (status & NGE_ISR_RX_IDLE) || 1632 (status & NGE_ISR_RX_OK)) 1633 nge_rxeof(sc); 1634 1635 if ((status & NGE_ISR_RX_IDLE)) 1636 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1637 1638 if (status & NGE_ISR_SYSERR) { 1639 nge_reset(sc); 1640 ifp->if_flags &= ~IFF_RUNNING; 1641 nge_init(sc); 1642 } 1643 1644 #if 0 1645 /* 1646 * XXX: nge_tick() is not ready to be called this way 1647 * it screws up the aneg timeout because mii_tick() is 1648 * only to be called once per second. 1649 */ 1650 if (status & NGE_IMR_PHY_INTR) { 1651 sc->nge_link = 0; 1652 nge_tick(sc); 1653 } 1654 #endif 1655 } 1656 1657 /* Re-enable interrupts. */ 1658 CSR_WRITE_4(sc, NGE_IER, 1); 1659 1660 if (ifp->if_snd.ifq_head != NULL) 1661 nge_start(ifp); 1662 1663 /* Data LED off for TBI mode */ 1664 1665 if(sc->nge_tbi) 1666 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1667 & ~NGE_GPIO_GP3_OUT); 1668 1669 return; 1670 } 1671 1672 /* 1673 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1674 * pointers to the fragment pointers. 1675 */ 1676 static int 1677 nge_encap(sc, m_head, txidx) 1678 struct nge_softc *sc; 1679 struct mbuf *m_head; 1680 u_int32_t *txidx; 1681 { 1682 struct nge_desc *f = NULL; 1683 struct mbuf *m; 1684 int frag, cur, cnt = 0; 1685 struct m_tag *mtag; 1686 1687 /* 1688 * Start packing the mbufs in this chain into 1689 * the fragment pointers. Stop when we run out 1690 * of fragments or hit the end of the mbuf chain. 1691 */ 1692 m = m_head; 1693 cur = frag = *txidx; 1694 1695 for (m = m_head; m != NULL; m = m->m_next) { 1696 if (m->m_len != 0) { 1697 if ((NGE_TX_LIST_CNT - 1698 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1699 return(ENOBUFS); 1700 f = &sc->nge_ldata->nge_tx_list[frag]; 1701 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1702 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1703 if (cnt != 0) 1704 f->nge_ctl |= NGE_CMDSTS_OWN; 1705 cur = frag; 1706 NGE_INC(frag, NGE_TX_LIST_CNT); 1707 cnt++; 1708 } 1709 } 1710 1711 if (m != NULL) 1712 return(ENOBUFS); 1713 1714 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1715 if (m_head->m_pkthdr.csum_flags) { 1716 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1717 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1718 NGE_TXEXTSTS_IPCSUM; 1719 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1720 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1721 NGE_TXEXTSTS_TCPCSUM; 1722 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1723 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1724 NGE_TXEXTSTS_UDPCSUM; 1725 } 1726 1727 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 1728 if (mtag != NULL) { 1729 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1730 (NGE_TXEXTSTS_VLANPKT|VLAN_TAG_VALUE(mtag)); 1731 } 1732 1733 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1734 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1735 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1736 sc->nge_cdata.nge_tx_cnt += cnt; 1737 *txidx = frag; 1738 1739 return(0); 1740 } 1741 1742 /* 1743 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1744 * to the mbuf data regions directly in the transmit lists. We also save a 1745 * copy of the pointers since the transmit list fragment pointers are 1746 * physical addresses. 1747 */ 1748 1749 static void 1750 nge_start(ifp) 1751 struct ifnet *ifp; 1752 { 1753 struct nge_softc *sc; 1754 struct mbuf *m_head = NULL; 1755 u_int32_t idx; 1756 1757 sc = ifp->if_softc; 1758 1759 if (!sc->nge_link) 1760 return; 1761 1762 idx = sc->nge_cdata.nge_tx_prod; 1763 1764 if (ifp->if_flags & IFF_OACTIVE) 1765 return; 1766 1767 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1768 IF_DEQUEUE(&ifp->if_snd, m_head); 1769 if (m_head == NULL) 1770 break; 1771 1772 if (nge_encap(sc, m_head, &idx)) { 1773 IF_PREPEND(&ifp->if_snd, m_head); 1774 ifp->if_flags |= IFF_OACTIVE; 1775 break; 1776 } 1777 1778 /* 1779 * If there's a BPF listener, bounce a copy of this frame 1780 * to him. 1781 */ 1782 BPF_MTAP(ifp, m_head); 1783 1784 } 1785 1786 /* Transmit */ 1787 sc->nge_cdata.nge_tx_prod = idx; 1788 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1789 1790 /* 1791 * Set a timeout in case the chip goes out to lunch. 1792 */ 1793 ifp->if_timer = 5; 1794 1795 return; 1796 } 1797 1798 static void 1799 nge_init(xsc) 1800 void *xsc; 1801 { 1802 struct nge_softc *sc = xsc; 1803 struct ifnet *ifp = &sc->arpcom.ac_if; 1804 struct mii_data *mii; 1805 int s; 1806 1807 if (ifp->if_flags & IFF_RUNNING) 1808 return; 1809 1810 s = splimp(); 1811 1812 /* 1813 * Cancel pending I/O and free all RX/TX buffers. 1814 */ 1815 nge_stop(sc); 1816 1817 if (sc->nge_tbi) { 1818 mii = NULL; 1819 } else { 1820 mii = device_get_softc(sc->nge_miibus); 1821 } 1822 1823 /* Set MAC address */ 1824 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1825 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1826 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1827 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1828 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1829 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1830 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1831 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1832 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1833 1834 /* Init circular RX list. */ 1835 if (nge_list_rx_init(sc) == ENOBUFS) { 1836 printf("nge%d: initialization failed: no " 1837 "memory for rx buffers\n", sc->nge_unit); 1838 nge_stop(sc); 1839 (void)splx(s); 1840 return; 1841 } 1842 1843 /* 1844 * Init tx descriptors. 1845 */ 1846 nge_list_tx_init(sc); 1847 1848 /* 1849 * For the NatSemi chip, we have to explicitly enable the 1850 * reception of ARP frames, as well as turn on the 'perfect 1851 * match' filter where we store the station address, otherwise 1852 * we won't receive unicasts meant for this host. 1853 */ 1854 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1855 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1856 1857 /* If we want promiscuous mode, set the allframes bit. */ 1858 if (ifp->if_flags & IFF_PROMISC) { 1859 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1860 } else { 1861 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1862 } 1863 1864 /* 1865 * Set the capture broadcast bit to capture broadcast frames. 1866 */ 1867 if (ifp->if_flags & IFF_BROADCAST) { 1868 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1869 } else { 1870 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1871 } 1872 1873 /* 1874 * Load the multicast filter. 1875 */ 1876 nge_setmulti(sc); 1877 1878 /* Turn the receive filter on */ 1879 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1880 1881 /* 1882 * Load the address of the RX and TX lists. 1883 */ 1884 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1885 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1886 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1887 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1888 1889 /* Set RX configuration */ 1890 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1891 /* 1892 * Enable hardware checksum validation for all IPv4 1893 * packets, do not reject packets with bad checksums. 1894 */ 1895 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1896 1897 /* 1898 * Tell the chip to detect and strip VLAN tag info from 1899 * received frames. The tag will be provided in the extsts 1900 * field in the RX descriptors. 1901 */ 1902 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1903 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1904 1905 /* Set TX configuration */ 1906 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1907 1908 /* 1909 * Enable TX IPv4 checksumming on a per-packet basis. 1910 */ 1911 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1912 1913 /* 1914 * Tell the chip to insert VLAN tags on a per-packet basis as 1915 * dictated by the code in the frame encapsulation routine. 1916 */ 1917 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1918 1919 /* Set full/half duplex mode. */ 1920 if (sc->nge_tbi) { 1921 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1922 == IFM_FDX) { 1923 NGE_SETBIT(sc, NGE_TX_CFG, 1924 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1925 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1926 } else { 1927 NGE_CLRBIT(sc, NGE_TX_CFG, 1928 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1929 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1930 } 1931 } else { 1932 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1933 NGE_SETBIT(sc, NGE_TX_CFG, 1934 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1935 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1936 } else { 1937 NGE_CLRBIT(sc, NGE_TX_CFG, 1938 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1939 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1940 } 1941 } 1942 1943 nge_tick(sc); 1944 1945 /* 1946 * Enable the delivery of PHY interrupts based on 1947 * link/speed/duplex status changes. Also enable the 1948 * extsts field in the DMA descriptors (needed for 1949 * TCP/IP checksum offload on transmit). 1950 */ 1951 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1952 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1953 1954 /* 1955 * Configure interrupt holdoff (moderation). We can 1956 * have the chip delay interrupt delivery for a certain 1957 * period. Units are in 100us, and the max setting 1958 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1959 */ 1960 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1961 1962 /* 1963 * Enable interrupts. 1964 */ 1965 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1966 #ifdef DEVICE_POLLING 1967 /* 1968 * ... only enable interrupts if we are not polling, make sure 1969 * they are off otherwise. 1970 */ 1971 if (ifp->if_ipending & IFF_POLLING) 1972 CSR_WRITE_4(sc, NGE_IER, 0); 1973 else 1974 #endif /* DEVICE_POLLING */ 1975 CSR_WRITE_4(sc, NGE_IER, 1); 1976 1977 /* Enable receiver and transmitter. */ 1978 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1979 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1980 1981 nge_ifmedia_upd(ifp); 1982 1983 ifp->if_flags |= IFF_RUNNING; 1984 ifp->if_flags &= ~IFF_OACTIVE; 1985 1986 (void)splx(s); 1987 1988 return; 1989 } 1990 1991 /* 1992 * Set media options. 1993 */ 1994 static int 1995 nge_ifmedia_upd(ifp) 1996 struct ifnet *ifp; 1997 { 1998 struct nge_softc *sc; 1999 struct mii_data *mii; 2000 2001 sc = ifp->if_softc; 2002 2003 if (sc->nge_tbi) { 2004 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2005 == IFM_AUTO) { 2006 CSR_WRITE_4(sc, NGE_TBI_ANAR, 2007 CSR_READ_4(sc, NGE_TBI_ANAR) 2008 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 2009 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 2010 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 2011 | NGE_TBIBMCR_RESTART_ANEG); 2012 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 2013 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 2014 & IFM_GMASK) == IFM_FDX) { 2015 NGE_SETBIT(sc, NGE_TX_CFG, 2016 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2017 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2018 2019 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2020 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2021 } else { 2022 NGE_CLRBIT(sc, NGE_TX_CFG, 2023 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2024 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2025 2026 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2027 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2028 } 2029 2030 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 2031 & ~NGE_GPIO_GP3_OUT); 2032 } else { 2033 mii = device_get_softc(sc->nge_miibus); 2034 sc->nge_link = 0; 2035 if (mii->mii_instance) { 2036 struct mii_softc *miisc; 2037 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2038 miisc = LIST_NEXT(miisc, mii_list)) 2039 mii_phy_reset(miisc); 2040 } 2041 mii_mediachg(mii); 2042 } 2043 2044 return(0); 2045 } 2046 2047 /* 2048 * Report current media status. 2049 */ 2050 static void 2051 nge_ifmedia_sts(ifp, ifmr) 2052 struct ifnet *ifp; 2053 struct ifmediareq *ifmr; 2054 { 2055 struct nge_softc *sc; 2056 struct mii_data *mii; 2057 2058 sc = ifp->if_softc; 2059 2060 if (sc->nge_tbi) { 2061 ifmr->ifm_status = IFM_AVALID; 2062 ifmr->ifm_active = IFM_ETHER; 2063 2064 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2065 ifmr->ifm_status |= IFM_ACTIVE; 2066 } 2067 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2068 ifmr->ifm_active |= IFM_LOOP; 2069 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2070 ifmr->ifm_active |= IFM_NONE; 2071 ifmr->ifm_status = 0; 2072 return; 2073 } 2074 ifmr->ifm_active |= IFM_1000_SX; 2075 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2076 == IFM_AUTO) { 2077 ifmr->ifm_active |= IFM_AUTO; 2078 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2079 & NGE_TBIANAR_FDX) { 2080 ifmr->ifm_active |= IFM_FDX; 2081 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2082 & NGE_TBIANAR_HDX) { 2083 ifmr->ifm_active |= IFM_HDX; 2084 } 2085 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2086 == IFM_FDX) 2087 ifmr->ifm_active |= IFM_FDX; 2088 else 2089 ifmr->ifm_active |= IFM_HDX; 2090 2091 } else { 2092 mii = device_get_softc(sc->nge_miibus); 2093 mii_pollstat(mii); 2094 ifmr->ifm_active = mii->mii_media_active; 2095 ifmr->ifm_status = mii->mii_media_status; 2096 } 2097 2098 return; 2099 } 2100 2101 static int 2102 nge_ioctl(ifp, command, data) 2103 struct ifnet *ifp; 2104 u_long command; 2105 caddr_t data; 2106 { 2107 struct nge_softc *sc = ifp->if_softc; 2108 struct ifreq *ifr = (struct ifreq *) data; 2109 struct mii_data *mii; 2110 int s, error = 0; 2111 2112 s = splimp(); 2113 2114 switch(command) { 2115 case SIOCSIFMTU: 2116 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2117 error = EINVAL; 2118 else { 2119 ifp->if_mtu = ifr->ifr_mtu; 2120 /* 2121 * Workaround: if the MTU is larger than 2122 * 8152 (TX FIFO size minus 64 minus 18), turn off 2123 * TX checksum offloading. 2124 */ 2125 if (ifr->ifr_mtu >= 8152) 2126 ifp->if_hwassist = 0; 2127 else 2128 ifp->if_hwassist = NGE_CSUM_FEATURES; 2129 } 2130 break; 2131 case SIOCSIFFLAGS: 2132 if (ifp->if_flags & IFF_UP) { 2133 if (ifp->if_flags & IFF_RUNNING && 2134 ifp->if_flags & IFF_PROMISC && 2135 !(sc->nge_if_flags & IFF_PROMISC)) { 2136 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2137 NGE_RXFILTCTL_ALLPHYS| 2138 NGE_RXFILTCTL_ALLMULTI); 2139 } else if (ifp->if_flags & IFF_RUNNING && 2140 !(ifp->if_flags & IFF_PROMISC) && 2141 sc->nge_if_flags & IFF_PROMISC) { 2142 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2143 NGE_RXFILTCTL_ALLPHYS); 2144 if (!(ifp->if_flags & IFF_ALLMULTI)) 2145 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2146 NGE_RXFILTCTL_ALLMULTI); 2147 } else { 2148 ifp->if_flags &= ~IFF_RUNNING; 2149 nge_init(sc); 2150 } 2151 } else { 2152 if (ifp->if_flags & IFF_RUNNING) 2153 nge_stop(sc); 2154 } 2155 sc->nge_if_flags = ifp->if_flags; 2156 error = 0; 2157 break; 2158 case SIOCADDMULTI: 2159 case SIOCDELMULTI: 2160 nge_setmulti(sc); 2161 error = 0; 2162 break; 2163 case SIOCGIFMEDIA: 2164 case SIOCSIFMEDIA: 2165 if (sc->nge_tbi) { 2166 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2167 command); 2168 } else { 2169 mii = device_get_softc(sc->nge_miibus); 2170 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2171 command); 2172 } 2173 break; 2174 default: 2175 error = ether_ioctl(ifp, command, data); 2176 break; 2177 } 2178 2179 (void)splx(s); 2180 2181 return(error); 2182 } 2183 2184 static void 2185 nge_watchdog(ifp) 2186 struct ifnet *ifp; 2187 { 2188 struct nge_softc *sc; 2189 2190 sc = ifp->if_softc; 2191 2192 ifp->if_oerrors++; 2193 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2194 2195 nge_stop(sc); 2196 nge_reset(sc); 2197 ifp->if_flags &= ~IFF_RUNNING; 2198 nge_init(sc); 2199 2200 if (ifp->if_snd.ifq_head != NULL) 2201 nge_start(ifp); 2202 2203 return; 2204 } 2205 2206 /* 2207 * Stop the adapter and free any mbufs allocated to the 2208 * RX and TX lists. 2209 */ 2210 static void 2211 nge_stop(sc) 2212 struct nge_softc *sc; 2213 { 2214 register int i; 2215 struct ifnet *ifp; 2216 struct mii_data *mii; 2217 2218 ifp = &sc->arpcom.ac_if; 2219 ifp->if_timer = 0; 2220 if (sc->nge_tbi) { 2221 mii = NULL; 2222 } else { 2223 mii = device_get_softc(sc->nge_miibus); 2224 } 2225 2226 untimeout(nge_tick, sc, sc->nge_stat_ch); 2227 #ifdef DEVICE_POLLING 2228 ether_poll_deregister(ifp); 2229 #endif 2230 CSR_WRITE_4(sc, NGE_IER, 0); 2231 CSR_WRITE_4(sc, NGE_IMR, 0); 2232 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2233 DELAY(1000); 2234 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2235 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2236 2237 if (!sc->nge_tbi) 2238 mii_down(mii); 2239 2240 sc->nge_link = 0; 2241 2242 /* 2243 * Free data in the RX lists. 2244 */ 2245 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2246 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2247 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2248 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2249 } 2250 } 2251 bzero((char *)&sc->nge_ldata->nge_rx_list, 2252 sizeof(sc->nge_ldata->nge_rx_list)); 2253 2254 /* 2255 * Free the TX list buffers. 2256 */ 2257 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2258 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2259 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2260 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2261 } 2262 } 2263 2264 bzero((char *)&sc->nge_ldata->nge_tx_list, 2265 sizeof(sc->nge_ldata->nge_tx_list)); 2266 2267 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2268 2269 return; 2270 } 2271 2272 /* 2273 * Stop all chip I/O so that the kernel's probe routines don't 2274 * get confused by errant DMAs when rebooting. 2275 */ 2276 static void 2277 nge_shutdown(dev) 2278 device_t dev; 2279 { 2280 struct nge_softc *sc; 2281 2282 sc = device_get_softc(dev); 2283 2284 nge_reset(sc); 2285 nge_stop(sc); 2286 2287 return; 2288 } 2289